Pulse signal processing method and device, equipment, storage medium and program product

Abstract

The invention provides a pulse signal processing method and device, equipment, a storage medium and a program product, and relates to the technical field of wireless, and the method comprises the steps: carrying out the periodic abnormality detection of a PP1S signal transmitted by a global navigation satellite system GNSS after a locking circuit outputs a locked PP1S signal; locking the current circuit state of the locking circuit under the condition that the detection result is single abnormality or loss abnormality, and outputting a PP1S locking signal based on a locking parameter corresponding to the current circuit state; or, under the condition that the detection result is normal, according to the currently detected PP1S signal sent by the GNSS, the locking parameter of the locking circuit is updated, and the locked PP1S signal is output based on the updated locking parameter. Thus, when the PP1S signal is abnormal, the clock circuit can output the stable PP1S signal, the possibility of clock output errors is reduced, and the accuracy of system synchronization is improved.

Description

Technical Field

[0001] The present application relates to the field of wireless technology, and in particular to a pulse signal processing method, apparatus, device, storage medium, and program product. Background Art

[0002] The clock supply method of existing base stations is as follows: Figure 1 As shown, a complex programmable logic device (CPLD) / field programmable gate array (FPGA) is generally used to receive the pulse per second (PP1S) signal of the Global Navigation Satellite System (GNSS), then de-jitter and frequency-divide it, and then hard-wire it to the FPGA chip and X86 chip respectively. The synchronization between the two is based on the same clock pulse signal, and both calculate the frame number, time slot number and other information based on the clock signal pulse signal.

[0003] However, the PP1S signal output by GNSS may be lost due to various interferences or sudden anomalies. The current response accuracy to these sudden situations is not high, which may cause errors in clock output and lead to inaccurate system synchronization. Summary of the Invention

[0004] The embodiments of the present application provide a pulse signal processing method, apparatus, device, storage medium, and program product, which solve the problem of inaccurate system synchronization caused by clock output errors due to abnormal PPIS signals.

[0005] In a first aspect, to achieve the above-mentioned objectives, embodiments of the present application provide a pulse signal processing method, comprising:

[0006] After the locking circuit outputs the locking pulse-per-second PP1S signal, periodic anomaly detection is performed on the PP1S signal sent by the global navigation satellite system GNSS;

[0007] When the detection result is a single abnormality or a lost abnormality, the current circuit state of the locking circuit is locked, and a locking PP1S signal is output based on a locking parameter corresponding to the current circuit state;

[0008] Alternatively, when the detection result is normal, the locking parameters of the locking circuit are updated according to the PPIS signal sent by the currently detected GNSS, and the locked PPIS signal is output based on the updated locking parameters.

[0009] The method further comprises:

[0010] Receive PP1S signals sent by the GNSS system;

[0011] By performing error processing on a plurality of continuously received PPIS signals, the error of PPIS signal jitter and the error of the crystal oscillator clock are eliminated, the locking circuit is locked and the current locking parameters are obtained, wherein the locking parameters include a locking difference and a locking relative difference.

[0012] The error processing is performed by using a plurality of continuously received PP1S signals to eliminate the error of PP1S signal jitter and the error of the crystal oscillator clock, lock the locking circuit and obtain the current locking parameters, including:

[0013] Among the multiple P1S signals received continuously, after receiving each of the first m P1S signals, starting the locking circuit and locking twice continuously according to the count value recorded by the local free counter; wherein m is an integer greater than or equal to 3;

[0014] After the locking circuit is locked twice consecutively, among a plurality of consecutively received P1S signals, after receiving each of the next n P1S signals, performing error calculation, error tracking, and error elimination based on the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain a current locking parameter; wherein n is an integer greater than or equal to 1;

[0015] The last PP1S signal among the first m PP1S signals is the first PP1S signal among the next n PP1S signals.

[0016] wherein, after receiving each of the first m PP1S signals, starting the locking circuit and locking twice in succession according to the count value recorded by the local free counter, including:

[0017] After receiving the PP1S signal for the first time, assigning the first count value currently recorded by the local free counter to the error variable;

[0018] After receiving the PP1S signal for the second time, calculating the absolute value of the first difference between the second count value currently recorded by the local free counter and the current error variable, and when the absolute value of the first difference is less than a first threshold, setting the flag indicating that the locking circuit is locked to 1, the locking circuit is started, and the locking circuit is locked once;

[0019] After receiving the PP1S signal for the third time, the absolute value of the second difference between the third count value currently recorded by the local free counter and the current error variable is calculated. When the absolute value of the second difference is less than the first threshold, it is determined that the locking circuit is locked for the second time.

[0020] After receiving each of the next n PP1S signals, error calculation, error tracking, and error elimination are performed based on the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain the current locking parameters, including:

[0021] for each of the last n PPIS signals, after receiving the PPIS signal, in a case where it is determined that the locking circuit is in a locked state according to a difference between a count value currently recorded by the local free counter and the error variable, determining a real-time error of the currently received PPIS signal according to a difference between a fourth count value currently recorded by the PPIS counter and a preset maximum count value of the PPIS counter, and updating the error variable according to the real-time error;

[0022] For non-first PPIS signals among the last n PPIS signals, determining a locking difference in the locking parameter according to the current error variable and a count value currently recorded by the local free counter;

[0023] For each PPIS signal after the second PPIS signal among the last n PPIS signals, determine the relative difference in the locking parameter according to the difference between the locking difference corresponding to the current PPIS signal and the locking difference corresponding to the previous PPIS signal adjacent to the current PPIS signal.

[0024] The periodic anomaly detection of the PP1S signal sent by the global navigation satellite system GNSS includes:

[0025] When, at a detection moment corresponding to the periodic anomaly detection, it is detected that a flag indicating a PP1S signal loss is set to 1, the detection result is determined to be a loss anomaly;

[0026] When it is detected that the locking error corresponding to the PP1S signal is outside the first range, the detection result is determined to be a single abnormality; wherein the locking error is the difference between the value of the error variable corresponding to the currently detected PP1S signal and the value recorded by the local free counter.

[0027] The method includes updating the locking parameters of the locking circuit according to the P1S signal sent by the currently detected GNSS, and outputting the locked P1S signal based on the updated locking parameters, including:

[0028] After receiving the currently detected PPIS signal sent by the GNSS, determining a relative difference corresponding to the currently detected PPIS signal sent by the GNSS;

[0029] Determine the current maximum count value of the PP1S output counter according to the preset maximum count value of the PP1S counter and the relative difference;

[0030] When the value recorded by the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output.

[0031] Wherein, when the detection result is a single abnormality or a lost abnormality, locking the current circuit state of the locking circuit, and outputting a locking PP1S signal based on the locking parameter corresponding to the current circuit state, including:

[0032] Acquire the locking parameter before the current anomaly detection, wherein the locking parameter includes a relative difference;

[0033] Determine the current maximum count value of the PP1S output counter according to the preset maximum count value of the PP1S counter and the currently acquired relative difference;

[0034] The PPIS output counter is used for counting, and when the count value of the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output.

[0035] Wherein, when the detection result is a single abnormality or a lost abnormality, before locking the current circuit state of the locking circuit and outputting a locking PP1S signal based on the locking parameter corresponding to the current circuit state, the method further includes:

[0036] When the detection result is a loss abnormality, the circuit lock state is maintained by switching to a local holding circuit state.

[0037] The method further comprises:

[0038] After the detection result is a loss anomaly, performing real-time detection on the PPIS signal sent by the GNSS;

[0039] In the case of detecting a PP1S signal sent by the GNSS, if the count value of the PP1S counter corresponding to the currently received PP1S is within the second range, determining that the currently received PP1S signal is normal, setting a flag indicating that the PP1S signal is lost to 0, and setting a flag indicating that the PP1S signal is online to 1;

[0040] After detecting the PP1S signal sent by the GNSS again, the current locking parameters are updated according to the currently detected PP1S signal;

[0041] According to the updated locking parameters, a locking PP1S signal is output.

[0042] In a second aspect, to achieve the above-mentioned objectives, embodiments of the present application provide a pulse signal processing device, comprising:

[0043] A first detection module is configured to perform periodic anomaly detection on a PP1S signal sent by a global navigation satellite system (GNSS) after the locking circuit outputs the locked pulse per second (PP1S) signal based on error processing;

[0044] A first processing module is configured to lock the current circuit state of the locking circuit when the detection result is a single abnormality or a lost abnormality, and output a locking PP1S signal based on a locking parameter corresponding to the current circuit state;

[0045] Alternatively, the second processing module is configured to update the locking parameters of the locking circuit according to the PPIS signal sent by the currently detected GNSS when the detection result is normal, and output the locking PPIS signal based on the updated locking parameters.

[0046] In the third aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a pulse signal processing device, including a transceiver, a processor, a memory, and a program stored on the memory and runnable on the processor; when the processor executes the program, it implements the pulse signal processing method described in the first aspect.

[0047] In a fourth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a readable storage medium on which a program or instruction is stored, and when the program or instruction is executed by a processor, the pulse signal processing method as described in the first aspect is implemented.

[0048] In a fifth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a computer program product, including computer instructions, which, when executed by a processor, implement the pulse signal processing method as described in the first aspect.

[0049] The beneficial effects of the above technical solution of this application are as follows:

[0050] In an embodiment of the present application, first, after the locking circuit outputs the locked pulse second PP1S signal, the P1S signal transmitted by the global navigation satellite system (GNSS) is periodically detected for anomalies. Second, if the detection result is a single anomaly or a loss anomaly, the current circuit state of the locking circuit is locked, and a locked P1S signal is output based on the locking parameters corresponding to the current circuit state. Alternatively, if the detection result is normal, the locking parameters of the locking circuit are updated based on the currently detected P1S signal transmitted by the GNSS, and a locked P1S signal is output based on the updated locking parameters. In this way, when the P1S signal transmitted by the GNSS is not received normally, a stable P1S signal is output based on the locking parameters corresponding to the current locking circuit state. When the P1S signal transmitted by the GNSS is received normally, the locking parameters of the locking circuit are updated based on the relevant information corresponding to the currently received P1S signal to track the error of the P1S signal. In this way, the clock can maintain the output of a stable and accurate P1S signal, reduce the possibility of clock output errors, and improve the accuracy of system synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a schematic diagram of the clock signal connection of a universal base station;

[0052] Figure 2 This is a flow chart of a pulse signal processing method according to an embodiment of the present application;

[0053] Figure 3 Schematic diagram of the process of de-jittering and tracking the elimination of errors in the PP1S signal according to an embodiment of the present application;

[0054] Figure 4 A schematic diagram of a process bundle for solving the locked output stage in an embodiment of the present application;

[0055] Figure 5 This is a second flow chart of the pulse signal processing method according to an embodiment of the present application;

[0056] Figure 6 This is a schematic structural diagram of a pulse signal processing device according to an embodiment of the present application;

[0057] Figure 7 This is a schematic diagram of the structure of a pulse signal processing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the technical problems, technical solutions and advantages to be solved by this application clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0059] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0060] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0061] Additionally, the terms "system" and "network" are often used interchangeably herein.

[0062] In the embodiments provided herein, it should be understood that "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0063] Before describing the embodiments of the present application, the relevant technical points are first described:

[0064] Local clock source provided by crystal oscillator:

[0065] A crystal oscillator is an electronic component that generates a stable oscillation frequency and is commonly used as a local clock source in communications systems. It operates by utilizing the piezoelectric effect. By applying an electric field to a specific crystal material, it generates mechanical vibrations, thereby producing a stable frequency signal. However, the frequency of a crystal oscillator is not completely stable. Over time, the internal physical properties of the crystal oscillator may change, causing its output frequency to drift. Furthermore, environmental factors such as temperature and voltage fluctuations can also affect the frequency of the crystal oscillator. This frequency drift can adversely affect the performance of the communication system, especially in applications requiring high-precision clock synchronization.

[0066] Reference clock sources provided by GNSS:

[0067] GNSS systems provide users with highly accurate PP1S time information by receiving signals from satellites. The atomic clocks in GNSS systems are extremely accurate and stable, and their time signals serve as reference clocks in communication systems. However, GNSS signals can be subject to various interferences during transmission, such as ionospheric delay errors, tropospheric delay errors, multipath effects, and receiver noise. These interferences can cause jitter in GNSS PP1S signals, meaning that the arrival time of the signal may fluctuate slightly. Although this jitter generally follows a normal distribution and is generally within 100ns for different receiver models, it clearly cannot meet the sub-nanosecond timing accuracy requirements of wireless communication systems in applications requiring extremely high clock precision.

[0068] As mentioned above, the clock supply method of the existing wireless communication base station is as follows: Figure 1 As shown, it is not suitable for scenarios where clock accuracy is required in new fields (such as sub-nanosecond accuracy requirements) or scenarios where PPIS signal stability is required in complex environments. Specifically, the above method has the following problems:

[0069] (1) The accuracy of jitter tracking and error elimination is not high: The PP1S signal output by GNSS may have deviations each time. The local crystal oscillator has frequency and phase errors in long-term operation. The simultaneous existence of the two is a mixed error. The timing accuracy achieved by the relevant algorithm in eliminating the above two types of errors cannot meet the requirements of high demand or complex scenarios.

[0070] (2) Lack of switching design to track PP1S loss and recovery: There is a lack of technical design in the following scenarios: The existing technology requires switching to the local clock after the GNSS PP1S signal is lost to maintain a stable clock signal output. At the same time, it is necessary to switch back to the GNSS PP1S signal to continue to maintain a stable clock signal output after the GNSS PP1S signal is automatically recovered after loss.

[0071] In practical applications, the PP1S signal may be lost due to various interferences or sudden anomalies. However, existing solutions have low accuracy in monitoring, tracking, switching, and responding to such anomalies, which may cause errors in clock output and inaccurate system synchronization.

[0072] In view of this, an embodiment of the present application provides a pulse signal processing method, which can be applied to an accelerator card (such as an FPGA accelerator card) in a BBU of a base station, such as Figure 2 As shown, the method includes:

[0073] Step 201: After the locking circuit outputs the locked pulse second (PP1S) signal, periodic anomaly detection is performed on the PP1S signal transmitted by the global navigation satellite system (GNSS). Specifically, when the locking circuit is locked and outputting a stable PP1S signal, periodic anomaly detection can be performed on the PP1S signal periodically transmitted by the GNSS to detect whether the PP1S signal is received at a specific time. The PP1S signal for periodic anomaly detection is the PP1S signal transmitted by the GNSS after the locking circuit is locked and maintaining a stable PP1S output.

[0074] Step 202A, when the detection result is a single abnormality or a lost abnormality, lock the current circuit state of the locking circuit, and output a locked PP1S signal based on the locking parameters corresponding to the current circuit state; that is, when it is determined that the PP1S signal has a single abnormality or a lost abnormality, control the locking circuit to output a stable PP1S signal according to the locking parameters corresponding to the current locking state, that is, output a stable PP1S signal in the same manner as the locked PP1S output by the locking circuit before the single abnormality or the lost abnormality of the PP1S signal.

[0075] Alternatively, in step 202B, if the detection result is normal, the locking parameters of the locking circuit are updated according to the currently detected P1S signal sent by the GNSS, and the locked P1S signal is output based on the updated locking parameters. In other words, when it is detected that the P1S signal sent by the GNSS has arrived normally, the current locking parameters can be updated based on parameters related to the currently received P1S signal (such as relative error). In this way, the error of the P1S signal and the error of the crystal oscillator can be tracked, ensuring that a stable P1S signal can be output.

[0076] In an embodiment of the present application, first, after the locking circuit outputs the locked pulse-per-second (PP1S) signal, the P1S signal transmitted by the global navigation satellite system (GNSS) is periodically detected for anomalies. Second, if the detection result is a single anomaly or a loss anomaly, the current circuit state of the locking circuit is locked, and a locked P1S signal is output based on the locking parameters corresponding to the current circuit state. Alternatively, if the detection result is normal, the locking parameters of the locking circuit are updated based on the currently detected P1S signal transmitted by the GNSS, and a locked P1S signal is output based on the updated locking parameters. In this way, when the P1S signal transmitted by the GNSS is not received normally, a stable P1S signal is output based on the locking parameters corresponding to the current locking circuit state. When the P1S signal transmitted by the GNSS is received normally, the locking parameters of the locking circuit are updated based on the relevant information corresponding to the currently received P1S signal to track the error of the P1S signal and the crystal oscillator error. In this way, the clock circuit can maintain the output of a stable and accurate P1S signal, reduce the possibility of clock output errors, and improve the accuracy of system synchronization.

[0077] Furthermore, as an optional implementation, before step 201, the method further includes:

[0078] Receive PP1S signals sent by the GNSS system;

[0079] By performing error processing on a plurality of continuously received PPIS signals, the error of PPIS signal jitter and the error of the crystal oscillator clock are eliminated, the locking circuit is locked and the current locking parameters are obtained, wherein the locking parameters include a locking difference and a locking relative difference.

[0080] It should be noted here that, in the present application, GNSS periodically sends a PP1S signal, wherein, in the above-mentioned optional implementation, the PP1S signal sent by the GNSS is used to lock the clock circuit so that the locked clock circuit can output a locked / stable PP1S signal based on the locking parameters, and the PP1S signal detected in step 201 is the PP1S signal sent by the GNSS after the above-mentioned optional implementation, and the locking circuit outputs a stable / locked PP1S signal based on the PP1S signal to achieve clock synchronization.

[0081] As a specific implementation, the optional implementation of "eliminating PP1S signal jitter errors and crystal oscillator clock errors by performing error processing on multiple consecutively received PP1S signals, locking the locking circuit, and obtaining current locking parameters" includes:

[0082] Among multiple P1S signals received consecutively, after receiving each of the first m P1S signals, the locking circuit is activated and locked twice consecutively based on the count value recorded by the local free counter, where m is greater than or equal to 3. That is, after each P1S signal sent by the GNSS is received, it is determined whether the locking circuit is locked based on the current count value recorded by the local free counter, and the locking circuit is activated after the locking circuit is locked for the first time.

[0083] Here, it should be noted that the local free counter starts counting after the execution subject of this application (such as the accelerator card) is powered on. It mainly uses the local clock calculation to realize 1-second counting, and automatically counts to the preset maximum count value of the PP1S signal (such as the measured average maximum count value of the statistical PP1S signal counter) and clears the number to 1, and continues to count for 1 second.

[0084] After the locking circuit has locked twice consecutively, after receiving each of the next n P1S signals among a plurality of consecutively received P1S signals, error calculation, error tracking, and error elimination are performed based on the count value recorded by the local free counter and the count value recorded by the P1S counter to obtain current locking parameters; where n is an integer greater than or equal to 1. In other words, after the locking circuit has locked twice consecutively, error detection (including jitter error of the P1S signal and / or crystal oscillator deviation) is performed based on the count value recorded by the local free counter and the count value recorded by the P1S counter for each subsequent P1S signal received, so as to update the locking parameters and achieve error tracking and elimination.

[0085] The last PP1S signal among the first m PP1S signals is the first PP1S signal among the next n PP1S signals.

[0086] As a more specific implementation, the step of “after receiving each of the first m P1S signals, starting the locking circuit and locking twice in succession according to the count value recorded by the local free counter” in the above specific implementation includes:

[0087] After receiving the PP1S signal for the first time, the first count value currently recorded by the local free counter is assigned to the error variable. That is, when the PP1S signal sent by the GNSS is received for the first time, the first count value currently recorded by the local free counter (Local_cnt1) is obtained and assigned to the error variable (Iterate_cnt), that is, Iterate_cnt1 = Local_cnt1. The initial value of the error variable is 0. Alternatively, the initial value of the error variable can be set to a value between 0 and MAX_num_1s (the maximum count value of the PP1S signal counted above). In this case, this step can be to compare the absolute value of the difference between Local_cnt1 and the error variable to see whether it is greater than a first threshold. If so, the locking circuit loses lock. If not, the locking circuit locks for the first time and updates the error variable to the sum of the absolute value of the difference between the error variable and the error variable before the update. In this way, the locking process time can be shortened.

[0088] After receiving the PP1S signal for the second time, the absolute value of the first difference between the second count value currently recorded by the local free counter and the current error variable is calculated, and when the absolute value of the first difference is less than a first threshold, the flag position indicating that the locking circuit is locked is set to 1, the locking circuit is started, and the locking circuit is locked once; wherein, the absolute value of the first difference is less than the first threshold, indicating that the PP1S deviation is not large and there is no abnormality.

[0089] After receiving the PP1S signal for the third time, the absolute value of the second difference between the third count value currently recorded by the local free counter and the current error variable is calculated. When the absolute value of the second difference is less than the first threshold, it is determined that the locking circuit is locked for the second time.

[0090] Stated another way, the above-mentioned more specific implementation process is as follows: after receiving each of the first m P1S signals, a first difference between the count value currently recorded by the local free counter and the current error variable is calculated. If the first difference is less than a first threshold, the locking circuit is determined to be locked, and the error variable is updated to the sum of the current error variable and the first difference. The initial value of the error variable is any preset value between 0 and MAX_num_1s. Furthermore, if the first difference is greater than or equal to the first threshold, the locking circuit is determined to be unlocked, and the locking circuit needs to be relocked starting with the next received P1S signal.

[0091] As another more specific implementation, the step of “after receiving each of the next n P1S signals, performing error calculation, error tracking, and error elimination based on the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain the current locking parameter” in the above specific implementation includes:

[0092] For each of the last n PPIS signals, after receiving the PPIS signal, when it is determined that the locking circuit is in a locked state based on the difference between the count value currently recorded by the local free counter and the error variable, a real-time error of the currently received PPIS signal is determined based on the difference between the fourth count value currently recorded by the PPIS counter and a preset maximum count value of the PPIS counter, and the error variable is updated based on the real-time error; here, updating the error variable specifically includes: updating the error variable to the sum of the current error variable and the real-time error.

[0093] For non-first PPIS signals among the last n PPIS signals, determining a locking difference in the locking parameter based on the current error variable and the count value currently recorded by the local free counter; wherein the locking difference is the difference between the current error variable and the count value currently recorded by the local free counter, and the locking difference is an unsigned number, in other words, the locking difference is the absolute value of the aforementioned difference;

[0094] For each PPIS signal after the second one of the last n PPIS signals, a relative difference in the locking parameter is determined based on a difference between a locking difference corresponding to the current PPIS signal and a locking difference corresponding to a previous PPIS signal adjacent to the current PPIS signal. Here, the relative difference is a difference between the locking difference corresponding to the current PPIS signal and the locking difference corresponding to the previous PPIS signal adjacent to the current PPIS signal.

[0095] Below, Figure 4 As an example, the implementation process of the above-mentioned multiple implementation methods is illustrated.

[0096] Step 401: First reception of lock_vld = 0. This step specifically involves the following: Upon first reception of the PP1S signal, the difference between Local_cnt (the current count value recorded by the local free counter) and Iterate_cnt (the current value of the error variable) is compared. The initial value of Iterate_cnt is 0. The locking process duration can be adjusted by setting the initial value of Iterate_cnt to a value between 0 and MAX_num_1s. This difference, |Local_cnt - Iterate_cnt|, is ≤ 10. If 10 × 4 = 40 ns, the PP1S is considered reliable. If it exceeds 40 ns, the PP1S is considered unreliable, and a PP1S abnormality alarm is issued. Where 4 is a parameter related to the clock crystal oscillator. After the comparison, Local_cnt is assigned to Iterate_cnt. The current circuit state is lock_vld = 0, indicating a loss of lock.

[0097] Step 402: Second reception, lock_vld = 1. This step specifically includes the following: The second reception of the PP1S signal: First, compare the difference between Local_cnt (the current count value recorded by the local free counter) and Iterate_cnt (the error parameter updated in step 401). If the PP1S deviation is small and there is no anomaly, since Local_cnt has already been assigned to Iterate_cnt during the first reception, the difference between Local_cnt and Iterate_cnt will be less than 10. Therefore, lock_vld = 1, and the locking circuit begins operation. If the PP1S deviation is large or abnormal at startup, the first lock can always be achieved. For the sake of simplicity, it is assumed that the second lock is achieved. The locking circuit obtains the first lock.

[0098] Step 403, third reception: lock_vld = 1, calibration = PP1S_cnt - MAX_num_1s, Iterate_cnt = Iterate_cnt + calibration. In this step, "=" means assignment. Specifically, this step involves receiving the PP1S signal for the third time. If there are no PP1S anomalies, the signal is considered locked. The locking circuit achieves a second lock. Here, steps 401 through 403 are intended to achieve two consecutive locks. If there are no PP1S anomalies after power-on, it is assumed that the third attempt will achieve two locks. Furthermore, after lock, the de-bouncing tracking error elimination design begins: Step 1: Error calculation: Compare PP1S_cnt with MAX_num_1s; calibration = PP1S_cnt - MAX_num_1s. Step 2: Counter update: Iterate_cnt = Iterate_cnt + calibration.

[0099] Step 404, fourth reception: lock_vld = 1, calibration = PP1S_cnt - MAX_num_1s, Iterate_cnt = Iterate_cnt + calibration, Δ1 = Iterate_cnt - Local_cnt. The "=" in this step indicates a value assignment. Specifically, this step involves receiving the PP1S signal for the fourth time, comparing the difference between Local_cnt and Iterate_cnt, and performing a third lock on the locking circuit. The process from steps 1 to 3 is identical to the three steps in step 4.3. Step 4: Output the locked difference, Δ1 = Iterate_cnt - Local_cnt. This third lock is performed to achieve a stable lock difference, Δ1, where Δ is an unsigned number.

[0100] Step 405, fifth reception: lock_vld = 1, calibration = PP1S_cnt - MAX_num_1s, Iterate_cnt = Iterate_cnt + calibration, Ω1 = Δ2 - Δ1. In this step, "=" signifies a value assignment. Specifically, this step involves receiving the PP1S signal for the fifth time, comparing the difference between Local_cnt and Iterate_cnt, and obtaining a fourth lock. Steps 1 through 4 are identical to the four steps in step 404. Step 5: Output the relative lock difference, Ω1 = Δ2 - Δ1, where Ω is a signed number.

[0101] Here, it should be noted that in order to quickly obtain the lock, the algorithm does not consider multiple locking processes to calculate the average value and assign it to Ω. Instead, it eliminates the error based on the real-time update of the tracking process, that is, Iterate_cnt = Iterate_cnt + calibration.

[0102] It should be noted that after determining the current locking error, a stable PP1S signal may be output based on the locking error. Specifically, continuing with the above example, this example further includes the following steps:

[0103] The PP1S signal is received for the sixth time, and the maximum value of the PP1S_out_cnt counter (PP1S output counter) is set to M = MAX_num_1s + Ω n , n=1,Ω n is the tracking error, Ω n =Δ n+1 -Δ n , each time M is counted, the number is cleared to 1 and the PP1S signal is output, and the locked PP1S signal is output to the subsequent frequency division module. If there is no abnormality in the subsequent PP1S signal, it is judged that lock_vld is not equal to 0, Ω nBased on the real-time change of the locking error Δ.

[0104] Next, combine Figure 3 , the PP1S signal de-jitter tracking error elimination algorithm is explained from different aspects.

[0105] a) Error source analysis:

[0106] (1) For the PP1S signal, the edge is taken first each time, and then the maximum count is calculated for 1 second each time. Each time the PP1S signal arrives, the PP1S_cnt counter is cleared to 1 and then counted again. The PP1S signal will jitter, and the count may be different each time. The maximum count each time the PP1S arrives is counted. MAX_num_1s is the average maximum count value of the PP1S_cnt of the PP1S signal measured N = 10,000 times. This statistical value MAX_num_1s is used as the accurate maximum count value of the PP1S signal.

[0107] (2) Compare PP1S_cnt to MAX_num_1s. If PP1S_cnt > MAX_num_1s, the PP1S signal arrives late. Conversely, if PP1S_cnt > MAX_num_1s, the PP1S signal arrives early. The error is calculated as calibration = PP1S_cnt - MAX_num_1s, where calibration is a signed number. Unstable PP1S signals can cause dynamic variations in PP1S_cnt. PP1S_cnt can also fluctuate due to the crystal oscillator clock frequency and phase. Therefore, PP1S_cnt fluctuations are affected by these two factors, resulting in errors in the output PP1S signal.

[0108] (3) Local free counter Local_cnt begins counting at power-up. Local_cnt uses the local clock to count one second. When it reaches the maximum value MAX_num_1s, it resets to 1 and continues counting in a loop. Local_cnt's count fluctuates due to the frequency and phase of the crystal oscillator clock.

[0109] Therefore, the error of the PP1S signal comes from the influence of the crystal clock frequency and phase, as well as the jitter of the PP1S signal.

[0110] b) Locking judgment process: This process is as follows Figure 4 shown.

[0111] c) Outputting the PP1S signal: that is, the sixth receiving process of the aforementioned PP1S signal.

[0112] d) Error elimination analysis:

[0113] In actual engineering implementation, the PP1S signal arrives early or late; the crystal oscillator frequency slows down or speeds up due to the influence of quality performance, and the phase changes will affect the stability of the circuit. For example, if the crystal oscillator frequency decreases, the clock slows down, the count remains unchanged, the time increases, and the time is inaccurate. In engineering testing, it was found that after one year of testing, the crystal oscillator occasionally had deviations. W should be counted in 1 second, and the crystal oscillator clock may slow down a little. In fact, only W-offset should be counted. The offset is a random value. If it is counted according to W, the time will exceed 1 second. Therefore, it is necessary to introduce error variables to eliminate the influence of crystal oscillator instability. This solution designs a de-jitter tracking fluctuation algorithm, which will reduce the impact of crystal oscillator deviation and ensure that the PP1S signal has a stable output PP1S signal within a certain jitter range. The following is a detailed introduction to the error source and error elimination method (corresponding to the aforementioned multiple optional implementation methods):

[0114] The initial value of Iterate_cnt is 0. After the first PP1S signal is received, the current value of Local_cnt is assigned to Iterate_cnt. When the PP1S signal is received a second time, the difference between Iterate_cnt and Local_cnt is again compared, resulting in Iterate_cnt = Local_cnt_old (the previous value of Local_cnt) minus Local_cnt (the current value). When the PP1S signal is received a third time, the jitter and tracking design begins, as detailed below.

[0115] PP1S jitter and inaccurate crystal oscillator clock will cause changes in the value of Local_cnt at each ratio point. Local_cnt will cycle, so calibration is required to track changes in Local_cnt.

[0116] As indicated in the previous steps:

[0117]

[0118] The simplification of formula variation 1 is that after the first PP1S arrives, Local_cnt (the first value) is assigned to Iterate_cnt, and then Iterate_cnt = Iterate_cnt + calibration. The update of Iterate_cnt is the first obtained Local_cnt plus the calibration each time.

[0119] The simplification of formula variation 2 is to simplify the complex formula, decomposing PP1S_cnt into a fixed value MAX_num_1s+η, where η is a variable value and can be positive or negative; Local_cnt_new is decomposed into a fixed value Local_cnt_old (the value obtained by the first lock)+δ2, where δ2 is a variable value and can be positive or negative.

[0120] The simplification of formula variation 3 is to let The jitter error η of PP1S usually obeys a normal distribution, and δ1=0 after a large amount of data accumulation.

[0121] About error Δ n =δ1-δ2, here we consider four cases:

[0122] Here, it is important to note that Local_cnt is a periodic count, and Iterate_cnt is the updated value each time. If there is no error, both are the values ​​after the first PP1S signal is received, and the circuit perfectly locks and outputs the second PP1S signal. The existence of errors causes the values ​​of the two to change. Compared with the previous value, if both values ​​are larger than the previous value, but the difference Δ n =δ1-δ2 remains unchanged, which means the ratio point is delayed, otherwise the ratio point is advanced.

[0123] Case 1: The PP1S signal is accurate, but the crystal oscillator clock (including frequency and phase) is inaccurate:

[0124] Formula Δ n =δ1-δ2. Since the two counters are caused by the same clock, the actual test crystal oscillator will be slower and need to be less counted. If δ1 is less than 0, it will change. If δ2 is less than 0, it will change. The difference Δ n =δ1-δ2 first becomes smaller and then tends to remain unchanged. If the clock speeds up, it will overcount. δ1 will change if it is greater than 0, and δ2 will change if it is greater than 0. The difference Δ n =δ1-δ2, first increases and then remains unchanged. Ω n =Δ n -Δ n-1 , changes in the crystal oscillator change stage, and does not change when the crystal oscillator tends to a certain stability. In the stage of faster frequency, Ω n When the frequency increases to a positive value, M needs to count more; conversely, when the frequency slows down, M needs to count less.

[0125] Case 2: The crystal oscillator clock is accurate, but the first PP1S signal is inaccurate:

[0126] If the first PP1S signal arrives late for the first time, calibration>0, Local_cnt>Local_cnt_old, δ1 and δ2 are both greater than 0. If it arrives late for the second time, the error is accumulated and the ratio point is delayed. If it arrives on time for the second time, calibration=0 and the ratio point remains unchanged. If it arrives early for the second time, calibration<0, δ1 and δ2 are less than 0, and the ratio point is advanced. Local_cnt_new becomes smaller, indicating that the ratio point is advanced. By introducing calibration, it can follow the changes in the ratio point. Although the data changes, the difference Δ n =δ1-δ2 remains unchanged, which can avoid the loss of lock caused by data changes, causing the circuit to repeatedly lose and lock and change Δ n and Ω n The value of affects the output PP1S signal.

[0127] Case 3: The crystal oscillator clock and the first PP1S signal are both accurate, the Local_cnt and Iterate_cnt data remain unchanged, and the difference is Δ n =δ1-δ2 unchanged, Ω n =Δ n -Δ n-1 The value of remains unchanged.

[0128] Case 4: Both the crystal oscillator clock and the first PP1S signal are inaccurate. According to the first and second cases, Δ n =δ1-δ2 may vary, but as long as |Δ n |≤10, it can be considered that the first PP1S signal of GNSS is reliable and the circuit crystal oscillator clock is reasonable and normal. Otherwise, an abnormal alarm is issued. n =Δ n -Δ n-1 The value of changes with the change, and the PP1S output in this state is stable. That is, the PP1S signal output by the above-mentioned various implementation methods of the embodiments of the present application is a stable PP1S signal.

[0129] By adopting the above-mentioned various implementation methods of the present application for circuit locking and error tracking, a simple algorithm is implemented so that the PPIS signal output by the locking circuit can eliminate the jitter of the GNSS PPIS signal and the error of the crystal oscillator, thereby achieving sub-nanosecond timing accuracy.

[0130] As an optional implementation, step 201 includes:

[0131] At the detection moment corresponding to the periodic abnormality detection, if it is detected that the flag bit representing the loss of the PP1S signal is set to 1, the detection result is determined to be a loss abnormality; wherein the flag bit of the loss of the PP1S signal is, for example, PP1S_lose;

[0132] When it is detected that the locking error corresponding to the PP1S signal is outside the first range, the detection result is determined to be a single abnormality; wherein the locking error is the difference between the value of the error variable corresponding to the currently detected PP1S signal and the value recorded by the local free counter.

[0133] The PP1S_online signal is defined as the normal arrival of PP1S and the error of PP1S is within a certain range. The formula is:

[0134]

[0135] in, It indicates the normal error range of PP1S and can be set to 32. PP1S_pulse indicates the time when the PP1S signal arrives.

[0136] If the PP1S error is too large or lost, PP1S_online is 0. There are two cases to explain here.

[0137] Single abnormality: PP1S signal abnormality means that the PP1S error is too large. According to the above formula, PP1S_online is 0. At this time, the PP1S signal will be restricted from participating in the current circuit state processing, and the circuit will maintain the previous state.

[0138] Loss of PP1S signal exception: Loss of the PP1S signal will cause PP1S_cnt to continue counting until it reaches the maximum value and overflows to 0. Furthermore, the loss of the PP1S signal will cause PP1S_cnt to remain 0 unless the PP1S signal arrives. In this state, set PP1S_lose (the flag indicating PP1S signal loss) to 1, indicating a PP1S signal loss scenario. At this time, PP1S_online is 0. When PP1S_lose is 1, PP1S_online must be 0.

[0139] That is to say, when a single abnormality or loss of abnormality occurs, the circuit locks the current circuit state, Iterate_cnt stops normal tracking, Local_cnt counts periodically, and when Δ n and Ω n Remain unchanged, PP1S_out_cnt samples the internal clock periodically and counts to stably output the PP1S signal.

[0140] As an optional implementation, step 202B includes:

[0141] After receiving the PP1S signal sent by the currently detected GNSS, determine the relative difference corresponding to the currently detected PP1S signal sent by the GNSS; as recorded in the aforementioned optional implementation method, the relative error of this step is the difference between the locking difference corresponding to the PP1S signal received this time and the locking difference corresponding to the adjacent previous received PP1S signal.

[0142] The current maximum count value of the PPIS output counter is determined according to the preset maximum count value of the PPIS counter and the relative difference; wherein the current maximum count value of the PPIS output counter is the sum of the preset maximum count value of the PPIS counter and the relative difference.

[0143] When the value recorded by the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output. In other words, the locked PPIS signal is output when the PPIS output counter counts to the current maximum count value.

[0144] As an optional implementation, step 202A includes:

[0145] The locking parameter before the current abnormality detection is obtained, wherein the locking parameter includes a relative difference; here, the locking parameter before the abnormality detection is specifically a locking parameter corresponding to a previous PP1S signal adjacent to the PP1S signal currently undergoing abnormality detection.

[0146] The current maximum count value of the PP1S output counter is determined according to the preset maximum count value of the PP1S counter and the currently obtained relative difference; wherein the current maximum count value of the PP1S output counter is the sum of the preset maximum count value of the PP1S counter and the relative difference.

[0147] The PPIS output counter is used for counting, and when the count value of the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output.

[0148] That is, when an abnormality in the current PPIS signal is detected, a stable PPIS signal is output based on the locking parameters before the currently received PPIS signal.

[0149] Furthermore, as an optional implementation, before step 202A, the method further includes:

[0150] If the detection result is a loss anomaly, the circuit lock state is maintained by switching to the local hold circuit state. In other words, if the PPIS signal is not detected, the local hold circuit is switched to maintain the output of the PPIS signal.

[0151] Furthermore, as an optional implementation, the method further includes:

[0152] After the detection result is a loss anomaly, the PPIS signal sent by the GNSS is detected in real time; the detection here is to determine when the PPIS signal is restored.

[0153] When a PP1S signal sent by GNSS is detected, if the count value of the PP1S counter corresponding to the currently received PP1S is within the second range, it is determined that the currently received PP1S signal is normal, and the flag position representing the PP1S signal loss is set to 0, and the flag position representing the PP1S signal online is set to 1; wherein the lower limit of the second range is

[0154] After the PPlS signal sent by the GNSS is detected again, the current locking parameters are updated according to the currently detected PPlS signal. Exemplarily, this step includes updating the current relative error based on the locking error corresponding to the currently detected PPlS signal.

[0155] Outputting a locked PPIS signal based on the updated locking parameters. This step includes determining the current maximum count value of the PPIS output counter based on the preset maximum count value of the PPIS counter and the currently acquired relative difference value; and counting using the PPIS output counter. When the count value of the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output.

[0156] Here, it should be noted that, as mentioned above, the PP1S signal is automatically restored after being lost, and the PP1S signal output by the internal clock is switched to the GNSS output to continue to calibrate and maintain the stable output of the circuit.

[0157] The key here is how to determine when the PP1S signal is restored after it is lost, how to make Iterate_cnt quickly approach Local_cnt so that lock_vld = 1 when the PP1S signal is restored, otherwise, lock_vld = 0, the PP1S signal output by the circuit is discontinuous, and the circuit is abnormal.

[0158] The key point of this algorithm's fast switching design is that when PP1S_lose is 1, Iterate_cnt = Local_cnt. When the PP1S signal is lost and restored, the PP1S signal resumes the first reception: PP1S_cnt resumes counting, when It is assumed that the PP1S signal is normal, PP1S_lose=0, PP1S_online=1, and the PP1S signal is received for the second time: it starts to follow the fluctuation to eliminate the error. The output PP1S signal follows the GNSS PP1S signal.

[0159] Below, Figure 5 Taking as an example, the implementation process of the second impulse signal processing method of the embodiment of the present application is described.

[0160] Step 501, PP1S signal detection; the received PP1S signal is detected for abnormality, and if the single deviation is too large, the single signal is discarded. If the PP1S signal is not detected, the local holding circuit is switched to maintain the output of the PP1S signal.

[0161] Step 502, error calculation: obtain the real-time error of the PP1S signal, calibration = PP1S_cnt - MAX_num_1s.

[0162] Step 503: Error tracking; real-time update of Iterate_cnt=Iterate_cnt+calibration.

[0163] Step 504, error elimination; according to the tracking elimination of the GNSS PP1S jitter error and the crystal oscillator clock error, solve Δ n =δ1-δ2.

[0164] Step 505: Periodic detection and judgment; if |Δ n |≤10, it can be considered that the GNSS PP1S signal is reliable and the circuit crystal oscillator clock is reasonable and normal, and step 510 is executed. If |Δ n |>10, the circuit is not locked, and step 506 is executed; if PP1S_lose is detected to be 1, it is known that PP1S is lost, and step 507 is executed; if it is determined to be an abnormality other than a single abnormality and a loss abnormality, step 512 is executed;

[0165] Step 506: A single exception keeps the last locked state;

[0166] Step 507, PP1S loss exception;

[0167] Step 508, switching to the local hold circuit state to maintain the circuit locked state;

[0168] Step 509, real-time monitoring of the PP1S signal;

[0169] Step 510, update the locking parameters; wherein, when step 510 is executed after step 506 or after step 508, step 510 specifically stops normal tracking by Iterate_cnt, counts periodically by Local_cnt, and the locking error and relative difference remain unchanged. When step 510 is executed after step 505, step 510 specifically updates the parameter Ω in the locked state. n =Δ n -Δ n-1 and M value.

[0170] Step 511: Output a stable PP1S signal. After the M value is updated, the PP1S_out_cnt counter outputs the PP1S signal when it reaches M.

[0171] Step 512: Determine that it is an unknown abnormality and do not lock; that is, determine that the current abnormality is an unknown abnormality, and the locking circuit will not lock at this time.

[0172] Step 513: Output an abnormal lock loss alarm.

[0173] It should be noted that the pulse signal processing method of the embodiment of the present application can be deployed in an FPGA accelerator card, that is, a clock synchronization circuit is set up in the FPGA accelerator card. Among them, there is only one FPGA chip in the FPGA accelerator card. The FPGA chip is directly used to receive the external PPIS signal. Then, Verilog code is written to implement the de-jitter and anti-interference error elimination algorithm to achieve the output of a stable and reliable PPIS signal. This signal is then divided and output as a 10ms signal. Then, the de-jitter and anti-interference error elimination algorithm is implemented on the 10ms signal to output a stable and reliable 10ms pulse signal with sub-nanosecond accuracy. This signal is used as the frame header of the wireless frame for base station synchronization.

[0174] Each of the aforementioned optional implementations features jitter tracking and calibration for jitter in the GNSS PP1S signal, ensuring PP1S signal stability. A corresponding jitter tracking and calibration mechanism also addresses potential jitter in the crystal oscillator clock. PP1S loss and recovery points are tracked, enabling automatic switching to maintain stable and accurate signal output. Furthermore, a loss-of-lock alarm function provides timely alerts when anomalies occur, ensuring the stability and reliability of the entire clock supply system.

[0175] Among them, in the process of implementing multi-stage locking and outputting a stable PP1S signal according to the input signal, by introducing calibration to update Iterate_cnt to track Local_cnt and then derive Δ n =δ1-δ2,Ωn =Δ n -Δ n-1 and M values. This allows for the deviations in the GNSS PP1S signal output and the frequency and phase errors of the local crystal oscillator to be analyzed separately, and algorithms designed to eliminate these errors are implemented within the algorithm design to track and eliminate them. Furthermore, in this process, the error classification is rational, the derivation of simplified formulas is simple, and the error elimination method is simple and widely applicable. Secondly, the judgment and handling of abnormal situations, whether single or lost, are accurate and rational, and the judgment and recovery of PP1S signal loss are rapid, precise, and simple. Thirdly, this algorithm monitors the GNSS PP1S signal and automatically switches to local clock operation upon GNSS signal loss, continuing signal correction while maintaining a stable signal output. When the GNSS PP1S signal is restored, the current circuit output state is recorded and operation continues using the GNSS signal. Switching errors are eliminated during both switching steps, thereby providing stable and accurate clock output and ensuring the stability of the system output signal. Furthermore, the switching algorithm is simple and easy to implement, with universal applicability.

[0176] In summary, this algorithm design can meet the 6G network's requirements for nanosecond and even sub-nanosecond timing accuracy. This design method provides a very practical reference design algorithm for both the clock synchronization circuit design of FPGA accelerator cards and the clock synchronization circuit design of other systems.

[0177] The embodiment of the present application also provides a pulse signal processing device, such as Figure 6 Shown, including:

[0178] A first detection module 601 is configured to perform periodic anomaly detection on a Pulse Per Second (PP1S) signal sent by a global navigation satellite system (GNSS) after the locking circuit outputs the locked Pulse Per Second (PP1S) signal based on error processing;

[0179] A first processing module 602A is configured to lock the current circuit state of the locking circuit when the detection result is a single abnormality or a lost abnormality, and output a locking PP1S signal based on a locking parameter corresponding to the current circuit state;

[0180] Alternatively, the second processing module 602B is configured to update the locking parameters of the locking circuit according to the PPIS signal sent by the currently detected GNSS when the detection result is normal, and output a locking PPIS signal based on the updated locking parameters.

[0181] Wherein, the device further includes:

[0182] A receiving module, used to receive PP1S signals sent by the GNSS system;

[0183] The third processing module is configured to eliminate the error of PPIS signal jitter and the error of the crystal oscillator clock by performing error processing on a plurality of continuously received PPIS signals, lock the locking circuit, and obtain current locking parameters, wherein the locking parameters include a locking difference and a locking relative difference.

[0184] Wherein, the third processing module includes:

[0185] a first processing submodule, configured to, after receiving each of the first m P1S signals among the plurality of consecutively received P1S signals, activate the locking circuit and lock the signal twice in succession according to the count value recorded by the local free counter; wherein m is an integer greater than or equal to 3;

[0186] a second processing submodule, configured to, after the locking circuit has locked twice consecutively, calculate, track, and eliminate errors among a plurality of consecutively received P1S signals, and after receiving each of the next n P1S signals, to obtain current locking parameters based on a count value recorded by the local free counter and a count value recorded by the PP1S counter; wherein n is an integer greater than or equal to 1;

[0187] The last PP1S signal among the first m PP1S signals is the first PP1S signal among the next n PP1S signals.

[0188] The first processing submodule includes:

[0189] a first processing unit, configured to assign a first count value currently recorded by the local free counter to an error variable after receiving the PP1S signal for the first time;

[0190] a second processing unit, configured to calculate, after receiving the PP1S signal for the second time, an absolute value of a first difference between a second count value currently recorded by the local free counter and a current error variable, and, if the absolute value of the first difference is less than a first threshold, set a flag indicating that the locking circuit is locked to 1, thereby activating the locking circuit and locking the locking circuit once;

[0191] a third processing unit, configured to calculate, after receiving the PP1S signal for the third time, an absolute value of a second difference between a third count value currently recorded by the local free counter and a current error variable, and determine that the locking circuit is locked for the second time when the absolute value of the second difference is less than the first threshold.

[0192] The second processing submodule includes:

[0193] a fourth processing unit, configured to, for each of the last n PPIS signals, after receiving the PPIS signal, determine a real-time error of the currently received PPIS signal based on a difference between a fourth count value currently recorded by the PPIS counter and a preset maximum count value of the PPIS counter, when the locking circuit is determined to be in a locked state based on a difference between a count value currently recorded by the local free counter and the error variable, and update the error variable based on the real-time error;

[0194] a fifth processing unit, configured to determine, for non-first PPIS signals among the last n PPIS signals, a locking difference in the locking parameter according to the current error variable and a count value currently recorded by the local free counter;

[0195] a sixth processing unit, configured to determine, for each PPIS signal after the second PPIS signal among the last n PPIS signals, a relative difference in the locking parameter based on a difference between a locking difference corresponding to a current PPIS signal and a locking difference corresponding to a previous PPIS signal adjacent to the current PPIS signal.

[0196] The first detection module 601 includes:

[0197] A first detection submodule is configured to, when detecting that a flag indicating a loss of the PPIS signal is set to 1 at a detection moment corresponding to the periodic anomaly detection, determine that the detection result is a loss anomaly;

[0198] a second detection submodule configured to determine that the detection result is a single abnormality when it is detected that the locking error corresponding to the PP1S signal is outside a first range; wherein the locking error is a difference between the value of the error variable corresponding to the currently detected PP1S signal and the value recorded by the local free counter.

[0199] The second processing module 602B includes:

[0200] a first determining submodule, configured to, after receiving the currently detected PPIS signal sent by the GNSS, determine a relative difference corresponding to the currently detected PPIS signal sent by the GNSS;

[0201] A second determining submodule is configured to determine a current maximum count value of the PPIS output counter based on a preset maximum count value of the PPIS counter and the relative difference;

[0202] The third processing submodule is configured to reset the count value of the PPIS output counter to 1 and output the locked PPIS signal when the value recorded by the PPIS output counter reaches the current maximum count value of the PPIS output counter.

[0203] The first processing module 602A includes:

[0204] An acquisition submodule, configured to acquire the locking parameters before the current anomaly detection, wherein the locking parameters include relative differences;

[0205] A third determining submodule is configured to determine a current maximum count value of the PP1S output counter according to a preset maximum count value of the PP1S counter and the currently acquired relative difference;

[0206] The fourth processing submodule is configured to count using the PPIS output counter, and when the count value of the PPIS output counter reaches the current maximum count value of the PPIS output counter, reset the count value of the PPIS output counter to 1 and output the locked PPIS signal.

[0207] Wherein, the device further includes:

[0208] The fourth processing module is configured to maintain the circuit locked state by switching to a local hold circuit state when the detection result is a loss exception.

[0209] Wherein, the device further includes:

[0210] A sending module, configured to perform real-time detection of the PPIS signal sent by the GNSS after the detection result is a loss anomaly;

[0211] a determination module, configured to, upon detecting a PP1S signal sent by the GNSS, determine that the currently received PP1S signal is normal if a count value of a PP1S counter corresponding to the currently received PP1S signal is within a second range, and set a flag indicating that the PP1S signal is lost to 0 and a flag indicating that the PP1S signal is online to 1;

[0212] An updating module, configured to update the current locking parameters according to the currently detected PP1S signal after detecting the PP1S signal sent by the GNSS again;

[0213] The output module is used to output a locking PP1S signal according to the updated locking parameters.

[0214] It should be noted here that the above-mentioned pulse signal processing device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned pulse signal processing method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0215] An embodiment of the present application also provides a pulse signal processing device, including a transceiver 710, a processor 700, a memory 720, and a program stored in the memory 720 and executable on the processor 700; wherein, when the processor 700 executes the program, the pulse signal processing method as described above is implemented.

[0216] The transceiver 710 is configured to receive and send data under the control of the processor 700 .

[0217] Among them, Figure 7 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking together various circuits of one or more processors represented by processor 700 and memory represented by memory 720. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are all well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. The transceiver 710 may be a plurality of components, i.e., a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium. The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 when performing operations.

[0218] The present application also provides a readable storage medium having a program stored thereon. When the program is executed by a processor, the pulse signal processing method described above is implemented, and the same technical effects are achieved. To avoid repetition, the description is omitted here. The readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0219] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course, by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for executing the methods described in each embodiment of the present application.

[0220] Therefore, an embodiment of the present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the pulse signal processing method as described above and can achieve the same technical effect. To avoid repetition, they will not be described here.

[0221] In embodiments of the present application, modules can be implemented in software so that they can be executed by various types of processors. For example, an identified executable code module can include one or more physical or logical blocks of computer instructions, for example, which can be constructed as objects, processes, or functions. Nevertheless, the executable code of the identified module does not need to be physically located together, but can include different instructions stored in different locations, which, when logically combined together, constitute the module and achieve the specified purpose of the module.

[0222] In fact, executable code module can be a single instruction or many instructions, and can even be distributed on a plurality of different code segments, distributed in the middle of different programs, and distributed across a plurality of memory devices.Similarly, operating data can be identified in the module, and can be implemented and organized in the data structure of any appropriate type according to any appropriate form.Described operating data can be collected as a single data set, or can be distributed in different locations (including on different storage devices), and can only be present on a system or network as an electronic signal at least in part.

[0223] When a module can be implemented using software, given the current state of hardware technology, those skilled in the art can build corresponding hardware circuits to implement the corresponding functions of the module, regardless of cost. The hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components. Modules may also be implemented using programmable hardware devices, such as field programmable gate arrays, programmable array logic, or programmable logic devices.

[0224] The above exemplary embodiments are described with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this application. Therefore, this application should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this application will be complete and impartial and will convey the scope of this application to those skilled in the art. In the drawings, component sizes and relative sizes may be exaggerated for clarity. The terminology used herein is for purposes of describing specific exemplary embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to encompass such plural forms. It will be further understood that the terms "comprising" and / or "including," when used in this specification, indicate the presence of the stated features, integers, steps, operations, components, and / or elements, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof. Unless otherwise indicated, when stated, a range of values ​​includes the upper and lower limits of that range and any subranges therebetween.

[0225] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A pulse signal processing method, characterized in that: include: After the locking circuit outputs the locking pulse-per-second PP1S signal, periodic anomaly detection is performed on the PP1S signal sent by the global navigation satellite system GNSS; When the detection result is a single abnormality or a lost abnormality, the current circuit state of the locking circuit is locked, and a locking PP1S signal is output based on a locking parameter corresponding to the current circuit state; Alternatively, when the detection result is normal, the locking parameters of the locking circuit are updated according to the PPIS signal sent by the currently detected GNSS, and the locked PPIS signal is output based on the updated locking parameters.

2. The method according to claim 1, characterized in that The method further comprises: Receive PP1S signals sent by the GNSS system; By performing error processing on a plurality of continuously received PPIS signals, the error of PPIS signal jitter and the error of the crystal oscillator clock are eliminated, the locking circuit is locked and the current locking parameters are obtained, wherein the locking parameters include a locking difference and a locking relative difference.

3. The method according to claim 2, characterized in that By using multiple continuously received PP1S signals for error processing, the PP1S signal jitter error and the crystal oscillator clock error are eliminated, the locking circuit is locked, and the current locking parameters are obtained, including: Among the multiple P1S signals received continuously, after receiving each of the first m P1S signals, starting the locking circuit and locking twice continuously according to the count value recorded by the local free counter; wherein m is an integer greater than or equal to 3; After the locking circuit is locked twice consecutively, among a plurality of consecutively received P1S signals, after receiving each of the next n P1S signals, performing error calculation, error tracking, and error elimination based on the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain a current locking parameter; wherein n is an integer greater than or equal to 1; The last PP1S signal among the first m PP1S signals is the first PP1S signal among the next n PP1S signals.

4. The method according to claim 3, characterized in that After receiving each of the first m P1S signals, the locking circuit is activated and locked twice in succession according to the count value recorded by the local free counter, including: After receiving the PP1S signal for the first time, assigning the first count value currently recorded by the local free counter to the error variable; After receiving the PP1S signal for the second time, calculating the absolute value of the first difference between the second count value currently recorded by the local free counter and the current error variable, and when the absolute value of the first difference is less than a first threshold, setting the flag position indicating that the locking circuit is locked to 1, the locking circuit is started and locked once; After receiving the PP1S signal for the third time, the absolute value of the second difference between the third count value currently recorded by the local free counter and the current error variable is calculated. When the absolute value of the second difference is less than the first threshold, it is determined that the locking circuit is locked for the second time.

5. The method according to claim 4, characterized in that After receiving each of the next n PP1S signals, error calculation, error tracking, and error elimination are performed based on the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain the current locking parameters, including: for each of the last n PPIS signals, after receiving the PPIS signal, in a case where it is determined that the locking circuit is in a locked state according to a difference between a count value currently recorded by the local free counter and the error variable, determining a real-time error of the currently received PPIS signal according to a difference between a fourth count value currently recorded by the PPIS counter and a preset maximum count value of the PPIS counter, and updating the error variable according to the real-time error; For non-first PPIS signals among the last n PPIS signals, determining a locking difference in the locking parameter according to the current error variable and a count value currently recorded by the local free counter; For each PPIS signal after the second PPIS signal among the last n PPIS signals, determine the relative difference in the locking parameter according to the difference between the locking difference corresponding to the current PPIS signal and the locking difference corresponding to the previous PPIS signal adjacent to the current PPIS signal.

6. The method according to claim 1, characterized in that Perform periodic anomaly detection on the PP1S signal sent by the Global Navigation Satellite System (GNSS), including: When, at a detection moment corresponding to the periodic anomaly detection, it is detected that a flag indicating a PP1S signal loss is set to 1, the detection result is determined to be a loss anomaly; When it is detected that the locking error corresponding to the PP1S signal is outside the first range, the detection result is determined to be a single abnormality; wherein the locking error is the difference between the value of the error variable corresponding to the currently detected PP1S signal and the value recorded by the local free counter.

7. The method according to claim 1, characterized in that Updating the locking parameters of the locking circuit according to the currently detected PP1S signal sent by the GNSS, and outputting the locked PP1S signal based on the updated locking parameters, including: After receiving the currently detected PPIS signal sent by the GNSS, determining a relative difference corresponding to the currently detected PPIS signal sent by the GNSS; Determine the current maximum count value of the PP1S output counter according to the preset maximum count value of the PP1S counter and the relative difference; When the value recorded by the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output.

8. The method according to claim 1, characterized in that When the detection result is a single abnormality or a lost abnormality, locking the current circuit state of the locking circuit and outputting a locking PP1S signal based on a locking parameter corresponding to the current circuit state include: Acquire the locking parameter before the current anomaly detection, wherein the locking parameter includes a relative difference; Determine the current maximum count value of the PP1S output counter according to the preset maximum count value of the PP1S counter and the currently acquired relative difference; The PPIS output counter is used for counting, and when the count value of the PPIS output counter reaches the current maximum count value of the PPIS output counter, the count value of the PPIS output counter is reset to 1, and the locked PPIS signal is output.

9. The method according to claim 1 or 8, characterized in that In the case where the detection result is a single abnormality or a lost abnormality, before locking the current circuit state of the locking circuit and outputting a locking PPIS signal based on a locking parameter corresponding to the current circuit state, the method further includes: When the detection result is a loss abnormality, the circuit lock state is maintained by switching to a local holding circuit state.

10. The method according to claim 1, characterized in that The method further comprises: After the detection result is a loss anomaly, performing real-time detection on the PPIS signal sent by the GNSS; In the case of detecting a PP1S signal sent by the GNSS, if the count value of the PP1S counter corresponding to the currently received PP1S is within the second range, determining that the currently received PP1S signal is normal, setting a flag indicating that the PP1S signal is lost to 0, and setting a flag indicating that the PP1S signal is online to 1; After detecting the PP1S signal sent by the GNSS again, the current locking parameters are updated according to the currently detected PP1S signal; According to the updated locking parameters, a locking PP1S signal is output.

11. A pulse signal processing device, characterized in that: include: A first detection module is configured to perform periodic anomaly detection on a PP1S signal sent by a global navigation satellite system (GNSS) after the locking circuit outputs the locked pulse per second (PP1S) signal based on error processing; A first processing module is configured to lock the current circuit state of the locking circuit when the detection result is a single abnormality or a lost abnormality, and output a locking PP1S signal based on a locking parameter corresponding to the current circuit state; Alternatively, the second processing module is configured to update the locking parameters of the locking circuit according to the PPIS signal sent by the currently detected GNSS when the detection result is normal, and output the locking PPIS signal based on the updated locking parameters.

12. A pulse signal processing device comprising a transceiver, a processor, a memory, and a program stored in the memory and executable on the processor; characterized in that: When the processor executes the program, the pulse signal processing method according to any one of claims 1 to 10 is implemented.

13. A readable storage medium having a program or instruction stored thereon, characterized in that: When the program or instruction is executed by a processor, the pulse signal processing method according to any one of claims 1 to 10 is implemented.

14. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the pulse signal processing method according to any one of claims 1 to 10.

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