Method for manufacturing circuit board, impedance compensation method, and circuit board

Abstract

This application relates to the field of circuit board manufacturing technology, and discloses a method for manufacturing a circuit board, an impedance compensation method, and a circuit board. The method includes: obtaining an inner layer circuit design diagram of the circuit board; dividing the inner layer circuit design diagram into a preset number of regions; calculating the residual copper ratio of each region; and adjusting the linewidth of the lines in the corresponding regions of the inner layer circuit design diagram based on the deviation between the residual copper ratio of each region and a preset standard residual copper ratio, so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design diagram. This application solves the problem of impedance inconsistency caused by changes in dielectric thickness, making high-speed signal transmission on the circuit board more stable and reliable.

Description

Technical Field

[0001] This application relates to the field of circuit board manufacturing technology, and in particular to a method for manufacturing a circuit board, an impedance compensation method, and a circuit board. Background Technology

[0002] During high-speed signal transmission, if impedance mismatch exists in the transmission path, some signal energy will be reflected at the point of impedance abrupt change, while the remaining energy continues to propagate forward along the transmission line. This impedance discontinuity can induce multiple reflections, leading to waveform distortion at the receiving end. Specifically, this manifests as decreased signal integrity and typical signal integrity defects such as overshoot, undershoot, and ringing, significantly affecting the quality of signal transmission. Summary of the Invention

[0003] In view of this, the embodiments of this application provide a method for manufacturing a circuit board, an impedance compensation method, and a circuit board, which can effectively solve the problem of impedance mismatch in the prior art, thereby affecting the quality of signal transmission.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a circuit board, comprising:

[0005] Obtain the inner layer circuit design diagram of the circuit board;

[0006] The inner circuit design diagram is divided into a predetermined number of regions;

[0007] Calculate the residual copper percentage for each of the aforementioned regions;

[0008] Based on the deviation between the residual copper rate of each region and the preset standard residual copper rate, the line width of the corresponding region of the inner layer circuit design is adjusted so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design.

[0009] In some embodiments, adjusting the linewidth of corresponding areas of the inner layer circuit design based on the deviation between the residual copper rate of each region and a preset standard residual copper rate includes:

[0010] If the residual copper rate in the current region is higher than the standard residual copper rate, the line width of the current region is increased.

[0011] If the residual copper rate in the current region is lower than the standard residual copper rate, the line width of the current region is reduced.

[0012] In some embodiments, the step of widening the line width of the current region if the residual copper rate of the current region is higher than the standard residual copper rate includes:

[0013] When the change in the residual copper rate of the current region relative to the standard residual copper rate increases by a first preset percentage, the line width of the line in the current region is increased positively by a second preset percentage.

[0014] In some embodiments, the step of reducing the line width of the current area if the residual copper rate of the current area is lower than the standard residual copper rate includes:

[0015] When the change in the residual copper rate of the current region relative to the standard residual copper rate decreases by a first preset percentage, the line width of the line in the current region is negatively reduced by a second preset percentage.

[0016] In some embodiments, before adjusting the linewidth of the corresponding area of ​​the inner layer circuit design based on the deviation between the residual copper rate of each region and the preset standard residual copper rate, the impedance compensation method further includes:

[0017] Determine the independent and densely packed lines in the inner layer circuit design diagram;

[0018] The line width of each independent line in the inner layer circuit design diagram is initially adjusted.

[0019] In some embodiments, dividing the inner layer circuit design diagram into a preset number of regions includes:

[0020] Based on the impedance tolerance of the circuit board, the number of regions divided in the inner layer circuit design is determined, and the number of regions increases as the impedance tolerance decreases.

[0021] In some embodiments, determining the number of regions divided in the inner layer circuit design based on the impedance tolerance of the circuit board includes:

[0022] When the impedance tolerance of the circuit board is the first preset tolerance, the inner layer circuit design diagram is divided into regions of the first grid number.

[0023] When the impedance tolerance of the circuit board is the second preset tolerance, the inner layer circuit design is divided into a region of the second grid number, wherein the first preset tolerance is greater than the second preset tolerance, and the first grid number is less than the second grid number.

[0024] In some embodiments, calculating the residual copper rate of each of the regions includes:

[0025] The residual copper rate of each region is calculated using image recognition technology; wherein the residual copper rate is the proportion of the copper foil area of ​​the current region to the total area of ​​the current region.

[0026] Secondly, embodiments of this application provide a circuit board, wherein the inner layer circuit of the circuit board is fabricated using at least one method described in the first aspect above.

[0027] Thirdly, embodiments of this application provide an impedance compensation method for a circuit board, comprising:

[0028] The inner circuit design of the circuit board is divided into a predetermined number of areas;

[0029] Calculate the residual copper percentage for each of the aforementioned regions;

[0030] Based on the deviation between the residual copper rate of each region and the preset standard residual copper rate, the line width of the corresponding region of the inner layer circuit design is adjusted.

[0031] The embodiments of this application have the following beneficial effects:

[0032] The method for manufacturing a circuit board according to this application includes: obtaining an inner layer circuit design diagram of the circuit board; dividing the inner layer circuit design diagram into a preset number of regions; calculating the residual copper rate of each region; and adjusting the linewidth of the lines in the corresponding regions of the inner layer circuit design diagram according to the deviation value between the residual copper rate of each region and the preset standard residual copper rate, so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design diagram. This application, by dividing the inner layer circuit design diagram of the circuit board into regions and adjusting the linewidth of the lines in the corresponding regions according to the residual copper rate of each region, compensates for the impedance difference caused by the change in dielectric thickness, solves the problem of impedance inconsistency caused by the change in dielectric thickness, addresses stricter impedance tolerance requirements, improves impedance control accuracy, and makes high-speed signal transmission more stable and reliable. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A first flowchart illustrating a method for manufacturing a circuit board according to an embodiment of this application is shown.

[0035] Figure 2 This paper shows a schematic diagram of the partitioning of the inner layer circuit design diagram according to an embodiment of this application;

[0036] Figure 3 A second flowchart illustrating the method for manufacturing a circuit board according to an embodiment of this application is shown;

[0037] Figure 4A schematic flowchart of the impedance compensation method for a circuit board according to an embodiment of this application is shown. Detailed Implementation

[0038] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0039] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0040] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0041] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0042] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0043] Considering the impedance mismatch issues in existing technologies that affect signal transmission quality, dielectric thickness is a key parameter among the many factors influencing the characteristic impedance of transmission lines. Changes in the dielectric layer thickness directly affect the trend of its characteristic impedance value. When the actual impedance value deviates from the design target value, an impedance mismatch occurs, leading to the aforementioned signal integrity problems. This application provides a method for manufacturing a circuit board, an impedance compensation method, and a circuit board. This application divides the inner layer circuit design of the circuit board into regions and adjusts the linewidth of the corresponding regions based on the residual copper ratio, compensating for impedance differences caused by dielectric thickness variations. This solves the impedance inconsistency problem caused by dielectric thickness variations, addresses stricter impedance tolerance requirements, improves impedance control accuracy, and makes high-speed signal transmission more stable and reliable.

[0044] The following describes the fabrication method of this circuit board using specific examples.

[0045] Figure 1 A schematic flowchart of a method for manufacturing a circuit board according to an embodiment of this application is shown. Exemplarily, the method includes steps S101-S104:

[0046] S101: Obtain the inner layer circuit design diagram of the circuit board.

[0047] For example, the inner layer circuit design can be in any format, such as a Gerber file or a bitmap. Understandably, the inner layer of the circuit board can be one or more of the following: ground layer, signal layer, power layer, etc. The inner layer circuit design of the circuit board can be made according to the actual application.

[0048] S102: Divide the inner layer circuit design diagram into a preset number of areas.

[0049] The number of regions in the inner layer circuit design can be determined based on the actual application. For example, the number of regions can be determined based on the impedance tolerance of the circuit board. Generally, the number of regions increases as the impedance tolerance of the circuit board decreases. It is understood that impedance is a key parameter in high-speed signal transmission; the smaller the impedance tolerance of the circuit board, the higher the requirement for circuit uniformity. To achieve higher precision control, more detailed analysis and compensation of the inner layer circuit are needed.

[0050] Multilayer board lamination of circuit boards involves cutting resin-coated polypropylene (PP) sheets and placing them between inner core boards or between core boards and copper foil. The PP sheets are then subjected to high temperature and pressure to melt the resin and fill the copper-free areas of the core boards. After cooling, the resin solidifies, bonding the core boards and copper foil together. The PP sheets flow in a liquid state under high temperature and pressure, filling the gaps between the boards. When the inner layer copper layer is small, PP sheets of the same thickness are evenly distributed in the gaps between layers, resulting in more resin filling. This leads to a thinner overall thickness of the PP sheets after cooling and solidification. The greater the difference in residual copper content between different areas, the more significant the change in dielectric thickness, resulting in impedance differences between different areas.

[0051] Since the dielectric thickness is uncontrollable, it is necessary to adjust the line width to offset the impact of this uneven dielectric thickness on impedance. The design is divided into several regions, and the residual copper rate of each region is calculated independently and the line width is compensated. The more regions there are, the more subtle changes in the residual copper rate can be captured, thereby allowing for more precise adjustment of the line width and achieving a more uniform impedance distribution to meet the impedance standards required by the circuit board.

[0052] Exemplary, when the impedance tolerance of the circuit board is a first preset tolerance, the inner layer circuit design is divided into regions of a first grid number; when the impedance tolerance of the circuit board is a second preset tolerance, the inner layer circuit design is divided into regions of a second grid number. It is understood that the first preset tolerance is greater than the second preset tolerance, and the first grid number is less than the second grid number. For example, when the impedance tolerance of the circuit board is ±7%, the inner layer circuit design is divided into 3×3 grid regions; when the impedance tolerance of the circuit board is ±5%, the inner layer circuit design is divided into 4×4 grid regions. It is understood that the number and method of dividing the inner layer circuit design are not limited; it can be divided only along the width direction of the design, or along the length direction of the design, or along both the width and length directions of the design. Figure 2 As shown, the design drawing can be divided into a 3×4 grid area.

[0053] S103: Calculate the residual copper rate for each region.

[0054] Understandably, the residual copper rate of a region is the proportion of the actual copper foil area within that region to the total area of ​​that region. Exemplarily, image recognition technology can be used to calculate the residual copper rate of each region. Specifically, an image of the inner layer circuit design is acquired, and the acquired image is processed with noise reduction and grayscale conversion to improve recognition accuracy. Then, based on the impedance tolerance of the circuit board, the entire image is divided into various regions. The number of pixels representing copper foil in each region and the total number of pixels are counted, and the proportion of copper foil pixels to the total number of pixels in that region is calculated to obtain the residual copper rate of that region.

[0055] It is understandable that using image recognition technology greatly improves the efficiency and accuracy of residual copper ratio calculation. More accurate residual copper ratio calculation leads to more reasonable linewidth compensation, thereby improving overall impedance consistency. Furthermore, this method is adaptable to design drawings of different resolutions and formats, and supports multiple area division methods.

[0056] S104: Based on the deviation between the residual copper rate of each region and the preset standard residual copper rate, adjust the line width of the corresponding region of the inner layer circuit design to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design.

[0057] The standard residual copper rate can be set according to actual application conditions, for example, a standard residual copper rate of 50%. As an example, the residual copper rate of each area is compared with the standard residual copper rate. If the residual copper rate of the current area is equal to the preset standard residual copper rate, the original line width of the current area is maintained; if the residual copper rate of the current area is higher than the standard residual copper rate, the line width of the current area is increased; if the residual copper rate of the current area is lower than the standard residual copper rate, the line width of the current area is reduced.

[0058] Regarding the degree of increase or decrease in linewidth, in one embodiment, it can be set that when the residual copper rate is higher than the standard residual copper rate, the linewidth is increased to a preset proportion of the original linewidth, for example, the linewidth is increased to 100.5% of the original linewidth; alternatively, it can be set that when the residual copper rate is higher than the standard residual copper rate, the linewidth is increased by a preset value, for example, the linewidth is increased by 5μm. Similarly, the degree of linewidth reduction can also be expressed by a preset proportion or a preset value.

[0059] In another implementation, for cases requiring an increase, the linewidth can be adjusted in stages based on the difference between the residual copper rate in the region and the standard residual copper rate. For example, when the change in the residual copper rate of the current region relative to the standard residual copper rate increases by a first preset percentage, the linewidth of the lines in the current region increases positively by a second preset percentage; for example, if the residual copper rate of the current region is compared to the standard residual copper rate of 50%, for every 5% increase, the linewidth increases by 0.8%, etc. Similarly, for cases requiring a decrease, for example, when the change in the residual copper rate of the current region relative to the standard residual copper rate decreases by a first preset percentage, the linewidth of the lines in the current region decreases negatively by a second preset percentage; for example, for every 5% decrease, the linewidth decreases by 0.8%, etc. The above values ​​are merely feasible examples and are not intended to be the only limitation.

[0060] It is understandable that segmented compensation coefficients are set according to the degree of deviation between the residual copper rate and the standard value, so that the line width compensation is more precise and can more accurately match the actual impedance requirements, thereby improving the impedance consistency of the overall line.

[0061] This embodiment employs a region division approach combined with residual copper ratio calculation and linewidth compensation strategies to achieve dual optimization at both the local and overall levels. Introducing the residual copper ratio as a key parameter makes compensation more targeted. The linewidth compensation mechanism effectively offsets impedance variations caused by dielectric thickness fluctuations, ensuring impedance uniformity across different regions and meeting high-precision impedance control requirements. Improved impedance uniformity reduces signal reflections and ringing during transmission, thereby enhancing signal integrity and transmission quality.

[0062] In one embodiment, Figure 3 This paper illustrates another flowchart of a method for manufacturing a circuit board according to an embodiment of this application. Based on the above embodiment, before step S104, the compensation method further includes:

[0063] S201: Determine the independent lines and dense lines in the inner layer circuit design diagram.

[0064] Understandably, isolated traces are those with ample space and no other closely spaced traces. During etching, the copper foil is subject to severe side etching, resulting in significant linewidth loss. Examples include isolated traces in the power layer and single signal lines far from other traces. Dense traces, on the other hand, are those with very small spacing and high density. They are etched at a lower rate, resulting in less linewidth loss.

[0065] Line spacing thresholds can be set according to actual application conditions. For example, it can be used to determine whether there are other lines within 5 mm around the current line; if so, it is considered a dense line, and if not, it is considered an independent line. Graphing software can be used to perform image recognition and analysis on the inner layer line design to classify the inner layer lines into independent lines and dense lines.

[0066] S202: Make preliminary adjustments to the line width of each independent line in the inner layer circuit design diagram.

[0067] During PCB manufacturing, independent traces, lacking surrounding support structures, are prone to over-etching during etching, resulting in narrower linewidths. Conversely, densely packed traces, with their tightly distributed copper foil, experience limited etching solution diffusion, slower etching speeds, and better linewidth retention. This linewidth inconsistency directly leads to impedance fluctuations. Therefore, it is necessary to compensate for the linewidth of each independent trace in the inner layer circuit design to offset etching losses.

[0068] The compensation value can be set according to the actual application, the etching process parameters, or the copper thickness of each independent line, to compensate for the line width of the corresponding independent line in the inner layer circuit design.

[0069] In this embodiment, not only the residual copper ratio is considered, but also the difference between independent lines and dense lines. Initial line width compensation is performed on independent lines, unifying the line width benchmark for different line types, making subsequent compensation based on residual copper ratio more consistent. Moreover, the step-by-step compensation mechanism can more effectively deal with the influence of multiple variables on impedance, so that the characteristic impedance of different regions tends to be consistent, thereby meeting the higher standard impedance control requirements.

[0070] In one embodiment, based on the above embodiments, after preparing the inner layer circuitry of the circuit board using the adjusted inner layer circuitry design, the impedance value of the circuit board with prepared inner layer circuitry can be measured using an impedance measuring device to verify the consistency of the impedance. Furthermore, the line width can also be adjusted based on the measured impedance value. Exemplarily, after preparing the inner layer circuitry of the circuit board using the adjusted inner layer circuitry design, the compensation method further includes:

[0071] The circuit board with the prepared inner layer circuitry is connected to the test fixture of the impedance measurement device. A step signal is sent using the time-domain reflectometry method, and the time difference and amplitude of the reflected wave are measured to calculate the impedance value. The impedance value is compared with the target impedance value to determine whether it meets the tolerance requirements. If it does not meet the requirements, the linewidth of the inner layer circuitry on the circuit board is adjusted according to the impedance value.

[0072] In this embodiment, by actually measuring the impedance value of the processed circuit board, the effectiveness of the linewidth compensation calculated based on the residual copper ratio can be evaluated. The linewidth on the circuit board is adjusted according to the impedance value to meet the requirements of higher precision impedance control; and the test results can serve as the basis for parameter adjustments during the design and manufacturing process of subsequent batches of products, forming a closed-loop control.

[0073] This application also provides a circuit board, exemplary of which the inner layer circuitry is fabricated using the method described above.

[0074] This application also provides an impedance compensation method for a circuit board. Figure 4 A schematic flowchart of an impedance compensation method for a circuit board according to an embodiment of this application is shown. Exemplarily, the impedance compensation method includes:

[0075] S301: Divide the inner layer circuit design of the circuit board into a preset number of areas;

[0076] S302: Calculate the residual copper rate for each region;

[0077] S303: Adjust the line width of the corresponding area of ​​the inner layer circuit design based on the deviation between the residual copper rate of each area and the preset standard residual copper rate.

[0078] It is understood that the steps in this embodiment have been explained in detail in the above embodiments, and will not be repeated here.

[0079] Exemplarily, the above preparation process includes: providing a core board, copper plating the core board, applying a photosensitive dry film to the copper surface of the copper-plated core board, and ensuring no air bubbles are present through hot pressing. Using ultraviolet light, the circuit pattern is transferred to the dry film through a photoplotting film generated from the adjusted inner layer circuit design, dissolving the unexposed areas; the dry film in the unexposed areas is removed with an alkaline solution, exposing the copper surface to be etched; the exposed copper is dissolved with an acidic etching solution to form the circuit pattern; the remaining dry film is removed to form a circuit board with prepared inner layer circuitry. Outer layer circuitry can be prepared on the circuit board with prepared inner layer circuitry according to the actual application.

[0080] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0081] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0082] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for manufacturing a circuit board, characterized in that, include: Obtain the inner layer circuit design diagram of the circuit board; The inner circuit design diagram is divided into a predetermined number of regions; Calculate the residual copper percentage for each of the aforementioned regions; Determine the independent and densely packed lines in the inner layer circuit design diagram; The linewidth of each independent line in the inner layer circuit design is compensated, and the compensation value is set according to the etching process parameters or the copper thickness of each independent line. Based on the deviation between the residual copper rate of each region and the preset standard residual copper rate, the line width of the corresponding region of the inner layer circuit design is adjusted so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design. The step of dividing the inner layer circuit design diagram into a preset number of regions includes: Based on the impedance tolerance of the circuit board, the number of regions divided in the inner layer circuit design is determined, and the number of regions increases as the impedance tolerance decreases.

2. The method for manufacturing a circuit board according to claim 1, characterized in that, The step of adjusting the linewidth of the corresponding area of ​​the inner layer circuit design based on the deviation between the residual copper rate of each area and the preset standard residual copper rate includes: If the residual copper rate in the current region is higher than the standard residual copper rate, the line width of the current region is increased. If the residual copper rate in the current region is lower than the standard residual copper rate, the line width of the current region is reduced.

3. The method for manufacturing a circuit board according to claim 2, characterized in that, If the residual copper rate in the current region is higher than the standard residual copper rate, the process of widening the line width in the current region includes: When the change in the residual copper rate of the current region relative to the standard residual copper rate increases by a first preset percentage, the line width of the line in the current region is increased positively by a second preset percentage.

4. The method for manufacturing a circuit board according to claim 2, characterized in that, If the residual copper rate in the current region is lower than the standard residual copper rate, the process of reducing the line width of the current region includes: When the change in the residual copper rate of the current region relative to the standard residual copper rate decreases by a first preset percentage, the line width of the line in the current region is negatively reduced by a second preset percentage.

5. The method for manufacturing a circuit board according to claim 1, characterized in that, The determination of the number of regions in the inner layer circuit design based on the impedance tolerance of the circuit board includes: When the impedance tolerance of the circuit board is the first preset tolerance, the inner layer circuit design diagram is divided into regions of the first grid number. When the impedance tolerance of the circuit board is the second preset tolerance, the inner layer circuit design is divided into a region of the second grid number, wherein the first preset tolerance is greater than the second preset tolerance, and the first grid number is less than the second grid number.

6. The method for manufacturing a circuit board according to claim 1, characterized in that, The calculation of the residual copper rate for each of the aforementioned regions includes: The residual copper rate of each region is calculated using image recognition technology; wherein the residual copper rate is the proportion of the copper foil area of ​​the current region to the total area of ​​the current region.

7. A circuit board, characterized in that, The circuit board is fabricated using the method described in any one of claims 1-6 to obtain the inner layer circuitry of the circuit board.

8. An impedance compensation method for a circuit board, characterized in that, include: The inner circuit design of the circuit board is divided into a predetermined number of areas; Calculate the residual copper percentage for each of the aforementioned regions; Determine the independent and densely packed lines in the inner layer circuit design diagram; The linewidth of each independent line in the inner layer circuit design is compensated, and the compensation value is set according to the etching process parameters or the copper thickness of each independent line. Based on the deviation between the residual copper rate of each region and the preset standard residual copper rate, the line width of the corresponding region of the inner layer circuit design is adjusted. The step of dividing the inner layer circuit design diagram into a preset number of regions includes: Based on the impedance tolerance of the circuit board, the number of regions divided in the inner layer circuit design is determined, and the number of regions increases as the impedance tolerance decreases.

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