Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device includes a substrate, a multilayer memory cell array disposed on the substrate, and a plurality of stacked gate transistors disposed on the substrate; each layer of storage unit array comprises a plurality of bit lines, each bit line is connected with a plurality of storage units, and the gate tubes are connected with the bit lines and used for gating the bit lines; the gate tube comprises a first semiconductor layer, and the first semiconductor layer is connected with the storage unit through a bit line; the material of the first semiconductor layer comprises monocrystalline silicon. The reliability of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] The present application provides a semiconductor device, a manufacturing method thereof, and an electronic device.

[0005] In some embodiments, the present application provides a method for manufacturing a semiconductor device, comprising:

[0006] forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of first sacrificial layers that are periodically and alternately stacked;

[0007] Patterning the stacked structure to form a multi-layer stacked memory cell array and a multi-layer stacked gate transistor; the memory cell array includes a bit line, and the gate transistor is connected to the bit line;

[0008] Forming a multi-layer stacked gate transistor includes: forming a through hole penetrating the stacked structure, forming a first semiconductor layer in the through hole, wherein the material of the first semiconductor layer includes single crystal silicon;

[0009] A first gate insulating layer and a first gate electrode covering the first semiconductor layer are sequentially formed in the through hole.

[0010] In some embodiments, forming a first semiconductor layer in the through hole includes:

[0011] forming an initial through hole penetrating the stacked structure;

[0012] Carving back the first sacrificial layer exposed by the initial through hole to form a first groove surrounding the initial through hole and communicating with the initial through hole, wherein the through hole includes the initial through hole and the first groove;

[0013] The initial semiconductor layer filling the initial through hole and the first groove is formed, and the initial semiconductor layer is patterned to retain only the initial semiconductor layer in the first groove as the first semiconductor layer, and the first semiconductor layers in any adjacent first grooves are disconnected from each other.

[0014] In some embodiments, forming the initial semiconductor layer filling the initial through hole and the first groove includes:

[0015] The substrate comprises a single crystal silicon substrate;

[0016] Exposing the single crystal silicon substrate when forming an initial through hole penetrating the stacked structure;

[0017] An initial semiconductor layer filling the initial through hole and the first groove is formed on the single crystal silicon substrate by an epitaxial growth process.

[0018] In some embodiments, forming a bit line in a multi-layer stacked memory cell array includes:

[0019] forming a first groove penetrating the stacked structure;

[0020] removing the first sacrificial layer in the first trench by wet etching to form a first accommodation space between adjacent first dielectric layers;

[0021] A conductive layer is formed in the first receiving space, wherein the conductive layer includes the bit line.

[0022] In some embodiments, when forming the through hole corresponding to the gate transistor, a through hole corresponding to the memory unit penetrating the stacked structure is simultaneously formed;

[0023] Depositing a second semiconductor layer, a second gate insulating layer, and a second gate electrode in sequence in the through hole corresponding to the memory cell;

[0024] The second semiconductor layer is a metal oxide semiconductor layer.

[0025] In some embodiments, the present application provides a semiconductor device comprising: a substrate, a multi-layer memory cell array disposed on the substrate, and a plurality of stacked gate transistors disposed on the substrate;

[0026] Each layer of the memory cell array includes a plurality of bit lines, and each of the bit lines is connected to a plurality of memory cells and one of the gate transistors;

[0027] The gate transistor includes a first semiconductor layer, which is connected to the memory cell via the bit line; a material of the first semiconductor layer includes single crystal silicon.

[0028] In some embodiments, the selection transistor further includes a first gate electrode and a first gate insulation layer, the first gate electrode extends along a first direction perpendicular to the substrate, the first gate insulation layer is arranged around the first gate electrode; the first semiconductor layer is arranged around the first gate insulation layer.

[0029] In some embodiments, each first semiconductor layer of each selection transistor is located in a through hole, the first semiconductor layer is located on the side wall of the through hole, the first gate insulation layer is located in the through hole, and the first gate electrode of each selection transistor is connected and extends in a direction perpendicular to the substrate.

[0030] In some embodiments, a plurality of common bit lines are stacked in sequence along a first direction perpendicular to the substrate, each of the common bit lines is connected to the bit line via the first semiconductor layer arranged in the same layer; the common bit lines are perpendicular to the extension direction of the bit lines.

[0031] In some embodiments, in a direction perpendicular to the extension of the bit line, a maximum distance of an outer profile of the first semiconductor layer is less than or equal to a width of the bit line.

[0032] In some embodiments, the substrate comprises a single crystal silicon substrate.

[0033] In some embodiments, the present application provides an electronic device, including: a semiconductor device provided by any of the above embodiments.

[0034] The embodiments of the present application can improve the stability and reliability of semiconductor devices.

[0035] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0037] Figure 1 A top view of a semiconductor device provided in an embodiment of the present application;

[0038] Figure 2 For the Figure 1 A schematic cross-sectional structure diagram perpendicular to the substrate in the second direction AA;

[0039] Figure 3 For the Figure 1 Schematic diagram of the cross-sectional structure perpendicular to the substrate in the third direction BB;

[0040] Figure 4A schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0041] Figure 5 A schematic flow chart of the sub-steps of forming an initial semiconductor layer embedded in a stacked structure and a mask layer;

[0042] Figures 6 to 36 This is a schematic diagram of the intermediate structures obtained in each step of the flow diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0043] Description of reference numerals:

[0044] 11-substrate;

[0045] 12-gating tube;

[0046] 121 - first semiconductor layer; 122 - first gate electrode; 123 - first gate insulating layer;

[0047] 13-bit line;

[0048] 20 - first transistor; 201 - second gate electrode; 202 - second gate insulating layer; 203 - second semiconductor layer; 204 - first source / drain; 205 - second source / drain;

[0049] 21-Capacitor;

[0050] 14-common bit line;

[0051] 15 - first dielectric layer; 16 - first sacrificial layer; 17 - mask layer; 120 - initial semiconductor layer; 124 - sacrificial pillar; 30 - initial through hole; 40 - first groove; 50 - first trench; 60 - first accommodation space; 18 - conductive layer; 19 - second dielectric layer; 70 - word line hole. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present application in conjunction with the accompanying drawings. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0053] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application refers to the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may refer to the element and the other element establishing a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0054] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0055] The present invention provides a method for manufacturing a semiconductor device. The flowchart of the method is shown in FIG. Figure 4 As shown, the method includes steps S101 to S104.

[0056] S101: If Figure 6 As shown, a stacked structure is formed on a substrate 11 , and the stacked structure includes multiple first dielectric layers 15 and multiple first sacrificial layers 16 that are periodically and alternately stacked.

[0057] Optionally, in some embodiments, the method may further include forming a mask layer 17 on top of the stacked structure.

[0058] Among them, the substrate 11 is a single crystal silicon substrate, or the substrate includes a single crystal silicon material, or the substrate includes a single crystal silicon film layer; the material of the first dielectric layer 15 and / or the mask layer 17 can be silicon dioxide, and the material of the first sacrificial layer 16 can be silicon nitride, silicon nitride, etc.

[0059] Optionally, in some embodiments, the thickness of the mask layer 17 may be greater than the thickness of the first dielectric layer 15. Since the thickness of the mask layer 17 is increased, the film layer below the mask layer 17 can be protected from being damaged during various etching processes.

[0060] Figure 6 It is a schematic diagram of a cross-sectional structure perpendicular to the substrate after a stacked structure and a mask layer 17 are sequentially formed on the substrate 11.

[0061] S102: Figure 1As shown, the stacked structure is patterned to form a plurality of memory cells and a plurality of bit lines 13 distributed in an array on the stacked structure, as well as a gate tube 12 for selecting each bit line 13. The gate tubes 12 corresponding to the bit lines 13 stacked in different layers are stacked and formed in the same through hole.

[0062] The gate tube is also called a gate transistor.

[0063] The stacking of the plurality of gate tubes may include: forming a Figure 14 The initial semiconductor layer 120 shown penetrates the stacked structure and the mask layer 17. The initial semiconductor layer 120 includes a sacrificial column 124 that penetrates the mask layer 17 and the stacked structure, and a first semiconductor layer 121 that surrounds the sacrificial column 124 and is arranged in the same layer as the first sacrificial layer 16. The material of the initial semiconductor layer 120 includes single crystal silicon.

[0064] The initial semiconductor layer 120 is an integrated structure, which can be understood as the sacrificial pillars 124 and the first semiconductor layer 121 being different regions of an independent semiconductor structure.

[0065] See also Figure 5 , forming an initial semiconductor layer 120 that penetrates the stacked structure and the mask layer 17, including the following sub-steps S21 to S23:

[0066] S21: Formation Figures 7 to 9 An initial through hole 30 passes through the mask layer 17 and the stacked structure.

[0067] S22 : etching back the first sacrificial layer 16 to expose the inner sidewall of the initial through hole 30 , to form a first groove 40 surrounding the initial through hole 30 and communicating with the initial through hole 30 .

[0068] Specifically, in some embodiments, a corrosive liquid can be introduced into the initial through hole 30 by wet etching, thereby selectively etching the first sacrificial layer 16 at the inner wall of the initial through hole 30, expanding the aperture of the first sacrificial layer 16, and reserving space for the subsequent formation of independent first semiconductor layers 121 retained after removing the sacrificial column 124.

[0069] By enlarging the aperture of the initial through hole 30 in the first sacrificial layer 16 and subsequently removing the single crystal silicon outside the first groove by etching, the parasitic transistor of the gate tube 12 can be removed, the noise of the semiconductor device can be reduced, the signal-to-noise ratio of the semiconductor device can be improved, and the reliability and stability of the semiconductor device can be improved.

[0070] S23: Formation Figure 14 The initial semiconductor layer 120 fills the initial through hole 30 and the first groove 40 , the sacrificial pillar 124 is located in the initial through hole 30 , and the first semiconductor layer 121 is located in the first groove 40 .

[0071] Optionally, the above step S23 may include: the substrate 11 is a single crystal silicon substrate, or the substrate contains single crystal silicon material, or the substrate contains a single crystal silicon film layer; based on the substrate 11 containing single crystal silicon exposed at the initial through hole 30, single crystal silicon is epitaxially grown in the initial through hole 30 and the first groove 40 to obtain an initial semiconductor layer 120.

[0072] The process of forming a plurality of memory cells and a plurality of bit lines 13 distributed in an array on the stacked structure may include the following sub-steps S31 to S34:

[0073] S31 : forming a first trench 50 penetrating the mask layer 17 and the stacked structure.

[0074] Figure 16 A top view of the first trench 50 formed through the mask layer 17 and the stacked structure with its trailing edge parallel to the substrate 11; Figure 17 A schematic cross-sectional structure diagram of the substrate 11 along the second direction AA after forming the first trench 50 penetrating the mask layer 17 and the stacked structure; Figure 18 It is a schematic diagram of a cross-sectional structure perpendicular to the substrate 11 along the third direction BB after forming the first trench 50 penetrating the mask layer 17 and the stacked structure.

[0075] Optionally, in some embodiments, there are multiple first trenches 50 , and the first trenches 50 extend perpendicular to the extending direction of the bit lines 13 (extend along the third direction BB), thereby etching out the AA region (memory cell region).

[0076] It should be noted that the distance between two adjacent first trenches 50 along the third direction BB is equal to the width of the bit line 13 formed in subsequent steps.

[0077] Optionally, in some embodiments, the width of the bit line 13 in the third direction BB is greater than or equal to the maximum aperture of the through-hole in step S22. In other words, in the third direction BB, the maximum distance of the outer contour of the first semiconductor layer 121 is less than or equal to the width of the bit line 13. This configuration can avoid damage to the first semiconductor layer 121 during the etching process to form the bit line 13, ensuring that the width of the first semiconductor layer 121 meets design requirements.

[0078] S32 : removing the first sacrificial layer 16 in the first trenches 50 by wet etching, so that first accommodation spaces 60 communicating with the first trenches 50 are formed in the initial memory cell array.

[0079] Figure 19 A top view parallel to the substrate 11 after the first sacrificial layer 16 is removed through the first trench 50 ; Figure 20is a schematic diagram of a cross-sectional structure perpendicular to the substrate 11 along the second direction AA after the first sacrificial layer 16 is removed through the first trench 50; Figure 21 1 is a schematic diagram of a cross-sectional structure perpendicular to the substrate 11 along the third direction BB after the first sacrificial layer 16 is removed through the first trench 50 .

[0080] Specifically, in some embodiments, all first sacrificial layers 16 can be completely removed by wet selective etching to form first accommodation spaces 60. The first accommodation spaces 60 are spaces between adjacent first dielectric layers.

[0081] S33 : forming a conductive layer 18 in the first receiving space 60 , wherein the conductive layer 18 includes the bit lines 13 in the memory cell array.

[0082] Figure 22 A top view of the conductive layer 18 formed in the first accommodation space 60 parallel to the substrate 11; Figure 23 1 is a schematic diagram of a cross-sectional structure perpendicular to the substrate 11 along the second direction AA after the conductive layer 18 is formed in the first accommodation space 60; Figure 24 It is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the third direction BB after the conductive layer 18 is formed in the first accommodation space 60 .

[0083] In some embodiments, the above step S33 may include: depositing a metal material on the first structure obtained after removing the first sacrificial layer 16 through the first trench 50, and removing the metal material on the surface, sidewall and inside of the first trench 50 of the first structure to replace the conductive layer 18. Figures 16 to 18 The first sacrificial layer 16 in the embodiment of the present invention.

[0084] Optionally, in some embodiments, after step S33 and before step S34, the step may further include removing portions of the conductive layer 18 located on both sides of the initial semiconductor layer 120 in a direction perpendicular to the extension of the bit line 13. This may be understood as removing portions of the conductive layer 18 on both sides of the region surrounding the first semiconductor layer 121 in a direction perpendicular to the extension of the bit line 13.

[0085] Figure 25 A top view parallel to the substrate 11 is shown after removing portions of the conductive layer 18 located on both sides of the initial semiconductor layer 120 in a direction perpendicular to the extending direction of the bit line 13; Figure 26 A schematic cross-sectional structure diagram perpendicular to the substrate 11 along the second direction AA after removing portions of the conductive layer 18 located on both sides of the initial semiconductor layer 120 in the extending direction perpendicular to the bit line 13; Figure 27 It is a schematic cross-sectional structure diagram perpendicular to the substrate 11 along the third direction BB after removing portions of the conductive layer 18 located on both sides of the initial semiconductor layer 120 in the extending direction perpendicular to the bit line 13 .

[0086] Specifically, in some embodiments, only the conductive layer 18 can be etched by wet selective etching to remove the conductive layer 18 on both sides of the initial semiconductor layer 120 along the third direction BB, thereby avoiding short circuit of the conductive layer 18 on both sides of the initial semiconductor layer 120 along the third direction BB.

[0087] S34: forming memory cells connected to the bit lines 13 to obtain a multi-layer memory cell array.

[0088] In some embodiments, each memory cell may include a first transistor and a capacitor connected to each other, and the first transistor and the capacitor are arranged along the second direction AA.

[0089] Optionally, in some embodiments, the above step S34 includes: forming a first transistor and a capacitor to obtain an intermediate structure; filling a second dielectric layer 19 in the gap of the intermediate structure, and performing a planarization process.

[0090] It is understood that the above step S34 may also include: filling the gaps of the structure obtained after step S33 with the second dielectric layer 19 and performing a planarization process. The step of forming the first transistor and capacitor is located after step S105 or at other locations, which is not limited here.

[0091] Figure 28 A top view parallel to the substrate 11 after filling the second dielectric layer 19 and performing a planarization process; Figure 29 A schematic cross-sectional structure diagram of the substrate 11 along the second direction AA after the second dielectric layer 19 is filled and planarized; Figure 30 It is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the third direction BB after the second dielectric layer 19 is filled and planarized.

[0092] S103: If Figures 31-32 , the sacrificial pillars 124 in the initial semiconductor layer 120 are removed to obtain the word line holes 70 .

[0093] Figure 31 To remove the portion of the sacrificial pillar 124 in the initial semiconductor layer 120 , a top view of the wordline hole 70 with its rear edge parallel to the substrate 11 is obtained; Figure 32 A schematic cross-sectional structure diagram perpendicular to the substrate 11 along the second direction AA after removing the sacrificial pillar 124 portion in the initial semiconductor layer 120 to obtain the word line hole 70; Figure 33 A schematic cross-sectional structure diagram of the word line hole 70 is obtained after removing the sacrificial pillar 124 in the initial semiconductor layer 120 and perpendicular to the substrate 11 along the third direction BB.

[0094] Optionally, in some embodiments, in a plane parallel to the substrate 11 , the size of the word line hole 70 is greater than or equal to the size of the sacrificial pillar 124 , so that the remaining first semiconductor layers 121 in the initial semiconductor layer 120 are separated from each other.

[0095] In this embodiment, in a plane parallel to the substrate 11 , the size of the wordline hole 70 is equal to the size of the sacrificial pillar 124 . In other words, the single crystal silicon in the initial through hole 30 is etched away, leaving only the single crystal silicon in the first groove 40 .

[0096] The hole including the initial through hole 30 and the first groove 40 is a through hole.

[0097] Optionally, in some embodiments, when forming a through hole corresponding to the selection transistor, a through hole corresponding to the storage unit of the through-stacked structure can be formed at the same time; the second semiconductor layer 203, the second gate insulation layer 202 and the second gate electrode 201 are sequentially deposited in the through hole corresponding to the storage unit; the second semiconductor layer 203 is a metal oxide semiconductor layer.

[0098] S104 : a first gate insulating layer 123 and a first gate electrode 122 are sequentially formed in the word line hole 70 .

[0099] Figure 34 A top view of the rear edge of the first gate insulating layer 123 and the first gate electrode 122 being formed in sequence along the word line hole 70 and parallel to the substrate 11; Figure 35 It is a schematic cross-sectional structure diagram perpendicular to the substrate 11 along the second direction AA after the first gate insulating layer 123 and the first gate electrode 122 are sequentially manufactured along the word line hole 70; Figure 36 It is a schematic cross-sectional structure diagram perpendicular to the substrate 11 along the third direction BB after the first gate insulating layer 123 and the first gate electrode 122 are sequentially manufactured along the word line hole 70 .

[0100] The material of the first gate insulating layer 123 may be a high-K material, and the material of the first gate electrode 122 may be polysilicon.

[0101] The beneficial technical effects brought about by the technical solution provided in the embodiment of the present application include: selecting single crystal silicon with higher mobility and better material stability as the channel material of the gate tube 12, thereby increasing the on-state current of the gate tube 12 and improving the stability and reliability of the transistor.

[0102] In some embodiments, the multi-layer memory cell array of the present application is periodically stacked, and each memory cell is stacked with multiple memory cells in the vertical direction. These memory cells are all formed in a hole, in which different layers of semiconductor layers are formed, as well as an integrated gate insulating layer and word line, and the gate is part of the word line. These semiconductor layers can be metal oxide semiconductor layers, which have lower leakage current. The semiconductor layer of the gate tube is single crystal silicon, and the on-state current is higher, which meets the stability and reliability requirements of the gate tube device. In 3D stacked semiconductor devices, these two types of transistors use different materials, which can meet the overall requirements of the device and improve the reliability of the entire semiconductor device.

[0103] Based on the same inventive concept, the embodiment of the present application provides a semiconductor device. The structural diagram of the semiconductor device is as follows: Figures 1 to 3 As shown, it includes: a substrate 11, a multi-layer memory cell array arranged on the substrate 11, and a gate tube 12 stacked on the substrate.

[0104] Each layer of the memory cell array includes a plurality of bit lines 13 extending along a column direction and a plurality of memory cells connected to each bit line 13 .

[0105] A plurality of bit lines 13 directly connected to the memory cells are connected to the same common bit line 14 via the gate transistors 12. Each gate transistor 12 is used to gate the common bit line 14 with one of the bit lines 13 to which it is connected.

[0106] The gate tube 12 described in the embodiment of the present application is a gate transistor.

[0107] The gate tube 12 includes a first semiconductor layer 121 , which is connected to the memory cell via the bit line 13 ; the material of the first semiconductor layer 121 includes single crystal silicon.

[0108] In the embodiment of the present application, single crystal silicon with higher mobility and better material stability is selected as the channel material of the gate tube 12, thereby increasing the on-state current of the gate tube 12 and improving the stability and reliability of the semiconductor device.

[0109] It should be noted that in order to Figure 1 More clear and easier for readers to read and understand, Figure 1 The substrate 11 and the dielectric layers are not shown (or are shown in a transparent graphic form) in the top view. Figure 2 and Figure 3 The dielectric layers are not shown (or are shown as transparent graphics).

[0110] See also Figures 1 to 3Optionally, in some embodiments, the gate tube 12 may further include a first gate electrode 122 and a first gate insulating layer 123, the first gate electrode 122 extends along a first direction perpendicular to the substrate 11, and the first gate insulating layer 123 is arranged around the periphery and bottom of the first gate electrode 122; the first semiconductor layer 121 is arranged around the periphery of the first gate insulating layer 123.

[0111] See also Figures 1 to 3 Optionally, in some embodiments, the multi-layer memory cell array includes a plurality of bit lines 13 stacked in a direction perpendicular to the substrate 11 , and a plurality of gate tubes 12 stacked in a direction perpendicular to the substrate 11 corresponding one-to-one to the plurality of bit lines 13 .

[0112] Each first semiconductor layer 121 of each gate tube 12 is located in the through hole, the first semiconductor layer 121 is located on the side wall of the through hole, the first gate insulating layer 123 is located in the through hole, the first gate electrode 122 of each gate tube 12 is connected and extends in a direction perpendicular to the substrate 11, and each first semiconductor layer 121 surrounds the side wall of the corresponding first gate electrode 122 and is insulated from the first gate electrode 122 by the first gate insulating layer 123.

[0113] For example, see Figures 1 to 3 , the number of gate tubes 12 is three, and the number of memory cell arrays is three layers. It should be noted that, Figure 1 The number of the gate tubes 12 and the number of the memory cell arrays are only examples and can be set as needed in actual applications. Usually, the number of the gate tubes 12 is the same as the number of the memory cell arrays, and each gate tube 12 transmits a control signal to the bit line 13 of a layer of the memory cell array.

[0114] Optionally, in some embodiments, the semiconductor device further includes a common bit line 14 arranged parallel to the substrate 11 ; in a plane parallel to the substrate 11 , the gate tube 12 is located between the memory cell array and the common bit line 14 .

[0115] See also Figures 1 to 3 Optionally, in some embodiments, the semiconductor device may further include a plurality of common bit lines 14 stacked in sequence along a first direction perpendicular to the substrate 11 and insulated from each other, each common bit line 14 being connected to each bit line 13 of the corresponding layer memory cell array via the first semiconductor layer 121 of the corresponding layer; the common bit lines 14 are perpendicular to the extension direction of the bit lines 13.

[0116] See also Figure 1 The number of common bit lines 14 is three, which can be set as needed in actual applications. Usually, the number of common bit lines 14, the number of gate tubes 12 and the number of memory cell arrays are the same.

[0117] See also Figure 1Optionally, in some embodiments, in an extension direction perpendicular to the bit line 13 , a maximum distance of an outer profile of the first semiconductor layer 121 is less than or equal to a width of the bit line 13 .

[0118] Such a configuration can avoid damaging the first semiconductor layer 121 during the process of etching to form the bit line 13 , thereby ensuring that the width of the first semiconductor layer 121 meets design requirements.

[0119] Optionally, in some embodiments, the memory cell may include a first transistor 20 and a capacitor 21 connected to each other.

[0120] The first transistor 20 may include a second gate electrode 201, a second gate insulating layer 202 and a second semiconductor layer 203. The second gate electrode 201 extends along a first direction perpendicular to the substrate 11. The second gate insulating layer 202 is arranged around the periphery and bottom of the second gate electrode 201. The second semiconductor layer 203 is arranged around the periphery and bottom of the second gate insulating layer 202.

[0121] The first transistor 20 may further include a first source / drain 204 and a second source / drain 205 . The first source / drain 204 of each first transistor is connected to the bit line 13 of the same layer. The second source / drain 205 of each first transistor 20 is connected to the capacitor 21 of the same layer.

[0122] Optionally, in some embodiments, the first source / drain 204 , the second source / drain 205 and the bit line 13 in the same layer of the memory cell array are prepared from the same conductive layer 18 .

[0123] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0124] In the embodiment of the present application, the gate transistor 12 of the semiconductor device includes a first semiconductor layer 121, and the material of the first semiconductor layer 121 includes single-crystal silicon. In other words, in the embodiment of the present application, single-crystal silicon, which has higher mobility and better material stability, is selected as the channel material of the gate transistor 12, thereby increasing the on-state current of the gate transistor 12 and improving the stability and reliability of the semiconductor device.

[0125] An embodiment of the present application provides an electronic device, which includes any semiconductor device provided in the above embodiments.

[0126] In this embodiment, since the electronic device adopts any one of the semiconductor devices provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0127] Optionally, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.

[0128] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any semiconductor device provided in the above-mentioned embodiments of this application in different devices according to actual application requirements, thereby obtaining the electronic device provided in the embodiments of this application.

[0129] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the related art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0130] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0131] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0132] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0133] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0134] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time. The execution order of these sub-steps or stages may be flexibly configured as required, and the embodiments of the present application do not limit this.

[0135] The above is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application also fall within the protection scope of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of first dielectric layers and a plurality of first sacrificial layers that are periodically and alternately stacked; Patterning the stacked structure to form a multi-layer stacked memory cell array and a multi-layer stacked gate transistor; the memory cell array includes a bit line, and the gate transistor is connected to the bit line; Forming a multi-layer stacked gate transistor includes: forming a through hole penetrating the stacked structure, forming a first semiconductor layer in the through hole, wherein the material of the first semiconductor layer includes single crystal silicon; A first gate insulating layer and a first gate electrode covering the first semiconductor layer are sequentially formed in the through hole.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: forming a first semiconductor layer in the through hole, comprising: forming an initial through hole penetrating the stacked structure; Carving back the first sacrificial layer exposed by the initial through hole to form a first groove surrounding the initial through hole and communicating with the initial through hole, wherein the through hole includes the initial through hole and the first groove; The initial semiconductor layer filling the initial through hole and the first groove is formed, and the initial semiconductor layer is patterned to retain only the initial semiconductor layer in the first groove as the first semiconductor layer, and the first semiconductor layers in any adjacent first grooves are disconnected from each other.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The substrate comprises a single crystal silicon substrate; Forming the initial semiconductor layer filling the initial through hole and the first groove includes: Exposing the single crystal silicon substrate when forming an initial through hole penetrating the stacked structure; An initial semiconductor layer filling the initial through hole and the first groove is formed on the single crystal silicon substrate by an epitaxial growth process.

4. The method for manufacturing a semiconductor device according to claim 1, 2 or 3, wherein: A bit line in a multi-layer stacked memory cell array is formed, comprising: forming a first groove penetrating the stacked structure; removing the first sacrificial layer in the first trench by wet etching to form a first accommodation space between adjacent first dielectric layers; A conductive layer is formed in the first receiving space, wherein the conductive layer includes the bit line.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: When forming the through hole corresponding to the gate transistor, simultaneously forming a through hole corresponding to the memory unit penetrating the stacked structure; Depositing a second semiconductor layer, a second gate insulating layer, and a second gate electrode in sequence in the through hole corresponding to the memory cell; The second semiconductor layer is a metal oxide semiconductor layer.

6. A semiconductor device, characterized in that: include: A substrate, a multi-layer memory cell array disposed on the substrate, and a plurality of stacked gate transistors disposed on the substrate; Each layer of the memory cell array includes a plurality of bit lines, and each of the bit lines is connected to a plurality of memory cells and one of the gate transistors; The gate transistor includes a first semiconductor layer, which is connected to the memory cell via the bit line; a material of the first semiconductor layer includes single crystal silicon.

7. The semiconductor device according to claim 6, wherein: The selection transistor further includes a first gate electrode and a first gate insulating layer. The first gate electrode extends along a first direction perpendicular to the substrate. The first gate insulating layer is arranged around the first gate electrode. The first semiconductor layer is arranged around the first gate insulating layer.

8. The semiconductor device according to claim 7, wherein: Each first semiconductor layer of each selection transistor is located in the through hole, the first semiconductor layer is located on the side wall of the through hole, the first gate insulating layer is located in the through hole, and the first gate electrode of each selection transistor is connected and extends in a direction perpendicular to the substrate.

9. The semiconductor device according to claim 8, wherein It also includes a plurality of common bit lines stacked in sequence along a first direction perpendicular to the substrate, each of the common bit lines is connected to the bit line via the first semiconductor layer arranged in the same layer; the common bit lines are perpendicular to the extending direction of the bit lines.

10. The semiconductor device according to any one of claims 8 to 9, characterized in that In an extension direction perpendicular to the bit line, a maximum distance of an outer profile of the first semiconductor layer is less than or equal to a width of the bit line.

11. The semiconductor device according to any one of claims 6 to 9, wherein: The substrate includes a single crystal silicon substrate.

12. An electronic device, characterized in that: include: A semiconductor device as claimed in any one of claims 6 to 11.

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