Memory device and manufacturing method thereof

Abstract

The invention provides a memory device and a manufacturing method thereof, and belongs to the technical field of semiconductor manufacturing, and the memory device comprises a CMOS wafer which comprises a complementary metal oxide semiconductor device and a first dielectric layer, and a first metal welding pad is formed on the first dielectric layer; the FRAM wafer comprises a second dielectric layer, and a second metal welding pad is formed on the second dielectric layer; a first dielectric layer of a CMOS wafer and a second dielectric layer of an FRAM wafer are bonded, and / or a first metal welding pad of the CMOS wafer and a second metal welding pad of the FRAM wafer are bonded, the FRAM and the CMOS device are manufactured on independent wafers based on Wafer-on-Wafer, then bonding of the CMOS wafer and the FRAM wafer is achieved, and the CMOS wafer and the FRAM wafer are allowed to be independently optimized under different thermal budgets.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a memory device and a manufacturing method thereof. Background Art

[0002] Ferroelectric Random Access Memory (FRAM) is a non-volatile memory fabricated by integrating ferroelectric thin films with silicon-based CMOS processes, leveraging the properties of ferroelectric thin films—their polarization can be reversed with an electric field and maintained even when power is removed. FRAM combines the advantages of dynamic random access memory (DRAM) and non-volatile memory, offering high read / write speeds, high read / write cycles, low power consumption, and non-volatility. It plays a crucial role in applications requiring fast response and high reliability, such as consumer electronics, smart cars, the Internet of Things, and industrial control. Lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT) thin films are the most widely used ferroelectric thin films in scientific research and production. However, the high fabrication temperatures (>600°C) required for PZT and SBT ferroelectric thin films make them incompatible with existing CMOS processes. Therefore, achieving high-performance ferroelectric thin films at lower temperatures has become a major challenge in FRAM research.

[0003] Current research primarily aims to achieve compatibility between FRAM and CMOS processes by optimizing the fabrication process for ferroelectric thin films and reducing the thermal budget. Examples include improving the traditional sol-gel fabrication process (550°C) and combining low-temperature magnetron sputtering with rapid thermal annealing (300°C). However, as CMOS technology continues to advance toward higher integration and lower power consumption, the relatively high thermal budget of FRAM ferroelectric thin films still conflicts with the low thermal budget pursued in CMOS processes. Furthermore, stress generated during the high-temperature fabrication of ferroelectric thin films can degrade CMOS device performance, such as affecting current control and increasing leakage current. When ferroelectric thin films are directly integrated into CMOS circuits, they can also react with electrode materials at higher temperatures, complicating the interface between the film and the electrode. Therefore, achieving FRAM integration in CMOS processes remains a pressing challenge. Summary of the Invention

[0004] In view of the compatibility issues between FRAM and CMOS processes in the prior art described above, the present application provides a memory device and a manufacturing method thereof. The FRAM memory cell and the logic circuit (CMOS circuit) are independently manufactured on different wafers through bonding technology, and then vertically stacked and integrated. This is used to solve compatibility issues such as thermal expansion coefficient mismatch and material interface reaction caused by high-temperature production of FRAM and low-temperature integration of logic circuits.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a memory device, comprising:

[0006] A CMOS wafer comprising a complementary metal oxide semiconductor device and a first dielectric layer, wherein a first metal bonding pad is formed in the first dielectric layer;

[0007] A FRAM wafer including a memory cell array and a second dielectric layer, wherein a second metal bonding pad is formed on the second dielectric layer;

[0008] The CMOS wafer and the FRAM wafer are bonded via the first metal bonding pad and the second metal bonding pad.

[0009] Optionally, the CMOS wafer includes a first front side and a first back side that are opposite to each other, the first dielectric layer is formed on the first back side, and the first metal bonding pad is formed in the first dielectric layer;

[0010] The FRAM wafer includes a second front side and a second back side that are oppositely arranged, the second dielectric layer is formed on the second front side, and the second metal bonding pad is formed on the second dielectric layer;

[0011] The first reverse surface of the CMOS wafer is bonded to the second front surface of the FRAM wafer, the first dielectric layer of the first reverse surface is bonded to the second dielectric layer of the second front surface, and the first metal welding pad of the first reverse surface is bonded to the second metal welding pad of the second front surface.

[0012] Optionally, the CMOS wafer includes a first front side and a first back side that are opposite to each other, the first dielectric layer is formed on the first front side, and the first metal bonding pad is formed in the first dielectric layer;

[0013] The FRAM wafer includes a second front side and a second back side that are opposite to each other, the second dielectric layer is formed on the second front side, and a second metal bonding pad is formed on the second dielectric layer;

[0014] The first front side of the CMOS wafer is bonded to the second front side of the FRAM wafer, the first dielectric layer of the first front side is bonded to the second dielectric layer of the second front side, and the first metal welding pad of the first front side is bonded to the second metal welding pad of the second front side.

[0015] Optionally, the CMOS wafer further includes a first redistribution layer, wherein the first redistribution layer is formed between the complementary metal oxide semiconductor device and the first dielectric layer;

[0016] The FRAM wafer further includes a second redistribution layer formed between the memory cell array and the second dielectric layer.

[0017] Optionally, the first dielectric layer of the CMOS wafer is bonded to the second metal bonding pad of the FRAM wafer, or the first metal bonding pad of the CMOS wafer is bonded to the second dielectric layer of the FRAM wafer.

[0018] Optionally, the first metal bonding pad of the CMOS wafer is flush with the first dielectric layer, or the first metal bonding pad is higher than the first dielectric layer;

[0019] The second metal bonding pad of the FRAM wafer is flush with the second dielectric layer, and the second metal bonding pad is higher than the second dielectric layer.

[0020] Optionally, the CMOS wafer includes a first contact interconnection structure, and the first contact interconnection structure includes a bit line interconnection structure, a word line interconnection structure, and a plate line interconnection structure;

[0021] The FRAM wafer includes a second contact interconnect structure;

[0022] The first contact interconnection structure is in communication with the second contact interconnection structure, and the second contact interconnection structure transmits a signal from the CMOS wafer to the memory cell array.

[0023] The present invention also provides a method for manufacturing a memory device, comprising the following steps:

[0024] Manufacturing a CMOS wafer includes: providing a first substrate, the first substrate including a first surface and a second surface disposed opposite to each other; forming a CMOS device on the first substrate; forming an interconnect structure on the first surface; forming a dielectric layer on the first surface or the second surface; and forming a first metal bonding pad on the dielectric layer;

[0025] Manufacturing a FRAM wafer includes: providing a second substrate, providing a second substrate, forming a memory cell array above the second substrate; forming a second redistribution layer above the memory cell array; forming a second dielectric layer above the second redistribution layer; forming a second metal bonding pad on the second dielectric layer;

[0026] The CMOS wafer and the FRAM wafer are bonded together.

[0027] Optionally, bonding the CMOS wafer and the FRAM wafer further includes:

[0028] The CMOS wafer includes a first front side and a first back side that are opposite to each other, and the FRAM wafer includes a second front side and a second back side that are opposite to each other;

[0029] The first back surface of the CMOS wafer is bonded to the first front surface of the FRAM wafer, or the first front surface of the CMOS wafer is bonded to the first front surface of the FRAM wafer.

[0030] Optionally, fabricating a CMOS wafer and fabricating a FRAM further includes:

[0031] Thinning the first substrate so that the thickness of the CMOS wafer is between 5 μm and 600 μm;

[0032] The second substrate is thinned so that the thickness of the FRAM wafer is between 5 μm and 400 μm.

[0033] As described above, the memory device and the manufacturing method thereof provided by the present invention have at least the following beneficial technical effects:

[0034] In the memory device and its manufacturing method of the present invention, FRAM memory elements and CMOS logic elements are formed on independent wafers based on wafer-on-wafer (WoW) technology, and the independently manufactured different devices are stacked and integrated in the vertical direction through bonding technology. For FRAM, independent high-temperature optimization is achieved, and stress caused by factors such as temperature changes and material thermal expansion coefficient mismatch will not be generated, resulting in device performance degradation, nor will it react with electrode materials when integrated with CMOS circuits at high temperatures. For CMOS, independent low-temperature optimization is achieved, avoiding thermal damage to CMOS devices caused by high temperature, while eliminating interface stress caused by thermal expansion coefficient mismatch, allowing CMOS circuits to continue to move towards the goals of smaller size, higher integration, and lower power consumption under a low thermal budget. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a flow chart of the memory manufacturing method provided by the present invention.

[0036] Figure 2 A schematic diagram of forming a CMOS device on a first substrate is shown.

[0037] Figure 3 Shown is a structural schematic diagram of forming an interconnection structure above a first substrate.

[0038] Figure 4 It is a schematic diagram showing the structure after the second surface of the first substrate is thinned.

[0039] Figure 5It is a schematic structural diagram showing a first dielectric layer formed on the second surface of the first substrate.

[0040] Figure 6 A schematic diagram showing a cross-section of a FRAM is shown.

[0041] Figure 6a Display as Figure 6 The cross-sectional view of the structure shown along the AA' direction.

[0042] Figure 7 Shown is a structural schematic diagram of the FRAM wafer provided in Example 3.

[0043] Figure 8 It is a schematic structural diagram showing the structure after the fourth surface of the second substrate is thinned.

[0044] Figure 9 Shown is a schematic structural diagram of the first type of storage device.

[0045] Figure 10 As shown, it is shown in Figure 5 The schematic diagram of the structure of the first contact interconnection structure formed in the CMOS wafer is shown.

[0046] Figure 11 Shown is a structural schematic diagram of forming a first dielectric layer on a CMOS wafer provided by the fourth embodiment.

[0047] Figure 12 Displayed as Figure 11 The structure diagram shown is a CMOS wafer placed on a temporary carrier.

[0048] Figure 13 Shown is a schematic structural diagram of a second memory device.

[0049] Reference numerals

[0050] 1. CMOS wafer; 10. First substrate; 101. First surface; 102. Second surface; 11. CMOS device; 111. Peripheral circuit; 12. Interconnect structure; 121. First redistribution layer; 122. First bonding pad; 13. First insulating layer; 14. First dielectric layer; 15. First contact interconnect structure; 151. Bit line interconnect structure; 152. Word line interconnect structure; 153. Plate line interconnect structure; 16. First metal bonding pad; 2. FRAM wafer; 20. Second Substrate; 21, injection region; 221, bit line; 2211, contact hole; 222, word line; 223, plate line; 231, first dielectric layer; 232, second dielectric layer; 233, second insulating layer; 24, capacitor; 241, connection structure; 25, second dielectric layer; 251, contact pad; 252, second redistribution layer; 26, second metal welding pad; 27, second contact interconnection structure; 3, first front side; 4, first back side; 5, second front side; 6, second back side; 7, temporary carrier. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity, positional relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solution of this party, and the component layout form may also be more complicated.

[0053] Example 1

[0054] This embodiment provides a memory device. Figure 9 , which is a schematic diagram of a memory device structure; the memory device structure provided in this embodiment includes: a CMOS wafer 1, including a CMOS device (complementary metal oxide semiconductor device) 11, a peripheral circuit 111 of the CMOS device, and a first dielectric layer 14, on which a first metal bonding pad 16 is formed; a FRAM wafer 2, including a second dielectric layer 25, on which a second metal bonding pad 26 is formed; the first dielectric layer 14 of the CMOS wafer 1 is bonded to the second dielectric layer 25 of the FRAM wafer 2, and the first metal bonding pad 16 of the CMOS wafer 1 is bonded to the second metal bonding pad 26 of the FRAM wafer 2.

[0055] Specifically, the CMOS wafer 1 includes a first front surface 3 and a first back surface 4 arranged opposite to each other; the FRAM wafer 2 includes a second front surface 5 and a second back surface 6 arranged opposite to each other. In the memory device provided in this embodiment, the first back surface 4 of the CMOS wafer 1 is bonded to the second front surface 5 of the FRAM wafer 2.

[0056] Specifically, the CMOS wafer 1 includes a CMOS device 11, an interconnect structure 12, a first dielectric layer 14, and a first metal pad 16. Specifically, the CMOS device 11 includes logic circuits (such as a controller, a signal amplifier, a power management unit, etc.), which are responsible for functions such as read and write control of the storage unit, data signal processing, and power management. To illustrate the connection structure, the peripheral circuit 111 of the CMOS device 11 is shown separately (for illustration only); the interconnect structure 12 includes a first redistribution layer 121 and a first bonding pad 122. The interconnect structure includes multi-layer metal wiring (such as a Cu dual damascene process) for optimizing signal paths and reducing parasitic capacitance and delay; the first bonding pad 122 is located at the end of the first redistribution layer 121 and is used to connect to an external circuit or bonding interface.

[0057] The first dielectric layer 14 is located on the first reverse side 4 of the CMOS wafer 1 and covers the CMOS devices, and is used to provide electrical insulation, mechanical protection and surface flattening, and serves as a flat bonding foundation for subsequent bonding. The first metal bonding pad 16 is located on the surface of the first dielectric layer 14, and the first metal bonding pad 16 is flush with the first dielectric layer 14. Specifically, the first dielectric layer 14 is made of copper (Cu) or aluminum (Al) and is used to bond with the second metal bonding pad 26 of the FRAM wafer to achieve electrical signal interconnection. Optionally, the first metal bonding pad 16 is higher than the surface of the first dielectric layer 14.

[0058] Specifically, the FRAM wafer 2 includes transistors and capacitors, specifically, combined with Figure 6 and Figure 6a As shown, Figure 6a Display as Figure 6 The cross-sectional view along the AA' direction is shown; the FRAM wafer 2 includes: word lines 222 arranged along the Y direction, which select the gates of an entire row of transistors and activate all cells in the row. Word lines 222 are deeply buried in the underlying dielectric layer; bit lines 221 arranged along the X direction, which are responsible for reading and writing data, are arranged crosswise with word lines 222, and word lines 222 are buried in the dielectric layer (first dielectric layer 231 and second dielectric layer 232 are shown); and plate lines 223 arranged parallel to bit lines 221 provide write voltage and read reference.

[0059] Specifically, in this embodiment, the transistor is represented by the injection region 21, which is located in the second substrate 20 and below the word line 222 and the bit line 221; the transistor source and drain regions formed by ion implantation in the injection region 21 are connected to the gate of the word line 222 to control the transistor switch. The transistor acts as a switching element of the storage unit to control the on and off of the read and write paths of the capacitor data. The capacitor 24 is an upright columnar structure, located directly above the intersection of the word line 222 and the bit line 221, and is connected to the drain of the transistor below it through a vertical storage node contact. The plate line 223 is on the top layer, designed along the X direction, parallel to the word line 222, and connected to the upper electrode of a row of capacitors 24.

[0060] Optionally, the FRAM further includes: a contact hole 2211 located between the bit line 221 and the injection region 21, the contact hole 2211 providing a vertical conductive path to physically connect the bit line 221 to the transistor source; an interconnection structure 241 passing through the first dielectric layer 231 and the second dielectric layer 232, the interconnection structure 241 enabling the capacitor 24 to be connected to the injection region 21, specifically, the interconnection structure 241 establishing a conductive path from the drain to the capacitor 24.

[0061] The first dielectric layer 231 separates the word line 222 and the bit line 221 to prevent short circuits between metal layers. The second dielectric layer 232 provides a flat base for the upper structure (capacitor 24).

[0062] Specifically, if Figure 9 As shown, the FRAM wafer 2 further includes a second dielectric layer 25 located on the second front side 5 of the FRAM wafer 2 and having a second metal bonding pad 26 formed therein. The second dielectric layer 25 is used to isolate the internal structures of the FRAM wafer 2 and provide a flat surface for the bonding interface, facilitating bonding between the second metal bonding pad 26 and the CMOS wafer 1. Optionally, the second metal bonding pad 26 is flush with the second dielectric layer 25 or higher than the second dielectric layer 25.

[0063] Specifically, the memory device structure also includes a contact interconnect structure, which includes a first contact interconnect structure 15 and a second contact interconnect structure 27. Specifically, the first contact interconnect structure 15 includes a bitline interconnect structure 151, a wordline interconnect structure 152, and a plateline interconnect structure 153. The first contact interconnect structure 15 is located within the CMOS wafer 1, vertically connecting the first redistribution layer 121 and the FRAM wafer 2, transmitting logic signals to the bonding interface; the second contact interconnect structure 27 is located within the FRAM wafer 2, connecting the memory cell array signal lines (bitlines 221, wordlines 222, and platelines 223) to the CMOS wafer 1, and the second contact interconnect structure 27 transmits signals from the CMOS wafer 1 to the memory cell array. Specifically, the bitline interconnect structure 151 transmits signals to the bitlines 221 via the second contact interconnect structure 27, and the plateline interconnect structure 153 transmits signals to the platelines 223 via the second contact interconnect structure 27. Optionally, the first contact interconnect structure 15 and the second contact interconnect structure 27 are made of the same material.

[0064] Specifically, in the memory structure provided in this embodiment, the CMOS wafer and the FRAM wafer are bonded via the first metal bonding pad 16 and the second metal bonding pad 26, and the first dielectric layer 14 and the second dielectric layer 25 are bonded. Alternatively, if the first metal bonding pad 16 is higher than the surface of the first dielectric layer 14, and the second metal bonding pad 26 is higher than the second dielectric layer 25, the CMOS wafer and the FRAM wafer are bonded only via the first metal bonding pad 16 and the second metal bonding pad 26.

[0065] In the memory structure provided by this embodiment, the CMOS wafer integrates peripheral circuits responsible for read and write control and signal processing of the storage array to improve storage density and energy efficiency. The FRAM wafer carries the storage cell array to realize data storage. The CMOS wafer and the FRAM wafer are vertically stacked by bonding, which shortens the signal processing delay.

[0066] Example 2

[0067] This embodiment also provides a memory device. Figure 13 , which is a schematic diagram of a second memory device structure; the memory device structure provided in this embodiment includes: a CMOS wafer 1, including a CMOS device 11, a peripheral circuit 111 of the CMOS device, and a first dielectric layer 14, on which a first metal bonding pad 16 is formed; a FRAM wafer 2, including a second dielectric layer 25, on which a second metal bonding pad 26 is formed; the first dielectric layer 14 of the CMOS wafer 1 is bonded to the second dielectric layer 25 of the FRAM wafer 2, and the first metal bonding pad 16 of the CMOS wafer 1 is bonded to the second metal bonding pad 26 of the FRAM wafer 2.

[0068] Specifically, CMOS wafer 1 includes a first front side 3 and a first back side 4 disposed opposite each other; FRAM wafer 2 includes a second front side 5 and a second back side 6 disposed opposite each other. In the memory device provided in this embodiment, first front side 3 of CMOS wafer 1 is bonded to second front side 5 of FRAM wafer 2. The remaining structure is similar to that described in Example 1 and will not be further described here.

[0069] The CMOS wafer and FRAM wafer are bonded face-to-face, which does not require through-holes with a high depth-to-width ratio and simplifies the process steps. The contact interconnection structure has a short route, which is suitable for storage arrays with high-frequency operation and has a faster response speed.

[0070] Example 3

[0071] This embodiment provides a method for manufacturing a memory device, such as Figure 1 FIG. 1 is a flow chart of a method for manufacturing a memory device according to an embodiment of the present invention. The method for manufacturing a memory device includes the following steps:

[0072] S1: Fabricating a CMOS wafer, comprising: providing a first substrate, the first substrate comprising a first surface and a second surface disposed opposite to each other; forming a CMOS device on the first substrate; forming an interconnect structure on the first surface; forming a dielectric layer on the first surface or the second surface; and forming a metal bonding pad on the dielectric layer;

[0073] S2: Fabricating a FRAM wafer, including: providing a second substrate, forming a memory cell array on the second substrate; forming a second redistribution layer above the memory cell array; forming a second dielectric layer above the second redistribution layer; forming a second metal bonding pad on the second dielectric layer;

[0074] S3: Bonding the CMOS wafer and the FRAM wafer.

[0075] Specifically, see Figures 2 to 5 , showing the specific steps for making CMOS wafers.

[0076] Specifically, if Figure 2 As shown, it is a schematic diagram showing a CMOS device formed on a first substrate; Figure 2 It can be seen that the first substrate 10 includes a first surface 101 and a second surface 102 disposed opposite to each other. Generally, the thickness of the first substrate 10 ranges from 50 μm to 800 μm, and the specific thickness can be selected according to actual needs. Specifically, this application does not limit the material of the first substrate 10.

[0077] Specifically, the steps of forming the CMOS device 11 include forming N + / P + Doping area, defining the source and drain of CMOS device 11, and depositing gate dielectric layer and gate electrode, the external electrical connection structure of CMOS device 11 is as follows Figure 2 The peripheral circuit 111 in the substrate 10 is formed. The specific process is relatively conventional and will not be described in detail in the present invention. Please refer to the prior art. Specifically, the CMOS device 11 can be arranged inside or above the first substrate 10. Specifically, for the convenience of demonstration, the CMOS device 11 is arranged above the first substrate 10 in this embodiment.

[0078] like Figure 3 As shown, it is a schematic structural diagram showing an interconnection structure formed on a first substrate; Figure 3 It can be seen that an interconnect structure 12 is formed above the first surface 101 of the first substrate 10. Specifically, the interconnect structure 12 includes a first redistribution layer 121 and a first bonding pad 122. The first redistribution layers 121 and the first bonding pads 122 are separated from each other by a first insulating layer 13. One of the first redistribution layers 121 is connected to the peripheral circuit 111 formed above the CMOS device 11.

[0079] like Figure 4 The structure diagram shown is a schematic diagram of the structure after the second surface of the first substrate is thinned; Figure 4 It can be seen that after the interconnection structure 12 is formed on the first surface 101 of the first substrate 10, a process step of thinning the second surface 102 of the first substrate 10 is also included to form a CMOS wafer 1. The thickness of the CMOS wafer 1 ranges from 5μm to 600μm. For example, it can be 10μm, 50μm, 200μm, 400μm, and any value within the above range. The specific thickness depends on the thickness to which the CMOS wafer 1 is subsequently thinned. The side close to the interconnection structure 12 and away from the first substrate 10 is defined as the first front side 3 of the CMOS wafer 1; the side away from the interconnection structure 12 and close to the first substrate 10 is defined as the first reverse side 4 of the CMOS wafer 1.

[0080] Optionally, the method further includes forming a first dielectric layer 14 on the second surface 102 of the first substrate 10. Figure 5, which is a schematic structural diagram of forming a first dielectric layer on the second surface of the first substrate. Specifically, in this embodiment, the first dielectric layer 14 is formed on the first reverse side 4 of the CMOS wafer 1. Optionally, the first dielectric layer 14 includes an oxide layer, which can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, spin coating and / or other suitable techniques. In this example, the thickness of the first dielectric layer 14 can range from 50nm to 200nm. Specifically, the first dielectric layer 14 is used to provide electrical isolation when bonding between the CMOS wafer 1 and the FRAM wafer 2 is subsequently achieved.

[0081] like Figure 6 Figure 2 shows a schematic diagram of a cross-section of a FRAM wafer. The core of the FRAM fabrication process is to three-dimensionally stack ferroelectric capacitors (the core of the 1T1C cell) on top of CMOS logic circuits (transistors, word lines, and bit lines) to increase storage density. The specific process steps include: constructing a CMOS transistor array (access transistors) on a silicon substrate, and then building a three-dimensional stack of ferroelectric capacitors on top of it, connected by metal interconnects (word lines, bit lines, and plate lines).

[0082] Specifically, if Figure 6 , which is a schematic diagram of the internal structure of the FRAM provided in this embodiment;

[0083] Specifically, a second substrate 20 is provided. Generally, the second substrate 20 is made of silicon, glass, or the like. Specifically, the steps for forming transistors on the second substrate 20 include: Shallow Trench Isolation (STI): etching the second substrate 20 to form shallow trenches, filling them with an oxide (e.g., SiO2), and performing chemical mechanical polishing (CMP) to planarize the trenches to isolate adjacent transistors. Well Implantation: ion implantation is used to form implantation regions 21 in predetermined areas. Implantation regions 21 include N-type wells and P-type wells (not shown) to prepare for NMOS and PMOS transistors.

[0084] The process also includes: gate stack formation: growing a thin gate oxide layer; depositing polysilicon or metal gate material; depositing a hard mask layer (such as silicon nitride); photolithographically defining the gate pattern; etching the hard mask, gate material, and gate oxide to form the gate structure; source / drain implantation: photolithographically defining the source / drain regions; performing lightly doped drain (LDD) implantation and sidewall formation (usually a silicon nitride / oxide stack); performing high-dose source / drain implantation to form the transistor's source and drain; high-temperature annealing to activate impurities; and silicide formation: depositing metal (such as nickel or cobalt) on top of the source, drain, and gate, and annealing to form a low-resistance silicide (such as NiSi or CoSi2). These process steps are all conventional technical means, and can be referred to in the prior art, so they will not be described in detail here.

[0085] Continue reading Figure 6Deeply buried word lines 222 are formed on the second substrate. This process specifically includes forming contact holes at the transistor gate locations where word lines are to be connected; depositing an adhesion layer / barrier layer (such as Ti / TiN), then filling the contact holes with a metal such as tungsten (W); depositing one or more metal layers (typically TiN as a barrier / adhesion layer and W as a low-resistance conductor); and etching the metal layers. These word lines are arranged in parallel, connecting the gates of a row of transistors. A first dielectric layer 231 is deposited, covering the word lines 222 and planarized using CMP. At this point, the word lines are deeply buried beneath the first dielectric layer 231.

[0086] Continue reading Figure 6 , forming bit lines 221 on the second substrate. This specifically includes: photolithography and etching of the first dielectric layer 231 to form contact holes at the transistor sources where the bit lines are to be connected; depositing an adhesion layer / barrier layer and filling the holes with a metal such as tungsten to form bit line contact holes 2211. Depositing a bit line metal layer, optionally using a Ti / TiN / Al-Cu / TiN stacked structure; photolithography to define the bit line pattern; and etching the metal layer to form bit lines 221 perpendicular to the word lines 222. Bit lines 221 connect to the sources of a column of transistors. Depositing a second dielectric layer 232 to cover the bit lines 221, at which point the bit lines 221 are also buried in the second dielectric layer 232.

[0087] Continue reading Figure 6 , forming a capacitor 24 on the second substrate. Specifically, it includes: photolithography and etching the second dielectric layer 232 covering the bit line 221 and the first dielectric layer 231 below, forming a deep contact hole at the drain position of the transistor that needs to be connected to the lower electrode of the ferroelectric capacitor 24; depositing an adhesion layer / barrier layer, and filling it with metals such as tungsten to form an interconnection structure 241. A ferroelectric material film is deposited using atomic layer deposition, sputtering or sol-gel methods; and the upper electrode material is deposited, which can optionally include Ir, Pt, RuO2, etc. The capacitor pattern is then defined by photolithography. Specifically, in this embodiment, the entire unit array area is covered, and discrete, vertical columnar capacitor 24 units are formed by sequentially etching the upper electrode, ferroelectric film, and lower electrode, and each capacitor 24 unit is located above its corresponding connection structure 214.

[0088] Continue reading Figure 6 , forming a plate line 223 on the second substrate. Specific steps include: etching the second insulating layer 233, forming a contact hole on top of the top electrode of the capacitor 24. Optionally, the plate line 223 typically directly contacts the top electrode of the entire memory cell array, so the contact hole may be a large opening covering the entire array. Depositing a plate line metal layer, optionally using a stacked structure such as Ti / TiN / Al-Cu / TiN. The plate line 223 is parallel to the bit line 221, covering and connecting the top electrodes of a row or block of ferroelectric capacitors 24, and serving as a common electrode.

[0089] like Figure 6a As shown, it is shown as Figure 6 The cross-sectional view along the AA' direction is shown, combined with Figure 6 and Figure 6a Definition: The direction extending along the bit line 221 is the X direction, the direction along the second substrate 20 pointing to the plate line 223 is the Z direction, and the direction perpendicular to the XZ plane pointing inward is the Y direction. Specifically, Figure 6a As shown, the word line 222 is arranged along the Y direction, the bit line 221 and the plate line 223 are arranged along the X direction, and the plate line 223 is located above the bit line 221 .

[0090] like Figure 7 , which is a schematic structural diagram of the FRAM wafer provided in this embodiment; Figure 7 For illustration only, the positional relationship among the word lines, bit lines, and plate lines is not shown.

[0091] Optionally, a redistribution layer is formed over the second substrate 20. Specifically, contact pads 251 are first formed to lead out the bit lines 221 and the plate lines 223. Each of the bit lines 221 and the plate lines 223 forms an independent contact pad. Then, a second redistribution layer 252 is formed over the contact pads 251.

[0092] Alternatively, as Figure 7 As shown, the process further includes forming a second dielectric layer 25 over the second rewiring layer 252 .

[0093] Specifically, a second contact interconnection structure 27 is formed along the second dielectric layer 25 toward one side of the second substrate 20. One end of the second contact interconnection structure 27 contacts the second redistribution layer 252 and the other end is exposed to the second dielectric layer 25, or one end of the second contact interconnection structure 27 contacts the second redistribution layer 252 and the other end is flush with the second dielectric layer 25. The specific etching process includes conventional means such as deep reactive ion etching. The filling, planarization and other process steps are conventional technical means and can be referred to in the prior art.

[0094] Optionally, an etch-stop layer (not shown) is formed between the second redistribution layer 252 and the second dielectric layer 25 to ensure that when etching the through-holes to form the second contact interconnect structure 27, the bottom of the through-holes stops precisely on the surface of the second redistribution layer 252, avoiding excessive etching that could damage the wiring. The etch-stop layer can optionally be made of silicon nitride, for example, and have a thickness between 10 and 20 nm.

[0095] The second metal pad 26 is further formed on a side of the second redistribution layer 252 away from the second substrate 20. Specifically, one end of the second metal pad 26 contacts the second redistribution layer 252, and the other end is exposed to the second dielectric layer 25, or the other end of the second metal pad 26 is flush with the first dielectric layer 14. In this embodiment, the other end of the second metal pad 26 is flush with the first dielectric layer 14.

[0096] like Figure 8 The structure shown is a schematic diagram after the fourth surface of the second substrate is thinned. The process step of thinning the second substrate 20 is to form a FRAM wafer 2, and the thickness of the FRAM wafer 2 includes 5μm-400μm. For example, it can be 10μm, 50μm, 100μm, 200μm, 300μm and any value within the above range, depending on the thickness to which the FRAM wafer 2 is subsequently thinned. The side close to the second rewiring layer 252 and away from the second substrate 20 is defined as the front side of the FRAM wafer 2; the side away from the second rewiring layer 252 and close to the second substrate 20 is defined as the back side of the FRAM wafer 2.

[0097] like Figure 9 As shown, it is a schematic diagram of the structure of the first memory device provided by the present application, that is, a schematic diagram of the structure after the CMOS wafer and the FRAM wafer are bonded; generally, there are two ways to bond the CMOS wafer 1 and the FRAM wafer 2, including bonding the first reverse side 4 of the CMOS wafer 1 to the second front side 5 of the FRAM wafer 2, or bonding the first front side 3 of the CMOS wafer 1 to the second front side 5 of the FRAM wafer 2.

[0098] Specifically, Figure 9 The embodiment shown provides a structural diagram of bonding the first back surface 4 of the CMOS wafer 1 to the second front surface 5 of the FRAM wafer 2. Specifically, before bonding, the process also includes: Figure 10 FIG. 1 is a schematic diagram showing a structure of forming a first contact interconnection structure in a CMOS wafer; specifically, Figure 5 A first contact interconnect structure 15 is formed in the illustrated CMOS wafer 1. The first contact interconnect structure 15 includes a bitline interconnect structure 151, a wordline interconnect structure 152, and a plateline interconnect structure 153. The process for forming the first contact interconnect structure 15 includes forming multiple through-holes on a side of the first dielectric layer 14 away from the first redistribution layer 121; and filling the formed through-holes with metal to form the first contact interconnect structure 15. Specifically, one end of the first contact interconnect structure 15 contacts the first redistribution layer 121, while the other end is exposed to the first dielectric layer 14, or the other end of the first contact interconnect structure 15 is flush with the first dielectric layer 14.

[0099] like Figure 9As shown, the signal from CMOS wafer 1 is transmitted to FRAM wafer 2 via first contact interconnect structure 15. Specifically, bitline interconnect structure 151 transmits the signal to bitline 221 of FRAM via second contact interconnect structure 27; plateline interconnect structure 153 transmits the signal to plateline 223 of FRAM via second contact interconnect structure 27.

[0100] Specifically, the process also includes forming first metal pads 16 on a side of the first dielectric layer 14 away from the first redistribution layer 121. Specifically, the positions and number of the first metal pads 16 formed on the CMOS wafer 1 must correspond one-to-one with the second metal pads 26 formed on the FRAM wafer 2. Specifically, the first metal pads 16 are exposed to the first dielectric layer 14, or the first metal pads 16 are flush with the first dielectric layer 14. In this embodiment, the first metal pads 16 are flush with the first dielectric layer 14.

[0101] Optionally, an etch stop layer (not shown in the figure) is also formed between the first rewiring layer 121 and the first dielectric layer 14 to ensure that when etching a through hole to form the first dielectric layer 14, the bottom of the through hole can stop precisely on the surface of the first rewiring layer 121 to avoid excessive etching that damages the wiring.

[0102] like Figure 9 As shown, the first back surface 4 of the CMOS wafer 1 is bonded to the second front surface 5 of the FRAM wafer 2. Specifically, the bonding method provided in this embodiment for bonding the CMOS wafer 1 and the FRAM wafer 2 is a hybrid bonding method, which simultaneously achieves a connection between the first metal bonding pad 16 and the second metal bonding pad 26 and a bond between the first dielectric layer 14 and the second dielectric layer 25. The metal bonding portion provides electrical connection, while the dielectric layer bonding provides mechanical support and insulation.

[0103] The manufacturing method of the memory device provided in this embodiment is to combine a CMOS wafer and a FRAM wafer together through a face-to-back bonding method. Through the wafer-on-wafer (WoW) wafer bonding technology, the manufacturing processes of FRAM and CMOS are separated, avoiding the potential damage to CMOS devices caused by high-temperature processing and improving the reliability of the overall circuit. By independently optimizing the manufacturing process of the FRAM ferroelectric film under a high thermal budget, the ferroelectric performance can be significantly improved; CMOS wafers are manufactured under a low thermal budget, which can continuously reduce the size of transistors, increase integration density, reduce power consumption, and meet the development trend of Moore's Law.

[0104] In addition, although WoW technology adds additional steps such as wafer bonding, by optimizing the processes on each wafer, the process complexity and scrap rate caused by incompatibility can be reduced, which helps reduce manufacturing costs in the long run.

[0105] Example 4

[0106] This embodiment also provides a method for manufacturing a memory device, which specifically includes the following steps:

[0107] S1: Fabricating a CMOS wafer, comprising: providing a first substrate, the first substrate comprising a first surface and a second surface disposed opposite to each other; forming a CMOS device on the first substrate; forming an interconnect structure on the first surface; forming a dielectric layer on the first surface or the second surface; and forming a metal bonding pad on the dielectric layer;

[0108] S2: Fabricating a FRAM wafer, including: providing a second substrate, forming a memory cell array on the second substrate; forming a second redistribution layer above the memory cell array; forming a second dielectric layer above the second redistribution layer; forming a second metal bonding pad on the second dielectric layer;

[0109] S3: Bonding the CMOS wafer and the FRAM wafer.

[0110] Steps S1-S2 are the same as those in the third embodiment and will not be described in detail.

[0111] like Figure 11 As shown in FIG. 1 , it is a schematic diagram showing a structure of forming a first dielectric layer on a first surface of a first substrate. As can be seen from the figure, the first dielectric layer 14 is formed on the first front surface 3 of the CMOS wafer 1. The specific formation steps are the same as those in the first embodiment of the present application. Specifically, Figure 11 As can be seen, a first contact interconnect structure 15 is also formed within the CMOS wafer 1. The first contact interconnect structure 15 includes a bitline interconnect structure 151, a wordline interconnect structure 152, and a plateline interconnect structure 153. Specifically, a plurality of through-holes are formed on a side of the first dielectric layer 14 away from the first substrate 10, and metal is filled into the formed through-holes to form the first contact interconnect structure 15. Specifically, one end of the first contact interconnect structure 15 contacts the first redistribution layer 121, and the other end is exposed to the first dielectric layer 14, or the other end of the first contact interconnect structure 15 is flush with the first dielectric layer 14.

[0112] Specifically, the process further includes forming a first metal pad 16 in the first dielectric layer 14 . Optionally, the first metal pad 16 exposes the first dielectric layer 14 , or the first metal pad 16 is buried in the first dielectric layer 14 and flush with the first dielectric layer 14 .

[0113] Specifically, the first front side 3 of the CMOS wafer 1 is bonded to the second front side 5 of the FRAM wafer 2. Figure 12 As shown, it is shown as Figure 11Specifically, the back of the CMOS wafer 1 is placed on the temporary carrier 7, the temporary carrier 7 and the CMOS wafer 1 are turned over, and the first front side 3 of the CMOS wafer 1 is bonded to the second front side 5 of the FRAM wafer 2, as shown in FIG. Figure 13 , which is a schematic diagram of the second memory device structure provided by the present application, i.e., a schematic diagram of the structure after bonding of a CMOS wafer and a FRAM wafer. Specifically, the bonding method provided in this embodiment is a hybrid bonding method, in which the first metal bonding pad 16 is bonded to the second metal bonding pad 26, and the first dielectric layer 14 is also bonded to the second dielectric layer 25. Optionally, the bonding method also includes metal-to-metal bonding and metal-to-dielectric layer bonding, which are similar to those discussed in Example 3 and will not be repeated here.

[0114] Specifically, the metal-to-dielectric layer bonding includes: bonding the first dielectric layer 14 of the CMOS wafer to the second metal bonding pad 26 of the FRAM wafer; and bonding the first metal bonding pad 16 of the CMOS wafer to the second dielectric layer 25 of the FRAM wafer.

[0115] The first back surface 4 of the CMOS wafer 1 is bonded to the second front surface 5 of the FRAM wafer 2. The manufacturing method of the memory device provided in this embodiment is to combine the CMOS wafer and the FRAM wafer together by face-to-face bonding.

[0116] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A memory device, characterized in that: include: A CMOS wafer comprising a complementary metal oxide semiconductor device and a first dielectric layer, wherein a first metal bonding pad is formed in the first dielectric layer; A FRAM wafer including a memory cell array and a second dielectric layer, wherein a second metal bonding pad is formed on the second dielectric layer; The CMOS wafer and the FRAM wafer are bonded via the first metal bonding pad and the second metal bonding pad.

2. The memory device according to claim 1, wherein: The CMOS wafer comprises a first front surface and a first back surface opposite to each other, the first dielectric layer is formed on the first back surface, and the first metal bonding pad is formed in the first dielectric layer; The FRAM wafer includes a second front side and a second back side that are oppositely arranged, the second dielectric layer is formed on the second front side, and the second metal bonding pad is formed on the second dielectric layer; The first reverse surface of the CMOS wafer is bonded to the second front surface of the FRAM wafer, the first dielectric layer of the first reverse surface is bonded to the second dielectric layer of the second front surface, and the first metal welding pad of the first reverse surface is bonded to the second metal welding pad of the second front surface.

3. The memory device according to claim 1, wherein: The CMOS wafer comprises a first front side and a first back side that are opposite to each other, the first dielectric layer is formed on the first front side, and the first metal bonding pad is formed in the first dielectric layer; The FRAM wafer includes a second front side and a second back side that are opposite to each other, the second dielectric layer is formed on the second front side, and a second metal bonding pad is formed on the second dielectric layer; The first front side of the CMOS wafer is bonded to the second front side of the FRAM wafer, the first dielectric layer of the first front side is bonded to the second dielectric layer of the second front side, and the first metal welding pad of the first front side is bonded to the second metal welding pad of the second front side.

4. The memory device according to claim 1, wherein: The CMOS wafer further includes a first redistribution layer formed between the complementary metal oxide semiconductor device and the first dielectric layer; The FRAM wafer further includes a second redistribution layer formed between the memory cell array and the second dielectric layer.

5. The memory device according to claim 1, wherein The first dielectric layer of the CMOS wafer is bonded to the second metal bonding pad of the FRAM wafer, or the first metal bonding pad of the CMOS wafer is bonded to the second dielectric layer of the FRAM wafer.

6. The memory device according to claim 1, wherein: The first metal bonding pad of the CMOS wafer is flush with the first dielectric layer, or the first metal bonding pad is higher than the first dielectric layer; The second metal bonding pad of the FRAM wafer is flush with the second dielectric layer, or the second metal bonding pad is higher than the second dielectric layer.

7. The memory device according to claim 1, wherein: The CMOS wafer includes a first contact interconnect structure, wherein the first contact interconnect structure includes a bit line interconnect structure, a word line interconnect structure and a plate line interconnect structure; The FRAM wafer includes a second contact interconnect structure; The first contact interconnection structure is in communication with the second contact interconnection structure, and the second contact interconnection structure transmits a signal from the CMOS wafer to the memory cell array.

8. A method for manufacturing a memory device, characterized in that: The following steps are involved: Manufacturing a CMOS wafer includes: providing a first substrate, the first substrate including a first surface and a second surface disposed opposite to each other; forming a CMOS device on the first substrate; forming an interconnect structure on the first surface; forming a first dielectric layer on the first surface or the second surface; and forming a first metal bonding pad on the first dielectric layer. Manufacturing a FRAM wafer includes: providing a second substrate, forming a memory cell array above the second substrate; forming a second redistribution layer above the memory cell array; forming a second dielectric layer above the second redistribution layer; forming a second metal bonding pad on the second dielectric layer; The CMOS wafer and the FRAM wafer are bonded together.

9. The method for manufacturing a memory device according to claim 8, wherein: Bonding the CMOS wafer and the FRAM wafer further includes: The CMOS wafer includes a first front side and a first back side that are opposite to each other, and the FRAM wafer includes a second front side and a second back side that are opposite to each other; Bonding the first reverse side of the CMOS wafer to the first front side of the FRAM wafer; Or the first front side of the CMOS wafer is bonded to the first front side of the FRAM wafer.

10. The method for manufacturing a memory device according to claim 8, wherein: The first dielectric layer of the CMOS wafer is bonded to the second dielectric layer of the FRAM wafer, and / or the first metal bonding pad of the CMOS wafer is bonded to the second metal bonding pad of the FRAM wafer.

11. The method for manufacturing a memory device according to claim 8, wherein: Fabricating CMOS wafers and making FRAM also includes: Thinning the first substrate so that the thickness of the CMOS wafer is between 5 μm and 600 μm; The second substrate is thinned so that the thickness of the FRAM wafer is between 5 μm and 400 μm.

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