Semiconductor device

Abstract

A semiconductor device comprises: a weakly p-doped semiconductor body (20) having a first surface (101) and a second surface (102) opposite the first surface (101) in a vertical direction (y); a high p-doped first semiconductor region (22) extending from the first surface (101) into the semiconductor body (20) within the limited region (320); a highly n-doped second semiconductor region (24) extending from the second surface (102) into the semiconductor body (20); and an n-doped third semiconductor region (26) extending horizontally spaced from the first semiconductor region (22) from the first surface (101) to the second surface (102).

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a power semiconductor diode. Background Art

[0002] Power semiconductor devices, such as semiconductor diodes, are used in many different applications. A diode essentially has a pn junction, which allows current to flow in one direction and blocks it in the other. In so-called PIN diodes, an additional intrinsic region or very low-doped region is located between a (highly) p-doped region and a (highly) n-doped region. As the demands placed on the applications in which semiconductor devices are used continue to increase, so too do the demands placed on the semiconductor devices themselves. At the same time, semiconductor devices must be manufactured as quickly and cost-effectively as possible. Summary of the Invention

[0003] The object is to provide a robust semiconductor component that meets high requirements and to provide a method for producing the semiconductor component quickly and cost-effectively.

[0004] A semiconductor device includes: a weakly p-doped semiconductor body having a first surface and a second surface opposite to the first surface in a vertical direction; a highly p-doped first semiconductor region extending from the first surface into the semiconductor body within a limited area; a highly n-doped second semiconductor region extending from the second surface into the semiconductor body; and an n-doped third semiconductor region extending from the first surface to the second surface at a horizontal distance from the first semiconductor region.

[0005] A method includes providing a weakly p-doped semiconductor body having a first surface and a second surface vertically opposite to the first surface; forming a highly p-doped first semiconductor region in the semiconductor body, wherein the first semiconductor region extends from the first surface into the semiconductor body within a limited area; forming a highly n-doped second semiconductor region, wherein the second semiconductor region extends from the second surface into the semiconductor body; and forming an n-doped third semiconductor region, wherein the third semiconductor region extends from the first surface to the second surface at a horizontal distance from the first semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will be explained in more detail below based on exemplary embodiments and with reference to the accompanying drawings. Here, the same reference numerals denote the same elements. The illustrations in the accompanying drawings are not drawn to scale.

[0007] Figure 1 schematically illustrates a cross section of a semiconductor device according to an embodiment;

[0008] Figure 2 schematically illustrates a cross section of a semiconductor device according to another embodiment;

[0009] Figure 3 includes Figures 3A to 3F , which exemplarily shows a method of manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0010] The following detailed description illustrates how the present invention can be implemented based on specific examples. It should be understood that the features of the various examples described herein can be combined with each other unless otherwise stated. When a particular element is referred to as a "first element," "second element," etc., the descriptions "first," "second," etc. are only used to distinguish the different elements from each other. This description is not associated with an order or enumeration. This means that, for example, a "second element" can exist even if there is no "first element."

[0011] Figure 1 A semiconductor device according to an embodiment of the present disclosure is shown. The semiconductor device includes a weakly p-doped semiconductor body 20 having a first surface 101 and a second surface 102 opposite the first surface 101 in a vertical direction y. The semiconductor device also includes a highly p-doped first semiconductor region 22 extending from the first surface 101 into the semiconductor body 20 within a limited area 320, and a highly n-doped second semiconductor region 24 extending from the second surface 102 into the semiconductor body 20. An n-doped third semiconductor region 26 extends from the first surface 101 to the second surface 102, spaced horizontally from the first semiconductor region 22. The distance d between the third semiconductor region 26 and the first semiconductor region 22 in the horizontal direction x is 0. A It may be, for example, between 100 μm and 1000 μm.

[0012] Thus, the semiconductor device is or has a so-called PIN diode, in which an additional intrinsic region or very low-doped region (weakly p-doped region of the semiconductor body 20) is present between a (high) p-doped region (first semiconductor region 22) and a (high) n-doped region (second semiconductor region 24). The first semiconductor region 22 can be electrically contacted, for example, by means of an anode metallization 41. The anode metallization 41 can be arranged in the region of the first semiconductor region 22 on the first surface 101 of the semiconductor body 20. However, in some embodiments, the anode metallization 41 may not cover the entire first semiconductor region 22. Figure 1 As shown in FIG. 4 , the edge region of the first semiconductor region 22 may not be covered by the anode metallization 41. The distance d between the edge of the anode metallization 41 and the edge of the first semiconductor region 22 in the horizontal direction x is 41It can be, for example, between 0 (zero) and 200 μm (micrometers). The second semiconductor region 24 can be electrically contacted by means of a cathode metallization 42. The cathode metallization 42 can be arranged in the region of the second semiconductor region 24 on the second surface 102 of the semiconductor body 20. Figure 1 In the embodiment shown, the cathode metallization 42 covers (substantially) the entire second surface 102 , for example.

[0013] In planar semiconductor devices, such as Figure 1 As shown, edge termination is usually required to terminate the electric field in the semiconductor device and dissipate the electric field through the edge. Figure 1 The third semiconductor region 26 is shown extending horizontally from the first semiconductor region 22 from the first surface 101 to the second surface 102, forming such an edge-terminated element. The third semiconductor region 26 is arranged in the edge region 310 of the semiconductor device, while the first semiconductor region 22 is arranged in the active region 320 of the semiconductor device. The second semiconductor region 24 generally extends to the entire second surface 102, and thus extends onto the active region 320 and onto the edge region 310. Figure 1 In the example shown, the second semiconductor region 24 is interrupted in the edge region 310 by the third semiconductor region 26 .

[0014] According to the embodiments described herein, the semiconductor body 20 is weakly p-doped. For example, the semiconductor body 20 has a p-doping ratio of less than 1E15 cm -3 Or even less than 1E13cm -3 In conventional, similar semiconductor devices, the semiconductor body is typically weakly n-doped. As described below, manufacturing corresponding semiconductor devices starting with weakly p-doped semiconductor bodies can be significantly faster and therefore more cost-effective than manufacturing semiconductor devices starting with weakly n-doped semiconductor bodies.

[0015] According to one example, the semiconductor body 20 is a silicon body doped with at least one of boron, aluminum, and gallium, the first semiconductor region 22 is doped with at least one of boron, aluminum, and gallium, and / or the second semiconductor region 24 is doped with at least one of phosphorus, arsenic, and antimony. The third semiconductor region 26 can, for example, be doped with a chalcogen element, such as sulfur, selenium, or tellurium. Chalcogen elements (such as sulfur, selenium, or tellurium, among other elements) diffuse rapidly into the weakly p-doped semiconductor body 20. Thus, the third semiconductor region 26 can be produced in approximately one hour or less, for example by diffusion. In contrast, the production of a similar semiconductor region (e.g., doped with aluminum) in a weakly n-doped semiconductor body typically takes approximately 48 hours or longer (e.g., up to a week). Thus, starting with the weakly p-doped semiconductor body 20, the entire semiconductor device can be manufactured in a very short time. This can significantly reduce the manufacturing costs of the semiconductor device. Furthermore, the energy required to manufacture the semiconductor device and the amount of carbon dioxide emissions are reduced.

[0016] like Figure 2 As shown by way of example in FIG, after the first semiconductor region 22, the second semiconductor region 24, and the third semiconductor region 26 have been fabricated, additional structures may be generated and / or applied in or to the semiconductor body 20. On the one hand, the anode metallization 41 may be applied in the region of the first semiconductor region 22 on the first surface 101 of the semiconductor body 20, while the cathode metallization 42 may be applied in the region of the second semiconductor region 24 on the second surface 102 of the semiconductor body 20. Furthermore, an optional passivation layer 30 may be applied to the first surface 101 in the region between the active region 320 and the chip edge CE (chip edge) of the semiconductor device (in the edge region 310 and in the region between the edge region 310 and the active region 320). The passivation layer 30 may extend in the horizontal direction x all the way to the first semiconductor region 22. According to one example, the passivation layer 30 and the first semiconductor region 22 may also slightly overlap. However, the passivation layer 30 is arranged spaced apart from the anode metallization 41 in the horizontal direction x. In another direction, the passivation layer 30 may extend (substantially) all the way to the chip edge CE. Typically, multiple semiconductor devices are manufactured on a single wafer and then separated (sliced) from one another. In the accompanying drawings, CE represents the edge of a semiconductor device before being separated from an adjacent semiconductor device. Edge CE typically passes through the third semiconductor region 26, so that the third semiconductor region 26 serves as an edge termination element for two semiconductor devices after slicing.

[0017] Furthermore, optionally, a fourth semiconductor region 28 can be produced extending from the first surface 101 into the third semiconductor region 26. The fourth semiconductor region 28 can be a (highly) n-doped semiconductor region, similar to the second semiconductor region 24. The fourth semiconductor region 28 can be configured to increase the surface concentration in the edge termination (third semiconductor region 26) region. The fourth semiconductor region 28 can be, for example, a semiconductor region doped with phosphorus. The dopant concentration of the fourth semiconductor region 28 can be at least two orders of magnitude greater than the dopant concentration of the third semiconductor region 26. The dopant concentration in the fourth semiconductor region 28 can be (substantially) uniform, or can decrease from the first surface 101 along the vertical direction y into the semiconductor body 20 (into the third semiconductor region 26).

[0018] The semiconductor body 20 may have a thickness W in the vertical direction y of, for example, between 100 μm and 1000 μm or between 250 μm and 400 μm. 20 The first semiconductor region 22 may have a thickness W in the vertical direction y of, for example, between 10 μm and 120 μm or between 10 μm and 60 μm. 22 The second semiconductor region 24 may have a thickness W between 10 μm and 120 μm or between 10 μm and 60 μm in the vertical direction y. 24 The thickness W of the first semiconductor region 22 is 22 This may depend, for example, in particular on the method used to produce the first semiconductor region 22. For example, if the first semiconductor region 22 is produced as a so-called singlet distribution (doped with a single dopant), this generally results in a small thickness W between 10 μm and 60 μm. 22 If the first semiconductor region 22 is produced according to another example as a so-called double profile (doped with two or more different dopants), the different dopants are usually introduced into the semiconductor body 20 at different depths, which usually results in a greater thickness W of the first semiconductor region 22 of up to 120 μm. 22 In each case, the first semiconductor region 22 and the second semiconductor region 24 are separated by a region of the weakly p-doped semiconductor body 20 .

[0019] 3 , a method for manufacturing a semiconductor device is described. The method includes providing a weakly p-doped semiconductor body 20 having a first surface 101 and a second surface 102 opposite the first surface 101 in a vertical direction y; forming a highly p-doped first semiconductor region 22 in the semiconductor body 20, wherein the first semiconductor region 22 extends from the first surface 101 into the semiconductor body 20 within a limited area 320; forming a highly n-doped second semiconductor region 24, wherein the second semiconductor region extends from the second surface 102 into the semiconductor body 20; and forming an n-doped third semiconductor region 26, wherein the third semiconductor region 26 extends from the first surface 101 to the second surface 102 at a horizontal distance from the first semiconductor region 22.

[0020] Figure 3A Here, a provided semiconductor body 20 is shown. Figure 3B As shown, a first semiconductor region 22 and a second semiconductor region 24 are formed in the semiconductor body 20. The first and second semiconductor regions 22 and 24 can be formed successively. For example, the formation of the first semiconductor region 22 can include an implantation method or a diffusion method. Similarly, the formation of the second semiconductor region 24 can also include an implantation method or a diffusion method. According to one example, the semiconductor body 20 can be a silicon body doped with at least one of boron, aluminum and gallium, the first semiconductor region 22 can be doped with at least one of boron, aluminum and gallium, and / or the second semiconductor region 24 can be doped with at least one of phosphorus, arsenic and antimony. The resulting highly p-doped first semiconductor region 22 can, for example, have a p-doped region of 1E15 cm -3 to 1E21cm -3 The dopant concentration of the highly n-doped second semiconductor region 24 may be between 1E15cm -3 to 1E21cm -3 The dopant concentration in the first semiconductor region 22 and the second semiconductor region 24 can be (substantially) uniform within the corresponding region, or decrease from the corresponding surface 101 , 102 in the vertical direction y into the semiconductor body 20 .

[0021] In the next step, if Figure 3C As shown in the exemplary embodiment, a first masking layer 50 and a second masking layer 52 can be applied to the first surface 101 and the second surface 102 of the semiconductor body 20, respectively. The first and second masking layers 50 and 52 can be formed simultaneously or sequentially. For example, the first and second masking layers 50 and 52 can each comprise one of silicon oxide, silicon oxynitride, or silicon nitride. However, other materials can also be used to prevent certain materials (such as chalcogenides) from diffusing into the semiconductor body. For example, the first and second masking layers 50 and 52 can be respectively produced by depositing the corresponding materials or by growing the corresponding materials on the semiconductor body 20.

[0022] Now refer to Figure 3D , the first and second masking layers 50, 52 can then be structured. In particular, openings can be formed in the first masking layer 50 and openings can be formed in the second masking layer 52, respectively, so that the areas below the first surface 101 and the second surface 102 are exposed. The structuring of the first and second masking layers 50, 52 can, for example, include a photolithography step (exposure step) and an etching step. The etching step can, for example, include a wet etching method or a dry etching method. In principle, other suitable etching methods are also feasible. Subsequently, an n-doped third semiconductor region 26 can be formed. The formation of the third semiconductor region 26 can, for example, include introducing a chalcogen element into the semiconductor body 20. Regardless of the material used to manufacture the third semiconductor region 26, the formation of the third semiconductor region 26 can include introducing a dopant via the first surface 101 and the second surface 102, respectively. For example, the dopant can be introduced by diffusion. The diffusion temperature can, for example, be between 700°C and 1100°C. Here, two separated semiconductor regions are initially produced by introducing dopants from both sides of the semiconductor body 20. If each of the two semiconductor regions is manufactured to have at least W 20 / 2, the initially separated semiconductor regions will eventually collide in the middle of the semiconductor body 20, thereby forming a continuous third semiconductor region 26 ( Figure 3E ).

[0023] If the third semiconductor region 26 is manufactured by means of diffusion, the diffusion can, for example, be carried out directly by means of a gas containing the corresponding material (for example, a chalcogen). Liquid or solid materials such as elemental sulfur can also be used here, which are converted into a gaseous state at the corresponding diffusion temperature. Alternatively, however, the third semiconductor region 26 can also be formed, for example, by depositing a doping layer and subsequently introducing a dopant into the semiconductor body 20, or by injecting a suitable material. The diffusion method can, for example, be a two-stage method, in which a (high) surface doping is generated in a first step and this surface doping is driven deeper into the semiconductor body 20 in a further step. However, a single-stage diffusion process in which the dopant is introduced directly into the semiconductor body 20 to the desired depth is also feasible. For example, a single-stage diffusion process can be applied when the dopant diffuses rapidly into the semiconductor body 20 (for example sulfur).

[0024] The resulting n-doped third semiconductor region 26 may have a density of at least 1E15 cm at the first surface 101 and the second surface 102, respectively. -3 The dopant concentration of the semiconductor body 20 decreases in the vertical direction y toward the middle of the semiconductor body 20. Figure 3FAs shown, the first and second masking layers 50, 52 can then be removed again. In a further step (not explicitly shown), the anode electrode 41, the cathode electrode 42, the highly n-doped fourth semiconductor region 28 extending from the first surface 101 into the third semiconductor region 26 and / or the passivation layer 30 can be produced by means of suitable methods.

[0025] As already mentioned above, the third semiconductor region 26 can be produced in particular in a weakly p-doped semiconductor body 20 quickly and in only a few steps, since the corresponding dopant (e.g., a chalcogen) can diffuse very quickly into the weakly p-doped semiconductor body 20. Furthermore, the steps required to produce the third semiconductor region 26 are also relatively uncomplicated and only consume minimal energy. Consequently, the resulting semiconductor device can be produced very quickly and cost-effectively. Furthermore, a PIN diode having the third semiconductor region 26, which extends from the first surface 101 through the entire semiconductor body 20 to the second surface 102, is also very stable.

Claims

1. A semiconductor device comprising: A weakly p-doped semiconductor body (20) having a first surface (101) and a second surface (102) opposite to the first surface (101) in a vertical direction (y); a highly p-doped first semiconductor region (22) extending from the first surface (101) into the semiconductor body (20) within a limited area (320); a highly n-doped second semiconductor region (24) extending from the second surface (102) into the semiconductor body (20); and An n-doped third semiconductor region (26) extends from the first surface (101) to the second surface (102) at a horizontal distance from the first semiconductor region (22).

2. The semiconductor device according to claim 1, wherein: The semiconductor body (20) is a silicon body doped with at least one of boron, aluminum and gallium, The first semiconductor region (22) is doped with at least one of boron, aluminum, gallium, and / or The second semiconductor region (24) is doped with at least one of phosphorus, arsenic and antimony.

3. The semiconductor device according to claim 1 or 2, wherein the third semiconductor region (26) is doped with a chalcogen element.

4. The semiconductor device according to claim 3, wherein the third semiconductor region (26) is doped with sulfur, selenium or tellurium.

5. The semiconductor device according to claim 1, wherein The semiconductor body (20) has a thickness (W) between 100 μm and 1000 μm or between 250 μm and 400 μm in the vertical direction (y). 20 ), The first semiconductor region (22) has a thickness (W) between 10 μm and 120 μm or between 10 μm and 60 μm in the vertical direction. 22 ),and The second semiconductor region (24) has a thickness (W) between 10 μm and 120 μm or between 10 μm and 60 μm in the vertical direction. 24 ).

6. The semiconductor device according to claim 1 , wherein the highly p-doped first semiconductor region ( 22 ) has a p-doped region of 1E15 cm -3 to 1E21cm -3 and the highly n-doped second semiconductor region (24) has a dopant concentration of 1E15 cm -3 to 1E21cm -3 dopant concentration between .

7. The semiconductor device according to claim 1, wherein the weakly p-doped semiconductor body (20) has a relative humidity of less than 1E15 cm -3 or less than 1E13cm -3 dopant concentration.

8. The semiconductor device according to claim 1 , wherein the distance (d A ) is between 100μm and 1000μm.

9. The semiconductor device according to claim 1 , wherein the n-doped third semiconductor region ( 26 ) has a density of at least 1E15 cm at the first surface ( 101 ) and at least 1E15 cm at the second surface ( 102 ). -3 The dopant concentration decreases in the vertical direction (y) toward the middle of the semiconductor body (20).

10. The semiconductor device according to any one of the preceding claims, further comprising: an anode electrode (41) disposed on the first surface (101) and electrically connected to the first semiconductor region (22); and A cathode electrode (42) is disposed on the second surface (102) and electrically connected to the second semiconductor region (24).

11. The semiconductor device according to one of the preceding claims, further comprising a highly n-doped fourth semiconductor region (28) extending from the first surface (101) into the third semiconductor region (26).

12. The semiconductor device according to one of the preceding claims, further comprising a passivation layer (30) arranged on the first surface (101), wherein the passivation layer (30) is arranged between the first semiconductor region (22) of the semiconductor device and an edge (CE) of the semiconductor device along a horizontal direction (x).

13. A method for manufacturing a semiconductor device, wherein the method comprises Providing a weakly p-doped semiconductor body (20) having a first surface (101) and a second surface (102) opposite to the first surface (101) in a vertical direction (y); forming a highly p-doped first semiconductor region (22) in the semiconductor body (20), wherein the first semiconductor region (22) extends from the first surface (101) into the semiconductor body (20) within a limited area (320); forming a highly n-doped second semiconductor region (24), wherein the second semiconductor region extends from the second surface (102) into the semiconductor body (20); and An n-doped third semiconductor region (26) is formed, wherein the third semiconductor region (26) extends from the first surface (101) to the second surface (102) at a horizontal distance from the first semiconductor region (22).

14. The method of claim 13, wherein forming a third semiconductor region (26) comprises introducing a chalcogen element into the semiconductor body (20).

15. The method according to claim 13 or 14, wherein The formation of the first semiconductor region (22) includes an implantation method or a diffusion method, and The formation of the second semiconductor region (24) includes an implantation method or a diffusion method.

16. The method according to one of claims 13 to 15, wherein the forming of the third semiconductor region (26) comprises a diffusion method or an implantation method.

17. The method according to any one of claims 13 to 16, further comprising before forming the third semiconductor region (26): applying a first masking layer (50) to said first surface (101), applying a second masking layer (52) to the second surface (102), structuring the first masking layer (50), and The second masking layer (52) is structured.

18. The method according to claim 17, wherein Applying the first masking layer (50) includes growing a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer, and Applying the second masking layer (52) includes growing a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

19. Method according to claim 17 or 18, wherein structuring the first and second masking layers (50, 52) comprises a photolithographic step and an etching step.

20. The method according to one of claims 17 to 19, wherein forming the third semiconductor region (26) comprises introducing dopants through the first surface (101) and the second surface (102).

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