Semiconductor device structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device structure and a forming method thereof. The method includes forming a fin structure from a substrate, and the fin structure includes a plurality of semiconductor layers. The method further includes depositing a gate dielectric layer around a portion of each of the plurality of semiconductor layers; an adhesion layer is deposited on the gate dielectric layer, and the adhesion layer surrounds the portion of each of the plurality of semiconductor layers. The method further includes depositing a fluorine-containing layer on the adhesion layer, and the fluorine-containing layer encompasses the portion of each of the plurality of semiconductor layers. The method further comprises the following steps: carrying out annealing treatment on the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; and forming a gate electrode layer on the gate dielectric layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, a need exists for improved processing and manufacturing of ICs. Summary of the Invention

[0004] In one aspect, an embodiment of the present application provides a method comprising: forming a fin structure from a substrate, wherein the fin structure includes a plurality of semiconductor layers; depositing a gate dielectric layer around a portion of each of the plurality of semiconductor layers; depositing an adhesion layer on the gate dielectric layer, wherein the adhesion layer surrounds the portion of each of the plurality of semiconductor layers; depositing a fluorine-containing layer on the adhesion layer, wherein the fluorine-containing layer surrounds the portion of each of the plurality of semiconductor layers; annealing the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; and forming a gate electrode layer on the gate dielectric layer.

[0005] In some implementations, the fluorine-containing layer is formed by an atomic layer deposition process.

[0006] In some implementations, the atomic layer deposition process includes a plurality of cycles, and each cycle includes introducing a first precursor into the processing chamber and introducing a second precursor into the processing chamber.

[0007] In some implementations, the first precursor includes WF6 and the second precursor includes B2H6 or SiH4.

[0008] In some implementations, the first precursor has a flow rate ranging from about 20 sccm to about 100 sccm, and the second precursor has a flow rate ranging from about 200 sccm to about 1500 sccm.

[0009] In some implementations, the fluorine-containing layer has a thickness ranging from about 18 angstroms to about 26 angstroms.

[0010] In some implementations, the method further includes performing a treatment process after depositing the adhesion layer and before depositing the fluorine-containing layer.

[0011] In some implementations, the treatment process removes oxide from the adhesion layer.

[0012] In another aspect, an embodiment of the present application provides a method comprising: forming a first fin structure and a second fin structure from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers and the second fin structure includes a second plurality of semiconductor layers; depositing a gate dielectric layer around a portion of each of the first plurality of semiconductor layers; depositing a first work function layer on portions of the gate dielectric layer surrounding each of the first plurality of semiconductor layers; depositing an adhesion layer over the first work function layer; depositing a fluorine-containing layer on the adhesion layer; annealing the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; depositing a second work function layer over the first work function layer; and depositing a bulk metal over the second work function layer.

[0013] In some implementations, the gate dielectric layer is deposited to surround a portion of each semiconductor layer in the second plurality of semiconductor layers.

[0014] In some implementations, the method further includes depositing a third work function layer on portions of the gate dielectric layer surrounding portions of each semiconductor layer in the second plurality of semiconductor layers.

[0015] In some implementations, an adhesion layer is deposited over the third work function layer.

[0016] In some implementations, the method further includes depositing a fourth work function layer over the third work function layer after removing the fluorine-containing layer.

[0017] In some implementations, the first work function layer and the second work function layer are n-type work function layers, and the third work function layer and the fourth work function layer are p-type work function layers.

[0018] In some implementations, the method further includes depositing a capping layer on the first work function layer, wherein the adhesion layer is deposited on the capping layer.

[0019] In some implementations, the capping layer includes silicon.

[0020] In another aspect, an embodiment of the present application provides a semiconductor device structure, comprising: a substrate portion extending from a substrate; a semiconductor layer disposed above the substrate portion; a gate dielectric layer surrounding at least a portion of the semiconductor layer, wherein the gate dielectric layer has a first fluorine concentration; a first work function layer surrounding the gate dielectric layer, wherein the first work function layer has a second fluorine concentration, which is greater than the first fluorine concentration; and a second work function layer surrounding the first work function layer, wherein the second work function layer has a third fluorine concentration, which is less than the second fluorine concentration.

[0021] In some implementations, the semiconductor device structure further includes a capping layer disposed between the first work function layer and the second work function layer, wherein the capping layer has a fourth fluorine concentration greater than the second fluorine concentration.

[0022] In some implementations, the semiconductor device structure further includes an adhesion layer disposed on the second work function layer.

[0023] In some implementations, the semiconductor device structure further includes a bulk metal disposed on the adhesion layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various aspects of the present disclosure may be best understood from the following specific implementations when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0025] Figures 1 to 6 are perspective views of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0026] 7A to 11A According to some embodiments Figure 6 Cross-sectional side views of various stages in the fabrication of a semiconductor device structure taken along line AA.

[0027] Figures 7B to 11B According to some embodiments Figure 6 Cross-sectional side views of various stages of fabricating a semiconductor device structure taken along line BB.

[0028] Figures 7C to 11C According to some embodiments Figure 6 Cross-sectional side views of various stages of fabricating a semiconductor device structure taken along line CC.

[0029] 12A to 12E are cross-sectional side views of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0030] Figure 12C-1 is a schematic diagram of a portion of a fluorine-containing layer of a semiconductor device structure according to some embodiments.

[0031] Figures 13A to 13G are cross-sectional side views of various stages in the fabrication of a semiconductor device structure according to an alternative embodiment. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0033] Additionally, spatially relative terms (e.g., "below," "lower," "above," "up," "top," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element or feature. Spatially relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0034] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs (e.g., gate-all-around (GAA) FETs (e.g., horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs)), implementations of some aspects of the present disclosure may be used in other processes and / or other devices (e.g., planar FETs, fin FETs, and other suitable devices). A person of ordinary skill in the art will readily understand that other modifications that may be made are contemplated within the scope of the present disclosure. Where a gate-all-around (GAA) transistor structure is employed, the GAA transistor structure may be patterned by any suitable method. For example, one or more photolithography processes, including double patterning processes or multi-patterning processes, may be used to pattern these structures. Typically, the double patterning process or multi-patterning process combines a photolithography process with a self-aligned process, thereby allowing the creation of patterns having a pitch that is, for example, smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0035] Figures 1 to 12EFIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 12E Additional operations are provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes is not limiting and may be interchangeable.

[0036] Figures 1 to 6 1 is a perspective view of various stages of fabricating a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0037] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0038] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate forming a nanostructured channel in a multi-gate device (e.g., a nanostructured channel FET). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first and second semiconductor layers 106, 108. The first and second semiconductor layers 106, 108 are made of semiconductor materials with different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, while the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, while the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0039] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0040] The first semiconductor layer 106 or a portion thereof may form (one or more) nanostructured channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to both elongated material portions having circular and substantially circular cross-sections and beam-shaped or strip-shaped material portions that are, for example, cylindrical in shape or have a substantially rectangular cross-section. The (one or more) nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructured transistor. The nanostructured transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode that surrounds the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is discussed further below.

[0041] Each first semiconductor layer 106 may have a thickness ranging between about 3 nm and about 9 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging between about 4 nm and about 14 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and is not intended to limit the scope of the specific claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. In some embodiments, the number of first semiconductor layers 106 ranges from 2 to 10.

[0042] exist Figure 2 , fin structures 112 are formed from the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multiple patterning operation including a photolithography process and an etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) lithography process. An etching process forms trenches 114 in unprotected areas through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0043] exist Figure 3In the embodiment of the present invention, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (e.g., a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed so that the top of the fin structure 112 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0044] exist Figure 4 In the embodiment of the present invention, the insulating material 118 is recessed to form the isolation region 120. The recessing of the insulating material 118 exposes some portions of the fin structure 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 reveals the trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from the substrate 101.

[0045] exist Figure 5 , one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structures 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers of the gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portions of the fin structure 112. Although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X-direction in some embodiments.

[0046] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacers 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0047] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100 .

[0048] exist Figure 6 In the embodiment, portions of the fin structure 112 that are not covered by the sacrificial gate structure 130 and the gate spacers 138 are recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of these portions of the fin structure 112 can be accomplished by an etching process (either an isotropic or anisotropic etching process), and the etching process can be selective to the first semiconductor layer 106 and the second semiconductor layer 108. The etching process can be a dry etch (e.g., RIE, NBE, etc.) or a wet etch (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0049] Figure 7A 、 Figure 7B and Figure 7C are along Figure 6 1 is a cross-sectional side view of the semiconductor device structure 100 taken along lines AA, BB, and CC.

[0050] Figure 8A 、 Figure 8B and Figure 8C According to some embodiments, Figure 6 AA, BB, and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 8A As shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant (such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminecatechol (EDP), or potassium hydroxide (KOH) solution) can be used to selectively etch the second semiconductor layer 108.

[0051] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. Dielectric spacers 144 can be made of a low-K dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). Dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and then removing portions of the conformal dielectric layer except for dielectric spacers 144 by anisotropic etching. During the anisotropic etching process, dielectric spacers 144 are protected by first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between dielectric spacers 144 along the X direction.

[0052] Figure 9A 、 Figure 9B and Figure 9C According to some embodiments, Figure 6 AA, BB, and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 9A and Figure 9C As shown, source / drain (S / D) regions 146 are formed from substrate portion 116. The S / D regions 146 can be grown vertically and horizontally to form facets that can correspond to crystal planes of the material used for substrate portion 116. In the present disclosure, source regions and drain regions can be used interchangeably and their structures are substantially the same. In addition, (one or more) source / drain regions can refer to the source or drain individually or collectively, depending on the context. The S / D regions 146 can be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-type dopants (e.g., boron (B)) can also be included in the S / D regions 146. The S / D regions 146 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0053] Figure 10A 、 Figure 10B and Figure 10C According to some embodiments, Figure 6 A cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100 is taken along lines AA, BB, and CC. Figure 10A 、 Figure 10B and Figure 10CIn the embodiment of the present invention, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of the ILD layer 164 may include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 164 , the semiconductor device structure 100 may be thermally treated to anneal the ILD layer 164 .

[0054] After forming the ILD layer 164, a planarization operation (eg, CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. Figure 10A and Figure 10B shown.

[0055] Figure 11A 、 Figure 11B and Figure 11C According to some embodiments, Figure 6 AA, BB, and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 11A and Figure 11B As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134 without removing the first gate spacers 138, the ILD layer 164, and the CESL 162.

[0056] The second semiconductor layer 108 may be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemistry used in the selective wet etching process removes the SiGe without substantially affecting the Si, the dielectric material of the gate spacers 138, and the dielectric spacers 144. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant (e.g., but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4)), a dry etchant (e.g., a fluorine-based (e.g., F2) or a chlorine-based gas (e.g., Cl2)), or any suitable isotropic etchant.

[0057] 12A to 12E 1 is a cross-sectional side view of various stages of fabricating a semiconductor device structure 100 according to some embodiments. Figure 12A As shown, after forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), an interfacial layer (IL) 169 is formed to surround the exposed portion of the first semiconductor layer 106 and the substrate portion 116, and a gate dielectric layer 170 is formed on the IL 169. In some embodiments, the IL 169 is selectively formed on the semiconductor material of the first semiconductor layer 106 and the substrate portion 116, and the gate dielectric layer 170 is also formed on the insulating material 118. In some embodiments, the IL 169 is an oxide layer, such as silicon oxide. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-K dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique.

[0058] In some embodiments, the Figure 12A The first semiconductor layer 106 on the left is the channel of the NMOS device, and the Figure 12A The first semiconductor layer 106 on the right side is a channel of a PMOS device adjacent to an NMOS device.

[0059] In some embodiments, a dipole process is performed to introduce a dipole material into the gate dielectric layer 170. The dipole process may include depositing a dipole layer (not shown) on the gate dielectric layer 170 and performing a thermal treatment to move the dipole material in the dipole layer into the gate dielectric layer 170. In some embodiments, different dipole layers are formed for NMOS devices and PMOS devices. For example, a dipole material suitable for an NMOS device may include lanthanum oxide (La2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), other n-type dipole materials, or a combination thereof; a dipole material suitable for a PMOS device may include aluminum oxide (Al2O3), TiO2, other p-type dipole materials, or a combination thereof. After the thermal treatment, the dipole layer is removed to expose the gate dielectric layer 170.

[0060] In some embodiments, after forming gate dielectric layer 170 (and in some embodiments, the dipole process), a fluorination process is performed to introduce fluorine into gate dielectric layer 170 and IL 169. Fluorine can repair or occupy oxygen vacancies in gate dielectric layer 170 and IL 169, and the fluorine in gate dielectric layer 170 and IL 169 can inhibit interdiffusion of elements between adjacent NMOS and PMOS devices. The fluorination process can be a gas immersion process using a fluorine-containing gas (e.g., NF3 or WF6). However, because gate dielectric layer 170 and IL 169 have multiple levels, the fluorine concentration at different locations in gate dielectric layer 170 and IL 169 may be non-uniform. Portions of gate dielectric layer 170 that are more exposed to the fluorine-containing gas and portions of IL 169 located thereunder may have a higher fluorine concentration than portions of gate dielectric layer 170 that are less exposed to the fluorine-containing gas and portions of IL 169 located thereunder. For example, the fluorine concentration in portions of gate dielectric layer 170 surrounding the topmost first semiconductor layer 106 can be significantly greater than the fluorine concentration in portions of gate dielectric layer 170 surrounding the bottommost first semiconductor layer 106. Furthermore, the fluorine concentration in portions of gate dielectric layer 170 located on the sides of first semiconductor layer 106 can be significantly greater than the fluorine concentration in portions of gate dielectric layer 170 located between vertically adjacent first semiconductor layers 106. Furthermore, because the critical dimensions of the gate electrode layer of the subsequently formed NMOS device and the critical dimensions of the gate electrode layer of the PMOS device are different, the fluorine concentration in gate dielectric layer 170 and IL 169 in the NMOS device can be significantly different from the fluorine concentration in gate dielectric layer 170 and IL 169 in the PMOS device. The uneven fluorine concentration in gate dielectric layer 170 may result in a reduced standard deviation (Vtσ) of the threshold voltage. Embodiments of the present disclosure provide a process for uniformly incorporating fluorine into gate dielectric layer 170.

[0061] like Figure 12B As shown, an adhesion layer 202 is formed on the gate dielectric layer 170. In some embodiments, the adhesion layer 202 is a conformal layer formed by a conformal process (e.g., an ALD process). The adhesion layer 202 may include any material capable of adhering to the subsequently formed fluorine-containing layer 204. In some embodiments, the adhesion layer 202 is made of or includes TiN.

[0062] like Figure 12C As shown, a fluorine-containing layer 204 is deposited on the adhesion layer 202. In some embodiments, if the semiconductor device structure 100 is exposed to air, the adhesion layer 202 is oxidized, and a treatment process may be performed to remove the oxidized portion of the adhesion layer 202. In some embodiments, the adhesion layer 202 includes TiN, and a surface portion of the adhesion layer 202 may be oxidized to form TiO. x The treatment process may be a gas impregnation process using a gas that can break the Ti-O bond. Thus, the TiO x In some embodiments, the gas of the gas impregnation process may be B2H6 or WF6, and the gas flow rate may range from about 800 standard cubic centimeters per minute (sccm) to about 900 sccm. The gas impregnation process may have a duration ranging from about 10 seconds to about 20 seconds.

[0063] After the treatment process, a fluorine-containing layer 204 is deposited. In some embodiments, the treatment chamber for performing the treatment process and the treatment chamber for depositing the fluorine-containing layer 204 are part of a cluster tool, and the semiconductor device structure 100 is not exposed to air between the treatment process and the deposition process. In other words, the treatment process and the deposition process are performed on the semiconductor device structure 100 without breaking vacuum.

[0064] In some embodiments, fluorine-containing layer 204 is formed by ALD to provide a uniform fluorine concentration within fluorine-containing layer 204. The ALD process for forming fluorine-containing layer 204 may include introducing a first precursor into a process chamber and adsorbing molecules of the first precursor onto exposed surfaces of semiconductor device structure 100 until the surfaces are saturated with molecules of the first precursor. The saturated molecules of the first precursor form an atomic layer of molecules of the first precursor. For example, the surface of adhesion layer 202 is saturated with molecules of the first precursor, and an atomic layer of molecules of the first precursor is formed on adhesion layer 202. In some embodiments, the first precursor includes WF6 gas, and the gas flow rate may range from approximately 20 sccm to approximately 100 sccm, for example, from approximately 50 sccm to approximately 65 sccm, with a pulse time of approximately 0.5 seconds to approximately 3 seconds, for example, from approximately 1.3 seconds to approximately 1.7 seconds. The flow rate of the first precursor ensures that the surface of adhesion layer 202 is saturated with molecules of the first precursor. For example, the surface of adhesion layer 202 is saturated with WF6 molecules. The saturated WF 6 molecules may form an atomic layer of WF 6 on the adhesion layer 202 .

[0065] Next, the processing chamber is cleaned to remove the first precursor from the processing chamber. Then, a second precursor is introduced into the processing chamber. The second precursor reacts with the atomic layer of molecules of the first precursor to form a layer. In some embodiments, the second precursor is B2H6 or SiH4, and the second precursor breaks the bonds of the molecules of the first precursor. For example, the second precursor breaks the WF bonds of the atomic WF6 layer to form a tungsten nucleation layer. In some embodiments, some fluorine atoms from the broken WF bonds are removed from the surface of the atomic layer, while some fluorine atoms from the broken WF bonds are trapped between adjacent tungsten atoms. Due to the structure of the WF6 atomic layer, the number of fluorine atoms trapped in the tungsten nucleation layer can be substantially constant. As a result, the fluorine concentration in the tungsten nucleation layer can be substantially uniform.

[0066] In some embodiments, the second precursor may have a flow rate ranging from about 200 sccm to about 1500 sccm, for example, from about 800 sccm to about 900 sccm, wherein the pulse time is about 0.5 seconds to about 3 seconds, for example, from about 1.7 seconds to about 2.1 seconds. The flow rate of the second precursor ensures that the WF bonds are broken, thereby having a constant number of fluorine atoms in the tungsten nucleation layer.

[0067] Next, another cleaning process can be performed to remove the second precursor from the process chamber. The cycle of introducing the first precursor into the process chamber, cleaning the process chamber, introducing the second precursor into the process chamber, and cleaning the process chamber can be repeated until the fluorine-containing layer 204 reaches a predetermined thickness. In some embodiments, the number of cycles of the ALD process ranges from about 6 to about 8, and the fluorine-containing layer 204 can have a thickness ranging from about 18 angstroms to about 26 angstroms. Fluorine atoms from the fluorine-containing layer 204 will diffuse into the gate dielectric layer 170 and the IL 169. Therefore, if the thickness of the fluorine-containing layer 204 is less than about 18 angstroms, the number of fluorine atoms in the fluorine-containing layer 204 is insufficient to diffuse into the gate dielectric layer 170 and the IL 169. On the other hand, if the thickness of the fluorine-containing layer 204 is greater than about 26 angstroms, manufacturing costs increase without significant advantages. In some embodiments, each cycle of the ALD process can be performed at a process temperature ranging from about 280 degrees Celsius to about 320 degrees Celsius and a process pressure ranging from about 4 Torr to about 8 Torr.

[0068] Figure 12C-1 is a schematic diagram of a portion of the fluorine-containing layer 204 of the semiconductor device structure 100 according to some embodiments. Figure 12C-1 As shown, the fluorine-containing layer 204 includes fluorine atoms 208 trapped between atoms 206 of a first precursor (e.g., tungsten atoms). For each cycle of the ALD process described above, the number of fluorine atoms 208 trapped between atoms 206 can be substantially constant. As a result, the fluorine concentration of the fluorine-containing layer 204 can be substantially constant relative to the location of the fluorine-containing layer 204. For example, the portion of the fluorine-containing layer 204 surrounding the topmost first semiconductor layer 106 can have the same fluorine concentration as the portion of the fluorine-containing layer 204 surrounding the bottommost first semiconductor layer 106. Furthermore, portions of the fluorine-containing layer 204 located on the sides of the first semiconductor layer 106 can have the same fluorine concentration as portions of the fluorine-containing layer 204 located between vertically adjacent first semiconductor layers 106. Furthermore, the portion of the fluorine-containing layer 204 located in an NMOS device can have the same fluorine concentration as the portion of the fluorine-containing layer 204 located in a PMOS device. In some embodiments, the fluorine-containing layer 204 is a tungsten layer having a substantially constant fluorine concentration.

[0069] Next, an annealing process is performed to drive fluorine from the fluorine-containing layer 204 into the gate dielectric layer 170 and the IL 169. The annealing process can be any suitable annealing process, such as a single wafer anneal or a batch anneal. The annealing process can be performed for about 10 seconds to about 20 seconds at a process temperature ranging from about 480 degrees Celsius to about 520 degrees Celsius. Fluorine atoms in the fluorine-containing layer 204 diffuse through the adhesion layer 202 and into the gate dielectric layer 170. In some embodiments, the fluorine atoms also diffuse through the gate dielectric layer 170 and into the IL 169. Because the fluorine concentration in the fluorine-containing layer 204 is substantially uniform, the fluorine concentration in the gate dielectric layer 170 and the IL 169 is substantially uniform. Better fluorine uniformity can lead to a reduction in Vtσ and a reduction or mitigation of metal boundary effects, which can occur when elements (e.g., dipole materials) at the boundary between NMOS and PMOS devices in gate dielectric layer 170 and IL 169 mix with each other, potentially causing Vt to shift (off target). In some embodiments, as a result of the uniform fluorine concentration in gate dielectric layer 170 and IL 169, both NMOS and PMOS devices have a metal boundary effect gain of about 30 mV to about 50 mV, compared to a metal boundary effect gain of 55 mV to about 80 mV when fluorine is incorporated into gate dielectric layer 170 and IL 169 using conventional processes.

[0070] like Figure 12D As shown, after the annealing process, the fluorine-containing layer 204 and the adhesion layer 202 are removed. The fluorine-containing layer 204 and the adhesion layer 202 may be removed by any suitable process. In some embodiments, a selective etching process is performed to remove the fluorine-containing layer 204 and the adhesion layer 202. The selective etching process may be a dry etching process or a wet etching process and does not substantially affect the gate dielectric layer 170 and the ILD layer 164.

[0071] like Figure 12EAs shown, a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate electrode layer 172 may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. In some embodiments, the gate electrode layer 172 of the NMOS device and the gate electrode layer 172 of the PMOS device are made of different materials and are formed at different times using one or more masks (not shown). For example, the gate electrode layer 172 of the NMOS device may include one or more n-type work function layers. The one or more n-type work function layers may include any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. The gate electrode layer 172 of the PMOS device may include one or more p-type work function layers. The one or more p-type work function layers may include any suitable p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or combinations thereof. The n-type work function layer and the p-type work function layer may be conformal layers formed by a conformal process (e.g., ALD). The gate electrode layer 172 may include a bulk metal for both the NMOS device and the PMOS device. In some embodiments, the bulk metal includes aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, or other suitable metals. The bulk metal may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may be deposited over the upper surface of the ILD layer 164. The gate electrode layer 172 formed over the ILD layer 164 is then removed by, for example, CMP until the top surface of the ILD layer 164 is exposed. The IL 169 , the gate dielectric layer 170 , and the gate electrode layer 172 may be collectively referred to as a gate structure.

[0072] Figures 13A to 13G are cross-sectional side views of various stages in the fabrication of a semiconductor device structure 100 according to an alternative embodiment. Figure 13A As shown, the gate dielectric layer 170 is formed to surround the first semiconductor layer 106. Figures 13A to 13G IL 169 is omitted. Figure 13BAs shown, an n-type work function layer 220 is formed on portions of the gate dielectric layer 170 in the NMOS device, and a p-type work function layer 222 is formed on portions of the gate dielectric layer 170 in the PMOS device. The n-type work function layer 220 and the p-type work function layer 222 may include different materials and may be formed at different times using one or more masks (not shown). The n-type work function layer 220 includes the aforementioned n-type work function material, while the p-type work function layer 222 includes the aforementioned p-type work function material. In some embodiments, the n-type work function layer 220 includes TiAl, while the p-type work function layer 222 includes TiN. The n-type work function layer 220 and the p-type work function layer 222 may be conformal layers formed by a conformal process (e.g., ALD).

[0073] like Figure 13C As shown, a capping layer 224 is deposited on the n-type work function layer 220 and the p-type work function layer 222, an adhesion layer 202 is deposited on the capping layer 224, and a fluorine-containing layer 204 is deposited on the adhesion layer 202. The capping layer 224 includes a material having a high etch selectivity relative to the adhesion layer 202. In some embodiments, the capping layer 224 is a silicon layer, such as an amorphous silicon layer or a polycrystalline silicon layer. The adhesion layer 202 and the fluorine-containing layer 204 can be deposited as described above, so that the fluorine concentration in the fluorine-containing layer 204 is substantially uniform.

[0074] Next, an annealing process is performed to drive fluorine into the capping layer 224, the work function layer 220, the work function layer 222, the gate dielectric layer 170, and the IL 169. Because the fluorine concentration in the fluorine-containing layer 204 is uniform, the fluorine concentration in the capping layer 224, the work function layer 220, the work function layer 222, the gate dielectric layer 170, and the IL 169 is substantially uniform. The work function layer 220 and the work function layer 222 having substantially uniform fluorine concentrations can further reduce metal boundary effects. In some embodiments, the fluorine concentration of the work function layer 220 (or work function layer 222) is significantly greater than the fluorine concentration of the gate dielectric layer 170, and the fluorine concentration of the gate dielectric layer 170 is significantly greater than the fluorine concentration of the IL 169.

[0075] like Figure 13D As shown, the fluorine-containing layer 204 and the adhesion layer 202 are removed. The capping layer 224 protects the n-type work function layer 220 and the p-type work function layer 222 from the etching process that removes the fluorine-containing layer 204 and the adhesion layer 202.

[0076] like Figure 13EAs shown, another n-type work function layer 226 is deposited on portions of the cap layer 224 in the NMOS device, while another p-type work function layer 228 is deposited on portions of the cap layer 224 in the PMOS device. Similar to the n-type work function layer 220 and the p-type work function layer 222, the n-type work function layer 226 and the p-type work function layer 228 include different materials and are formed at different times using one or more masks (not shown).

[0077] In some embodiments, the n-type work function layer 226 and the n-type work function layer 220 comprise different materials, and fluorine may affect the two layers in different ways. For example, when the n-type work function layer 220 is combined with fluorine, the metal boundary effect is reduced. However, fluorine may have an adverse effect on the electrical properties or physical properties of the n-type work function layer 226. Similarly, the p-type work function layer 228 and the p-type work function layer 222 comprise different materials, and fluorine may affect the two layers in different ways. For example, when the p-type work function layer 222 is combined with fluorine, the metal boundary effect is reduced. However, fluorine may have an adverse effect on the electrical properties or physical properties of the p-type work function layer 228. Therefore, in some embodiments, the n-type work function layer 226 and the p-type work function layer 228 are deposited after fluorine is incorporated into each layer. In some embodiments, the n-type work function layer 226 and the p-type work function layer 228 are substantially free of fluorine. In some embodiments, the fluorine concentration increases along the direction from the cap layer 224 to the gate dielectric layer 170 and along the direction from the cap layer 224 to the subsequently formed bulk metal 232 ( Figure 13G ) direction. In other words, in some embodiments, the concentration of fluorine is highest in the cap layer 224 and decreases both inwardly and outwardly. In some embodiments, the fluorine concentration of the n-type work function layer 220 is significantly greater than the fluorine concentration of the n-type work function layer 226, and the fluorine concentration of the p-type work function layer 222 is significantly greater than the fluorine concentration of the p-type work function layer 228. In some embodiments, the n-type work function layer 226 and the p-type work function layer 228 are not present, and a single work function layer is deposited on the cap layer 224. The single work function layer can be a TiN layer. The fluorine concentration in the single work function layer can be significantly less than the fluorine concentration in the n-type work function layer 220 or the p-type work function layer 222. In some embodiments, the single work function layer does not contain fluorine.

[0078] In some embodiments, n-type work function layer 220 includes two or more fluorinated layers, while n-type work function layer 226 includes two or more non-fluorinated layers. Similarly, in some embodiments, p-type work function layer 222 includes two or more fluorinated layers, while p-type work function layer 228 includes two or more non-fluorinated layers.

[0079] like Figure 13FAs shown, another adhesion layer 230 is deposited over n-type work function layer 226 and p-type work function layer 228. Adhesion layer 230 may include the same material as adhesion layer 202 and may be formed using the same process as adhesion layer 202. Next, bulk metal 232 is deposited over adhesion layer 230. In some embodiments, bulk metal 232 does not adhere to n-type work function layer 226 and p-type work function layer 228, and adhesion layer 230 facilitates adhesion to bulk metal 232. In some embodiments, bulk metal 232 is made of or includes tungsten. IL 169, gate dielectric layer 170, work function layer 220, work function layer 226 (or work function layer 222, work function layer 228), cap layer 224, adhesion layer 230, and bulk metal 232 may be collectively referred to as a gate structure. In some embodiments, adhesion layer 230 is optional and is not present in the gate structure.

[0080] Embodiments of the present disclosure provide a method for forming a semiconductor device structure 100. The method includes depositing a fluorine-containing layer 204 using an ALD process such that the fluorine concentration within the fluorine-containing layer 204 is substantially uniform. The fluorine-containing layer 204 can be deposited at any location within the gate structure, and a subsequent annealing process drives the fluorine in the fluorine-containing layer 204 into layers below the fluorine-containing layer 204 (e.g., the gate dielectric layer 170 and the IL 169). Some embodiments can achieve various advantages. For example, because the fluorine-containing layer 204 has a uniform fluorine concentration, the fluorine concentration in the gate dielectric layer 170 and the IL 169 is substantially uniform. The gate dielectric layer 170 and the IL 169 having a uniform fluorine concentration can contribute to a reduction in metal boundary effects and a reduction in Vtσ.

[0081] One embodiment is a method. The method includes forming a fin structure from a substrate, wherein the fin structure includes a plurality of semiconductor layers. The method also includes depositing a gate dielectric layer around a portion of each of the plurality of semiconductor layers; depositing an adhesion layer on the gate dielectric layer, wherein the adhesion layer surrounds the portion of each of the plurality of semiconductor layers. The method also includes depositing a fluorine-containing layer on the adhesion layer, wherein the fluorine-containing layer surrounds the portion of each of the plurality of semiconductor layers. The method also includes annealing the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; and forming a gate electrode layer on the gate dielectric layer.

[0082] Another embodiment is a method. The method includes forming a first fin structure and a second fin structure from a substrate, the first fin structure including a first plurality of semiconductor layers, and the second fin structure including a second plurality of semiconductor layers. The method also includes depositing a gate dielectric layer around a portion of each semiconductor layer in the first plurality of semiconductor layers; depositing a first work function layer on portions of the gate dielectric layer surrounding the portions of each semiconductor layer in the first plurality of semiconductor layers; depositing an adhesion layer over the first work function layer; depositing a fluorine-containing layer over the adhesion layer; performing an annealing process on the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; depositing a second work function layer over the first work function layer; and depositing a bulk metal over the second work function layer.

[0083] Another embodiment provides a semiconductor device structure. The structure includes a substrate portion extending from a substrate, a semiconductor layer disposed over the substrate portion, and a gate dielectric layer surrounding at least a portion of the semiconductor layer, wherein the gate dielectric layer has a first fluorine concentration. The structure also includes a first work function layer surrounding the gate dielectric layer, wherein the first work function layer has a second fluorine concentration greater than the first fluorine concentration. The structure also includes a second work function layer surrounding the first work function layer, wherein the second work function layer has a third fluorine concentration less than the second fluorine concentration.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: forming a fin structure from a substrate, wherein the fin structure comprises a plurality of semiconductor layers; depositing a gate dielectric layer around a portion of each semiconductor layer of the plurality of semiconductor layers; depositing an adhesion layer on the gate dielectric layer, wherein the adhesion layer surrounds the portion of each semiconductor layer in the plurality of semiconductor layers; depositing a fluorine-containing layer on the adhesion layer, wherein the fluorine-containing layer surrounds the portion of each semiconductor layer in the plurality of semiconductor layers; annealing the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; and A gate electrode layer is formed on the gate dielectric layer.

2. The method according to claim 1, wherein The fluorine-containing layer is formed by an atomic layer deposition process.

3. The method according to claim 2, wherein: The atomic layer deposition process includes a plurality of cycles, and each cycle includes introducing a first precursor into a processing chamber and introducing a second precursor into the processing chamber.

4. The method according to claim 3, wherein: The first precursor includes WF6, and the second precursor includes B2H6 or SiH4.

5. The method according to claim 3, wherein: The first precursor has a flow rate ranging from about 20 sccm to about 100 sccm, and the second precursor has a flow rate ranging from about 200 sccm to about 1500 sccm.

6. The method according to claim 1, wherein The fluorine-containing layer has a thickness ranging from about 18 angstroms to about 26 angstroms. 7 . The method of claim 1 , further comprising performing a treatment process after depositing the adhesion layer and before depositing the fluorine-containing layer.

8. The method according to claim 7, wherein: The treatment process removes oxide from the adhesion layer.

9. A method comprising: forming a first fin structure and a second fin structure from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers and the second fin structure includes a second plurality of semiconductor layers; depositing a gate dielectric layer around a portion of each semiconductor layer in the first plurality of semiconductor layers; depositing a first work function layer on portions of the gate dielectric layer surrounding the portions of each semiconductor layer of the first plurality of semiconductor layers; depositing an adhesion layer on the first work function layer; depositing a fluorine-containing layer on the adhesion layer; annealing the fluorine-containing layer; removing the fluorine-containing layer and the adhesion layer; depositing a second work function layer on the first work function layer; and A bulk metal is deposited over the second work function layer.

10. A semiconductor device structure comprising: a substrate portion extending from the substrate; a semiconductor layer disposed on the substrate portion; a gate dielectric layer surrounding at least a portion of the semiconductor layer, wherein the gate dielectric layer has a first fluorine concentration; a first work function layer surrounding the gate dielectric layer, wherein the first work function layer has a second fluorine concentration greater than the first fluorine concentration; and A second work function layer surrounds the first work function layer, wherein the second work function layer has a third fluorine concentration that is less than the second fluorine concentration.

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