Semiconductor device
By providing a second conductive portion and an n-type semiconductor region with a high impurity concentration in the semiconductor device, the impact ionization problem when the semiconductor device is turned off is solved, and the avalanche resistance and voltage withstand performance are improved.
Patent Information
- Application Number
- CN202411141789.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-14
- Filing Date
- 2024-08-20
- Publication Date
- 2025-09-19
AI Technical Summary
Conventional semiconductor devices are prone to parasitic transistor activation due to impact ionization when turned off, leading to avalanche breakdown and excessive current, affecting the device's durability.
A second conductive portion is provided in the semiconductor device with its lower end located below the first conductive portion, and an n-type semiconductor region with a high impurity concentration is provided therebetween to suppress the occurrence of impact ionization. At the same time, the width and depth of the conductive portion are optimized to control the expansion of the depletion layer.
The generation of parasitic transistors is effectively suppressed, and the avalanche resistance and voltage withstand performance of the semiconductor device are improved.
Smart Images
Figure CN120676672A_ABST
Abstract
Description
[0001] Related applications
[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2024-040229 (filing date: March 14, 2024), the entire contents of which are incorporated herein by reference. Technical Field
[0003] Embodiments of the present invention generally relate to semiconductor devices. Background Art
[0004] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. Semiconductor devices preferably have a high durability. Summary of the Invention
[0005] Embodiments provide a semiconductor device capable of improving durability.
[0006] According to one embodiment, a semiconductor device includes: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the first conductivity type; a first conductive portion; a fourth semiconductor region of the second conductivity type; a fifth semiconductor region of the first conductivity type; and a second electrode. The first semiconductor region is provided on the first electrode. The first semiconductor region includes a first portion and a second portion located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region. The second semiconductor region is provided on the first portion. The third semiconductor region is provided on the second semiconductor region. The first conductive portion opposes the second semiconductor region in a second direction perpendicular to the first direction, with a first insulating layer interposed therebetween. The fourth semiconductor region is provided on the second portion. The second conductive portion opposes the fourth semiconductor region in the second direction, with a second insulating layer interposed therebetween. The lower end of the second conductive portion is located below the lower end of the first conductive portion. The fifth semiconductor region is provided between the second portion and the lower end of the second conductive portion. The fifth semiconductor region has a higher first conductivity type impurity concentration than the second portion. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 It is a top view showing a semiconductor device according to an embodiment.
[0008] Figure 2It will Figure 1 An enlarged perspective sectional view of part II.
[0009] Figure 3 yes Figure 1 Sectional view III-III.
[0010] Figure 4 (a) and Figure 4 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0011] Figure 5 (a) and Figure 5 (b) is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0012] Figure 6 It is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0013] Figure 7 It will Figure 3 An enlarged sectional view of a portion of FIG.
[0014] Figure 8 It is a cross-sectional view showing a portion of a semiconductor device according to a modification of the embodiment.
[0015] Figure 9 It will Figure 8 An enlarged cross-sectional view of a portion of the DETAILED DESCRIPTION
[0016] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. may not necessarily be the same as in reality. In addition, even when representing the same part, there are cases where the sizes and ratios of each other are represented differently depending on the drawings. In this application specification and each figure, the same reference numerals are marked for elements that are identical to those already described, and detailed descriptions are omitted as appropriate.
[0017] In the following description and drawings, n + 、n、n - and p + 、p - The symbols indicate the relative levels of each impurity concentration. Specifically, a symbol marked with a "+" indicates a higher impurity concentration than a symbol not marked with either a "+" or a "-," and a symbol marked with a "-" indicates a lower impurity concentration than a symbol not marked with either a "+" or a "-." When each region contains both p-type and n-type impurities, these symbols indicate the relative levels of the actual impurity concentration after these impurities compensate for each other.
[0018] Each embodiment described below may be implemented by inverting the p-type and n-type properties of each semiconductor region.
[0019] Figure 1 It is a top view showing a semiconductor device according to an embodiment. Figure 2 It will Figure 1 An enlarged perspective sectional view of part II. Figure 3 yes Figure 1 Sectional view III-III.
[0020] The semiconductor device 100 of the embodiment is a MOSFET. Figures 1 to 3 As shown, the semiconductor device 100 includes n - Type (first conductivity type) drift region 1 (first semiconductor region), p - Type (second conductivity type) base region 2 (second semiconductor region), n + Type source region 3 (third semiconductor region), p - type semiconductor region 4 (fourth semiconductor region), n-type semiconductor region 5 (fifth semiconductor region), n + Type drain region 6, p - The semiconductor region 7, the first conductive portion 11, the first insulating layer 11a, the second conductive portion 12, the second insulating layer 12a, the drain electrode 21 (first electrode), the source electrode 22 (second electrode), and the gate pad 23. Figure 2 In FIG, the source electrode 22 is indicated by a dotted line.
[0021] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction of the drift region 1 is defined as the Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction of the drift region 1 is called "up", and the opposite direction is called "down". These directions are based on the relationship between the drain electrode 21 and the n - The relative position relationship of the drift area 1 is independent of the direction of gravity.
[0022] like Figure 1 As shown, a source electrode 22 and a gate pad 23 are provided on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are separated from each other and electrically isolated.
[0023] like Figure 2 As shown in FIG. 1 , a drain electrode 21 is provided on the lower surface of the semiconductor device 100. + The type drain region 6 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21.- Type drift region 1 is set at n + Type drain region 6. n - Type drift region 1 via n + The type drain region 6 is electrically connected to the drain electrode 21. - The n-type impurity concentration in the drift region 1 is n + The n-type impurity concentration in the n-type drain region 6 is low.
[0024] like Figures 1 to 3 As shown, n - The drift region 1 includes a first portion 1a and a second portion 1b. The second portion 1b is located around the first portion 1a on the XY plane (first surface). The first portion 1a is located in the cell region. The cell region is the area where current primarily flows during operation of the semiconductor device 100. The second portion 1b is located in the termination region. The termination region is the area where the depletion layer extends toward the periphery of the semiconductor device 100 when the semiconductor device 100 is at its withstand voltage.
[0025] like Figure 2 and Figure 3 As shown, p - The mold base region 2 is arranged above the first portion 1a. + Type source region 3 is set in p - The first conductive portion 11 is provided on the first portion 1a via the first insulating layer 11a. The first conductive portion 11 is separated from the p-type substrate region 2 in the X direction by the first insulating layer 11a. - The mold base area 2 is opposite.
[0026] like Figure 3 As shown, p - The second conductive portion 12 is provided on the second portion 1b via the second insulating layer 12a. The second conductive portion 12 is provided on the second portion 1b via the second insulating layer 12a. - The second conductive portion 12 is located opposite to the first conductive portion 11 .
[0027] In p - No n-type semiconductor region 4 is provided. + n-type semiconductor region such as the n-type source region 3. For example, in the p - The upper portion of the semiconductor region 4 is connected to the n-type semiconductor region 4 in the X direction. + There is no n-type semiconductor region at the position parallel to the source region 3, and there is a p-type semiconductor region. - type semiconductor region 4.
[0028] The n-type semiconductor region 5 is provided between the second portion 1b and the lower end of the second conductive portion 12. The n-type impurity concentration in the n-type semiconductor region 5 is higher than that in the second portion 1b. The n-type semiconductor region 5 is preferably formed from p - type semiconductor region 4 is separated.
[0029] like Figure 3 As shown, p - The type semiconductor region 7 is provided on the second portion 1b. - The semiconductor region 4 is located in the p-type region in the X direction. - Type matrix region 2 and p - The second conductive portion 12 is located between the p-type semiconductor regions 7. - Type semiconductor region 4 and p - Type semiconductor region 7. - The length ratio p of the semiconductor region 7 in the X direction is - The length of the semiconductor region 4 in the X direction is long.
[0030] The source electrode 22 is provided on the p - Type matrix area 2, n + Type source region 3, p - type semiconductor region 4, and p - The source electrode 22 is on the p-type semiconductor region 7. - Type matrix area 2, n + Type source region 3, p - type semiconductor region 4, and p - type semiconductor region 7 is electrically connected.
[0031] The first conductive portion 11 and the source electrode 22 are electrically separated from each other by an insulating layer 11 b . The second conductive portion 12 and the source electrode 22 are electrically separated from each other by an insulating layer 12 b . The first conductive portion 11 and the second conductive portion 12 are electrically connected to a gate pad 23 .
[0032] like Figure 2 and Figure 3 As shown, p - Type matrix area 2, n + A plurality of the type source regions 3 and the first conductive portions 11 are respectively provided on the first portion 1a along the X direction. - Type matrix region 2, p - The semiconductor region 4, the first conductive portion 11 and the second conductive portion 12 extend in the Y direction. - The type base region 2 and the plurality of first conductive parts 11 are arranged alternately.
[0033] exist Figure 3FIG. 1 shows the structure of one end side of the semiconductor device 100 in the X direction. The structure of the other end side of the semiconductor device 100 in the X direction is similar to that of FIG. Figure 3 The structure shown is substantially bilaterally symmetrical. That is, one second conductive portion 12 is provided at one end side of the semiconductor device 100 in the X direction, and another second conductive portion 12 is provided at the other end side of the semiconductor device 100 in the X direction. - Type matrix area 2, multiple n + The type source region 3 and the plurality of first conductive portions 11 are located between a pair of second conductive portions 12 separated from each other in the X direction.
[0034] like Figure 2 As shown, p - The p-type base region 2 may also include a contact region 2a with a high p-type impurity concentration. Figure 3 As shown, p - The p-type semiconductor region 4 may also include a contact region 4a with a high p-type impurity concentration. - The p-type semiconductor region 7 may include a contact region 7a having a high p-type impurity concentration. The contact region 2a, the contact region 4a, and the contact region 7a are in contact with the source electrode 22.
[0035] like Figure 2 As shown, in a p - On the base region 2, a plurality of contact regions 2a and a plurality of n + Type source regions 3 are arranged alternately in the Y direction. + The length Ls of the source region 3 in the Y direction is longer than the length Lb of the contact region 2a in the Y direction. The length Lb corresponds to the length of the n adjacent regions in the Y direction. + The distance between the type source regions 3.
[0036] The operation of the semiconductor device 100 will be described. In a state where a positive voltage is applied to the drain electrode 21 relative to the source electrode 22, a voltage greater than a threshold value is applied to the first conductive portion 11. - The channel (inversion layer) is formed in the n-type matrix region 2. Electrons pass through the channel from the source electrode 22 to the n-type matrix region 2. - The type drift region 1 flows, and the semiconductor device 100 becomes conductive. Afterwards, if the voltage applied to the first conductive portion 11 is lower than the threshold, the p - The channel in the base region 2 disappears, and the semiconductor device 100 enters the off state. The first conductive portion 11 functions as a gate electrode for controlling the flow of current in the semiconductor device 100 .
[0037] In p -There is no n-type semiconductor region electrically connected to the source electrode 22 on the n-type semiconductor region 4. Therefore, even when a voltage higher than a threshold value is applied to the second conductive portion 12, the p - No current flows in the inversion layer of the CMOS semiconductor region 4 either.
[0038] An example of the material of each component is described. - Type drift region 1, p - Type matrix area 2, n + Type source region 3, p - type semiconductor region 4, n-type semiconductor region 5, n + type drain region 6, and p - The n-type semiconductor region 7 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The first conductive portion 11 and the second conductive portion 12 include a conductive material such as polycrystalline silicon. The first insulating layer 11a, the insulating layer 11b, the second insulating layer 12a, and the insulating layer 12b include an insulating material such as silicon oxide. The drain electrode 21, the source electrode 22, and the gate pad 23 include a metal such as titanium, gold, or aluminum.
[0039] The preferred range of the impurity concentration of each semiconductor region is as follows. - The n-type impurity concentration in the drift region 1 is 1.0×10 16 atom / cm 3 Above and 1.0×10 18 atom / cm 3 Below. - Type matrix region 2, p - type semiconductor region 4, and p - The n-type impurity concentration in the semiconductor region 7 is 1.0×10 17 atom / cm 3 Above and 1.0×10 19 atom / cm 3 Below. + The n-type impurity concentration in the source region 3 is 5.0×10 18 atom / cm 3 Above and 5.0×10 20 atom / cm 3 The n-type impurity concentration in the contact region 2a, the contact region 4a, and the contact region 7a is 5.0×10 18 atom / cm 3 Above and 5.0×10 20 atom / cm 3 Below. +The n-type impurity concentration in the drain region 6 is 1.0×10 19 atom / cm 3 Above and 1.0×10 21 atom / cm 3 the following.
[0040] Figure 4 (a) Figure 4 (b) Figure 5 (a) Figure 5 (b) and Figure 6 It is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0041] An example of a method for manufacturing the semiconductor device 100 is described. First, a semiconductor device including n - Type drift regions 1 and n + The semiconductor substrate Sub of the type drain region 6. Figure 4 As shown in (a), in n - A plurality of openings OP1 are formed on the upper surface of the drift region 1. The plurality of openings OP1 are arranged in the X direction, and each opening OP1 extends in the Y direction. - An opening OP2 is formed on the upper surface of the drift region 1. The opening OP2 is formed deeper than the opening OP1. The opening OP2 is located outside the region where the semiconductor device 100 is formed relative to the plurality of openings OP1.
[0042] The semiconductor substrate Sub is thermally oxidized. As a result, the inner surface of the opening OP1, the inner surface of the opening OP2, and the n - An insulating layer 10a is formed on the upper surface of the drift region 1. Figure 4 As shown in FIG. 5 ( b ), n-type impurities are ion-implanted into the bottom of the opening OP2 to form the n-type semiconductor region 5 .
[0043] A polysilicon layer is formed by chemical vapor deposition (CVD) to fill the opening OP1 and the opening OP2. The upper surface of the polysilicon layer is retreated by etching. Figure 5 As shown in (a) of FIG. 1 , the first conductive portion 11 is formed inside the opening OP1 , and the second conductive portion 12 is formed inside the opening OP2 .
[0044] Ion implantation of p-type impurities and n-type impurities is done sequentially. - The upper part of the drift region 1 forms a p - Type matrix area 2, n + Type source region 3, p - type semiconductor region 4, and p - The insulating layer 10b covering these semiconductor regions is formed by CVD. Figure 5 As shown in (b), n+ Type source region 3, p - Type semiconductor region 4, and p - The insulating layer 10b and the insulating layer 10a are etched so that the upper surface of the type semiconductor region 7 is exposed.
[0045] A metal layer is formed by CVD, sputtering, etc. The metal layer is patterned to form a source electrode 22 and a gate pad 23 (not shown). + The lower surface of the drain region 6 is ground until n + The drain region 6 has a predetermined thickness. Figure 6 As shown, after grinding, n + The drain electrode 21 is formed by sputtering on the lower surface of the type drain region 6. As described above, the semiconductor device 100 of the embodiment is manufactured.
[0046] Advantages of the embodiment will be described.
[0047] The semiconductor device 100 includes n - Type drift region 1, p - Type matrix region 2, and n + The parasitic transistor is formed by the n-type source region 3. When the semiconductor device 100 is turned off, impact ionization (avalanche breakdown) occurs inside the semiconductor device 100. A large number of carriers (electrons and holes) are generated by the impact ionization. Electrons pass through n - The holes are discharged to the drain electrode 21 through the p-type drift region 1. - type base region 2, and discharged to the source electrode 22. At this time, if p - The potential of the base region 2 increases due to the holes, and the parasitic transistor can operate. If a large current flows through the semiconductor device 100 due to the operation of the parasitic transistor, the semiconductor device 100 may be destroyed. Therefore, it is desirable that the parasitic transistor is difficult to operate.
[0048] The semiconductor device 100 includes a first conductive portion 11 and a second conductive portion 12. When the semiconductor device 100 is turned off, the n - The potential difference between the drift region 1 and the first conductive portion 11, and n - The potential difference between the drift region 1 and the second conductive portion 12 generates impact ionization near the lower end of the first conductive portion 11 and near the lower end of the second conductive portion 12. In particular, in the semiconductor device 100, the lower end of the second conductive portion 12 is located below the lower end of the first conductive portion 11. Therefore, when the semiconductor device 100 is turned off, impact ionization primarily occurs near the lower end of the second conductive portion 12.
[0049] When impact ionization occurs near the lower end of the second conductive portion 12, holes mainly move to the p - Type semiconductor region 4 and p - type semiconductor region 7 flows. - type semiconductor region 4 and p - No n-type semiconductor region 7 is provided. + n-type semiconductor region such as the n-type source region 3. + The height of the source region 3 (position in the Z direction) is p - A portion of the p-type semiconductor region 4 and - Part of the type semiconductor region 7. That is, in the case of a p - Type semiconductor region 4 and p - No parasitic transistor exists in the region of the semiconductor region 7. By providing the second conductive portion 12, the generation of a parasitic transistor in the semiconductor device 100 can be suppressed, thereby improving the avalanche resistance of the semiconductor device 100.
[0050] On the other hand, when the lower end of the second conductive portion 12 is located below the lower end of the first conductive portion 11, the second conductive portion 12 and the n + The distance between the type drain region 6 is greater than the distance between the first conductive portion 11 and the n + The distance between the n-type drain region 6 is short. In the region below the second conductive portion 12, the depletion layer easily reaches the n-type drain region 6. + type drain region 6, resulting in a decrease in the breakdown voltage of the semiconductor device 100.
[0051] To address this issue, in the embodiment, an n-type semiconductor region 5 is provided between the second portion 1b and the second conductive portion 12. The n-type impurity concentration in the n-type semiconductor region 5 is higher than that in the second portion 1b. The provision of the n-type semiconductor region 5 suppresses the expansion of the depletion layer in the region below the second conductive portion 12. This can thereby suppress a decrease in the breakdown voltage of the semiconductor device 100.
[0052] According to the embodiment, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device 100 and improve the avalanche withstand capability of the semiconductor device 100 .
[0053] Figure 7 It will Figure 3 An enlarged sectional view of a portion of FIG.
[0054] The width W2 of the second conductive portion 12 may also be the same as the width W1 of the first conductive portion 11. Alternatively, Figure 7As shown, the width W2 of the second conductive portion 12 may also be wider than the width W1 of the first conductive portion 11. The width is the length in the X direction. When the width W2 is wider than the width W1, impact ionization is more likely to occur near the lower end of the second conductive portion 12. As a result, the avalanche resistance of the semiconductor device 100 can be further improved. For example, the width W2 is preferably 1.01 times or more and 3 times or less of the width W1, and more preferably 1.02 times or more and 2 times or less. In addition, when the width of the first conductive portion 11 or the second conductive portion 12 changes in the Z direction, the width W2 is preferably 1.01 times or more and 3 times or less of the width W1, and more preferably 1.02 times or more and 2 times or less of the width W1. - Type drift region 1 and p - The height at which the pn junction exists between the type base regions 2 is measured as width W1 or width W2.
[0055] As described above, the lower end of the second conductive portion 12 is located below the lower end of the first conductive portion 11. For example, the depth D2 of the second conductive portion 12 is greater than the depth D1 of the first conductive portion 11. The depth D1 corresponds to the depth D2 of the second conductive portion 12 from n + The depth D2 is the distance in the Z direction from the upper surface of the p-type source region 3 to the lower end of the first conductive portion 11. - The depth D2 is the distance in the Z direction from the upper surface of the n-type semiconductor region 4 to the lower end of the second conductive portion 12. The longer the depth D2, the more likely impact ionization occurs near the lower end of the second conductive portion 12. On the other hand, if the depth D2 is too long, the withstand voltage of the semiconductor device 100 will decrease even if the n-type semiconductor region 5 is provided. For example, the depth D2 is preferably 1.01 times or more and 1.3 times or less of the depth D1, and more preferably 1.02 times or more and 1.2 times or less.
[0056] Distance d2 can be the same as distance d1 or longer than distance d1. Distance d1 is the distance between adjacent first conductive portions 11 in the X direction. Distance d2 is the distance in the X direction between the second conductive portion 12 and the first conductive portion 11 adjacent to the second conductive portion 12. Distance d2 can be different from distance d1 or the same as distance d1. The difference between distance d1 and distance d2 is preferably small. If distance d2 is too short compared to distance d1, p - The width of the p-type semiconductor region 4 becomes smaller, and it is difficult for holes to pass through the p-type semiconductor region 4. - The type semiconductor region 4 is discharged. If the distance d2 is too long compared to the distance d1, the second conductive portion 12 is separated from the first conductive portion 11, and impact ionization is likely to occur near the lower end of the first conductive portion 11. For example, the distance d2 is preferably 0.78 times or more and 1.5 times or less of the distance d1, and more preferably 0.85 times or more and 1.2 times or less. It is most preferred that the distance d1 and the distance d2 are the same. In addition, when the distance d1 or the distance d2 changes in the Z direction, the distance d2 is n - Type drift region 1 and p -The height at which the pn junction exists between the type base regions 2 is measured as the distance d1 or the distance d2.
[0057] The higher the n-type impurity concentration in the n-type semiconductor region 5, the more the extension of the depletion layer in the region below the second conductive portion 12 can be suppressed. On the other hand, if the n-type impurity concentration in the n-type semiconductor region 5 is too high, the electric field concentrates near the n-type semiconductor region 5, and the withstand voltage of the semiconductor device 100 may be reduced. Therefore, the n-type impurity concentration in the n-type semiconductor region 5 is preferably n - The concentration of the n-type impurity is preferably 8 times or more and 300 times or less, and more preferably 10 times or more and 100 times or less, the concentration of the n-type impurity in the drift region 1 .
[0058] (Variation)
[0059] Figure 8 It is a cross-sectional view showing a portion of a semiconductor device according to a modification of the embodiment.
[0060] Figure 8 The semiconductor device 110 shown in the figure further includes a third conductive portion 13 compared to the semiconductor device 100. The third conductive portion 13 is provided on the second portion 1b. The third conductive portion 13 is located between the first conductive portion 11 and the second conductive portion 12 in the X direction. A p is provided between the first conductive portion 11 and the third conductive portion 13. - Type semiconductor region 4. Another p-type semiconductor region 4 is provided between the second conductive portion 12 and the third conductive portion 13. - The third conductive portion 13 is separated from each p-type semiconductor region 4 by a third insulating layer 13a in the X direction. - The third conductive portion 13 and the source electrode 22 are electrically isolated from each other by the insulating layer 13b. The third conductive portion 13 is electrically connected to the gate pad 23.
[0061] Figure 9 It will Figure 8 An enlarged cross-sectional view of a portion of the
[0062] like Figure 9 As shown, the lower end of the third conductive portion 13 is located above the lower end of the second conductive portion 12. The lower end of the third conductive portion 13 may also be located above the lower end of the first conductive portion 11. By locating the lower end of the third conductive portion 13 above the lower end of the second conductive portion 12, impact ionization is less likely to occur near the lower end of the third conductive portion 13. The third conductive portion 13 is closer to n than the second conductive portion 12. + The third conductive portion 13 is located at a distance from the parasitic transistor 3. That is, the distance between the third conductive portion 13 and the parasitic transistor is shorter than the distance between the second conductive portion 12 and the parasitic transistor. By suppressing the impact ionization near the lower end of the third conductive portion 13, the holes generated by the impact ionization can be suppressed from being transferred to the p-type source region 3.- The type base region 2 flows. This can improve the avalanche resistance of the semiconductor device 110.
[0063] The depth D3 of the third conductive portion 13 is shorter than the depth D1 and shorter than the depth D2. + The depth D3 is the distance in the Z direction from the upper surface of the source region 3 to the lower end of the third conductive portion 13. For example, the depth D3 is preferably 0.85 times or more and 0.99 times or less of the depth D1, and more preferably 0.95 times or more and 0.99 times or less.
[0064] The width W3 of the third conductive portion 13 is narrower than the width W2. Width W3 can be the same as width W1, or, as shown, narrower than width W1. When width W3 is narrower than width W2, impact ionization is less likely to occur near the lower end of the third conductive portion 13. This further improves the avalanche withstand capability of the semiconductor device 110. For example, width W3 is preferably 0.75 times or greater and 0.98 times or less of width W2, and more preferably 0.85 times or greater and 0.95 times or less.
[0065] The distance d3 may be the same as or different from the distance d1. The distance d3 is the distance in the X direction between the third conductive portion 13 and the first conductive portion 11 adjacent to the third conductive portion 13. The difference between the distance d1 and the distance d3 is preferably small. If the distance d3 is too short than the distance d1, then p - The width of the p-type semiconductor region 4 becomes smaller, and it is difficult for holes to pass through the p-type semiconductor region 4. - The first conductive portion 11 is discharged from the semiconductor region 4. If the distance d3 is too long compared to the distance d1, impact ionization is likely to occur near the lower end of the first conductive portion 11. For example, the distance d3 is preferably 0.85 times or more and 1.15 times or less of the distance d1, and more preferably 0.95 times or more and 1.05 times or less. Most preferably, the distance d1 and the distance d3 are equal.
[0066] The distance d4 can be the same as the distance d1 or Figure 9 As shown, it is longer than the distance d1. In the semiconductor device 110, the lower end of the third conductive portion 13 is located above the lower end of the first conductive portion 11 and the lower end of the second conductive portion 12. Therefore, impact ionization is more likely to occur near the lower end of the second conductive portion 12 adjacent to the third conductive portion 13 than in the semiconductor device 100. As the distance d4 is long, p - The width of the semiconductor region 4 is wide, which can effectively discharge a large number of holes generated by impact ionization. For example, the distance d4 is preferably greater than 1.0 times and less than 1.5 times the distance d1, and more preferably greater than 1.02 times and less than 1.2 times.
[0067] Embodiments of the present invention include the following features.
[0068] (Feature 1)
[0069] A semiconductor device comprising:
[0070] a first electrode;
[0071] a first semiconductor region of a first conductivity type, disposed on the first electrode, comprising a first portion and a second portion, wherein the second portion is located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region;
[0072] a second semiconductor region of a second conductivity type, disposed on the first portion;
[0073] a third semiconductor region of the first conductivity type, disposed on the second semiconductor region;
[0074] a first conductive portion facing the second semiconductor region via a first insulating layer in a second direction perpendicular to the first direction;
[0075] a fourth semiconductor region of the second conductivity type, disposed on the second portion;
[0076] a second conductive portion, facing the fourth semiconductor region with the second insulating layer interposed therebetween in the second direction, and having a lower end located below the lower end of the first conductive portion;
[0077] a fifth semiconductor region of the first conductivity type, provided between the second portion and the lower end of the second conductive part, and having a higher first conductivity type impurity concentration than the second portion; and
[0078] The second electrode is disposed on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region.
[0079] (Feature 2)
[0080] The semiconductor device according to feature 1,
[0081] The length of the second conductive portion in the second direction is longer than the length of the first conductive portion in the second direction.
[0082] (Feature 3)
[0083] The semiconductor device according to feature 1 or 2,
[0084] further comprising a third conductive portion located between the first conductive portion and the second conductive portion in the second direction,
[0085] The third conductive portion faces the fourth semiconductor region with a third insulating layer interposed therebetween in the second direction.
[0086] (Feature 4)
[0087] The semiconductor device according to feature 3,
[0088] The lower end of the second conductive portion is located below a lower end of the third conductive portion.
[0089] (Feature 5)
[0090] The semiconductor device according to feature 4,
[0091] The lower end of the third conductive portion is located above the lower end of the first conductive portion.
[0092] (Feature 6)
[0093] The semiconductor device according to any one of features 3 to 5,
[0094] The length of the third conductive portion in the second direction is shorter than the length of the first conductive portion in the second direction, and shorter than the length of the second conductive portion in the second direction.
[0095] (Feature 7)
[0096] The semiconductor device according to any one of features 3 to 6,
[0097] A distance between the second conductive portion and the third conductive portion in the second direction is longer than a distance between the first conductive portion and the third conductive portion in the second direction.
[0098] (Feature 8)
[0099] The semiconductor device according to any one of features 1 to 7,
[0100] A pair of second conductive portions are provided that are separated from each other in the second direction,
[0101] The plurality of second semiconductor regions and the plurality of first conductive portions are alternately arranged in the second direction and are located between the pair of second conductive portions.
[0102] The relative height of the impurity concentration between each semiconductor region in each embodiment described above can be confirmed using, for example, a scanning electrostatic capacitance microscope (SCM). In addition, the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).
[0103] Several embodiments of the present invention have been described above, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the scope of the invention described in the claims and their equivalents. In addition, the above-mentioned embodiments can also be combined with each other for implementation.
Claims
1. A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type, disposed on the first electrode, comprising a first portion and a second portion, wherein the second portion is located around the first portion along a first plane perpendicular to a first direction from the first electrode toward the first semiconductor region; a second semiconductor region of a second conductivity type, disposed on the first portion; a third semiconductor region of the first conductivity type, disposed on the second semiconductor region; a first conductive portion facing the second semiconductor region via a first insulating layer in a second direction perpendicular to the first direction; a fourth semiconductor region of the second conductivity type, disposed on the second portion; a second conductive portion, facing the fourth semiconductor region with the second insulating layer interposed therebetween in the second direction, and having a lower end located below the lower end of the first conductive portion; a fifth semiconductor region of the first conductivity type, provided between the second portion and the lower end of the second conductive portion, and having a higher first conductivity type impurity concentration than the second portion; as well as The second electrode is disposed on the second semiconductor region, the third semiconductor region, and the fourth semiconductor region.
2. The semiconductor device according to claim 1, The length of the second conductive portion in the second direction is longer than the length of the first conductive portion in the second direction.
3. The semiconductor device according to claim 1, further comprising a third conductive portion located between the first conductive portion and the second conductive portion in the second direction, The third conductive portion faces the fourth semiconductor region with a third insulating layer interposed therebetween in the second direction.
4. The semiconductor device according to claim 3, The lower end of the second conductive portion is located below a lower end of the third conductive portion.
5. The semiconductor device according to claim 4, The lower end of the third conductive portion is located above the lower end of the first conductive portion.
6. The semiconductor device according to claim 3, The length of the third conductive portion in the second direction is shorter than the length of the first conductive portion in the second direction, and shorter than the length of the second conductive portion in the second direction.
7. The semiconductor device according to claim 3, A distance between the second conductive portion and the third conductive portion in the second direction is longer than a distance between the first conductive portion and the third conductive portion in the second direction.
8. The semiconductor device according to claim 1, A pair of second conductive portions are provided that are separated from each other in the second direction, The plurality of second semiconductor regions and the plurality of first conductive portions are alternately arranged in the second direction and are located between the pair of second conductive portions.
Citation Information
Patent Citations
Composition for forming protective film containing specific crosslinking agent and pattern forming method using the same
JP2024040229A