Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate which comprises a first region and a second region; the gate structures comprise a first gate structure located on the first region and a second gate structure located on the second region, and the first gate structure comprises a channel layer, a first gate dielectric layer, a first barrier layer and a first metal layer which are sequentially stacked from bottom to top; wherein the first gate dielectric layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked from bottom to top, the first sub-layer and the second sub-layer both comprise IV-group elements which are the same as those of the channel layer, and the proportion of N elements in the first sub-layer is higher than that of N elements in the second sub-layer. The electrical performance of the gate structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In order to enhance the performance of a MOS (Metal-Oxide-Semiconductor) transistor, a stress material may be formed in the channel region of the MOS transistor to improve carrier mobility.

[0003] The stress material used in the channel region of the PMOS transistor is silicon germanium. The silicon germanium material in the channel region introduces compressive strain, which can improve the mobility of holes in the PMOS transistor.

[0004] However, the surface characteristics of the channel region of the existing silicon germanium material still need to be improved, which affects the electrical performance of the gate structure. Summary of the Invention

[0005] Based on this, the present application provides a semiconductor device and a method for manufacturing the same to improve the electrical performance of the gate structure in the channel layer.

[0006] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising:

[0007] a substrate comprising a plurality of active regions defined by isolation trenches;

[0008] A plurality of first gate structures, located on the active area, comprising a channel layer, a first gate dielectric layer, a first barrier layer and a first metal layer stacked in sequence from bottom to top;

[0009] Among them, the first gate dielectric layer includes a first sublayer and a second sublayer stacked in sequence from bottom to top, the first sublayer and the second sublayer both include the same Group IV element as the channel layer, and the proportion of N elements in the first sublayer is higher than the proportion of N elements in the second sublayer.

[0010] In some embodiments of the present application, the proportion of O element in the second sublayer is higher than the proportion of O element in the first sublayer, and the first sublayer directly contacts the top surface of the channel layer and the bottom surface of the second sublayer.

[0011] In some embodiments of the present application, the channel layer includes a silicon germanium layer, and the concentration of germanium in the silicon germanium layer increases in a gradient or gradually in a direction away from the top surface of the substrate.

[0012] In some embodiments of the present application, the first gate dielectric layer further includes:

[0013] The third sublayer is located between the second sublayer and the first barrier layer, and the third sublayer is a high dielectric constant material layer.

[0014] In some embodiments of the present application, a plurality of second gate structures are further included, located on the active area, the second gate structure including a second gate dielectric layer, a second barrier layer, and a second metal layer stacked in sequence from bottom to top, the second gate dielectric layer including a fourth sublayer and a fifth sublayer, and the proportion of N elements in the first sublayer is higher than the proportion of N elements in the fourth sublayer.

[0015] In some embodiments of the present application, the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

[0016] In a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising:

[0017] providing a substrate comprising a plurality of active regions defined by isolation trenches;

[0018] forming a plurality of first gate structures, wherein the first gate structures are formed on the active area and include a channel layer, a first gate dielectric layer, a first barrier layer, and a first metal layer stacked in sequence from bottom to top;

[0019] Forming the first gate dielectric layer includes forming a first sublayer and a second sublayer stacked in sequence from bottom to top, wherein the proportion of N element in the first sublayer is higher than the proportion of N element in the second sublayer.

[0020] In some embodiments of the present application, the channel layer includes a silicon germanium layer, and forming the first sublayer includes: performing a reduction treatment on the channel layer using a reducing gas; and after the reduction treatment, performing a nitridation treatment on the channel layer using a nitrogen-containing gas.

[0021] In some embodiments of the present application, the reducing gas includes at least one of H2, CO and NF3.

[0022] In some embodiments of the present application, the nitrogen-containing gas includes at least one of NH3, N2, N2O, and NO.

[0023] In some embodiments of the present application, the proportion of O element in the second sublayer is higher than the proportion of O element in the first sublayer, and the first sublayer directly contacts the top surface of the channel layer and the bottom surface of the second sublayer.

[0024] In some embodiments of the present application, forming the second sub-layer includes: performing oxidation treatment on a portion of the thickness of the first sub-layer using an oxygen-containing gas; the oxygen-containing gas includes O2.

[0025] In some embodiments of the present application, the second gate structure includes a second gate dielectric layer, a second barrier layer, and a second metal layer stacked in sequence from bottom to top, the second gate dielectric layer includes a fourth sublayer and a fifth sublayer, and the proportion of N elements in the first sublayer is higher than the proportion of N elements in the fourth sublayer.

[0026] The semiconductor device and preparation method in the embodiments of the present application, the semiconductor device includes: a substrate, the substrate includes a first region and a second region; multiple gate structures, including a first gate structure located on the first region and a second gate structure located on the second region, the first gate structure includes a channel layer, a first gate dielectric layer, a first barrier layer and a first metal layer stacked in sequence from bottom to top; wherein the first gate dielectric layer includes a first sublayer, a second sublayer and a third sublayer stacked in sequence from bottom to top, the first sublayer and the second sublayer both include the same Group IV element as the channel layer, and the proportion of N element in the first sublayer is higher than the proportion of N element in the second sublayer. Since both the first sublayer and the second sublayer include the same Group IV elements as the channel layer, and the proportion of N elements in the first sublayer is higher than that in the second sublayer, the first sublayer with such characteristics can better prevent the germanium element in the channel layer (especially in the surface layer) from diffusing upward (toward the first gate dielectric layer), which is beneficial to improving the electrical performance of the gate structure. In addition, when the first sublayer is formed, the dangling bonds on the surface of the channel layer will be passivated (for example, hydrogen atoms will combine with the dangling bonds), thereby reducing the interface state density (Dit), which can further improve the performance of the PMOS transistor.

[0027] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 A schematic flow chart of a method for preparing a semiconductor device according to some embodiments of the present application;

[0030] Figure 2 A schematic cross-sectional view of a method for preparing a semiconductor device according to some embodiments of the present application after providing a substrate;

[0031] Figure 3 A schematic cross-sectional view of a semiconductor device manufacturing method after forming a channel layer according to some embodiments of the present application;

[0032] Figure 4 A schematic cross-sectional view of a semiconductor device after reduction treatment in a method for preparing the semiconductor device provided in some embodiments of the present application;

[0033] Figure 5 A schematic cross-sectional view of a semiconductor device after nitridation treatment in a method for preparing the semiconductor device provided in some embodiments of the present application;

[0034] Figure 6 A schematic cross-sectional view of a semiconductor device after oxidation treatment in a method for preparing a semiconductor device provided in some embodiments of the present application;

[0035] Figure 7 A schematic cross-sectional view of a semiconductor device manufacturing method after forming a multi-layer film layer in some embodiments of the present application;

[0036] Figure 8 A schematic cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present application after forming a first gate structure and a second gate structure;

[0037] Figure 9 A schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a sidewall spacer, a source region, and a drain region in some embodiments of the present application;

[0038] Figure 10 A schematic cross-sectional view of a method for manufacturing a semiconductor device after forming a dielectric layer and a metal connection structure in some embodiments of the present application;

[0039] Description of reference numerals:

[0040] Substrate 100; groove 101; channel layer 102; germanium oxide layer 103; silicon oxide layer 104; isolation trench 105; protective layer 106; first sublayer 107; fourth sublayer 108; second sublayer 109; third sublayer 110; first barrier layer 111; first metal layer 112; first cap layer 113; fifth sublayer 114; second barrier layer 115; second metal layer 116 ; second cap layer 117; first source region 118; first drain region 119; second source region 120; second drain region 121; high-k material layer 122; barrier material layer 123; gate material layer 124; cap layer 125; second spacer 126; first spacer 127; first dielectric layer 128; second dielectric layer 129; second metal connection structure 130; first metal connection structure 131;

[0041] First region 11; second region 12; reduction treatment 21; nitridation treatment 22; oxidation treatment 23. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0044] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0045] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0046] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] The structures of the embodiments of the present application should not be limited to the specific shapes shown in the drawings, but include shape deviations due to, for example, manufacturing technology.

[0048] It can be understood that in the drawings of the present application, some adjacent film layers made of the same processing film material are drawn as being connected to make them close to the actual structure.

[0049] The existing process for forming a PMOS transistor with a silicon germanium channel generally includes: providing a substrate; forming a groove in the substrate; using an epitaxial process to fill the groove with silicon germanium material to form a silicon germanium channel; forming a gate structure on the silicon germanium channel; and forming a source region and a drain region in the substrate on both sides of the gate structure. The surface properties of the silicon germanium channel formed in this way still need to be improved. Specifically, the surface layer of the silicon germanium channel is easily oxidized, forming an amorphous mixed oxide layer (such as SiGeO x ), there may be dangling bonds at the interface between the mixed oxide layer and the silicon germanium channel, resulting in an increase in the interface state density (Dit), affecting the performance of the PMOS transistor, and the germanium in the surface layer of the silicon germanium channel is also easy to diffuse toward the gate structure, causing the germanium concentration on the surface of the silicon germanium channel to decrease, which also affects the electrical performance of the gate structure.

[0050] To this end, an embodiment of the present application provides a method for preparing a semiconductor device. Figure 1 A schematic flow chart of a method for preparing a semiconductor device according to some embodiments of the present application is provided. Figure 1 , a method for preparing a semiconductor device, comprising the steps of:

[0051] Step S101, providing a substrate, the substrate including a plurality of active areas defined by isolation trenches;

[0052] Step S102 , forming a plurality of first gate structures, wherein the first gate structures are formed on the active area and include a channel layer, a first gate dielectric layer, a first barrier layer, and a first metal layer stacked in sequence from bottom to top;

[0053] Forming the first gate dielectric layer includes forming a first sublayer and a second sublayer stacked in sequence from bottom to top, wherein the proportion of N element in the first sublayer is higher than the proportion of N element in the second sublayer.

[0054] The specific process of the method for preparing the semiconductor structure is described in detail below with reference to the accompanying drawings. Figures 1-10 Schematic diagram of the cross-sectional structure of each stage in a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0055] First, combined with reference Figure 1 and Figure 2 , step S101 is performed to provide a substrate 100 , where the substrate 100 includes a plurality of active regions defined by isolation trenches 105 .

[0056] The substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate including Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (SOI), or silicon-germanium-on-insulator (SiGe-on-insulator).

[0057] The substrate 100 may be doped with certain impurity ions as needed. In one example, the substrate 100 may be doped with P-type impurity ions, including one or more of boron ions, gallium ions, or indium ions. In another example, the substrate 100 may be doped with N-type impurity ions, including one or more of phosphorus ions, arsenic ions, or antimony ions.

[0058] Multiple active areas may include at least one first region 11 and at least one second region 12. Adjacent first regions 11, adjacent second regions 12, and adjacent first regions 11 and second regions 12 may be isolated by isolation trenches 105. The first region 11 and the second region 12 may be adjacent or non-adjacent. Subsequently, a PMOS transistor is formed in the first region 11 of the substrate 100, and an NMOS transistor is formed in the second region 12 of the substrate 100. Figure 2 In the figure, only one first area 11 and one second area 12 are used as examples for description.

[0059] In some embodiments, the isolation trench 105 is a shallow trench isolation (STI) structure. In one example, the material of the shallow trench isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0060] In some embodiments, the method further includes forming a groove 101 in the substrate 100 of the first region 11, and subsequently forming a channel layer 102 of a PMOS transistor in the groove 101 (refer to Figure 2), the recess 101 is formed by an etching process, including an anisotropic plasma etching process. In one example, before etching the substrate 100 in the first region 11, a protective layer 106 is formed on the surface of the substrate in the second region 12. The material of the protective layer 106 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and photoresist. In other embodiments, the recess 101 may not be formed in the substrate 100 in the first region 11, and a channel layer may be subsequently formed directly on the surface of the substrate 100 in the first region 11.

[0061] Next, combined with reference Figure 1 and Figure 8 , performing step S102 to form a plurality of first gate structures, wherein the first gate structures are formed on the active area, and the first gate structures include a channel layer 102, a first gate dielectric layer, a first barrier layer 111, and a first metal layer 112 stacked in sequence from bottom to top;

[0062] Forming the first gate dielectric layer includes forming a first sublayer 107 and a second sublayer 109 stacked sequentially from bottom to top, wherein the proportion of N element in the first sublayer 107 is higher than the proportion of N element in the second sublayer 109 .

[0063] In some embodiments, when performing step S102 , the first gate dielectric layer further includes a third sub-layer 110 located between the second sub-layer 109 and the first barrier layer 111 , and the third sub-layer 110 is a high dielectric constant material layer.

[0064] In some embodiments, the following Figure 3-Figure 8 The specific process of step 102 is described in detail.

[0065] refer to Figure 3 , a channel layer 102 is formed in the groove 101 in the first region 11 .

[0066] Channel layer 102 comprises a silicon germanium layer. When used as the channel of a PMOS transistor, the silicon germanium layer can improve the mobility of holes in the PMOS transistor. Channel layer 102 is formed using an epitaxial growth process, specifically a selective epitaxial growth process. In some embodiments, the concentration of germanium in the silicon germanium layer increases in a gradient or gradually increases away from the top surface of substrate 100.

[0067] After the channel layer 102 (or silicon germanium layer) is formed, the material on the surface of the channel layer 102 (or silicon germanium layer) will be naturally oxidized to form a mixed oxide layer (such as SiGeO x), the mixed oxide layer also serves as part of the channel layer 102 (or silicon germanium layer). The mixed oxide layer typically exhibits a layered structure and generally includes multiple oxide layers. In some embodiments, the multiple oxide layers include a germanium oxide layer 103 and a silicon oxide layer 104. The presence of the mixed oxide layer may result in the presence of dangling bonds at the interface between the mixed oxide layer and the channel layer 102 (or silicon germanium layer), resulting in an increase in the interface state density (Dit), which affects the performance of the PMOS transistor (such as the mobility of holes). In addition, the germanium in the surface layer of the channel layer 102 (or silicon germanium layer) will be oxidized and easily diffuse toward the gate structure, which will reduce the germanium concentration in the surface layer of the channel layer 102 (or silicon germanium layer), also affecting the mobility of holes. The present application subsequently performs corresponding treatment on the mixed oxide layer (germanium oxide layer 103 and silicon oxide layer 104) to improve the surface properties of the (germanium oxide layer 103 and silicon oxide layer 104), thereby eliminating dangling bonds on the surface of the channel layer 102 (or silicon germanium layer), thereby reducing the interface state density (Dit), thereby improving the electrical performance of the gate structure. In addition, the remaining germanium after the treatment of the germanium oxide layer 103 can diffuse back into the channel layer 102 (or silicon germanium layer), and the film layer formed by the corresponding treatment of the mixed oxide layer (germanium oxide layer 103 and silicon oxide layer 104) can also prevent the germanium in the channel layer 102 (or silicon germanium layer) from diffusing toward the first gate dielectric layer, thereby ensuring the germanium concentration in the surface layer of the channel layer 102 (or silicon germanium layer), which is conducive to further improving the electrical performance of the gate structure, thereby improving the performance of the PMOS transistor.

[0068] refer to Figure 3 and Figure 4 , the channel layer 102 is subjected to a reduction treatment 21 using a reducing gas; after the reduction treatment 21 , the channel layer 102 is subjected to a nitridation treatment 22 using a nitrogen-containing gas to form a first sublayer 107 on the surface of the channel layer 102 .

[0069] When the channel layer 102 is subjected to a reduction treatment 21 using a reducing gas, the bond energy of the Ge-O bond in the germanium oxide layer 103 is lower than the bond energy of the Si-O bond in the silicon oxide layer 104. As a result, the germanium oxide layer 103 is preferentially reduced. Specifically, the oxygen in the germanium oxide layer 103 is combined with the reducing gas and removed, while the germanium in the germanium oxide layer 103 is retained. Furthermore, during the reduction treatment 21, dangling bonds at the interface between the channel layer 102 (or silicon germanium layer) and the germanium oxide layer 103 are passivated (for example, hydrogen atoms bind to dangling bonds), thereby reducing the interface state density (Dit), preventing hole scattering, and improving the electrical performance of the gate structure, thereby enhancing the performance of the PMOS transistor. In some embodiments, the reducing gas includes at least one of H2, CO, and NF3.

[0070] After the reduction treatment 21, when the channel layer 102 is subjected to a nitridation treatment 22 using a nitrogen-containing gas, nitrogen (N) enters the silicon oxide layer 104, forming a first sublayer 107. The first sublayer 107 includes Si, O, and N. During the nitridation treatment 22, the intrusion of nitrogen (N) causes the remaining germanium (Ge) in the germanium oxide layer 103 after the reduction treatment 21 to diffuse into the channel layer 102 (or silicon germanium layer) due to the squeeze effect and concentration gradient. This ensures the concentration of germanium in the channel layer 102 (or silicon germanium layer), particularly in the surface layer, and further improves the electrical performance of the gate structure. In some embodiments, the nitrogen-containing gas includes at least one of NH3, N2, N2O, and NO.

[0071] In a specific embodiment, the reduction treatment 21 and the nitridation treatment 22 are respectively carried out in furnace tubes, the reducing gas used in the reduction treatment 21 includes H2, the temperature range when the reduction treatment 21 is carried out is 550 degrees Celsius-750 degrees Celsius, and the flow rate range of hydrogen is 100sccm-1000sccm; the nitrogen-containing gas used in the nitridation treatment 22 includes NH3, the temperature range when the nitridation treatment 22 is carried out is 800 degrees Celsius-1000 degrees Celsius, and the flow rate of ammonia is 100sccm-1000sccm.

[0072] refer to Figure 6 , an oxygen-containing gas is used to perform an oxidation treatment 23 on a portion of the thickness of the first sub-layer 107 , and a second sub-layer 109 is formed on the first sub-layer 107 .

[0073] During oxidation treatment 23, nitrogen (N) in the surface layer of first sublayer 107 is pushed downward by oxygen (O), resulting in a lower nitrogen (N) content in second sublayer 109 than in first sublayer 107. The O content in second sublayer 109 is higher than that in first sublayer 107. With these characteristics, first sublayer 107 effectively prevents germanium in channel layer 102 (or silicon germanium layer) (particularly in the surface layer) from diffusing upward (toward the first gate dielectric layer), further ensuring the germanium concentration in channel layer 102 (or silicon germanium layer) (particularly in the surface layer), which is beneficial for further improving the electrical performance of the gate structure. Both first sublayer 107 and second sublayer 109 serve as part of the first gate dielectric layer.

[0074] In some embodiments, the second sub-layer 109 includes silicon (Si) and oxygen (O).

[0075] In some embodiments, the oxidation treatment 23 is performed in a furnace tube, the oxygen-containing gas includes O2, the temperature range of the oxidation treatment 23 is 800 degrees Celsius-1200 degrees Celsius, and the flow rate range of oxygen is 50 sccm-600 sccm.

[0076] In some embodiments, after the second sub-layer 109 is formed, the remaining first sub-layer 107 directly contacts the top surface of the channel layer 102 and the bottom surface of the second sub-layer 109 .

[0077] In some embodiments, when the oxidation treatment 23 is performed, a fourth sublayer 108 is simultaneously formed on the surface of the substrate 100 in the second region 12. The fourth sublayer 108 serves as part of the second gate dielectric layer of the NMOS transistor subsequently formed in the second region 12. The fourth sublayer 108 may not contain nitrogen elements (for example, in some embodiments, the aforementioned nitridation treatment 22 may be performed only on the first region 11), or the proportion of N elements in the fourth sublayer 108 is lower than the proportion of N elements in the first sublayer 107 to meet the different electrical performance requirements of NMOS transistors and PMOS transistors.

[0078] In some embodiments, reference Figure 7 , a high dielectric constant material layer 122 , a barrier material layer 123 , a gate material layer 124 and a capping layer 125 are sequentially formed on the substrate 100 covering the first region 11 and the second region.

[0079] High-k material layer 122 is subsequently used to form the third sublayer of the first gate dielectric layer of the PMOS transistor and the fifth sublayer 114 of the second gate dielectric layer of the NMOS transistor. High-k material layer 122 is a High-K material film layer having a dielectric constant (K) generally greater than 3.9. In one example, the material of high-k material layer 122 includes one or more of HfO2, Al2O3, ZrO2, HfSiO, HfSiON, HfTaO, and HfZrO.

[0080] The barrier material layer 123 (barrier layer) is subsequently used to form a first barrier layer for the PMOS transistor and a second barrier layer for the NMOS transistor. The first barrier layer is used to prevent metal in a subsequently formed first metal layer from diffusing downward into the first gate dielectric layer. The second barrier layer is used to prevent metal in a subsequently formed second metal layer from diffusing downward into the second gate dielectric layer.

[0081] The gate material layer 124 is subsequently used to form a first metal layer (first gate electrode) of a PMOS transistor and a second metal layer (second gate electrode) of an NMOS transistor.

[0082] The capping layer 125 serves as a hard mask layer for subsequent etching of the gate material layer 124, the barrier material layer 123, and the high-k dielectric layer 122. The capping layer 125 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.

[0083] refer to Figure 8, the capping layer 125, the gate material layer 124, the barrier material layer 123 and the high dielectric constant material layer 122 are etched in sequence, and a third sub-layer 110, a first barrier layer 111, a first metal layer 112 and a first capping layer 113 are stacked in sequence from bottom to top on the second sub-layer 109 in the first region 11, and a fifth sub-layer 114, a second barrier layer 115, a second metal layer 116 and a second capping layer 117 are stacked in sequence from bottom to top on the fourth sub-layer 108 in the second region 12, thereby forming a first gate structure and a second gate structure.

[0084] The first gate dielectric layer formed includes a first sublayer 107, a second sublayer 109 and a third sublayer 110 stacked in sequence from bottom to top, and the second gate dielectric layer formed includes a fourth sublayer 108 and a fifth sublayer 114. The thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer, thereby realizing the adjustment of different threshold voltages of transistors (including PMOS transistors and NMOS transistors) formed on the first area and the second area.

[0085] In some embodiments, the preparation method further comprises: referring to Figure 9 A first spacer 127 is formed on the sidewall of the first gate structure; a second spacer 126 is formed on the sidewall of the second gate structure; a first source region 118 and a first drain region 119 are formed in the substrate 100 in the first region 11 on both sides of the first spacer 127; a second source region 120 and a second drain region 121 are formed in the substrate 100 in the second region 12 on both sides of the second spacer 126; Figure 10 A first dielectric layer 128 and a second dielectric layer 129 covering the first gate structure and the second gate structure are formed on the substrate 100; a first metal connection structure 131 electrically connected to the first source region 118 and the first drain region 119, and a second metal connection structure 130 electrically connected to the second source region 120 and the second drain region 121 are formed in the first dielectric layer 128 and the second dielectric layer 129.

[0086] The aforementioned method of the present application realizes the integrated fabrication of transistors with different characteristics in the first region and the second region.

[0087] The present application also provides a semiconductor device, referring to Figure 8 ,include:

[0088] A substrate 100 including a plurality of active regions defined by isolation trenches 105;

[0089] A plurality of first gate structures, located on the active area, including a channel layer 102, a first gate dielectric layer, a first barrier layer 111 and a first metal layer 112 stacked in sequence from bottom to top;

[0090] Among them, the first gate dielectric layer includes a first sublayer 107 and a second sublayer 109 stacked in sequence from bottom to top, and the first sublayer 107 and the second sublayer 109 both include the same Group IV elements as the channel layer 102, and the proportion of N elements in the first sublayer 107 is higher than the proportion of N elements in the second sublayer 109.

[0091] In some embodiments, the proportion of O element in the second sublayer 109 is higher than the proportion of O element in the first sublayer 107 , and the first sublayer 107 directly contacts the top surface of the channel layer 102 and the bottom surface of the second sublayer 109 .

[0092] In some embodiments, the channel layer 102 includes a silicon germanium layer, and the concentration of germanium in the silicon germanium layer increases in a gradient or gradually increases in a direction away from the top surface of the substrate 100 .

[0093] In some embodiments, the first gate dielectric layer further comprises:

[0094] The third sub-layer 110 is located between the second sub-layer 109 and the first barrier layer 111 . The third sub-layer 110 is a high dielectric constant material layer.

[0095] In some embodiments, multiple second gate structures are further included, located on the active area, the second gate structures include a second gate dielectric layer, a second barrier layer 115, and a second metal layer 116 stacked in sequence from bottom to top, the second gate dielectric layer includes a fourth sublayer 108 and a fifth sublayer 114, and the proportion of N elements in the first sublayer 107 is higher than the proportion of N elements in the fourth sublayer 108.

[0096] In some embodiments, the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

[0097] It should be noted that the limitations or descriptions of the same or similar parts in this embodiment (semiconductor device) and the aforementioned embodiment (method for preparing a semiconductor device) will not be repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the aforementioned embodiment for details.

[0098] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. Within this specification, the schematic descriptions of these terms do not necessarily refer to the same embodiment or example.

[0099] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a plurality of active regions defined by isolation trenches; A plurality of first gate structures, located on the active area, comprising a channel layer, a first gate dielectric layer, a first barrier layer and a first metal layer stacked in sequence from bottom to top; Among them, the first gate dielectric layer includes a first sublayer and a second sublayer stacked in sequence from bottom to top, the first sublayer and the second sublayer both include the same Group IV element as the channel layer, and the proportion of N elements in the first sublayer is higher than the proportion of N elements in the second sublayer.

2. The semiconductor device according to claim 1, wherein The proportion of the O element in the second sub-layer is higher than the proportion of the O element in the first sub-layer, and the first sub-layer directly contacts the top surface of the channel layer and the bottom surface of the second sub-layer.

3. The semiconductor device according to claim 1, wherein The channel layer includes a silicon germanium layer. In a direction away from the top surface of the substrate, the concentration of germanium in the silicon germanium layer increases in a gradient or gradually increases.

4. The semiconductor device according to claim 1, wherein The first gate dielectric layer further comprises: The third sublayer is located between the second sublayer and the first barrier layer, and the third sublayer is a high dielectric constant material layer.

5. The semiconductor device according to claim 1, wherein It also includes multiple second gate structures, located on the active area, the second gate structures include a second gate dielectric layer, a second barrier layer and a second metal layer stacked in sequence from bottom to top, the second gate dielectric layer includes a fourth sublayer and a fifth sublayer, and the proportion of N elements in the first sublayer is higher than the proportion of N elements in the fourth sublayer.

6. The semiconductor device according to claim 5, wherein The thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

7. A method for preparing a semiconductor device, characterized in that: include: providing a substrate comprising a plurality of active regions defined by isolation trenches; forming a plurality of first gate structures, wherein the first gate structures are formed on the active area and include a channel layer, a first gate dielectric layer, a first barrier layer, and a first metal layer stacked in sequence from bottom to top; Forming the first gate dielectric layer includes forming a first sublayer and a second sublayer stacked in sequence from bottom to top, wherein the proportion of N element in the first sublayer is higher than the proportion of N element in the second sublayer.

8. The method for preparing a semiconductor device according to claim 7, wherein: The channel layer includes a silicon germanium layer, and forming the first sublayer includes: performing a reduction treatment on the channel layer using a reducing gas; and after the reduction treatment, performing a nitridation treatment on the channel layer using a nitrogen-containing gas.

9. The method for preparing a semiconductor device according to claim 8, wherein: The reducing gas includes at least one of H2, CO and NF3.

10. The method for preparing a semiconductor device according to claim 8, wherein: The nitrogen-containing gas includes at least one of NH3, N2, N2O and NO.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: The proportion of the O element in the second sub-layer is higher than the proportion of the O element in the first sub-layer, and the first sub-layer directly contacts the top surface of the channel layer and the bottom surface of the second sub-layer.

12. The method for preparing a semiconductor device according to claim 11, wherein: Forming the second sub-layer includes: performing oxidation treatment on a portion of the thickness of the first sub-layer using an oxygen-containing gas; the oxygen-containing gas includes O2.

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