Super junction power semiconductor device with improved edge termination

Abstract

The invention relates to a super junction power semiconductor device with improved edge termination. The present description provides a super junction power semiconductor device. An example super junction power semiconductor device has a die of semiconductor material including a structural layer having a first doping type, the die having an active region forming an active cell and an edge region surrounding the active region at a periphery of the die. An edge termination arrangement at the edge region has a plurality of edge termination trenches extending through the structural layer, the plurality of edge termination trenches being filled with a dielectric material and having respective doping layers of the second doping type at sidewalls thereof. The edge termination arrangement has an electrical connection structure to electrically connect together the respective doped layers at sidewalls of the edge termination trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATION(S)

[0002] This application claims the benefit of priority from Italian Patent Application No. 102024000005977, filed on March 18, 2024, entitled “DISPOSITIVO SEMICONDUTTOREDIPOTENZA A SUPERGIUNZIONE CON TERMINAZIONE DI BORDO PERFEZIONATA”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The present solution relates to a superjunction power semiconductor device with improved edge termination. Background Art

[0004] Superjunction power semiconductor devices, such as MOSFET devices, are based on the principle of charge balancing or charge compensation, according to which the charge in a structural layer of a first conductivity or doping type (e.g., an n-type epitaxial layer) is compensated or balanced by doped pillars or pillars formed in the same layer and having a second conductivity or doping type (in this example, p-type doping). This technology is advantageous, for example, in achieving a trade-off between the breakdown voltage and on-resistance of the power semiconductor device.

[0005] However, the manufacturing cost of this technology is quite high because the formation of doped columns requires complex manufacturing steps, such as multiple implantation and epitaxial growth steps, or complete filling (no voids) of deep trenches with high aspect ratios, for example up to 20 (depth):1 (width).

[0006] Furthermore, as with all power devices, edge termination is required to achieve the desired breakdown voltage performance, and proper design of edge termination for these superjunction power semiconductor devices is generally not a simple process.

[0007] Recently, architectures for charge-balanced dual trench superjunction MOSFET devices have been proposed that allow overcoming at least some of the above problems, see for example US 2023 / 0107611 A1.

[0008] Advantageously, the fabrication of such a superjunction MOSFET device does not require multiple epitaxial processing steps nor epitaxial filling of deep trenches in order to form the pillar-shaped charge balancing structure for the MOSFET cell.

[0009] However, such a superjunction MOSFET device also has to address the problem of providing efficient edge termination, particularly given that the charge balancing structure of the last MOSFET cell may see a high voltage difference between the reference (ground) potential of the corresponding body and source regions and the high voltage at the edge of the same device (corresponding to the drain-source voltage of the superjunction MOSFET device 1), which may result in an undesirable distribution of the electric field lines.

[0010] One known solution that has been proposed for edge termination is to provide a dielectric-filled deep and wide trench as protection around the active area of ​​the device and to place a field plate on top.

[0011] For example, this technology is disclosed in Noblecourt, S. et al., "Design Optimisation of the Deep Trench Termination for Superjunction Power Devices," International Journal of Microelectronics and Computer Science, Vol. 6, No. 4, 2015.

[0012] However, this solution has the disadvantages of being difficult to control the depth of this larger trench while manufacturing the charge balancing trench in the active area; and also of the complexity of achieving complete filling (no voids) of this last trench. Summary of the Invention

[0013] The present solution generally aims to overcome the limitations of known super junction power devices, in particular with regard to providing an efficient edge termination region.

[0014] According to the present solution, there is thus provided a super junction power device, as defined in the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order that the present disclosure may be better understood, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0016] Figure 1 shows a cross section of a portion of a super junction power device;

[0017] Figure 2 shows a cross section of a portion of a super junction power device and a corresponding edge termination region according to an aspect of the present solution;

[0018] Figure 3 is a diagram of potential distribution in an edge region of a super junction power device;

[0019] Figures 4A-4Kshows cross sections of a power semiconductor device in successive steps of a manufacturing process relating to a first embodiment of an edge termination arrangement;

[0020] Figure 5 In a possible embodiment Figure 4K a plan view of an edge portion of a power semiconductor device;

[0021] Figure 6A In another embodiment, Figure 4K a plan view of an edge portion of a power semiconductor device;

[0022] Figure 6B Shown Figure 6A A cross section of a power semiconductor device;

[0023] Figures 7A-7K shows cross sections of a power semiconductor device in successive steps of a manufacturing process relating to a second embodiment of an edge termination arrangement;

[0024] Figure 8 shows a possible embodiment according to Figure 7K a plan view of an edge portion of a power semiconductor device; and

[0025] Figures 9A-9H Cross sections of a power semiconductor device in connection with a third embodiment of an edge termination arrangement are shown in successive steps of a manufacturing process. DETAILED DESCRIPTION

[0026] As discussed below, one aspect of the present solution relates to an improved edge termination for a superjunction power semiconductor device, particularly a MOSFET device, comprising dielectric-filled trenches with doped sidewalls disposed in the periphery of the device's active region. In particular, the sidewalls of adjacent trenches are electrically connected and maintained at a floating potential, thereby achieving a gradual distribution of voltage potential and proper confinement of electric field lines in the edge region of the superjunction power semiconductor device.

[0027] like Figure 1 As shown in FIG, a superjunction power semiconductor device, in particular a MOSFET device, generally designated 1, comprises a die 20' of a semiconductor material, for example silicon (or other semiconductor material, such as silicon carbide), the die comprising a substrate 29 having a low thickness (approximately 20-200 μm) and a high concentration of a first doping type, for example n ++ (For example, doping concentrations up to 4e 16 cm -3 ).

[0028] The epitaxial layer 27 is formed on the substrate 29 and has a first doping type and a lower concentration (eg, n-type).

[0029] The MOSFET cells 5 are formed at a top surface 27 a of the epitaxial layer 27 opposite to the substrate 29. Each MOSFET cell 5 of the trench-gate type comprises: a gate region 6 made of doped polysilicon, arranged in a corresponding gate trench 7 formed through a shallow portion of the epitaxial layer 27; a body region 8 of a second doping type (p-type), laterally surrounding the gate trench 7 and separated from the gate trench 7 by a thin dielectric layer 9; and a source region 10 of a first doping type (n-type), arranged on the body region 8, laterally opposite to the corresponding gate trench 7.

[0030] The power semiconductor device 1 further comprises a plurality of charge balancing deep trenches 12 filled with a dielectric, in particular an oxide, extending through the epitaxial layer 27 and reaching the underlying substrate 29. In the active region of the MOSFET device, each MOSFET cell 5 is arranged between an adjacent pair of charge balancing deep trenches 12.

[0031] In particular, the power semiconductor device 1 includes a thin doped layer 14 of a second doping type (p-type) at the sidewalls of each charge balancing deep trench 12, for example, with a width ranging from ten nanometers to two hundred nanometers, in order to compensate for the epitaxial n-type charge under depletion and achieve charge balance. These thin doped layers 14 constitute p-doped pillars, thereby allowing for corresponding narrow and heavily doped n-type epitaxial drift regions, thereby improving the trade-off between on-resistance and breakdown voltage (generally speaking, the smaller the width, the better the performance in terms of on-resistance).

[0032] The power semiconductor device 1 also includes a drain contact layer 15 at the back side of the substrate 29; and a source contact layer 16 above the top surface 27a of the epitaxial layer 27 (which represents the drift region of the device), which source contact layer 16 contacts both the body region 8 and the source region 10 through a contact element (or "plug") 18, extends vertically through the dielectric region 19, covers the top surface 27a, and crosses the source region 10 to reach the body region 8 (the source contact layer 16 is typically maintained at a reference voltage potential, for example, ground GND).

[0033] Figure 2 An improved edge termination arrangement 22 of a power semiconductor device 1 according to an aspect of the present solution is shown.

[0034] An edge termination arrangement 22 is formed in an edge region 28 of the power semiconductor device 1 at the periphery of the die 20 ′, which surrounds an active region (here indicated at 26 ) where the active cells 5 are formed.

[0035] Figure 2 Only one of the active cells 5 is shown, which is the one closest to the edge region 28; Figure 2In a manner not shown in FIG. 1 , the power semiconductor device 1 comprises a plurality of charge balancing deep trenches in the active region 26, which are formed in the epitaxial layer 27 and reach the substrate 29 and comprise a dielectric filling region and a thin doped layer at the sidewalls of the trenches (as described above). Figure 1 discussed).

[0036] According to one aspect of the present solution, the edge termination arrangement 22 comprises a plurality of edge termination deep trenches 30 which are arranged in a regular distribution in the edge region 28, each edge termination deep trench 30 traversing the epitaxial layer 27 and reaching the substrate 29 and comprising a dielectric filling region 31 and a thin doped layer (also indicated by 14) at its sidewalls.

[0037] The edge termination arrangement 22 also includes an electrical connection structure 34 ( Figure 2 ), the electrical connection structures 34 are configured to electrically connect together (i.e., short-circuit) the thin doped layers 14 at the sidewalls of each edge-terminating deep trench 30. In particular, the first of these electrical connection structures 34 (closest to the active area 26) is connected to the source and body regions of the last active cell 5 in the active area 26 and to the source contact layer 16 (so as to be at a reference or ground potential); all other electrical connection structures 34 are left floating (i.e., not connected to any specific voltage potential).

[0038] like Figure 3 As schematically shown in , the resulting effect is that the potential in the edge region 28 of the power semiconductor device 1 gradually shifts from the reference potential (GND, 0V) to a drain-source voltage of, for example, 180-190V (each incremental voltage step corresponds to one of the electrical connection structures 34).

[0039] Above Figure 2 In a manner not shown in the figures, the edge-termination deep trench 30 has a ring-shaped configuration surrounding the active area 26 of the power semiconductor device 1, with the radius increasing as it moves away from the active area 26. Moreover, the electrical connection structures 34 may not be continuous along the ring of the respective edge-termination deep trench 30, but rather be regularly distributed along the ring with a given separation distance (as will be disclosed in more detail below).

[0040] First reference Figure 4A , a first embodiment of a process for manufacturing a power semiconductor device 1 is now discussed, with particular reference to the manufacture of the edge termination arrangement 22 in the edge region 28 (simultaneously with the manufacture of the active cells 5 in the active region 26 ).

[0041] Figure 4AThe substrate 29 and the epitaxial layer 27 of the power semiconductor device 1 are shown, both located in the active region 26 and the edge region 28 of the power semiconductor device 1. In the following, unless otherwise specified, the steps to be discussed are intended to be performed simultaneously in both the active region 26 and the edge region 28 of the semiconductor device 1.

[0042] The first step of the manufacturing process envisages forming, starting from the top surface 27 a of the epitaxial layer 27, a shallow trench 40, for example having a width of 0.1 to 1 μm along a first axis x of the horizontal plane xy (parallel to the top surface 27 a) and a depth of 0.5 to 2 μm in the vertical direction along a vertical axis z orthogonal to the horizontal plane xy. In the active region 26, the shallow trench 40 is designed to form a gate trench for the active cell 5 of the power semiconductor device 1.

[0043] like Figure 4B As shown in FIG, a thin dielectric layer 41 is formed on top surface 27a and in shallow trenches 40 (coating the lateral walls and bottom thereof) by, for example, thermal oxidation.

[0044] Then, a polysilicon region 42 is formed in the shallow trench 40. Figure 4C In particular, the polysilicon region 42 is separated from the epitaxial layer 27 by the dielectric layer 41 .

[0045] like Figure 4D As shown in FIG, in the surface portion of the epitaxial layer 27, at its top surface 27a, a doped layer 43 of a second doping type (p-type) is formed; in the active region 26, this doped layer 43 is designed to form a body region for the active unit 5 of the power semiconductor device 1.

[0046] Then, the manufacturing process envisions, Figure 4E , a thin dielectric layer 41 is removed from the top surface 27a of the epitaxial layer 27, and then shallow doping is performed only in the active area 26 of the power semiconductor device 20 to form a shallow doped layer 44 with a first doping type (n-type); in the active area 26, this shallow doped layer 44 is designed to form a source region for the active unit 5 of the power semiconductor device 1.

[0047] after, Figure 4F Deep trenches are etched through the epitaxial layer 27 and into the substrate 29, each deep trench being formed between a corresponding pair of shallow trenches 40. In particular, these deep trenches are designed to form a plurality of charge balancing deep trenches 12 in the active region 26 and a plurality of edge termination deep trenches 30 in the edge region 28.

[0048] Subsequently, as described Figure 4FAs shown in FIG, the sidewalls of the deep trench are doped to form thin doped layers (also indicated by 14) of the second doping type (p-type). In particular, these thin doped layers 14 are continuous with and in contact with the doped regions 43' of the previously formed doped layer 43 (also of the second doping type).

[0049] The manufacturing process then continues, Figure 4G , filling the deep trench 46 with a dielectric filling region 47 (eg, silicon oxide). This step also results in the formation of a dielectric layer 48 on the top surface 27a of the epitaxial layer 27.

[0050] like Figure 4H As shown in FIG, contact openings 49 are then opened through the dielectric layer 48 and the underlying doped region 43' (and the shallow doped layer 44 in the active area 26). In particular, a pair of contact openings 49 are formed at the sides of each shallow trench 40, separated by a distance from the corresponding thin dielectric layer 41.

[0051] like Figure 4I As shown in FIG, the contact opening 49 is then filled with a conductive material (eg, tungsten) to form a contact (or “plug”) 50 within the contact opening 49 .

[0052] A thin barrier layer 52 of a conductive material, such as TiN, is then deposited on the dielectric layer 48. Figure 4J As shown in FIG, the thin barrier layer contacts the contact 50 from above.

[0053] Barrier layer 52 is continuous in active region 26 .

[0054] According to a particular aspect of the present solution, the barrier layer 52 is patterned in the edge region 28 so as to define barrier portions 54 configured to electrically connect in pairs the thin doped layers 14 of the respective edge-termination deep trenches 30. In particular, each barrier portion 54 contacts from above a pair of contacts 50 arranged at the sides of the respective edge-termination deep trench 30 and reaching the doped regions 43 ′ of the doped layer 43; thus, these barrier portions 54 together with the respective contacts 50 define the above electrical connection structure 34 of the edge-termination arrangement 22.

[0055] like Figure 4K As shown in , the manufacturing process then continues with forming a thick top metal layer 56 on the barrier layer 52 in the active area 26 alone to define a source contact layer of the power semiconductor device 1 .

[0056] As discussed above, in possible embodiments of the edge termination arrangement 22 , the contact structure 34 is not continuous along the ring around the active region 26 .

[0057] in this regard, Figure 5FIG. 1 shows a top view of an edge portion of a power semiconductor device 1, wherein the electrical connection structure 34 is not continuous along the extension direction of the corresponding edge-terminating deep trench 30, but is continuous along the extension direction (in FIG. Figure 5 , are regularly distributed with a given separation distance along the second axis y) of the horizontal plane xy.

[0058] In particular, the blocking portion 54 of the electrical connection structure 34 has a much smaller longitudinal extension than the corresponding edge termination deep trench 30 and is arranged at a certain separation distance along the extension direction of the edge termination deep trench 30 (at Figure 5 In the example of FIG. 5 , the blocking portion 54 has a substantially rectangular shape in the horizontal plane xy).

[0059] The contacts 50 coupled to the corresponding blocking portions 54 also have substantially the same longitudinal extension as the blocking portions 54 .

[0060] In this case, the electrical continuity between the electrical connection structures 34 is ensured by the underlying doped region 43 ′, which is continuous along a ring around the active region 26 .

[0061] Furthermore, in the illustrated embodiment, the blocking portions 54 associated with adjacent edge termination deep trenches 30 are staggered in the above-defined extension direction so that the electrical connection structures 34 of adjacent edge termination deep trenches 30 are not aligned (in the embodiment shown). Figure 5 , along the first axis x of the horizontal plane xy). In the Figure 5 In the embodiment shown in , the barrier portion 54 of any given edge termination deep trench 30 and the next non-adjacent edge termination deep trench 30 are instead aligned along the first axis x.

[0062] This embodiment of the electrical connection structure 34 may be particularly advantageous in all cases where the reduction in width of the edge-terminated deep trench 30 may cause problems in the production of the contact 50 transverse to said trench.

[0063] According to yet another embodiment of the present solution, reference is now made to Figure 6A and Figure 6B Discussing this embodiment, the electrical connection structures 34 in the edge region 28 are also electrically connected (short-circuited) to the polysilicon regions 42 formed within the shallow trenches 40, so that these polysilicon regions 42 are also kept floating and at the same voltage potential as the corresponding electrical connection structures 34. This solution may be advantageous, allowing for further improved control over the confinement of the electric field lines in the edge region 28.

[0064] In this regard, additional contacts (indicated by 50') are thus formed through the dielectric layer 48 to reach the polysilicon region 42 of the corresponding underlying shallow trench 40; and in addition to the contacts 50 defined above, the blocking portion 54 of the electrical connection structure 34 is constructed to electrically contact corresponding contacts of these additional contacts 50'.

[0065] In particular, Figure 6A and Figure 6B In the embodiment shown in , the additional contact members 50 ′ are arranged in a localized manner at the corner regions of the respective blocking portions 54 . Figure 6A and Figure 6B As shown in FIG, a localized enlargement of the shallow trench 40 can be provided in said corner region in order to accommodate a further contact 50 ′.

[0066] First reference Figure 7A A second embodiment of the edge termination arrangement 22 of the power semiconductor device 1 will now be discussed, which differs from the embodiments discussed above in that there are no shallow trenches 40 in the edge region 28 .

[0067] In fact, if Figure 7A As shown in , a first step of the manufacturing process envisages forming shallow trenches 40 only in the active area 26 , wherein said shallow trenches 40 are designed to form gate trenches for the active cells 5 of the power semiconductor device 1 ; no shallow trenches are formed in the edge area 28 .

[0068] like Figure 7B As shown in , a thin dielectric layer 41 is then formed by, for example, thermal oxidation, on the top surface 27a of the epitaxial layer 27 and in the shallow trenches 40 in the active area 26 (coating the lateral walls and bottom thereof).

[0069] Subsequently, a doped polysilicon region 42 is formed in the shallow trench 40 in the active area 26. Figure 7C .

[0070] like Figure 7D As shown in , next, a doped layer 43 of a second doping type (p type) is formed in the surface portion of the epitaxial layer 27 at its top surface 27 a to form a body region for the active cell 5 of the power semiconductor device 1 in the active region 26 .

[0071] In particular, the doped layer 43 is appropriately patterned in the edge region 28 so as not to be present in the separated portion 27 ′ of the epitaxial layer 27 ; in other words, the doped layer 43 has corresponding doped regions 43 ′ in the edge region 28 , which are separated in the horizontal plane by the separated portion 27 ′ of the epitaxial layer 27 .

[0072] The manufacturing process is then envisioned, Figure 7EFirst, the thin dielectric layer 41 is removed from the top surface 27a of the epitaxial layer 27, and then shallow doping is performed only in the active area 26 of the power semiconductor device 1 to form a shallow doped layer 44 with a first doping type (n-type) to form a source region for the active unit 5.

[0073] after, Figure 7F , deep trenches are etched through the epitaxial layer 27 and into the substrate 29. In the active area 26, each resulting charge balancing deep trench 12 is formed between a corresponding pair of shallow trenches 40; in the edge area 28, the resulting edge-termination deep trench 30 is formed at the doped region 43' of the doped layer 43.

[0074] Subsequently, the sidewalls of the deep trench 46 are doped to form a thin doped layer 14, as described above. Figure 7F In particular, the thin doped layer 14 of each edge-terminating deep trench 30 is continuous with the corresponding doped region 43 ′ of the doped layer 43 .

[0075] The manufacturing process then continues, Figure 7G , filling the deep trench 46 with a dielectric filling region 47 , and forming a dielectric layer 48 on the top surface 27 a of the epitaxial layer 27 .

[0076] like Figure 7H As shown in FIG, contact openings 49 are then opened through the dielectric layer 48 and the underlying doped layer 43 (and the shallow doped layer 44 in the active area 26). In particular, in the active area 26, a pair of contact openings 49 are formed at the sides of each shallow trench 40; in the edge area 28, a pair of contact openings 49 are instead formed at the sides of the corresponding separated portions 27' of the epitaxial layer 27, reaching the corresponding doped regions 43' of the doped layer 43.

[0077] like Figure 7I As shown in FIG, contact opening 49 is then filled with a conductive material, such as tungsten, to form a contact (or “plug”) 50 .

[0078] A thin barrier layer 52 made of a conductive material such as TiN is then deposited on the dielectric layer 48. Figure 7J As shown in FIG, the thin barrier layer contacts the contact 50 from above.

[0079] The barrier layer 52 is continuous in the active area 26. As discussed above, the barrier layer 52 is patterned in the edge region 28 so as to define a barrier portion 54 that is configured to electrically connect the thin doped layer 14 at the sidewalls of each adjacent edge-termination deep trench 30. In particular, each barrier portion 54 contacts a pair of contacts 50 arranged at the sides of the corresponding edge-termination deep trench 30 from above; thus, these barrier portions 54, together with the corresponding contacts 50, define the electrical connection structure 34 of the edge-termination arrangement 22 discussed above.

[0080] like Figure 7K As shown in , the manufacturing process then continues with forming a thick top metal layer 56 on the barrier layer 52 in the active area 26 alone to define the source contact layer 16 of the power semiconductor device 1 .

[0081] An advantage of this embodiment is that no shallow trenches need to be formed in the edge region 28. However, by arranging polysilicon-filled shallow trenches 40 between contacts 50, the previously discussed embodiments may allow for better confinement of the electric field lines in the edge region 28.

[0082] Furthermore, in this embodiment, Figure 8 As shown in FIG (this figure relates to the edge portion of the power semiconductor device 1), the electrical connection structure 34 may be discontinuous along the extension direction of the corresponding edge-terminating deep trench 30, but may be continuous along the extension direction (in the FIG). Figure 8 , are regularly distributed along the second axis y) with a given separation distance.

[0083] In this case, the blocking portion 54 of the connecting structure 34 is continuous along the extension direction; instead, the contact pieces 50 (in the example, having a substantially rectangular shape in the horizontal plane xy) are arranged in a localized manner, along said extension direction (in Figure 8 , arranged at a certain separation distance along the second axis y).

[0084] Furthermore, the contacts 50 are staggered in the extension direction so that the contacts 50 of adjacent edge-terminated deep trenches 30 are not aligned (in Figure 8 , along the first axis x of the horizontal plane xy). In the Figure 8 In the embodiment shown in , the contact 50 of any given edge termination deep trench 30 and the next non-adjacent edge termination deep trench 30 are instead aligned along the first axis x.

[0085] First reference Figure 9A, a third embodiment of the edge termination arrangement 22 of the power semiconductor device 1 is now discussed, which envisages forming the electrical connection structure 34 of the edge termination arrangement 22 using a self-aligned process. This process will be discussed with particular reference to the formation of the edge termination arrangement 22 in the edge region 28 (the formation of the active cells 5 in the active region 26 will not be disclosed again).

[0086] like Figure 9A As shown in , the process first forms a thin dielectric layer (also indicated at 41 ) on the top surface 27 a of the epitaxial layer 27 and, in this case, a thin passivation layer 60 , such as nitride, on the thin dielectric layer 41 .

[0087] Then, deep trenches are etched through epitaxial layer 27 (and thin dielectric layer 41 and passivation layer 60) and into substrate 29 (not shown here) to form edge-stop deep trenches 30 in edge region 28. The sidewalls of edge-stop deep trenches 30 are doped to form thin doped layer 14.

[0088] Thereafter, the edge-stop deep trench 30 is filled with a dielectric filling region 47 , and a dielectric layer 48 is also formed on the top surface 27 a of the epitaxial layer 27 .

[0089] like Figure 9B As shown in , a planarization step is then performed (eg, with CMP—chemical mechanical polishing), which results in the removal of the portion of dielectric layer 48 above thin passivation layer 60 .

[0090] after, Figure 9C , etching of the surface portion of the dielectric fill region 47 is performed, resulting in the formation of a contact hole 62 at the top of each edge-terminated deep trench 30 at the top surface 27a of the epitaxial layer 27. Figure 9C As shown in , the etching also results in the removal of portions of the thin dielectric layer 41 below the thin passivation layer 60 laterally relative to the contact hole 62 in the horizontal plane xy.

[0091] Then, if Figure 9D As shown in , a step of polysilicon deposition is performed, the polysilicon being doped with the second doping type (p-type), resulting in the formation of a polysilicon layer 64 on the thin passivation layer 60 and within the contact hole 62 at the top of the edge-stopping deep trench 30 .

[0092] like Figure 9E As shown in , this polysilicon layer 64 is then recessed (for example using CMP techniques) to the level of the thin passivation layer 60, leaving only a bridge portion 64' of said polysilicon layer 64, filling the corresponding contact hole 62, thereby closing the corresponding edge-terminated deep trench 30 at the top.

[0093] These bridge portions 64 ′ here form an electrical connection between the thin doped layers 14 of the corresponding edge-terminated deep trenches 30 .

[0094] The thin passivation layer 60 is then removed, as Figure 9F As shown in FIG, and a thick dielectric layer (again indicated by 48) is formed over the top surface 27a of the epitaxial layer 27 and on the bridging portion 64', as shown in FIG. Figure 9G As shown in .

[0095] According to one aspect of the present solution, an annealing step (eg RTA, rapid thermal annealing) is then performed, such as Figure 9H As shown in , this results in lateral diffusion of dopants from the doped polysilicon of bridging portion 64 ′, resulting in the formation of doped regions 68 in epitaxial layer 27 that are in contact with bridging portion 64 ′ and with thin doped layer 14 at the sidewalls of edge-terminating deep trench 30 .

[0096] Thus, in this embodiment, the bridging portion 64 ′ and the doped region 68 define the electrical connection structure 34 of the edge termination arrangement 22 discussed above.

[0097] Advantageously, in this case, the electrical connection structure 34 is obtained in a self-aligned manner with respect to the thin doped layer 14 at the sidewalls of the edge-terminated deep trench 30 , thus with a simplified process flow.

[0098] The advantages of the proposed solution are clear from the foregoing description.

[0099] The disclosed solution provides an edge termination arrangement for a power semiconductor device (particularly of the charge-balanced superjunction type), wherein a charge-balanced deep trench in the edge region with a thin doping layer at its sidewalls allows for a corresponding narrow and heavily doped n-type epitaxial drift region, which improves the trade-off between on-resistance and breakdown voltage.

[0100] In particular, these thin doped layers are short-circuited by appropriate connection structures to keep the charge balancing deep trenches at floating potential, allowing to distribute the potential at the edge regions, thus avoiding the escape of equipotential lines near the surface of the epitaxial layer.

[0101] Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure as defined in the appended claims.

[0102] In particular, it is emphasized that the discussed solution can be applied to different types of power semiconductor devices, such as power diodes or JFETs.

[0103] Furthermore, it is conceivable not to provide the last edge termination deep trench 30 (ie, the trench furthest from the active area 26) with an electrical connection structure 34, as this last deep trench can withstand a certain amount of potential drop with reduced impact on the termination balance.

Claims

1. A super junction power semiconductor device, comprising a die of semiconductor material, the die comprising a substrate and a structure layer formed on the substrate and having a first doping type, in, The die has an active area in which active cells are formed and an edge area surrounding the active area at a periphery of the die, and the die includes a plurality of charge balancing deep trenches filled with a dielectric in the active area, the plurality of charge balancing deep trenches extending between corresponding pairs of active cells through the structural layer and reaching the substrate, each charge balancing deep trench having a doping layer of the second doping type at its sidewall, The superjunction power semiconductor device further includes an edge termination arrangement at the edge region, the edge termination arrangement including a plurality of edge termination trenches extending through the structural layer and reaching the substrate, filled with a dielectric, and having respective doped layers of a second doping type at sidewalls thereof; Wherein, the edge termination arrangement includes an electrical connection structure configured to electrically connect corresponding doped layers at sidewalls of the plurality of edge termination trenches together.

2. The superjunction power semiconductor device according to claim 1, wherein: A first electrical connection structure closest to the active region among the electrical connection structures is electrically connected to the last active cell in the active region, and all other electrical connection structures are at a floating potential.

3. The super junction power semiconductor device according to claim 1, wherein: The electrical connection structure includes a corresponding bridging conductive portion, each bridging conductive portion is arranged above and spans the corresponding edge termination trench and electrically shorts the corresponding doped layer at the sidewall of the corresponding edge termination trench.

4. The superjunction power semiconductor device according to claim 1, comprising a dielectric layer on a top surface of the structural layer; Each of the electrical connection structures includes: a pair of contacts arranged at one or more sides of the respective edge termination trenches, traversing the dielectric layer and designed to electrically contact the respective doped layers; and a blocking portion disposed on the dielectric layer and contacting the pair of contacts from above.

5. The super junction power semiconductor device according to claim 4, wherein: the edge termination arrangement comprising a doped region located at a top surface of the structured layer and having the same doping type as the doped layer, the doped region being arranged laterally to the plurality of edge termination trenches to contact the respective doped layers; The pair of contacts are configured to reach a doped region in the structural layer.

6. The super junction power semiconductor device according to claim 5, wherein: The edge termination arrangement includes a shallow trench in the structural layer at a top surface of the structural layer, the shallow trench being arranged between the pair of contacts and including a polysilicon region separated from the doped region by a dielectric layer.

7. The super junction power semiconductor device according to claim 6, wherein: The electrical connection structure further includes: an additional contact traversing the dielectric layer and configured to electrically contact the polysilicon region of the corresponding shallow trench; wherein the blocking portion of the electrical connection structure is configured to also contact the corresponding additional contact from above.

8. The super junction power semiconductor device according to claim 5, wherein: The doped regions are separated by a separate portion of the epitaxial layer disposed between the pair of contacts.

9. The super junction power semiconductor device according to claim 1, wherein: The electrical connection structure includes a conductive bridging portion arranged at the top surface of the structural layer and closing the corresponding edge-terminated trench at the top; and a doped region in the structural layer, the doped region contacting the bridging portion and contacting one or more thin doped layers at the sidewalls of the respective edge termination trenches.

10. The super junction power semiconductor device according to claim 1, wherein: The electrical connection structures are not continuous along the extension direction of the corresponding edge termination deep trenches, but are regularly distributed at a given separation distance along the extension direction.

11. The super junction power semiconductor device according to claim 1, wherein: The superjunction power semiconductor device is a trench-gate power MOSFET device.

12. A process for manufacturing a superjunction power semiconductor device, comprising: forming an active area having active cells and an edge area surrounding the active area at the periphery of the die in a die of semiconductor material having a substrate and a structure layer having a first doping type on the substrate, Forming the active area includes forming a plurality of charge balancing deep trenches filled with a dielectric, the plurality of charge balancing deep trenches extending between corresponding active cell pairs through the structural layer and reaching the substrate, each charge balancing deep trench having a doping layer of the second doping type at its sidewall, forming an edge termination arrangement having a plurality of edge termination trenches at the edge region, the plurality of edge termination trenches extending through the structural layer and reaching the substrate, being filled with a dielectric material and having respective doped layers of a second doping type at their sidewalls; as well as Wherein, forming the edge termination arrangement includes forming an electrical connection structure configured to electrically connect corresponding doped layers at sidewalls of the plurality of edge termination trenches together.

13. The process for manufacturing a super junction power semiconductor device according to claim 12, wherein: Forming the electrical connection structure includes forming bridging conductive portions, each bridging conductive portion being disposed above and spanning a corresponding edge termination trench and electrically shorting the corresponding doped layer.

14. The process for manufacturing a super junction power semiconductor device according to claim 13, further comprising: forming a dielectric layer on a top surface of the structural layer; as well as Wherein, forming the electrical connection structure includes forming: a pair of contacts, the pair of contacts being arranged at one or more sides of the corresponding edge termination trench, traversing the dielectric layer and being designed to electrically contact the corresponding doped layer of the corresponding edge termination trench; and a blocking portion disposed on the dielectric layer and contacting the pair of contacts from above.

15. The process for manufacturing a super junction power semiconductor device according to claim 14, further comprising: before forming the plurality of edge termination trenches, forming a shallow trench in the structural layer at a top surface of the structural layer, the shallow trench comprising a polysilicon region separated from the epitaxial layer by a dielectric layer; forming a doped layer in a surface portion of the epitaxial layer at the top surface; And wherein forming the electrical connection structure comprises: forming a pair of contact openings through the dielectric layer and the underlying doped layer at one or more sides of each of the shallow trenches; filling the contact openings with a conductive material to form the pair of contacts; and A barrier layer of conductive material deposited on the dielectric layer is patterned to define the barrier portion.

16. The process for manufacturing a super junction power semiconductor device according to claim 15, wherein: Forming the electrical connection structure further includes: forming additional contacts across the dielectric layer to electrically contact the polysilicon regions of the corresponding shallow trenches; and The blocking portion of the electrical connection structure is configured to also contact the corresponding further contact from above.

17. The process for manufacturing a super junction power semiconductor device according to claim 14, further comprising: patterning a doped layer in a surface portion of the epitaxial layer at the top surface to define doped regions separated by separate portions of the epitaxial layer before forming the plurality of edge termination trenches; wherein the plurality of edge termination trenches are formed at the doping regions of the doping layer; and Wherein, forming the electrical connection structure includes: forming a pair of contact openings at one or more sides of the corresponding separated portions of the epitaxial layer, the pair of contact openings reaching the corresponding doped regions of the doped layer; filling the contact opening with a conductive material to define the pair of contacts; and A barrier layer of conductive material deposited on the dielectric layer is patterned to define the barrier portion.

18. The process for manufacturing a super junction power semiconductor device according to claim 13, wherein: Forming the electrical connection structure includes: forming contact holes at a top surface of the epitaxial layer at tops of the plurality of edge termination trenches; depositing and patterning a doped polysilicon layer to form a bridging portion within the contact hole that closes the plurality of edge termination trenches at top; and An annealing step is performed, thereby causing dopants to diffuse laterally from the doped polysilicon layer of the bridging portion and form a doped region in the structural layer, the doped region contacting the bridging portion and contacting one or more thin doped layers at sidewalls of corresponding edge termination trenches of the plurality of edge termination trenches.

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