Semiconductor device, preparation method and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method and electronic equipment, the semiconductor device comprises a semiconductor substrate, an insulating material layer and a gate structure, the gate structure comprises a high-k metal gate and a metal covering layer, and the metal covering layer is arranged on one side, back to the semiconductor substrate, of the high-k metal gate. The high-k metal gate comprises a gate metal layer, a high-k dielectric layer and a gate oxide layer. The metal covering layer covers at least part of the area of the surface, back to the semiconductor substrate, of the gate metal layer, and the resistivity of the metal film of the metal covering layer is smaller than that of the metal film of the gate metal layer, so that the resistance of the whole gate structure is reduced. Moreover, the resistivity of the metal film of the metal covering layer is smaller than that of the metal film of the gate metal layer, so that when the driving voltage is conducted in the extension direction of the high-k metal gate, the adverse effect of resistance on the driving voltage in the extension direction of the high-k metal gate is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art

[0002] With the development of complementary metal-oxide-semiconductor (CMOS) manufacturing processes, the feature size of CMOS devices has become smaller and smaller, resulting in the gate structure in CMOS devices generally adopting high-k (dielectric constant) metal gate (HKMG). However, as the critical dimension (CD) of the high-k metal gate shrinks, after the high-k dielectric layer and gate oxide layer are set, the filling ratio of the metal gate (such as W) will decrease, resulting in an increase in the resistance of the high-k metal gate. In addition, the high-k metal gate also has resistance in the extension direction. After the high-k metal gate receives the driving voltage through the contact hole (contact), the driving voltage is also highly affected by the resistance during the conduction process along the extension direction of the high-k metal gate, affecting device performance. Summary of the Invention

[0003] The present application provides a semiconductor device, a manufacturing method, and an electronic device for reducing the resistance of a gate structure and reducing the influence of the resistance in the extension direction of a high-k metal gate on a driving voltage.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a semiconductor substrate, an insulating material layer, and a gate structure, wherein the semiconductor substrate includes a channel region, the insulating material layer is disposed on the semiconductor substrate, and the insulating material layer has a groove, the groove being used to expose the channel region. The gate structure is filled in the groove, and the gate structure includes a high-k metal gate and a metal capping layer, the metal capping layer being disposed on the side of the high-k metal gate facing away from the semiconductor substrate, the high-k metal gate including a gate metal layer, a high-k dielectric layer disposed between the gate metal layer and the trench, and a gate oxide layer disposed between the high-k dielectric layer and the trench. In the present application, the metal capping layer covers at least a portion of the surface of the gate metal layer facing away from the semiconductor substrate, and the metal film resistivity of the metal capping layer is less than the metal film resistivity of the gate metal layer, thereby reducing the resistance of the entire gate structure. Moreover, since the metal film resistivity of the metal covering layer is lower than that of the gate metal layer, when the driving voltage is conducted through the metal covering layer (or the combined structure of the metal covering layer and the gate metal layer) in the extension direction of the high-k metal gate, the adverse effect of the resistance on the driving voltage in the extension direction of the high-k metal gate is reduced, thereby improving device performance.

[0005] Furthermore, because the metal capping layer covers at least a portion of the surface of the gate metal layer facing away from the semiconductor substrate, the contact resistance of the high-k metal gate can be reduced. Furthermore, the provision of the metal capping layer eliminates the need for restricting the manufacturing process of the high-k metal gate, allowing the high-k metal gate to be directly manufactured using the manufacturing processes known in the art, thereby reducing the design and manufacturing costs of the high-k metal gate.

[0006] In the present application, the material of the gate metal layer can be set to one or a combination of tungsten (W) and cobalt (Co). If the material of the gate metal layer is set to tungsten, the material of the metal cover layer in the present application can be selected from a material whose metal film resistivity is less than that of tungsten. Alternatively, if the material of the gate metal layer is set to cobalt, the material of the metal cover layer in the present application can be selected from a material whose metal film resistivity is less than that of cobalt. Alternatively, if the material of the gate metal layer is set to a combination of tungsten and cobalt, the material of the metal cover layer in the present application can be selected from a material whose metal film resistivity is less than that of the metal film resistivity of the combination of tungsten and cobalt.

[0007] Since the resistivity of metal films increases with the reduction of feature size, the resistivity of metal films of molybdenum (Mo) and ruthenium (Ru) increases at a slower rate and has high thermal stability. In the embodiment of the present application, the material of the metal covering layer can be set to one or a combination of molybdenum and ruthenium. In addition, since Mo has good adhesion to the surrounding dielectric materials during process integration and does not require film layers such as TiN / TaN adhesion layers to occupy space. Therefore, in different application scenarios and structures of semiconductor devices, Mo has different degrees of advantages over materials such as W, Co, and Ru. Based on this, in practical applications, Mo can be preferentially used to form a metal covering layer to reduce the resistance of the gate structure.

[0008] In some embodiments, the metal capping layer covers the entire surface of the gate metal layer facing away from the semiconductor substrate. Thus, the metal capping layer covers the entire surface of the gate metal layer facing away from the semiconductor substrate, further reducing the resistance of the entire gate structure and the adverse effect of the resistance on the driving voltage in the direction in which the high-k metal gate extends, thereby further improving device performance. Furthermore, because the metal capping layer covers the entire surface of the gate metal layer facing away from the semiconductor substrate, the contact resistance of the high-k metal gate can be further reduced.

[0009] In some embodiments, the metal capping layer covers the entire surface of the high-k metal gate facing away from the semiconductor substrate. This arrangement is equivalent to the metal capping layer directly contacting the sidewalls of the trench, further increasing the area of ​​the metal capping layer, further reducing the resistance of the entire gate structure, further reducing the adverse effect of the resistance on the driving voltage in the extension direction of the high-k metal gate, and further reducing the contact resistance of the high-k metal gate.

[0010] In some embodiments, the high-k metal gate further includes a work function layer disposed between the high-k dielectric layer and the gate metal layer. Thus, the work function layer provides a desired work function for the transistor to enhance device performance, such as improved threshold voltage.

[0011] Exemplarily, the work function layer can be configured to be a metal, metal carbide, metal nitride, or a combination thereof that can provide a work function value suitable for the device. For example, the work function layer can be made of tantalum, tantalum nitride, or a combination thereof. Alternatively, the work function layer can also be made of titanium, titanium nitride, or a combination thereof.

[0012] In some embodiments, in order to transmit signals to the gate structure, the semiconductor device further includes a first insulating dielectric layer and a gate contact portion, the first insulating dielectric layer is filled in the groove, and the first insulating dielectric layer is arranged on the side of the metal cover layer facing away from the semiconductor substrate. In addition, the first insulating dielectric layer has a gate contact hole, the gate contact hole is used to expose a portion of the surface area of ​​the metal cover layer facing away from the semiconductor substrate, the gate contact portion is filled in the gate contact hole, and the gate contact portion is connected to the metal cover layer. Exemplarily, the first end of the gate contact portion can be in direct contact with the metal cover layer to achieve electrical connection and reduce contact resistance. Afterwards, one or more layers of interconnection layers can be prepared on the side of the gate structure facing away from the semiconductor substrate to transmit signals for the semiconductor device through the interconnection layer. Based on this, the second end of the gate contact portion can be connected to one of the interconnection layers, and the signal is transmitted to the gate structure through the interconnection layer and the gate contact portion.

[0013] In some embodiments, the insulating material layer may include a first gate spacer and a second gate spacer spaced apart from each other, and the spacing area between the first gate spacer and the second gate spacer may form the above-mentioned groove, that is, the gate structure is arranged between the first gate spacer and the second gate spacer to reduce the short channel effect through the first gate spacer and the second gate spacer.

[0014] In some embodiments, the semiconductor substrate further includes a first polar region and a second polar region disposed on either side of the channel region, the first gate spacer covering a portion of the first polar region, and the second gate spacer covering a portion of the second polar region. Furthermore, the insulating material layer further includes a second insulating dielectric layer, the second insulating dielectric layer covering a portion of the first polar region not covered by the first gate spacer and a portion of the second polar region not covered by the second gate spacer. The second insulating dielectric layer has a first contact hole and a second contact hole, the first contact hole being configured to expose a portion of the first polar region not covered by the first gate spacer, and the second contact hole being configured to expose a portion of the second polar region not covered by the second gate spacer. Furthermore, to facilitate signal transmission, the semiconductor device further includes a first contact portion and a second contact portion, the first contact portion being filled in the first contact hole and connected to the first polar region, and the second contact portion being filled in the second contact hole and connected to the second polar region. With this arrangement, signals can be transmitted to the first polar region via the first contact portion, and to the second polar region via the second contact portion. Furthermore, the first contact portion can be connected to one of the aforementioned interconnect layers, with signals being transmitted to the first polar region via the interconnect layer and the first contact portion. Furthermore, the second contact portion may be connected to one of the above-mentioned interconnection layers, and a signal may be transmitted to the second polar region through the interconnection layer and the second contact portion.

[0015] In a second aspect, an embodiment of the present application further provides an electronic device, which includes various terminal devices and electronic devices. For example, the terminal devices include but are not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (PCs), wearable devices, smart broadband and other devices. The electronic devices include but are not limited to communication devices such as wireless networks, fixed networks, servers, and device modules, memories and other devices, which are not listed here one by one. In addition, the electronic device includes a circuit board and a semiconductor device, which is arranged on the circuit board. The semiconductor device can be a semiconductor device as in the first aspect or various possible designs of the first aspect. Since the above-mentioned semiconductor device can reduce the resistance of the gate structure and reduce the influence of the resistance in the extension direction of the high-k metal gate on the driving voltage, the performance of the above-mentioned semiconductor device is better, and thus the performance of the electronic device including the above-mentioned semiconductor device is also better. In addition, the principle of solving the problem of the electronic device is similar to the principle that the aforementioned semiconductor device can solve the problem, so the technical effect of the electronic device can refer to the technical effect of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0016] In a third aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, the method comprising:

[0017] forming a dummy gate structure, a first polar region, a second polar region, and an insulating material layer on the channel region of the semiconductor substrate, with the insulating material layer exposing a surface of the dummy gate structure facing away from the semiconductor substrate, and with the insulating material layer covering at least a portion of the first polar region and at least a portion of the second polar region;

[0018] Etching and removing the dummy gate structure to form a groove in the insulating material layer, and making the groove expose the channel region;

[0019] Depositing a high-k metal gate in the groove, wherein the high-k metal gate includes a gate metal layer, a high-k dielectric layer disposed between the gate metal layer and the trench, and a gate oxide layer disposed between the high-k dielectric layer and the trench;

[0020] Depositing a metal capping layer on the sidewalls of the groove and on the surface of the high-k metal gate facing away from the semiconductor substrate, wherein the thickness of the metal capping layer at the sidewalls of the groove is smaller than the thickness of the metal capping layer at the surface of the high-k metal gate facing away from the semiconductor substrate; and the metal film resistivity of the metal capping layer is smaller than the metal film resistivity of the gate metal layer;

[0021] The metal covering layer is etched to remove the metal covering layer at the sidewall of the groove, and the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate is thinned.

[0022] In some embodiments, depositing the metal capping layer may include the following process: depositing the metal capping layer using a physical vapor deposition process, thereby forming a thickness difference. Exemplarily, the physical vapor deposition process includes but is not limited to magnetron sputtering.

[0023] In some embodiments, the ratio of the lateral and vertical etching rates can also be adjusted by adjusting the parameters of the etching process. For example, the etching rate of the metal covering layer at the side wall of the etching groove is greater than or equal to the etching rate of the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate, thereby completely etching the metal covering layer at the side wall of the groove and thinning the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate, thereby retaining a certain thickness of the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0025] Figure 2 A schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0026] Figures 3a to 3h They are respectively a structural schematic diagram of a semiconductor device in an embodiment of the present application during the preparation process;

[0027] Figure 4 Schematic diagram of another structure of a semiconductor device in an embodiment of the present application;

[0028] Figures 5a to 5c They are respectively another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process;

[0029] Figure 6 This is another structural schematic diagram of the semiconductor device in the embodiment of the present application.

[0030] Reference numerals

[0031] 100-housing; 200-circuit board; 300-semiconductor device; 310-semiconductor substrate; 320-insulating material layer; 321a-first gate spacer; 321b-second gate spacer; 322-second insulating dielectric layer; 330-gate structure; 331-high-k metal gate; 332-metal capping layer; 3311-gate metal layer; 3312-high-k dielectric layer; 3313-gate oxide layer; 3314-work function layer; 341-first contact portion; 342-second contact portion; 343-gate contact portion; 350-shallow trench isolation structure; 360-first insulating dielectric layer; 410-dummy gate structure; A1-channel region; A2-first polar region; A3-second polar region; AX-groove; KG1-gate contact hole; KG2-first contact hole; KG3-second contact hole. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "at least one" means one or more, where "multiple" means two or more. In view of this, in the embodiments of the present application, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and next associated objects are in an "or" relationship. In addition, words such as "first" and "second" are only used for the purpose of distinguishing the description and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, in the embodiments of the present application, "connection" refers to electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, A and B are connected, which can be either directly connected to A and B or indirectly connected to A and B through one or more other electrical components. For example, A and B are connected, or A and C are directly connected, and C and B are directly connected, and A and B are connected through C.

[0033] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0034] In order to facilitate the understanding of the semiconductor device, preparation method and electronic device provided by the embodiment of the present application, the application scenario thereof is first introduced below. The semiconductor device provided by the embodiment of the present application can be widely used in various electronic devices, including various terminal devices and network devices. For example, terminal devices include but are not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (personal computers, PCs), wearable devices, smart broadband and other devices. Network devices include but are not limited to wireless network devices, fixed network devices, servers and other communication devices, as well as device modules, memories, etc., which are not listed here one by one.

[0035] Figure 1 This is a structural diagram of an electronic device in an embodiment of the present application. Figure 1The electronic device includes a housing 100, a circuit board 200 disposed within the housing 100, and a semiconductor device 300 secured to the circuit board 200. The semiconductor device 300 and the circuit board 200 may be electrically connected using bonding, adhesive bonding, or other connection methods, thereby enabling signal transmission between the semiconductor device 300 and the circuit board 200. For example, the semiconductor device 300 may be a chip, such as a logic processing chip or a memory chip, without limitation herein.

[0036] It is understandable that the structure shown in the embodiment of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include Figure 1 More or fewer components than those shown in the figures may be used, some components may be combined, some components may be separated, or different component arrangements may be used.

[0037] Figure 2 This is a schematic diagram of the structure of a semiconductor device in an embodiment of the present application. Figure 2The semiconductor device 300 proposed in this application may include: a semiconductor substrate 310, an insulating material layer 320, and a gate structure 330. The semiconductor substrate 310 includes a channel region A1, the insulating material layer 320 is disposed on the semiconductor substrate 310, and the insulating material layer 320 has a groove AX, which is used to expose the channel region A1. In addition, the gate structure 330 is filled in the groove AX, and the gate structure 330 includes a high-k metal gate 331 and a metal capping layer 332. The metal capping layer 332 is disposed on the side of the high-k metal gate 331 facing away from the semiconductor substrate 310. In addition, the high-k metal gate 331 may include a gate metal layer 3311, a high-k dielectric layer 3312 disposed between the gate metal layer 3311 and the trench, and a gate oxide layer 3313 disposed between the high-k dielectric layer 3312 and the trench. In practical applications, the resistivity of the metal film increases as the feature size decreases, and generally increases significantly when it decreases to below about 20nm. This phenomenon is related to various factors such as the mean free path of electrons in the material and grain boundary scattering. Since the metal film resistivity of different metal materials increases to different degrees as the feature size decreases, in this application, by covering at least a portion of the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310 with a metal capping layer 332, and making the metal film resistivity of the metal capping layer 332 lower than the metal film resistivity of the gate metal layer 3311, the resistance of the entire gate structure 330 can be reduced. In addition, since the metal film resistivity of the metal capping layer 332 is lower than the metal film resistivity of the gate metal layer 3311, the driving voltage can be transmitted through the metal capping layer 332 (or the combined structure of the metal capping layer 332 and the gate metal layer 3311) in the extension direction of the high-k metal gate 331, thereby reducing the adverse effect of the resistance on the driving voltage in the extension direction of the high-k metal gate 331, thereby improving device performance.

[0038] Furthermore, because the metal capping layer 332 covers at least a portion of the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310, the contact resistance of the high-k metal gate 331 can be reduced. Furthermore, the provision of the metal capping layer 332 eliminates the need to restrict the manufacturing process of the high-k metal gate 331, allowing the high-k metal gate 331 to be manufactured directly using a manufacturing process known in the art. This also reduces the design and manufacturing costs of the high-k metal gate 331.

[0039] Reference Figure 2The gate oxide layer 3313 is disposed on the bottom wall of the recess AX, but not on the sidewalls of the recess AX. That is, the gate oxide layer is disposed between the high-k dielectric layer 3312 and the bottom wall of the recess AX. In actual processes, the gate oxide layer 3313 can be formed by oxidizing the surface of the semiconductor substrate in the channel region. It is understood that in another embodiment, the gate oxide layer 3313 can also be disposed on the sidewalls of the recess AX, which is not limited here.

[0040] Reference Figure 2 , the metal capping layer 332 can cover the entire area of ​​the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310, that is, the metal capping layer 332 does not cover the high-k dielectric layer 3312. With this configuration, the metal capping layer 332 can be used to cover the entire area of ​​the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310, further reducing the resistance of the entire gate structure 330 and further reducing the adverse effect of the resistance on the driving voltage in the extension direction of the high-k metal gate 331, thereby further improving device performance. In addition, because the metal capping layer 332 covers the entire area of ​​the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310, the contact resistance of the high-k metal gate 331 can be further reduced. It is worth mentioning that due to limitations in process conditions or other factors, some deviations or errors may exist in the actual process, resulting in the description in this patent that "the metal covering layer 332 covers the entire area of ​​the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310" may not be completely accurate. For example, the description above of "the metal covering layer 332 covers the entire area of ​​the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310" may be allowed within the allowable error range. Therefore, as long as the relationship described above of "the metal covering layer 332 covers the entire area of ​​the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310" roughly meets the above conditions, it falls within the scope of protection of this application.

[0041] Reference Figure 2The metal capping layer 332 can cover the entire surface area of ​​the high-k metal gate 331 facing away from the semiconductor substrate 310. That is, the metal capping layer 332 covers the entire surface area of ​​the gate metal layer 3311 facing away from the semiconductor substrate 310 and the entire surface area of ​​the high-k dielectric layer 3312 facing away from the semiconductor substrate 310. This configuration is equivalent to the metal capping layer 332 directly contacting the sidewalls of the trench, further increasing the area of ​​the metal capping layer 332, further reducing the resistance of the entire gate structure 330, further reducing the adverse effect of the resistance on the driving voltage in the extension direction of the high-k metal gate 331, and further reducing the contact resistance of the high-k metal gate 331. It is worth mentioning that due to limitations in process conditions or other factors, some deviations or errors may exist in the actual process, resulting in the description in this patent that "the metal cover layer 332 covers the entire surface area of ​​the high-k metal gate 331 on the side facing away from the semiconductor substrate 310" may not be completely accurate. For example, the description above of "the metal cover layer 332 covers the entire surface area of ​​the high-k metal gate 331 on the side facing away from the semiconductor substrate 310" may be allowed within the allowable error range. Therefore, as long as the relationship described above that "the metal cover layer 332 covers the entire surface area of ​​the high-k metal gate 331 on the side facing away from the semiconductor substrate 310" roughly meets the above conditions, it falls within the scope of protection of this application.

[0042] In the present application, the material of the gate metal layer 3311 can be set to one or a combination of tungsten (W) and cobalt (Co). Among them, if the material of the gate metal layer 3311 is set to tungsten, the material of the metal cover layer 332 in the present application can be selected from a material whose metal film resistivity is less than that of tungsten. Alternatively, if the material of the gate metal layer 3311 is set to cobalt, the material of the metal cover layer 332 in the present application can be selected from a material whose metal film resistivity is less than that of cobalt. Alternatively, if the material of the gate metal layer 3311 is set to a combination of tungsten and cobalt, the material of the metal cover layer 332 in the present application can be selected from a material whose metal film resistivity is less than that of the metal film resistivity of the combination of tungsten and cobalt.

[0043] Since the resistivity of metal films increases with the reduction of feature size, the resistivity increase rate of metal films of molybdenum (Mo) and ruthenium (Ru) is relatively slow and the thermal stability is high. In the embodiment of the present application, the material of the metal capping layer 332 can be set to one or a combination of molybdenum and ruthenium. In addition, since Mo has good adhesion to the surrounding dielectric materials in process integration and does not require film layers such as TiN / TaN adhesion layers to occupy space. Therefore, in different application scenarios and structures of semiconductor devices, Mo has different degrees of advantages over materials such as W, Co, and Ru. Based on this, in practical applications, Mo can be preferentially used to form the metal capping layer 332 to reduce the resistance of the gate structure 330. It is worth mentioning that when the metal capping layer 332 covers the entire area of ​​the surface of the high-k metal gate 331 facing away from the semiconductor substrate 310, it is estimated that the use of Mo to form the metal capping layer 332 can reduce the resistance by about 30%. It is understandable that the 30% is only estimated and does not represent the percentage by which the resistance of a semiconductor device must be reduced in actual applications. Due to the influence of different process conditions and preparation factors, the specific value of the percentage by which the resistance of the semiconductor device actually prepared can be reduced may be different. Therefore, the percentage by which the resistance of the semiconductor device actually prepared can be reduced needs to be determined based on actual applications and is not limited here.

[0044] Continue to refer to Figure 2 The insulating material layer 320 includes a first gate spacer 321a and a second gate spacer 321b spaced apart from each other, and a groove AX is formed in the spacing area between the first gate spacer 321a and the second gate spacer 321b, that is, a gate structure 330 is arranged between the first gate spacer 321a and the second gate spacer 321b to reduce the short channel effect through the first gate spacer 321a and the second gate spacer 321b.

[0045] Continue to refer to Figure 2 The semiconductor substrate 310 further includes a first polar region A2 and a second polar region A3 disposed on both sides of the channel region A1. The first gate spacer 321a covers a portion of the first polar region A2, and the second gate spacer 321b covers a portion of the second polar region A3. Furthermore, the insulating material layer 320 further includes a second insulating dielectric layer 322. The second insulating dielectric layer 322 covers a portion of the first polar region A2 not covered by the first gate spacer 321a and a portion of the second polar region A3 not covered by the second gate spacer 321b.

[0046] It is understandable that the semiconductor device in the present application may have one or more transistors, wherein the gate structure 330 can serve as the gate of the transistor, the first polar region A2 can serve as the source region of the transistor, and the second polar region A3 can serve as the drain region of the transistor, or the first polar region A2 can serve as the drain region of the transistor, and the second polar region A3 can serve as the source region of the transistor. Moreover, when the semiconductor device has multiple transistors, the multiple transistors can share the same gate structure, that is, one gate structure can extend to cover the gates of multiple transistors. In addition, the dielectric constant (k) of the high-k dielectric layer 3312 is greater than the dielectric constant of silicon dioxide, which helps to reduce gate leakage and allow faster switching of transistors. In addition, in order to isolate different transistors, a shallow trench isolation (STI) structure 350 is also provided in the semiconductor substrate 310.

[0047] It is worth mentioning that the transistors in this application can be metal-oxide-semiconductor field-effect transistors (MOSFETs) of different structures. For example, MOSFETs can be Figure 2 The planar MOSFET device shown, or the MOSFET may also be a Fin Field-Effect Transistor (Fin FET), etc., and the implementation of its gate may refer to the implementation of the planar MOSFET device and is not limited here.

[0048] To prepare Figure 2 Taking the structure of the semiconductor device shown in FIG. 1 as an example, the method for manufacturing the semiconductor device provided in the embodiment of the present application may include the following contents:

[0049] (1)Reference Figure 3a , Figure 3aThis is a structural schematic diagram of a semiconductor device in an embodiment of the present application during the preparation process. A semiconductor substrate 310 is provided, and the semiconductor substrate 310 can have various structures. For example, the semiconductor substrate 310 is a silicon substrate, a silicon-on-insulator (SOI) substrate, etc., wherein the SOI substrate can have a stacked lower silicon layer, a buried insulating layer, and an upper silicon layer. STI trenches can be formed by etching the upper silicon layer or the silicon substrate of the SOI substrate, and a dielectric material (for example, silicon dioxide, silicon nitride, etc.) is deposited in the STI trench to form an STI structure 350, thereby defining the area where the transistor is located. Afterwards, a dummy gate structure 410 is formed on the semiconductor substrate 310 where the channel region A1 needs to be formed. The dummy gate structure may include a dummy gate and a dummy gate oxide layer disposed between the dummy gate and the semiconductor substrate. Afterwards, a first gate sidewall 321a and a second gate sidewall 321b are formed on the semiconductor substrate 310 on both sides of the dummy gate structure 410. Exemplarily, the material of the dummy gate may be polysilicon or metal, which is not limited here.

[0050] (2)Reference Figure 3b , Figure 3b This is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. Among them, the area of ​​the semiconductor substrate 310 on the side of the first gate sidewall 321a facing away from the dummy gate structure 410 and the area on the side of the second gate sidewall 321b facing away from the dummy gate structure 410 are doped respectively to form a first polar region A2 and a second polar region A3. For example, an ion implantation process can be used to perform ion doping on the area of ​​the semiconductor substrate 310 on the side of the first gate sidewall 321a facing away from the dummy gate structure 410 and the area on the side of the second gate sidewall 321b facing away from the dummy gate structure 410 to form a first polar region A2 and a second polar region A3. In addition, the doping ions in the first polar region A2 and the second polar region A3 can be N-type doping ions, such as one or more of phosphorus ions, arsenic ions and antimony ions. Alternatively, the doping ions in the first polar region A2 and the second polar region A3 can be P-type doping ions, such as one or more of boron ions and aluminum ions.

[0051] (3)Reference Figure 3c , Figure 3c FIG3 is another structural diagram of a semiconductor device during fabrication according to an embodiment of the present application. A dielectric material (e.g., silicon dioxide, silicon nitride, etc.) is deposited on a semiconductor substrate 310 to form a second insulating dielectric layer 322. The second insulating dielectric layer 322 covers the area of ​​the first polar region A2 not covered by the first gate spacer 321a and the area of ​​the second polar region A3 not covered by the second gate spacer 321b.

[0052] (4)Reference Figure 3d , Figure 3d This is another structural diagram of the semiconductor device during the manufacturing process in an embodiment of the present application, wherein the dummy gate structure 410 is removed by etching, and a groove AX is formed between the first gate spacer 321a and the second gate spacer 321b, so that the groove AX exposes the channel region A1.

[0053] (5)Reference Figure 3e , Figure 3e Schematic diagram of another structure of the semiconductor device in the manufacturing process of the embodiment of the present application. In which, a gate oxide layer 3313 is formed on the bottom wall of the groove AX, so that the gate oxide layer 3313 covers the channel area A1 of the semiconductor substrate 310. Then, tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicate (HfSiO x ) or other high-k dielectric materials, a high-k dielectric layer 3312 is deposited, and the high-k dielectric layer 3312 covers the gate oxide layer 3313, covers the sidewalls of the first gate spacer 321a located in the groove AX, covers the sidewalls of the second gate spacer 321b located in the groove AX, covers the surface of the first gate spacer 321a facing away from the semiconductor substrate 310, covers the surface of the second gate spacer 321b facing away from the semiconductor substrate 310, and covers the surface of the second insulating dielectric layer 322 facing away from the semiconductor substrate 310. Subsequently, a gate metal layer 3311 is deposited on the high-k dielectric layer 3312 using a metal material such as tungsten or cobalt, and the gate metal layer 3311, the high-k dielectric layer 3312, and the gate oxide layer 3313 fill the groove AX. In this way, a high-k metal gate 331 is formed.

[0054] (6)Reference Figure 3f , Figure 3f : This is another structural schematic diagram of the semiconductor device in the embodiment of the present application during the preparation process. In particular, the high-k dielectric layer 3312 and the gate metal layer 3311 are planarized by a chemical mechanical polishing (CMP) process to remove the portions of the high-k dielectric layer 3312 and the gate metal layer 3311 outside the groove AX. Thereafter, an etching process is used to etch the high-k dielectric layer 3312 and the gate metal layer 3311, respectively, so that the high-k dielectric layer 3312 and the gate metal layer 3311 are embedded in the groove AX, that is, the surface of the high-k dielectric layer 3312 facing away from the semiconductor substrate 310 and the surface of the gate metal layer 3311 facing away from the semiconductor substrate 310 are both lower than the surface of the first gate sidewall 321a facing away from the semiconductor substrate 310 and the surface of the second gate sidewall 321b facing away from the semiconductor substrate 310.

[0055] (7)Reference Figure 3g , Figure 3gAnother structural schematic diagram of the semiconductor device in the preparation process of the embodiment of the present application. Among them, a metal material with a resistivity of the metal thin film less than that of the metal thin film resistor of the gate metal layer 3311, such as one or a combination of molybdenum and ruthenium, is used to deposit a metal covering layer 332 on the side wall of the groove AX and the surface of the gate metal layer 3311 (or high-k metal gate 331) on the side facing away from the semiconductor substrate 310, and the thickness H1 of the metal covering layer 332 at the side wall of the groove AX is less than the thickness H2 of the metal covering layer 332 at the surface of the gate metal layer 3311 (or high-k metal gate 331) on the side facing away from the semiconductor substrate 310. In addition, a metal covering layer 332 with a thickness of H4 may also be deposited on the surface of the first gate sidewall 321a on the side facing away from the semiconductor substrate 310, the surface of the second gate sidewall 321b on the side facing away from the semiconductor substrate 310, and the surface of the second insulating dielectric layer 322 on the side facing away from the semiconductor substrate 310, and this H4 may be the same as H2 or H4 is greater than or less than H2.

[0056] Exemplarily, a physical vapor deposition (PVD) process can be used to deposit the metal covering layer 332, and the deposition rate of the metal covering layer 332 deposited on the surface of the high-k metal gate 331 on the side facing away from the semiconductor substrate 310 is greater than the deposition rate of the metal covering layer 332 at the side wall of the groove AX, so as to form a thickness difference between H1 and H2. For example, the PVD process includes but is not limited to magnetron sputtering.

[0057] (8) Refer to Figure 3h , Figure 3h Another structural schematic diagram of the semiconductor device in the preparation process of the embodiment of the present application. Among them, an etching process is used to etch the metal covering layer 332 to remove the metal covering layer 332 at the side wall of the groove AX and thin the metal covering layer 332 at the surface of the gate metal layer 3311 (or high-k metal gate 331) on the side facing away from the semiconductor substrate 310. And the thickness of the thinned metal covering layer 332 is H3, and H3 < H2. It can be understood that H3 may be the same as H1, or H3 may also be different from H1, for example, H3 < H1 or H1 < H3.

[0058] For example, the ratio of the lateral and vertical etching rates can also be adjusted by adjusting the parameters of the etching process. For example, the etching rate of the metal covering layer 332 at the side wall of the etching groove AX is adjusted to be greater than or equal to the etching rate of the metal covering layer 332 at the surface of the high-k metal gate 331 facing away from the semiconductor substrate 310, thereby completely etching the metal covering layer 332 at the side wall of the groove AX and thinning the metal covering layer 332 at the surface of the high-k metal gate 331 facing away from the semiconductor substrate 310, thereby allowing a certain thickness of the metal covering layer 332 to be retained on the surface of the high-k metal gate 331 facing away from the semiconductor substrate 310.

[0059] In addition, when a metal covering layer 332 is deposited on the surface of the first gate spacer 321a facing away from the semiconductor substrate 310, the surface of the second gate spacer 321b facing away from the semiconductor substrate 310, and the surface of the second insulating dielectric layer 322 facing away from the semiconductor substrate 310, the metal covering layer 332 in this area can be partially retained or completely removed.

[0060] Figure 4 This is another structural diagram of the semiconductor device in the embodiment of the present application, referring to Figure 4 The semiconductor device in this embodiment is a variation of the semiconductor device in the above embodiment. Similarities are not described here. The difference lies in that, to enable signal transmission to the gate structure 330, the semiconductor device 300 further includes: a first insulating dielectric layer 360 and a gate contact 343. The first insulating dielectric layer 360 is disposed in the recess AX and on the side of the metal capping layer 332 facing away from the semiconductor substrate 310. Furthermore, the first insulating dielectric layer 360 has a gate contact hole KG1, which is used to expose a portion of the surface of the metal capping layer 332 facing away from the semiconductor substrate 310. The gate contact 343 is filled in the gate contact hole KG1 and connected to the metal capping layer 332. For example, the first end of the gate contact 343 is in direct contact with the metal capping layer 332, achieving electrical connection and reducing contact resistance. Subsequently, one or more interconnect layers can be formed on the side of the gate structure 330 facing away from the semiconductor substrate 310 to facilitate signal transmission for the semiconductor device via the interconnect layers. Based on this, the second end of the gate contact 343 may be connected to one of the interconnection layers, and a signal may be transmitted to the gate structure 330 through the interconnection layer and the gate contact 343 .

[0061] In order to transmit the signal to the first polar region A2, refer to Figure 4A first contact hole KG2 is provided in the second insulating dielectric layer 322. The first contact hole KG2 is used to expose a portion of the first polar region A2 that is not covered by the first gate spacer 321a. The first contact hole KG2 is filled with a first contact portion 341, and the first contact portion 341 is connected to the first polar region A2. Exemplarily, the first end of the first contact portion 341 is in direct contact with the first polar region A2 to achieve electrical connection, or a metal silicide is provided between the first end of the first contact portion 341 and the first polar region A2 to achieve electrical connection through the metal silicide and reduce contact resistance. In addition, the second end of the first contact portion 341 is connected to one of the interconnect layers, and a signal is transmitted to the first polar region A2 through the interconnect layer and the first contact portion 341.

[0062] In order to transmit the signal to the second polar region A3, refer to Figure 4 , a second contact hole KG3 is also provided in the second insulating dielectric layer 322. The second contact hole KG3 is used to expose a portion of the second polar region A3 that is not covered by the second gate spacer 321b. The second contact hole KG3 is filled with a second contact portion 342, and the second contact portion 342 is connected to the second polar region A3. Exemplarily, the first end of the second contact portion 342 is in direct contact with the second polar region A3 to achieve electrical connection, or a metal silicide is provided between the first end of the second contact portion 342 and the second polar region A3 to achieve electrical connection through the metal silicide and reduce contact resistance. In addition, the second end of the second contact portion 342 is connected to one of the interconnect layers, and a signal is transmitted to the second polar region A3 through the interconnect layer and the second contact portion 342.

[0063] in addition, Figure 4 The method for manufacturing the structure of the semiconductor device shown can be modified from the method in the above embodiment, and the difference lies in that:

[0064] exist Figure 3g Afterwards, refer to Figure 5a , Figure 5a FIG2 is another structural schematic diagram of a semiconductor device during fabrication in an embodiment of the present application. An etching process is employed to etch the metal capping layer 332, remove the metal capping layer 332 from the sidewalls of the groove AX, and thin the metal capping layer 332 at the surface of the gate metal layer 3311 (or high-k metal gate 331) facing away from the semiconductor substrate 310. Furthermore, the surface of the metal capping layer 332 at the surface of the gate metal layer 3311 (or high-k metal gate 331) facing away from the semiconductor substrate 310 is lower than both the surface of the first gate spacer 321a facing away from the semiconductor substrate 310 and the surface of the second gate spacer 321b facing away from the semiconductor substrate 310, thereby forming a half-filled structure of the metal capping layer 332 in the groove AX.

[0065] Reference Figure 5b , Figure 5b This is another structural schematic diagram of a semiconductor device during fabrication in an embodiment of the present application. A dielectric material is deposited in the groove AX on the side of the metal capping layer 332 facing away from the semiconductor substrate 310 to form a first insulating dielectric layer 360. The first insulating dielectric layer 360 may cover the entire surface area of ​​the metal capping layer 332 facing away from the semiconductor substrate 310. It is worth noting that due to process limitations or other factors, some deviations or errors may exist in actual processes, resulting in the description in this patent that "the first insulating dielectric layer 360 may cover the entire surface area of ​​the metal capping layer 332 facing away from the semiconductor substrate 310" may not be completely accurate. For example, the description above that "the first insulating dielectric layer 360 may cover the entire surface area of ​​the metal capping layer 332 facing away from the semiconductor substrate 310" may be within the allowable error range. Therefore, as long as the above conditions are generally met, the description that "the first insulating dielectric layer 360 may cover the entire surface area of ​​the metal capping layer 332 facing away from the semiconductor substrate 310" falls within the scope of protection of this application. Next, an etching process is used to etch the first insulating dielectric layer 360 to form a gate contact hole KG1 that penetrates the first insulating dielectric layer 360. The gate contact hole KG1 exposes a portion of the surface of the metal cover layer 332 facing away from the semiconductor substrate 310. A metal material is then deposited in the gate contact hole KG1 to form a gate contact 343, thereby connecting the gate contact 343 to the metal cover layer 332.

[0066] Reference Figure 5c , Figure 5c This is another structural schematic diagram of the semiconductor device during the fabrication process in an embodiment of the present application. An etching process is used to etch the second insulating dielectric layer 322 to form a first contact hole KG2 and a second contact hole KG3 that penetrate the second insulating dielectric layer 322. The first contact hole KG2 exposes a portion of the first polar region A2, and the second contact hole KG3 exposes a portion of the second polar region A3. Subsequently, metal material is deposited in the first contact hole KG2 and the second contact hole KG3 to form a first contact portion 341 and a second contact portion 342. The first contact portion 341 is electrically connected to the first polar region A2, and the second contact portion 342 is electrically connected to the second polar region A3.

[0067] Figure 6 This is another structural diagram of the semiconductor device in the embodiment of the present application, referring to Figure 6The semiconductor device in this embodiment is a modification of the semiconductor device in the above embodiment. Similarities are not described here. The difference lies in that the high-k metal gate 331 further includes a work function layer 3314, and the work function layer 3314 is disposed between the high-k dielectric layer 3312 and the gate metal layer 3311. Thus, the work function layer 3314 provides a desired work function for the transistor to enhance device performance, such as improving the threshold voltage.

[0068] For example, the work function layer 3314 can be configured to be a metal, metal carbide, metal nitride, or a combination thereof that can provide a work function value suitable for the device. For example, the work function layer 3314 can be made of tantalum, tantalum nitride, or a combination thereof. Alternatively, the work function layer 3314 can also be made of titanium, titanium nitride, or a combination thereof.

[0069] in addition, Figure 6 The method for fabricating the structure of the semiconductor device shown in the figure can be modified from the method of the above embodiment. The difference lies in that after depositing a high-k dielectric layer 3312 on the gate oxide layer 3313, a work function layer 3314 is deposited on the high-k dielectric layer 3312 using a deposition process. Subsequently, a gate metal layer 3311 is deposited on the high-k dielectric layer 3312 using a metal material such as tungsten, cobalt, aluminum, or titanium. The gate metal layer 3311, the high-k dielectric layer 3312, and the gate oxide layer 3313 fill the recess AX. In this manner, a high-k metal gate 331 is formed.

[0070] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor substrate including a channel region; an insulating material layer, disposed on the semiconductor substrate, wherein the insulating material layer has a groove, and the groove is used to expose the channel region; a gate structure filled in the groove, the gate structure comprising a high-k metal gate and a metal covering layer, the metal covering layer being disposed on a side of the high-k metal gate facing away from the semiconductor substrate; The high-k metal gate includes a gate metal layer, a high-k dielectric layer arranged between the gate metal layer and the trench, and a gate oxide layer arranged between the high-k dielectric layer and the trench. The metal covering layer covers at least a portion of the surface of the gate metal layer facing away from the semiconductor substrate, and the metal film resistivity of the metal covering layer is less than the metal film resistivity of the gate metal layer.

2. The semiconductor device according to claim 1, wherein The material of the metal covering layer is one or a combination of molybdenum and ruthenium.

3. The semiconductor device according to claim 1 or 2, wherein: The metal capping layer covers the entire area of ​​the surface of the high-k metal gate facing away from the semiconductor substrate.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The high-k metal gate further includes a work function layer, and the work function layer is arranged between the high-k dielectric layer and the gate metal layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein: Also includes: a first insulating dielectric layer and a gate contact portion, wherein the first insulating dielectric layer fills the groove and is disposed on a side of the metal cover layer facing away from the semiconductor substrate; The first insulating dielectric layer has a gate contact hole, which is used to expose a portion of the surface of the metal cover layer facing away from the semiconductor substrate. The gate contact portion is filled in the gate contact hole and connected to the metal cover layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The insulating material layer includes a first gate spacer and a second gate spacer spaced apart from each other, and the groove is formed in a spaced area between the first gate spacer and the second gate spacer.

7. The semiconductor device according to claim 6, wherein The semiconductor substrate further includes a first polar region and a second polar region disposed on both sides of the channel region, the first gate spacer covers a portion of the first polar region, and the second gate spacer covers a portion of the second polar region; The insulating material layer further includes a second insulating dielectric layer, the second insulating dielectric layer covering a portion of the first polar region not covered by the first gate spacer and a portion of the second polar region not covered by the second gate spacer, the second insulating dielectric layer having a first contact hole and a second contact hole, the first contact hole being used to expose a portion of the first polar region not covered by the first gate spacer, and the second contact hole being used to expose a portion of the second polar region not covered by the second gate spacer; The semiconductor device further includes: a first contact portion and a second contact portion, wherein the first contact portion is filled in the first contact hole and connected to the first polar region, and the second contact portion is filled in the second contact hole and connected to the second polar region.

8. An electronic device, characterized in that: The invention comprises a circuit board and the semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is arranged on the circuit board.

9. A method for preparing a semiconductor device, characterized in that: include: forming a dummy gate structure, a first polar region, a second polar region, and an insulating material layer on a channel region of a semiconductor substrate, wherein the insulating material layer exposes a surface of the dummy gate structure facing away from the semiconductor substrate, and the insulating material layer covers at least a portion of the first polar region and at least a portion of the second polar region; Etching and removing the dummy gate structure to form a groove in the insulating material layer, and making the groove expose the channel region; Depositing a high-k metal gate in the groove, wherein the high-k metal gate includes a gate metal layer, a high-k dielectric layer disposed between the gate metal layer and the trench, and a gate oxide layer disposed between the high-k dielectric layer and the trench; Depositing a metal covering layer on the sidewalls of the groove and the surface of the high-k metal gate facing away from the semiconductor substrate, wherein the thickness of the metal covering layer at the sidewalls of the groove is smaller than the thickness of the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate; The metal film resistivity of the metal covering layer is less than the metal film resistivity of the gate metal layer; The metal covering layer is etched to remove the metal covering layer at the sidewall of the groove, and the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate is thinned.

10. The preparation method according to claim 9, wherein The deposited metal covering layer comprises: The metal capping layer is deposited using a physical vapor deposition process.

11. The preparation method according to claim 9 or 10, characterized in that: An etching rate of the metal covering layer at the sidewall of the groove is greater than or equal to an etching rate of the metal covering layer at the surface of the high-k metal gate facing away from the semiconductor substrate.

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