Method for manufacturing semiconductor device and semiconductor device
By forming a trench structure with a wide energy gap channel on the silicon substrate, the problem of spike electric fields caused by narrow band gap materials in the transistor structure is solved, and high-voltage, high-current transistor elements are realized, which are compatible with CMOS processes and avoid heat accumulation and complex process design.
Patent Information
- Application Number
- CN202410285701.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-19
AI Technical Summary
The narrow bandgap materials of existing transistor structures limit the application of high voltage and large current, leading to spike electric field problems, and traditional solutions are complex and difficult to integrate with low-voltage logic circuits.
A wide energy gap channel is formed on a silicon substrate by etching and depositing a wide energy gap semiconductor material layer to form a trench structure, which is compatible with CMOS technology and avoids heat accumulation problems.
The invention realizes high-voltage and high-current transistor elements under high voltage, solves specific problems that have not been solved in the prior art, realizes high-voltage and high-current transistor elements under high voltage, solves specific problems that have not been solved in the prior art, realizes surface morphology changes or special structures, solves specific problems that have not been solved in the prior art, realizes high-voltage and high-current transistor elements, solves the peak electric field problem that has not been effectively solved in the prior art, and is compatible with advanced CMOS manufacturing processes.
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Figure CN120676703A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device with a wide bandgap channel and a method for fabricating the same. Background Art
[0002] The rapid development of power electronics technologies in recent years, including solar electronics, automotive electronics, and high-frequency, high-power density power modules, has led to higher demands on the power density of power electronics. Furthermore, in response to the rise of electric vehicles, transistor technology is also evolving towards high voltage, high current, and high power. Summary of the Invention
[0003] One embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a patterned mask on the substrate; etching the substrate using the patterned mask to form a trench; depositing a material layer on the patterned mask and in the trench to form a channel in the trench, wherein the material layer is a wide band gap (WBG) semiconductor material; removing the patterned mask and the material layer on the patterned mask; and forming a plurality of transistors and a plurality of isolation features in the substrate and the channel.
[0004] In some embodiments, the substrate is a silicon substrate.
[0005] In some embodiments, depositing the material layer on the patterned mask and in the trenches includes conformally depositing the material layer.
[0006] In some embodiments, the wide bandgap semiconductor material comprises various third-generation semiconductor materials such as gallium nitride, silicon carbide, two-dimensional electron channel materials such as graphene, molybdenum disulfide, and oxide semiconductor materials such as gallium oxide, diamond, aluminum nitride, boron nitride, or other combinations thereof.
[0007] In some embodiments, the step of removing the material layer on the patterned mask includes removing and planarizing the material layer on the patterned mask and forming a top surface on the channel.
[0008] Another embodiment of the present disclosure provides a semiconductor device comprising a substrate, a channel, at least one first transistor, at least one second transistor, and at least one first isolation feature. The channel is formed in the substrate, wherein the channel comprises a wide-gap semiconductor material. The at least one first transistor is formed in the channel, and the at least one second transistor is formed in the substrate. The at least one first isolation feature is disposed between the at least one first transistor and the at least one second transistor.
[0009] In some embodiments, the top surface of the channel is coplanar with the top surface of the substrate.
[0010] In some embodiments, at least a first transistor includes a pair of first source / drain features disposed below a top surface of a channel; and a first gate disposed above the top surface of the channel.
[0011] In some embodiments, the at least one second transistor includes a pair of second source / drain features disposed below the top surface of the substrate and a second gate disposed above the top surface of the substrate.
[0012] In some embodiments, the semiconductor device further includes at least one second isolation feature and at least one third isolation feature, wherein the second isolation feature is disposed in the substrate, and the at least one third isolation feature is disposed in the channel. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The various aspects of the present disclosure will be most easily understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard operating procedures, various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. To make the above and other objects, features, advantages, and embodiments of the present disclosure more readily apparent, the accompanying drawings are described as follows:
[0014] Figure 1 A flow chart is shown of a method for fabricating a semiconductor device according to one embodiment of the present disclosure.
[0015] Figures 2 to 6 The figures are cross-sectional views of one embodiment of the semiconductor device fabricated according to the present disclosure at different fabrication stages. DETAILED DESCRIPTION
[0016] To provide a more complete and detailed description of the present disclosure, the following illustrative descriptions of embodiments and examples of the present disclosure are provided. However, these descriptions are not intended to be the only forms of implementing or using the embodiments of the present disclosure. The embodiments disclosed below may be combined or substituted with one another where beneficial, and other embodiments may be added to one embodiment without further description or explanation. In the following description, numerous specific details are detailed to facilitate a thorough understanding of the embodiments. However, the embodiments of the present disclosure may be practiced without these specific details.
[0017] Additionally, spatially relative terms, such as "lower" and "upper," are used to facilitate describing the relative relationship of one element or feature to other elements or features in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.
[0018] As used herein, unless the context specifically limits the use of the articles, "a," "an," and "the" may refer generally to one or more. It will be further understood that the use of "comprises," "includes," "has," and similar words herein specify the stated features, regions, integers, steps, operations, elements, and / or components, but does not exclude the stated or additional one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.
[0019] Furthermore, when a number or a range of numbers is described using the words "about," "approximately," and the like, the terms are intended to encompass numbers within a reasonable range that takes into account variations that inherently occur during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having characteristics associated with the number, a number or range of numbers encompasses a reasonable range that includes the described number, such as within + / - 10% of the described number. Furthermore, the present disclosure may repeatedly reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.
[0020] To achieve high-voltage, high-current transistors, trench transistors are becoming the trend in the development of high-power transistors. Silicon-complementary metal oxide semiconductor (Si-CMOS) fabrication allows the fabrication of various computing circuits on a single chip. However, the narrow bandgap (1.1V) of current transistor structures limits the operating Vcc to less than 10V, requiring additional diffusion length to dissipate the peak electric field. Traditionally, to address this issue, additional diffusion lengths or specialized processes have been designed, such as lateral double-diffused metal oxide semiconductor transistors (LDMOS), vertical double-diffused metal oxide semiconductor transistors (vertical DMOS), and insulated-gate bipolar transistors (IGBT). While these designs can effectively address the peak electric field, they are often complex and difficult to integrate with low-voltage logic circuits, increasing device processing complexity.
[0021] In view of this, some embodiments of the present disclosure provide a method for preparing a semiconductor device with a wide bandgap channel, in which a wide bandgap channel is formed in a high voltage operating area to replace the original silicon substrate. The material of the wide bandgap channel can be inserted before the CMOS process to solve the heat storage problem of the wide bandgap channel processing. Furthermore, this method does not require additional layout space loading, surface morphology changes or special structures, and is fully compatible with advanced CMOS manufacturing. The wide bandgap channel allows not only high voltage, but also low leakage. The wide bandgap channel structure can be processed for system-on-chips with multiple drain supply voltages (Vdd).
[0022] Several embodiments and experimental examples are listed below to further illustrate the method for manufacturing a semiconductor device and the semiconductor device disclosed herein. However, these are for illustration purposes only and are not intended to limit the present disclosure. The scope of protection of the present disclosure shall be determined by the appended claims.
[0023] Although the methods disclosed herein are described below using a series of operations or steps, the order in which these operations or steps are presented should not be construed as limiting the present disclosure. For example, certain operations or steps may be performed in a different order and / or concurrently with other steps. Furthermore, not all illustrated operations, steps, and / or features must be performed to implement the presently disclosed embodiments. Furthermore, each operation or step described herein may include multiple sub-steps or actions.
[0024] For the sake of clarity, features and elements that are known in the art and are not necessary for understanding the described principles may be omitted.
[0025] Figure 1 A flow chart illustrating a method for fabricating a semiconductor device according to one embodiment of the present disclosure is shown. Figures 2 to 6 The following are cross-sectional views of an embodiment of the semiconductor device disclosed herein at different stages of manufacture. Figure 1 As shown, the method 10 includes steps S11 to S16.
[0026] In step S11, a substrate 110 is provided, such as Figure 2 As shown. The substrate 110 is a silicon substrate. In some embodiments, the substrate 110 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.
[0027] In step S12, a patterned mask 120 is formed on the substrate 110, such as Figure 2 A patterned mask 120 is formed on the substrate 110 , wherein the patterned mask 120 exposes a portion of the substrate 110 that is intended to be a wide bandgap channel and masks the remaining portion of the substrate 110 .
[0028] In step S13, the substrate 110 is etched using the patterned mask 120 to form a trench 130, as shown in FIG. Figure 3 As shown. In detail, a photoresist layer is formed on the substrate 110, and the mask includes transparent and opaque features that form a pattern on the photoresist layer. Next, a developer removes multiple portions of the photoresist layer, thereby forming a photoresist pattern. The photoresist pattern is then used as a patterned mask 120 in a subsequent etching process to transfer the pattern to the substrate 110 below. There are two types of processes commonly used to develop exposed photoresist layers: a positive tone development (PTD) process and a negative tone development (NTD) process. The positive developer process uses a positive developer that selectively dissolves and removes multiple exposed portions of the photoresist layer. The negative developer process uses a negative developer that selectively dissolves and removes multiple unexposed portions of the photoresist layer. In some embodiments, the patterned mask 120 includes a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.
[0029] Next, a trench 130 etching process is performed, including using a dry etching or wet etching process to remove the portion of the substrate 110 that is not shielded by the patterned mask 120. In some embodiments, the depth of the etched trench 130 is selected to be deeper than the source / drain 151 region but shallower than the isolation feature 160 (e.g., Figure 6 (as shown) to protect the transistor from damage by high voltage, achieving high-voltage resistance. In other embodiments, the depth of the etched trench 130 can be shallower than the depth of the source / drain 151 region, allowing the channel 131 to maintain minimum channel properties and withstand a specific high voltage. In other words, the thickness of the channel 131 depends on the required voltage resistance. In theory, the thickness of the channel 131 is proportional to the high-voltage resistance. In other embodiments, the depth of the etched trench 130 can be the same as the depth of the isolation feature 160, achieving even better high-voltage resistance.
[0030] In step S14, a material layer 140 is deposited on the patterned mask 120 and in the trench 130 to form a channel 131 in the trench 130, wherein the material layer 140 is a wide bandgap semiconductor material, such as Figure 4As shown. A material layer 140 is deposited in the trench 130 to form a channel 131. Since the material layer 140 is a wide-gap semiconductor material with wide-gap characteristics, it has a higher breakdown electric field and lower leakage current. In addition, because wide-gap materials have better thermal conductivity than silicon materials, they are very suitable for environments that require high-temperature operation, such as automotive transistors. In some embodiments, the wide-gap semiconductor material includes various third-generation semiconductors (such as gallium nitride (GaN) and silicon carbide (SiC)), two-dimensional electron channel materials (such as graphene and molybdenum disulfide (MoS2)), and oxide semiconductor materials (such as gallium oxide (Ga2O3), diamond, aluminum nitride (AlN), boron nitride (BN)), or combinations thereof. Therefore, the channel 131 is a channel 131 with wide-gap characteristics. In some embodiments, the step of depositing the material layer 140 on the patterned mask 120 and in the trench 130 includes conformally depositing the material layer 140. In some embodiments, an annealing step is optionally performed after step S14.
[0031] In step S15, the patterned mask 120 and the material layer 140 on the patterned mask 120 are removed. Figure 5 As shown, chemical mechanical polishing (CMP) is performed to remove excess material layer 140 on patterned mask 120 and planarize the top surface 132 of channel 131. This also removes patterned mask 120 and planarizes the top surface 111 of substrate 110. In some embodiments, the top surface 132 of planarized channel 131 is coplanar with the top surface 111 of substrate 110. In some embodiments, the wide-gap semiconductor material formed in channel 131 is fabricated prior to the CMOS process. This eliminates the need for a high-temperature annealing process during subsequent CMOS processing, potentially damaging the transistor and preventing heat buildup during wide-gap channel processing.
[0032] In step S16, a plurality of transistors and a plurality of isolation features are formed in the substrate and the channel, such as Figure 6 As shown. After the above steps complete the formation of a wide bandgap channel 131 on the substrate 110, the following steps can be completed using CMOS-compatible processes: such as photolithography, silicon etching, channel filling, and CMP steps. In some embodiments, the substrate 110 and the channel 131 may also include various p-type doped regions and / or n-type doped regions, implemented through processes such as ion implantation and / or diffusion. These doped regions include n-wells, p-wells, and various channel doping profiles, which are configured to form various integrated circuit devices, such as CMOS transistors. The transistor 150 includes a source / drain 151 and a gate 152.
[0033] In some embodiments, the source / drain 151 is formed below the top surface 111 of the substrate 110 by processes such as photolithography, silicon etching, channel filling, and CMP, while the gate 152 is formed above the top surface 111 of the substrate 110. In some embodiments, a dielectric layer is formed between the gate 152 and the top surface 111, and the material is an oxide such as silicon oxide.
[0034] In other embodiments, the source / drain 151 is formed below the top surface 132 of the channel 131 by processes such as photolithography, silicon etching, channel filling, and CMP, while the gate 152 is formed above the top surface 132 of the channel 131. In some embodiments, a dielectric layer is provided between the gate 152 and the top surface 132, and the material is an oxide such as silicon oxide.
[0035] In some embodiments, substrate 110 and channel 131 may also include various isolation features 160. Isolation features 160 separate various device regions in substrate 110 and channel 131. In some embodiments, isolation features 160 are formed below the top surface 111 of substrate 110 and below the top surface 132 of channel 131. In some embodiments, isolation features 160 may include shallow trench isolation (STI) features. Formation of shallow trench isolation may include etching shallow trenches in substrate 110 and channel 131 and filling the shallow trenches with an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. Chemical mechanical polishing (CMP) may be performed to polish away excess insulating material and planarize the top surface of the isolation features.
[0036] Figure 6 A schematic cross-sectional view of a semiconductor device 100 according to one embodiment of the present disclosure is shown. Semiconductor device 100 includes a substrate 110, a channel 131, at least one first transistor 150A, at least one second transistor 150B, and at least one first isolation feature 160A. Channel 131 is formed in substrate 110, wherein channel 131 comprises a wide-bandgap semiconductor material. In some embodiments, a top surface 132 of channel 131 is coplanar with top surface 111 of substrate 110.
[0037] The transistors 150 located at different locations are distinguished. The transistor located in the channel 131 is defined as a first transistor 150A, and the transistor located in the substrate 110 is defined as a second transistor 150B. At least one first transistor 150A is formed in the channel 131 and includes a pair of first source / drain features 151A and a first gate 152A. The first source / drain features 151A are disposed below the top surface 132 of the channel 131, and the first gate 152A is disposed above the top surface 132 of the channel 131. At least one second transistor 150B is formed in the substrate 110 and includes a pair of second source / drain features 151B and a second gate 152B. The second source / drain features 151B are disposed below the top surface 111 of the substrate 110, and the second gate 152B is disposed above the top surface 111 of the substrate 110.
[0038] Isolation features 160 located at different locations are distinguished: the isolation feature 160 disposed between the first transistor 150A and the second transistor 150B is defined as a first isolation feature 160A; the isolation feature 160 disposed in the substrate 110 is defined as a second isolation feature 160B; and the isolation feature 160 disposed in the channel 131 is defined as a third isolation feature 160C. In some embodiments, a top surface 161A of the first isolation feature 160A is coplanar with the top surface 132 of the channel 131 and the top surface 111 of the substrate 110. In some embodiments, the first isolation feature 160A is disposed at the interface between the substrate 110 and the channel 131, that is, a portion of the first isolation feature 160A is disposed in the substrate 110 and another portion of the first isolation feature 160A is disposed in the channel 131, to prevent current leakage between the adjacent first transistor 150A and the second transistor 150B.
[0039] This disclosure proposes a wide-bandgap channel structure that enables high-voltage bias operation. Using additional masking, etching, and removal, a heterogeneous wide-bandgap channel is selectively deposited on a substrate. This method requires no additional layout footprint, no surface topography changes, and no specialized structures, and is fully compatible with advanced CMOS manufacturing.
[0040] Although the present disclosure has been disclosed above in the form of embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.
[0041]
Explanation of symbols
[0042] 10: Method
[0043] 100: Semiconductor devices
[0044] 110: Substrate
[0045] 111: Top surface
[0046] 120: Patterned Mask
[0047] 130: Groove
[0048] 131: Channel
[0049] 132: Top surface
[0050] 140: Material layer
[0051] 150: Transistor
[0052] 150A: First transistor
[0053] 150B: Second transistor
[0054] 151: Source / Drain
[0055] 151A: First source / drain characteristics
[0056] 151B: Second source / drain characteristics
[0057] 152: Gate
[0058] 152A: First gate
[0059] 152B: Second gate
[0060] 160: Isolation Features
[0061] 160A: First isolation feature
[0062] 160B: Second isolation feature
[0063] 160C: Third isolation feature
[0064] 161A: Top surface
[0065] S11~S16: steps.
Claims
1. A method for preparing a semiconductor device, characterized in that: Include: providing a substrate; forming a patterned mask on the substrate; etching the substrate using the patterned mask to form trenches; Depositing a material layer on the patterned mask and in the trench to form a channel in the trench, wherein the material layer is a wide-bandgap semiconductor material; removing the patterned mask and the material layer on the patterned mask; as well as A plurality of transistors and a plurality of isolation features are formed in the substrate and the channel. The method according to claim 1 , wherein the substrate is a silicon substrate. 3 . The method according to claim 1 , wherein the step of depositing the material layer on the patterned mask and in the trench comprises conformally depositing the material layer. 4 . The method according to claim 1 , wherein the wide-gap semiconductor material comprises a third-generation semiconductor material, a two-dimensional channel electron material, an oxide semiconductor material, or a combination thereof. 5 . The method according to claim 1 , wherein the step of removing the material layer on the patterned mask comprises removing and planarizing the material layer on the patterned mask to form a top surface on the channel.
6. A semiconductor device, characterized in that: Include: substrate; A channel is formed in the substrate, wherein the channel comprises a wide-gap semiconductor material; At least one first transistor is formed in the channel; At least one second transistor is formed in the substrate; and At least one first isolation feature is disposed between the at least one first transistor and the at least one second transistor. The semiconductor device of claim 6 , wherein a top surface of the channel is coplanar with a top surface of the substrate.
8. The semiconductor device according to claim 6, wherein the at least one first transistor comprises: a pair of first source / drain features disposed below a top surface of the channel; and The first gate is disposed above the top surface of the channel.
9. The semiconductor device according to claim 6, wherein the at least one second transistor comprises: a pair of second source / drain features disposed below the top surface of the substrate; and The second gate is disposed above the top surface of the substrate.
10. The semiconductor device according to claim 6, wherein The system further comprises at least one second isolation feature and at least one third isolation feature. The second isolation feature is disposed in the substrate, and the at least one third isolation feature is disposed in the channel.