Back contact solar cell and preparation method thereof

Abstract

The invention relates to a back contact solar cell and a preparation method thereof. The back contact solar cell comprises: a semiconductor substrate having a light facing surface and a backlight surface, the backlight surface comprising a first region; the first intrinsic amorphous semiconductor layer is arranged on the backlight surface and located in the first area; the first doped microcrystalline state semiconductor layer is arranged on the first intrinsic amorphous state semiconductor layer and located on the side, away from the semiconductor substrate, of the first intrinsic amorphous state semiconductor layer; the second doped microcrystalline state semiconductor layer is arranged on the first doped microcrystalline state semiconductor layer and is positioned on one side, far away from the semiconductor substrate, of the first doped microcrystalline state semiconductor layer; wherein the conduction type of the first doped microcrystalline-state semiconductor layer is the same as that of the second doped microcrystalline-state semiconductor layer, and the doping concentration of the second doped microcrystalline-state semiconductor layer is larger than that of the first doped microcrystalline-state semiconductor layer. The photoelectric conversion efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to solar cell technology, and in particular to a back-contact solar cell and a method for preparing the same. Background Art

[0002] A solar cell is a photoelectric conversion semiconductor device, which is usually a homojunction diode structure formed by a single semiconductor material, or a heterojunction (HJT) diode structure formed by combining two or more semiconductor materials.

[0003] Semiconductor materials absorb sunlight from the environment, generating electrons and holes, commonly referred to as photogenerated carriers. After separation by the diode's built-in electric field, the electrons and holes accumulate in the n-type and p-type semiconductor regions, respectively, forming an electric potential. To effectively transport these electrons and holes to external circuits, metal electrodes are typically formed on the front (first light-receiving) and back (second light-receiving) surfaces. These electrodes form good electrical contact with the semiconductor material, effectively transporting the photogenerated carriers to the external circuit.

[0004] Heterojunction solar cells combine the advantages of both single-crystal silicon and amorphous silicon solar cells, boasting low-temperature fabrication processes, high conversion efficiency, and excellent high-temperature characteristics. Due to their low temperature coefficient and bifacial power generation, heterojunction solar cells have significant market potential and have become a key area of ​​research and breakthrough within the industry.

[0005] In recent years, the photoelectric performance of heterojunction cells has been greatly improved. In order to further improve the efficiency of traditional heterojunction cells, heterojunction cells with a full back electrode structure have emerged. By removing the shielding of sunlight by the grid lines, the absorption efficiency of incident light is increased. Summary of the Invention

[0006] Research has found that the heterojunction cells using a full back electrode structure in related technologies still need to be optimized in terms of photoelectric conversion efficiency and cost.

[0007] In view of this, embodiments of the present disclosure provide a back-contact solar cell and a method for manufacturing the same, which can improve photoelectric conversion efficiency.

[0008] In one aspect of the present disclosure, there is provided a back-contact solar cell comprising:

[0009] A semiconductor substrate having a light-facing surface and a backlight surface, wherein the backlight surface includes a first region;

[0010] A first intrinsic amorphous semiconductor layer is provided on the backlight surface and is located in the first region;

[0011] a first doped microcrystalline semiconductor layer, disposed on the first intrinsic amorphous semiconductor layer and located on a side of the first intrinsic amorphous semiconductor layer away from the semiconductor substrate; and

[0012] a second doped microcrystalline semiconductor layer, disposed on the first doped microcrystalline semiconductor layer and located on a side of the first doped microcrystalline semiconductor layer away from the semiconductor substrate;

[0013] The conductivity type of the first doped microcrystalline semiconductor layer is the same as the conductivity type of the second doped microcrystalline semiconductor layer, and the doping concentration of the second doped microcrystalline semiconductor layer is greater than the doping concentration of the first doped microcrystalline semiconductor layer.

[0014] In some embodiments, the doping concentration of the first doped microcrystalline semiconductor layer is less than or equal to 1×10 17 atoms / cm 3 The doping concentration of the second doped microcrystalline semiconductor layer is greater than 1×10 17 atoms / cm 3 , and less than or equal to 1×10 20 atoms / cm 3 .

[0015] In some embodiments, the thickness of the first doped microcrystalline semiconductor layer is less than the thickness of the second doped microcrystalline semiconductor layer.

[0016] In some embodiments, the thickness of the first doped microcrystalline semiconductor layer is greater than or equal to 0.5 nm and less than or equal to 10 nm; the thickness of the second doped microcrystalline semiconductor layer is greater than or equal to 10 nm and less than or equal to 50 nm.

[0017] In some embodiments, the backlight surface further includes a second region and a third region, the first region and the second region are arranged at intervals along at least one direction perpendicular to the thickness direction of the semiconductor substrate, and the third region is located between adjacent first and second regions;

[0018] Wherein, the back contact solar cell further comprises:

[0019] A second intrinsic amorphous semiconductor layer is located in the third region, and a portion of the layer is disposed on the backlight surface; and

[0020] a second doped amorphous semiconductor layer, disposed on the second intrinsic amorphous semiconductor layer and located on a side of the second intrinsic amorphous semiconductor layer away from the semiconductor substrate;

[0021] The second doped amorphous semiconductor layer and the second doped microcrystalline semiconductor layer are continuously connected at the boundary between the first region and the third region, and the conductivity type of the second doped amorphous semiconductor layer is the same as the conductivity type of the second doped microcrystalline semiconductor layer.

[0022] In some embodiments, a thickness of the second intrinsic amorphous semiconductor layer is greater than a thickness of the first intrinsic amorphous semiconductor layer.

[0023] In some embodiments, the second intrinsic amorphous semiconductor layer is continuously connected to the first intrinsic amorphous semiconductor layer at a boundary between the first region and the third region.

[0024] In some embodiments, the thickness of the second intrinsic amorphous semiconductor layer is greater than or equal to 7 nm and less than or equal to 20 nm; the thickness of the first intrinsic amorphous semiconductor layer is greater than or equal to 3 nm and less than or equal to 10 nm.

[0025] In some embodiments, the back-contact solar cell further comprises:

[0026] a tunneling passivation layer, disposed on the backlight surface and located in the second region, the tunneling passivation layer also being located in a portion of the third region adjacent to the second region; and

[0027] a doped polycrystalline semiconductor layer, disposed on the tunneling passivation layer and located on a side of the tunneling passivation layer away from the semiconductor substrate;

[0028] The conductivity type of the doped polycrystalline semiconductor layer is opposite to that of the second doped amorphous semiconductor layer, and another portion of the second intrinsic amorphous semiconductor layer is disposed on the doped polycrystalline semiconductor layer.

[0029] In some embodiments, the back-contact solar cell further comprises:

[0030] a conductive thin film layer, disposed on the second doped microcrystalline semiconductor layer, the second doped amorphous semiconductor layer and the doped polycrystalline semiconductor layer;

[0031] In which, the conductive film layer is continuously arranged at the junction of the first area and the third area, and the conductive film layer is continuously arranged at the junction of the second area and the third area. The conductive film layer is provided with an isolation groove penetrating along the thickness direction at least in the third area, and the isolation groove is used to insulate and isolate the parts of the conductive film layer corresponding to the first area and the second area respectively.

[0032] In some embodiments, the back-contact solar cell further comprises:

[0033] a first electrode, located on a side of the second doped microcrystalline semiconductor layer away from the semiconductor substrate; and

[0034] a second electrode, located on a side of the doped polycrystalline semiconductor layer away from the semiconductor substrate;

[0035] The first electrode and the second electrode correspond to the first region and the second region respectively, and are used to derive carriers of different conductive types respectively.

[0036] In some embodiments, the back-contact solar cell further comprises:

[0037] A passivation layer is provided on the light-facing surface; and

[0038] The anti-reflection layer is disposed on the passivation layer and is located on a side of the passivation layer away from the semiconductor substrate.

[0039] In one aspect of the present disclosure, a method for preparing the aforementioned back-contact solar cell is provided, comprising:

[0040] Providing a semiconductor substrate, wherein the semiconductor substrate has a light-facing surface and a backlight surface, and the backlight surface includes a first region;

[0041] A stacked structure is formed in the first area of ​​the backlight surface, in which a first intrinsic amorphous semiconductor layer, a first doped microcrystalline semiconductor layer, and a second doped microcrystalline semiconductor layer are stacked in sequence, wherein the conductivity type of the first doped microcrystalline semiconductor layer and the conductivity type of the second doped microcrystalline semiconductor layer are the same, and the doping concentration of the second doped microcrystalline semiconductor layer is greater than the doping concentration of the first doped microcrystalline semiconductor layer.

[0042] In some embodiments, the step of forming a stacked structure in which a first intrinsic amorphous semiconductor layer, a first doped microcrystalline semiconductor layer, and a second doped microcrystalline semiconductor layer are stacked in sequence in the first region of the backlight surface comprises:

[0043] forming an initial intrinsic amorphous semiconductor layer in the first region;

[0044] forming a first doped amorphous semiconductor layer on the initial intrinsic amorphous semiconductor layer;

[0045] performing laser modification treatment on the first doped amorphous semiconductor layer;

[0046] In which, during the laser modification process of the first doped amorphous semiconductor layer, the first doped amorphous semiconductor layer is converted into the second doped microcrystalline semiconductor layer by laser, and a partial thickness of the initial intrinsic amorphous semiconductor layer is crystallized, and the doping elements in the first doped amorphous semiconductor layer diffuse into the crystallized part of the initial intrinsic amorphous semiconductor layer, so that the crystallized part of the initial intrinsic amorphous semiconductor layer is converted into the first doped microcrystalline semiconductor layer; the part of the initial intrinsic amorphous semiconductor layer located on the side of the first doped microcrystalline semiconductor layer adjacent to the semiconductor substrate is defined as the first intrinsic amorphous semiconductor layer.

[0047] In some embodiments, the backlight surface further includes a second region and a third region, the first region and the second region are arranged at intervals along at least one direction perpendicular to the thickness direction of the semiconductor substrate, and the third region is located between adjacent first and second regions;

[0048] Before the step of performing laser modification treatment on the first doped amorphous semiconductor layer, the preparation method further comprises:

[0049] forming a second intrinsic amorphous semiconductor layer on a portion of the third region of the backlight surface;

[0050] forming a second doped amorphous semiconductor layer on the second intrinsic amorphous semiconductor layer, wherein the conductivity type of the second intrinsic amorphous semiconductor layer is the same as the conductivity type of the second doped microcrystalline semiconductor layer;

[0051] The initial intrinsic amorphous semiconductor layer and the second intrinsic amorphous semiconductor layer are obtained through an integrated formation process.

[0052] In some embodiments, the first doped amorphous semiconductor layer and the second doped amorphous semiconductor layer are obtained by an integrated formation process.

[0053] In some embodiments, before forming the second intrinsic amorphous semiconductor layer, the preparation method further includes:

[0054] forming a tunnel passivation layer on the second region and a portion of the third region adjacent to the second region;

[0055] forming a doped polycrystalline semiconductor layer on the tunnel passivation layer, wherein the conductivity type of the doped polycrystalline semiconductor layer is opposite to the conductivity type of the second doped amorphous semiconductor layer;

[0056] Another portion of the second intrinsic amorphous semiconductor layer is formed on the doped polycrystalline semiconductor layer.

[0057] In some embodiments, the preparation method further comprises:

[0058] forming a conductive thin film layer integrally on the second doped microcrystalline semiconductor layer, the second doped amorphous semiconductor layer and the doped polycrystalline semiconductor layer;

[0059] An isolation groove is provided in the portion of the conductive film layer corresponding to at least the third region and passes through the portion along the thickness direction, so as to insulate and isolate the portions of the conductive film layer corresponding to the first region and the second region respectively.

[0060] In some embodiments, the preparation method further comprises:

[0061] forming a first electrode on a side of the second doped microcrystalline semiconductor layer away from the semiconductor substrate;

[0062] forming a second electrode on a side of the doped polycrystalline semiconductor layer away from the semiconductor substrate;

[0063] The first electrode and the second electrode correspond to the first region and the second region respectively, and are used to derive carriers of different conductive types respectively.

[0064] In some embodiments, the preparation method further comprises:

[0065] forming a passivation layer on the light-facing surface;

[0066] An anti-reflection layer is formed on the passivation layer.

[0067] According to an embodiment of the present disclosure, a stacked structure in which a first intrinsic amorphous semiconductor layer, a first doped microcrystalline semiconductor layer, and a second doped microcrystalline semiconductor layer are stacked in sequence is set in the first area of ​​the backlight surface of the semiconductor substrate. In this stacked structure, the conductivity type of the first doped microcrystalline semiconductor layer and the conductivity type of the second doped microcrystalline semiconductor layer are the same, and the doping concentration of the second doped microcrystalline semiconductor layer is greater than the doping concentration of the first doped microcrystalline semiconductor layer. In this way, there is a transition in which the doping concentration of the first intrinsic amorphous semiconductor layer decreases from the second doped microcrystalline semiconductor layer to the first intrinsic amorphous semiconductor layer in the stacked structure in the first area.

[0068] Compared with the doped amorphous semiconductor layer, the microcrystalline semiconductor material contained in the first doped microcrystalline semiconductor layer and the second doped microcrystalline semiconductor layer allows a higher doping concentration and can achieve lower parasitic absorption, which is beneficial to improving lateral conductivity and fill factor, improving short-circuit current and battery conversion efficiency. For the stacked structure with a transition of reduced doping concentration, the first doped microcrystalline semiconductor layer with a lower doping concentration can weaken the damage of the second doped microcrystalline semiconductor layer with a higher doping concentration to the passivation performance of the first intrinsic amorphous semiconductor layer, improve the passivation performance, inhibit the recombination of carriers at the interface between the first doped microcrystalline semiconductor layer and the first intrinsic amorphous semiconductor layer, reduce recombination losses, and is beneficial to improving the open circuit voltage and fill factor, thereby improving the photoelectric conversion efficiency of the solar cell as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0070] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0071] Figure 1 is a schematic diagram of the layer structure of some embodiments of the back-contact solar cell according to the present disclosure;

[0072] Figure 2 yes Figure 1 An enlarged schematic diagram of the position corresponding to the middle ellipse D;

[0073] Figure 3 is a schematic flow chart of some embodiments of a method for preparing a back-contact solar cell according to the present disclosure;

[0074] Figure 4-13 Schematic diagrams of multiple processing steps of an embodiment of the method for preparing a back-contact solar cell disclosed in the present invention.

[0075] It should be understood that the size of each part shown in the drawings is not drawn according to the actual proportional relationship.In addition, the same or similar reference numerals represent the same or similar components.

[0076] Description of reference numerals:

[0077] 10. semiconductor substrate; 11. light-facing surface; 111. velvet surface; 12. backlight surface;

[0078] A, first area; B, second area; C, third area;

[0079] 20. Initial intrinsic amorphous semiconductor layer; 21. First intrinsic amorphous semiconductor layer; 22. First doped microcrystalline semiconductor layer; 23. Second doped microcrystalline semiconductor layer; 24. First doped amorphous semiconductor layer;

[0080] 31. a second intrinsic amorphous semiconductor layer; 32. a second doped amorphous semiconductor layer;

[0081] 41. Tunneling passivation layer; 42. Doped polycrystalline semiconductor layer; 43. Mask layer;

[0082] 50. conductive film layer; 51. isolation trench;

[0083] 61. First electrode; 62. Second electrode;

[0084] 71. Passivation layer; 72. Anti-reflection layer;

[0085] SL, sunlight; x, arrangement direction; z, thickness direction. DETAILED DESCRIPTION

[0086] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the present disclosure, its application, or use. The present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that unless otherwise specifically stated, the relative arrangement of parts and steps, the composition of materials, numerical expressions, and numerical values ​​set forth in these embodiments should be interpreted as being merely exemplary and not as limiting.

[0087] The terms "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different parts. The terms "include" or "comprises" and similar terms mean that the elements before the term include the elements listed after the term, and do not exclude the possibility of also including other elements. The terms "upper", "lower", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0088] In the present disclosure, when a specific device is described as being located between a first device and a second device, an intervening device may or may not be present between the specific device and the first device or the second device. When a specific device is described as being connected to another device, the specific device may be directly connected to the other device without an intervening device, or may be not directly connected to the other device but with an intervening device.

[0089] All terms (including technical or scientific terms) used in this disclosure have the same meaning as understood by one of ordinary skill in the art to which this disclosure belongs, unless otherwise specifically defined. It should also be understood that terms defined in, for example, commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0090] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0091] In order to further improve the efficiency of traditional heterojunction cells, heterojunction cells with a full back electrode structure have emerged in related technologies. By removing the shielding of sunlight by the grid lines, the absorption efficiency of incident light is increased.

[0092] Research has found that the heterojunction cells using a full back electrode structure in related technologies still need to be optimized in terms of photoelectric conversion efficiency and cost.

[0093] In view of this, embodiments of the present disclosure provide a back-contact solar cell and a method for manufacturing the same, which can improve photoelectric conversion efficiency.

[0094] Figure 1 Schematic diagram of the layer structure of some embodiments of the back-contact solar cell according to the present disclosure. Figure 2 yes Figure 1 An enlarged schematic diagram of the position corresponding to the middle ellipse D.

[0095] refer to Figure 1 and Figure 2 The embodiment of the present disclosure provides a back-contact solar cell, including: a semiconductor substrate 10 , a first intrinsic amorphous semiconductor layer 21 , a first doped microcrystalline semiconductor layer 22 , and a second doped microcrystalline semiconductor layer 23 .

[0096] The semiconductor substrate 10 has a light-facing surface 11 and a backlight surface 12, wherein the backlight surface 12 includes a first area A. Figure 1 As shown, the light-facing surface 11 is located on the side adjacent to the sunlight SL relative to the backlight surface 12. A portion of the backlight surface 12 is marked as a first area A. Figure 1 The backlight surface 12 may include one or more first areas A.

[0097] The disclosed embodiments do not specifically limit the material and conductivity type of semiconductor substrate 10. Alternatively, semiconductor substrate 10 may be a silicon substrate, a germanium substrate, or a gallium arsenide substrate. Alternatively, semiconductor substrate 10 may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0098] The first intrinsic amorphous semiconductor layer 21 is disposed on the backlight surface 12 and located in the first region A. The first intrinsic amorphous semiconductor layer 21 can be an intrinsic amorphous silicon thin film covering the entire surface of the first region A of the backlight surface 12, or other intrinsic amorphous materials such as intrinsic amorphous germanium.

[0099] The first doped microcrystalline semiconductor layer 22 is disposed on the first intrinsic amorphous semiconductor layer 21 and is located on a side of the first intrinsic amorphous semiconductor layer 21 away from the semiconductor substrate 10. The second doped microcrystalline semiconductor layer 23 is disposed on the first doped microcrystalline semiconductor layer 22 and is located on a side of the first doped microcrystalline semiconductor layer 22 away from the semiconductor substrate 10.

[0100] The first doped microcrystalline semiconductor layer 22 and the second doped microcrystalline semiconductor layer 23 both include crystalline particles with a grain size in the micrometer or nanometer range, such as microcrystalline silicon or nanosilicon. Compared to doped amorphous semiconductor materials, the microcrystalline semiconductor materials included in the first doped microcrystalline semiconductor layer 22 and the second doped microcrystalline semiconductor layer 23 allow for a higher doping concentration, thereby increasing lateral conductivity and fill factor, reducing parasitic absorption, and thereby improving short-circuit current and battery conversion efficiency.

[0101] The conductivity type of the first doped microcrystalline semiconductor layer 22 is the same as the conductivity type of the second doped microcrystalline semiconductor layer 23 , and the doping concentration of the second doped microcrystalline semiconductor layer 23 is greater than the doping concentration of the first doped microcrystalline semiconductor layer 22 .

[0102] like Figure 1 As shown, the first intrinsic amorphous semiconductor layer 21, the first doped microcrystalline semiconductor layer 22, and the second doped microcrystalline semiconductor layer 23 may form a stacked structure stacked sequentially in the first region A of the backlight surface 12 of the semiconductor substrate 10. Thus, the stacked structure has a transition where the doping concentration decreases from the second doped microcrystalline semiconductor layer 23 to the first intrinsic amorphous semiconductor layer 21.

[0103] For this type of stacked structure with a transition of decreasing doping concentration, the first doped microcrystalline semiconductor layer 22 with a lower doping concentration can weaken the damage to the passivation performance of the first intrinsic amorphous semiconductor layer 21 caused by the second doped microcrystalline semiconductor layer 23 with a higher doping concentration, thereby improving the passivation performance, inhibiting the recombination of carriers at the interface between the first doped microcrystalline semiconductor layer and the first intrinsic amorphous semiconductor layer, and reducing recombination losses.

[0104] In some embodiments, the doping concentration of the first doped microcrystalline semiconductor layer 22 is less than or equal to 1×10 17 atoms / cm3 The doping concentration of the second doped microcrystalline semiconductor layer 23 is greater than 1×10 17 atoms / cm 3 , and less than or equal to 1×10 20 atoms / cm 3 .

[0105] The doping concentration of the first doped microcrystalline semiconductor layer 22 is less than or equal to 1×10 17 atoms / cm 3 For example, the doping concentration of the first doped microcrystalline semiconductor layer 22 is 1×10 13 atoms / cm 3 , 1×10 14 atoms / cm 3 , 1×10 15 atoms / cm 3 , 1×10 16 atoms / cm 3 , 1×10 17 atoms / cm 3 The first doped microcrystalline semiconductor layer 22 with such a doping concentration is close to the intrinsic semiconductor layer in characteristics, and can realize the transition of doping concentration between the second doped microcrystalline semiconductor layer 23 with a higher doping concentration and the first intrinsic amorphous semiconductor layer 21, thereby improving the passivation performance of the first intrinsic amorphous semiconductor layer 21.

[0106] The doping concentration of the second doped microcrystalline semiconductor layer 23 is greater than 1×10 17 atoms / cm 3 , and less than or equal to 1×10 20 atoms / cm 3 For example, the doping concentration of the second doped microcrystalline semiconductor layer 23 is 1×10 18 atoms / cm 3 , 1×10 19 atoms / cm 3 , 1×10 20 atoms / cm 3 The second doped microcrystalline semiconductor layer 23 with such a doping concentration can reduce the lateral resistance of the film layer, improve the lateral conductivity and fill factor, and also reduce the parasitic absorption of light to improve the short-circuit current effect.

[0107] In some embodiments, the thickness of the first doped microcrystalline semiconductor layer 22 is less than the thickness of the second doped microcrystalline semiconductor layer 23 .

[0108] The thickness of the second doped microcrystalline semiconductor layer 23 is greater than that of the first doped microcrystalline semiconductor layer 22. In this way, the thicker second doped microcrystalline semiconductor layer 23 with a higher doping concentration can be used to achieve the main effect of reducing the lateral resistance of the film layer and improving the lateral conductivity and fill factor. The thinner first doped microcrystalline semiconductor layer 22 with a lower doping concentration can reduce the parasitic absorption of light while achieving the doping concentration transition effect, which is beneficial to improving the short-circuit current.

[0109] In some embodiments, the thickness of the first doped microcrystalline semiconductor layer 22 is greater than or equal to 0.5 nm and less than or equal to 10 nm; the thickness of the second doped microcrystalline semiconductor layer 23 is greater than or equal to 10 nm and less than or equal to 50 nm.

[0110] The thickness of the first doped microcrystalline semiconductor layer 22 is greater than or equal to 0.5 nm and less than or equal to 10 nm. For example, the thickness of the first doped microcrystalline semiconductor layer 22 can be 0.5 nm, 1 nm, 3 nm, 5 nm, 8 nm, 10 nm, etc. The first doped microcrystalline semiconductor layer 22 of this thickness can take into account the balance between short-circuit current and fill factor when achieving the transition of doping concentration between the second doped microcrystalline semiconductor layer 23 with a higher doping concentration and the first intrinsic amorphous semiconductor layer 21.

[0111] The thickness of the second doped microcrystalline semiconductor layer 23 is greater than 10 nm and less than or equal to 50 nm. For example, the thickness of the second doped microcrystalline semiconductor layer 23 can be 11 nm, 15 nm, 18 nm, 22 nm, 25 nm, 30 nm, 36 nm, 42 nm, 50 nm, etc. The second doped microcrystalline semiconductor layer 23 of this thickness can effectively improve the lateral conductivity and is conducive to the improvement of the fill factor.

[0112] refer to Figure 1 and Figure 2 In some embodiments, the backlight surface 12 further includes a second region B and a third region C, the first region A and the second region B are arranged at intervals along at least one direction perpendicular to the thickness direction z of the semiconductor substrate 10, and the third region C is located between the adjacent first region A and the second region B.

[0113] The back-contact solar cell further includes a second intrinsic amorphous semiconductor layer 31 and a second doped amorphous semiconductor layer 32. The second intrinsic amorphous semiconductor layer 31 is located in the third region C, with a portion thereof disposed on the backlight surface 12. The second doped amorphous semiconductor layer 32 is disposed on the second intrinsic amorphous semiconductor layer 31 and on a side of the second intrinsic amorphous semiconductor layer 31 away from the semiconductor substrate 10.

[0114] The second doped amorphous semiconductor layer 32 is continuously connected to the second doped microcrystalline semiconductor layer 23 at the boundary between the first region A and the third region C. The conductivity type of the second doped amorphous semiconductor layer 32 is the same as the conductivity type of the second doped microcrystalline semiconductor layer 23. In an alternative embodiment, the conductivity type of the second doped microcrystalline semiconductor layer 23 and the second doped amorphous semiconductor layer 32 is opposite to the conductivity type of the semiconductor substrate 10.

[0115] Depending on the conductivity type of the doped semiconductor layers disposed in the first region A and the second region B, in some embodiments, the first region A is a P-type region and the second region B is an N-type region. In other embodiments, the first region A is an N-type region and the second region B is a P-type region. The height difference between the second region B and the first region A can range from 0 to 6 microns, for example, 0 micron (i.e., the second region B is at the same height as the first region A), 1 micron, 3 microns, 5 microns, 6 microns, etc. A height transition can be formed in the third region C between the first region A and the second region B.

[0116] The backlight surface 12 may include one or more second regions B. The first regions A and the second regions B are arranged alternately along at least one direction perpendicular to the thickness direction z of the semiconductor substrate 10. For example, a plurality of first regions A and a plurality of second regions B are alternately arranged linearly along an arrangement direction x perpendicular to the thickness direction z of the semiconductor substrate 10, or a plurality of first regions A and a plurality of second regions B are arranged in an array perpendicular to the thickness direction z of the semiconductor substrate 10, and a plurality of first regions A and a plurality of second regions B are alternately arranged linearly in a row direction and alternately arranged linearly in a column direction.

[0117] The backlight surface 12 may include one or more third regions C. The third regions C are located between adjacent first regions A and second regions B along the arrangement direction of the first regions A and second regions B, so as to isolate the first regions A and second regions B from each other.

[0118] A second intrinsic amorphous semiconductor layer 31 is provided in the third region C, and a portion of the second intrinsic amorphous semiconductor layer 31 is formed on the backlight surface 12. The second intrinsic amorphous semiconductor layer 31 and the first intrinsic amorphous semiconductor layer 21 can be formed through independent processes or in an integrated process.

[0119] The conductivity type of the second doped amorphous semiconductor layer 32 is the same as the conductivity type of the second doped microcrystalline semiconductor layer 23. For example, the conductivity types of the second doped amorphous semiconductor layer 32 and the second doped microcrystalline semiconductor layer 23 are both P-type or N-type. The second doped amorphous semiconductor layer 32 disposed in the third region C contains an amorphous semiconductor material, such as amorphous silicon, and therefore has lower conductivity than the second doped microcrystalline semiconductor layer 23, resulting in lower leakage current, which helps improve battery reliability.

[0120] The second doped amorphous semiconductor layer 32 is formed on the first intrinsic amorphous semiconductor layer 21 and is continuously connected to the second doped microcrystalline semiconductor layer 23 at a boundary between the first region A and the third region C.

[0121] Taking the second doped amorphous semiconductor layer 32 as a doped amorphous silicon layer and the second doped microcrystalline semiconductor layer 23 as a doped microcrystalline silicon layer as an example, the two are continuously connected at the boundary between the first region A and the third region C. This structure can be achieved by locally laser-modifying the doped amorphous silicon layer. For example, after the first region A and the third region C form an integral doped amorphous silicon layer, the portion of the doped amorphous silicon layer corresponding to the first region A is locally laser-modified, so that part of the amorphous silicon in this doped amorphous silicon layer is converted into microcrystalline silicon. This results in a doped microcrystalline silicon layer and a doped amorphous silicon layer continuously connected at the boundary between the first region A and the third region C, thereby simplifying the process.

[0122] In some embodiments, the thickness of the second intrinsic amorphous semiconductor layer 31 is greater than the thickness of the first intrinsic amorphous semiconductor layer 21 .

[0123] The thickness of the second intrinsic amorphous semiconductor layer 31 is greater than that of the first intrinsic amorphous semiconductor layer 21. This allows the thicker second intrinsic amorphous semiconductor layer 31 to improve the passivation effect of the third region C, thereby improving the reliability of the battery. Furthermore, amorphous semiconductor materials have higher parasitic absorption than microcrystalline semiconductor materials, but the thinner first intrinsic amorphous semiconductor layer helps the first intrinsic amorphous semiconductor layer 21 increase the short-circuit current, thereby improving the battery's open-circuit voltage, fill factor, and photoelectric conversion efficiency.

[0124] refer to Figure 1 and Figure 2 In some embodiments, the second intrinsic amorphous semiconductor layer 31 is continuously connected to the first intrinsic amorphous semiconductor layer 21 at a boundary between the first region A and the third region C.

[0125] Taking the example of the first intrinsic amorphous semiconductor layer 21 and the second intrinsic amorphous semiconductor layer 31 being both intrinsic amorphous silicon layers, and the two being continuously connected at the boundary between the first region A and the third region C, this structure can be achieved by locally laser-modifying the doped amorphous silicon layer formed on the integral intrinsic amorphous silicon layer. For example, after the integral intrinsic amorphous silicon layer and the doped amorphous silicon layer are sequentially formed in the first region A and the third region C, the portion of the doped amorphous silicon layer corresponding to the first region A is locally laser-modified. Under the action of the laser, the dopant in the doped amorphous silicon layer in the portion of the first region A diffuses into the intrinsic amorphous silicon layer, forming a first doped microcrystalline semiconductor layer and a second doped microcrystalline semiconductor layer with a transition in doping concentration. This correspondingly reduces the thickness of the intrinsic amorphous silicon layer in the first region A. Thus, an intrinsic amorphous silicon layer having different thicknesses and continuously connected at the boundary between the first region A and the third region C is obtained, thereby simplifying the process.

[0126] In some embodiments, the thickness of the second intrinsic amorphous semiconductor layer 31 is greater than or equal to 7 nm and less than or equal to 20 nm; the thickness of the first intrinsic amorphous semiconductor layer 21 is greater than or equal to 3 nm and less than or equal to 10 nm.

[0127] The thickness of the first intrinsic amorphous semiconductor layer 21 is greater than or equal to 3 nm and less than or equal to 10 nm. For example, the thickness can be 3 nm, 5 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc. The first intrinsic amorphous semiconductor layer 21 of such a thickness in the first region A is beneficial for improving the open-circuit voltage, fill factor, and photoelectric conversion efficiency of the battery while also ensuring the passivation effect of the first region A.

[0128] The thickness of the second intrinsic amorphous semiconductor layer 31 is greater than or equal to 7 nm and less than or equal to 20 nm. For example, the thickness can be 7 nm, 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, etc. The second intrinsic amorphous semiconductor layer 31 of such thickness can effectively improve the passivation effect of the third region C.

[0129] refer to Figure 1 and Figure 2 In some embodiments, the back-contact solar cell further includes a tunneling passivation layer 41 and a doped polycrystalline semiconductor layer 42. The tunneling passivation layer 41 is disposed on the backlight surface 12 and located in the second region B. The tunneling passivation layer 41 is also located in a portion of the third region C adjacent to the second region B.

[0130] The doped polycrystalline semiconductor layer 42 is disposed on the tunnel passivation layer 41 and is located on a side of the tunnel passivation layer 41 away from the semiconductor substrate 10. The conductivity type of the doped polycrystalline semiconductor layer 42 is opposite to the conductivity type of the second doped amorphous semiconductor layer 32, and another portion of the second intrinsic amorphous semiconductor layer 31 is disposed on the doped polycrystalline semiconductor layer 42. In an alternative embodiment, the conductivity type of the doped polycrystalline semiconductor layer 42 is the same as the conductivity type of the semiconductor substrate 10.

[0131] The tunnel passivation layer 41 can be formed in the second region B and the third region C of the backlight surface 12, adjacent to the second region B. It can be, but is not limited to, silicon oxide with a thickness of 0.5 to 3 nm. The conductivity type of the doped polycrystalline semiconductor layer 42 is opposite to that of the second doped amorphous semiconductor layer 32. For example, the conductivity type of the doped polycrystalline semiconductor layer 42 is N-type, while the conductivity type of the second doped amorphous semiconductor layer 32 is P-type. The doped polycrystalline semiconductor layer 42 can be, but is not limited to, a doped polysilicon layer with a thickness of 20 to 200 nm.

[0132] like Figure 2 As shown, the third region C can be divided into two regions, C1 and C2. In region C2, a tunnel passivation layer 41, a doped polycrystalline semiconductor layer 42, a second intrinsic amorphous semiconductor layer 31, and a second doped amorphous semiconductor layer 32 are sequentially formed from the backlight surface 12. In region C1, a second intrinsic amorphous semiconductor layer 31 and a second doped amorphous semiconductor layer 32 are sequentially formed from the backlight surface 12.

[0133] refer to Figure 1 and Figure 2 In some embodiments, the back-contact solar cell further includes a conductive thin film layer 50 , which is disposed on the second doped microcrystalline semiconductor layer 23 , the second doped amorphous semiconductor layer 32 and the doped polycrystalline semiconductor layer 42 .

[0134] The conductive film layer 50 is provided with an isolation trench 51 penetrating along the thickness direction z at least in the third region C. The isolation trench 51 is used to insulate and isolate the portions of the conductive film layer 50 corresponding to the first region A and the second region B.

[0135] For the isolation trench 51, it can be as follows Figure 2 As shown, a groove is formed at a certain position within the conductive film layer 50 corresponding to the third region C, or a groove can be formed at the edge positions on both sides of the conductive film layer 50 corresponding to the third region C. In addition to forming a groove in the portion of the conductive film layer 50 corresponding to the third region C, a groove can also be formed at a position adjacent to the third region C in the first region A and / or the second region B, thereby forming an isolation groove 51 extending beyond the third region C.

[0136] The isolation trench 51 of the conductive film layer 50 removes the conductive film material, forming an opening structure that penetrates along the thickness direction z. In this way, the portions of the conductive film layer 50 corresponding to the first region A and the second region B can be insulated and isolated by the isolation trench 51. The width of the isolation trench 51 is 5-250 microns, for example, 5 microns, 20 microns, 50 microns, 100 microns, 140 microns, 180 microns, 210 microns, 250 microns, etc.

[0137] The material of the conductive film layer 50 can be a multilayer material / laminated material / mixture of one or more doped metal oxides / nitrides, the metal oxide can be one of indium oxide, tin oxide, zinc oxide, cadmium oxide, and titanium nitride, the metal nitride can be titanium nitride, and the doping element can be one or more of indium, tin, calcium, aluminum, cadmium, zinc, cerium and fluorine.

[0138] In some embodiments, the conductive film layer 50 is continuously disposed at the boundary between the first region A and the third region C, and the conductive film layer 50 is continuously disposed at the boundary between the second region B and the third region C. This allows the conductive film layer 50 to completely cover the first region A and the second region B, thereby fully conducting carriers from the first region A and the second region B. In other embodiments, the isolation trench 51 may extend to the edge of the first region A near the third region C, and to the edge of the second region B near the third region B. This can reduce the process precision requirements for forming the isolation trench 51.

[0139] In addition to providing the isolation trench 51 on the conductive film layer 50 , an isolation structure may also be provided on other layers of the conductive film layer 50 adjacent to the semiconductor substrate 10 .

[0140] like Figure 2 As shown, in region C1, the conductive film layer 50 is located on the surface of the second doped amorphous semiconductor layer 32 away from the semiconductor substrate 10. In other embodiments, the conductive film layer 50 may not be disposed on the surface of the second doped amorphous semiconductor layer 32 away from the semiconductor substrate 10 in region C1.

[0141] refer to Figure 1 In some embodiments, the back-contact solar cell further includes a first electrode 61 and a second electrode 62. The first electrode 61 is located on a side of the second doped microcrystalline semiconductor layer 23 away from the semiconductor substrate 10. The second electrode 62 is located on a side of the doped polycrystalline semiconductor layer 42 away from the semiconductor substrate 10. The first electrode 61 and the second electrode 62 correspond to the first region A and the second region B, respectively, and are used to conduct carriers of different conductivity types.

[0142] like Figure 1 As shown, the first electrode 61 may be disposed on a portion of the conductive film layer 50 corresponding to the first region A, and the second electrode 62 may be disposed on a portion of the conductive film layer 50 corresponding to the second region B.

[0143] The first electrode 61 and the second electrode 62 may be, but are not limited to, a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, and a nickel / copper / silver multilayer electrode, or a stack of several of them.

[0144] refer to Figure 1 and Figure 2 In some embodiments, the back-contact solar cell further includes a passivation layer 71 and an anti-reflection layer 72. The passivation layer 71 is disposed on the light-facing surface 11, and the anti-reflection layer 72 is disposed on the passivation layer 71 and located on a side of the passivation layer 71 away from the semiconductor substrate 10.

[0145] The passivation layer 71 may be, but is not limited to, at least one of an intrinsic silicon-containing film and a doped silicon-containing film of the same conductivity type as the semiconductor substrate 10. The intrinsic silicon-containing film may be a stacked structure of one or more thin film layers such as microcrystalline silicon, amorphous silicon, silicon oxide or silicon carbide, and the thickness may be 1 to 15 nm. For an N-type semiconductor substrate 10, the doped silicon-containing film is N-type; for a P-type semiconductor substrate 10, the doped silicon-containing film is N-type. The doped silicon-containing film may be a stacked structure of one or more thin film layers such as microcrystalline silicon, amorphous silicon, silicon oxide or silicon carbide, and the thickness is not more than 30 nm. The passivation layer 71 may also be made of silicon oxide SiO X , alumina AlO X , gallium oxide GaO X , titanium oxide TiO X A single layer film or a stacked layer film of several kinds, the thickness of which is 1~15nm.

[0146] The anti-reflection layer 72 may be made of, but not limited to, silicon nitride SiN X , silicon oxynitride SiN X O 1-X , silicon oxide SiO X 、Magnesium fluoride MgF X , lithium fluoride LiF, a single layer film or a stacked layer film of several kinds, with a thickness of 1~300nm.

[0147] Figure 3 Schematic diagram of some embodiments of the method for preparing a back-contact solar cell according to the present disclosure. Figure 3 In addition to the back-contact solar cells of the aforementioned embodiments, the present disclosure also provides a method for preparing the aforementioned back-contact solar cells. The method includes: step S1 and step S2.

[0148] In step S1 , a semiconductor substrate 10 is provided, wherein the semiconductor substrate 10 has a light-facing surface 11 and a light-back surface 12 , and the light-back surface 12 includes a first area A.

[0149] In step S2, a stacked structure is formed in the first area A of the backlight surface 12, in which a first intrinsic amorphous semiconductor layer 21, a first doped microcrystalline semiconductor layer 22, and a second doped microcrystalline semiconductor layer 23 are stacked in sequence, wherein the conductivity type of the first doped microcrystalline semiconductor layer 22 and the conductivity type of the second doped microcrystalline semiconductor layer 23 are the same, and the doping concentration of the second doped microcrystalline semiconductor layer 23 is greater than the doping concentration of the first doped microcrystalline semiconductor layer 22.

[0150] The first doped microcrystalline semiconductor layer 22 and the second doped microcrystalline semiconductor layer 23 both include crystalline particles with a grain size in the micrometer or nanometer range, such as microcrystalline silicon or nanosilicon. The microcrystalline semiconductor material contained in the first doped microcrystalline semiconductor layer 22 and the second doped microcrystalline semiconductor layer 23 allows for a higher doping concentration than that of a doped amorphous semiconductor layer, thereby increasing lateral conductivity and fill factor, reducing parasitic absorption, and thereby improving short-circuit current and battery conversion efficiency.

[0151] The conductivity type of the first doped microcrystalline semiconductor layer 22 is the same as the conductivity type of the second doped microcrystalline semiconductor layer 23 , and the doping concentration of the second doped microcrystalline semiconductor layer 23 is greater than the doping concentration of the first doped microcrystalline semiconductor layer 22 .

[0152] For this type of stacked structure with a transition of decreasing doping concentration, the first doped microcrystalline semiconductor layer 22 with a lower doping concentration can weaken the damage to the passivation performance of the first intrinsic amorphous semiconductor layer 21 caused by the second doped microcrystalline semiconductor layer 23 with a higher doping concentration, thereby improving the passivation performance, inhibiting the recombination of carriers at the interface between the first doped microcrystalline semiconductor layer and the first intrinsic amorphous semiconductor layer, and reducing recombination losses.

[0153] The stacked structure in which the first intrinsic amorphous semiconductor layer 21, the first doped microcrystalline semiconductor layer 22, and the second doped microcrystalline semiconductor layer 23 are stacked in sequence can be achieved using various known processes. For example, the first doped microcrystalline semiconductor layer 22 and the second doped microcrystalline semiconductor layer 23 can be sequentially formed on the first intrinsic amorphous semiconductor layer 21 using a microcrystallization device in conjunction with a mask. In addition, other preparation processes can also be used to achieve the above-mentioned stacked structure.

[0154] Figure 4-13 Schematic diagrams of multiple processing steps of an embodiment of the method for preparing a back-contact solar cell disclosed in the present invention. Figure 4-13In some embodiments, the step of forming a stacked structure in which a first intrinsic amorphous semiconductor layer 21, a first doped microcrystalline semiconductor layer 22, and a second doped microcrystalline semiconductor layer 23 are stacked in sequence in the first area A of the backlight surface 12 in step S2 includes: forming an initial intrinsic amorphous semiconductor layer 20 in the first area A; forming a first doped amorphous semiconductor layer 24 on the initial intrinsic amorphous semiconductor layer 20; and performing laser modification treatment on the first doped amorphous semiconductor layer 24.

[0155] During the laser modification process of the first doped amorphous semiconductor layer 24, the laser is used to transform the first doped amorphous semiconductor layer 24 into the second doped microcrystalline semiconductor layer 23, and a portion of the thickness of the initial intrinsic amorphous semiconductor layer 20 is crystallized. The doping elements in the first doped amorphous semiconductor layer 24 diffuse into the crystallized portion of the initial intrinsic amorphous semiconductor layer 20, thereby transforming the crystallized portion of the initial intrinsic amorphous semiconductor layer 20 into the first doped microcrystalline semiconductor layer 22. The portion of the initial intrinsic amorphous semiconductor layer 20 located on the side of the first doped microcrystalline semiconductor layer 22 adjacent to the semiconductor substrate 10 is defined as the first intrinsic amorphous semiconductor layer 21.

[0156] Specifically, the initial intrinsic amorphous semiconductor layer 20 and the first doped amorphous semiconductor layer 24 may be sequentially deposited using a process such as plate-type plasma enhanced chemical vapor deposition (PECVD). For example, the initial intrinsic amorphous semiconductor layer 20 may be formed using a PECVD process, and the first doped amorphous semiconductor layer 24 may be formed using a PECVD process containing a doping source.

[0157] Taking the sequential formation of an intrinsic amorphous silicon layer and a doped amorphous silicon layer in the first region A as an example, the doped amorphous silicon layer is subjected to laser modification. For example, the doped amorphous silicon layer is laser modified using an ultraviolet laser with a power of less than 100W. Under the action of the laser, the doped amorphous silicon layer crystallizes, forming microcrystalline particles within the thin film, thereby converting it into a doped microcrystalline silicon layer with a higher doping concentration. At the same time, the laser also acts on the intrinsic amorphous silicon layer adjacent to the doped amorphous silicon layer, causing a portion of the intrinsic amorphous silicon layer to also crystallize. Furthermore, the doping elements in the doped amorphous silicon layer are able to diffuse toward one side of the intrinsic amorphous silicon layer and enter the crystallized portion of the intrinsic amorphous silicon layer, thereby obtaining a doped microcrystalline silicon layer with a lower doping concentration.

[0158] Compared to other fabrication processes, such as direct plate-type PECVD growth of microcrystalline films, the laser modification process employed in this embodiment requires relatively low-cost laser equipment, significantly reducing the cost of solar cell fabrication, thereby facilitating large-scale production. Furthermore, the fabrication of each layer in the aforementioned stacked structure fully utilizes the laser's effects on the crystallization of semiconductor materials and the diffusion of dopant elements, simplifying the fabrication process and making solar cell fabrication more economical and convenient.

[0159] refer to Figure 1 In some embodiments, the backlight surface 12 further includes a second region B and a third region C, the first region A and the second region B are arranged at intervals along at least one direction perpendicular to the thickness direction z of the semiconductor substrate 10, and the third region C is located between the adjacent first region A and the second region B.

[0160] Before the step of performing laser modification treatment on the first doped amorphous semiconductor layer 24, the preparation method further includes: forming a second intrinsic amorphous semiconductor layer 31 in a portion of the third region C of the backlight surface 12; forming a second doped amorphous semiconductor layer 32 on the second intrinsic amorphous semiconductor layer 31, wherein the conductivity type of the second intrinsic amorphous semiconductor layer 31 is the same as the conductivity type of the second doped microcrystalline semiconductor layer 23; wherein the initial intrinsic amorphous semiconductor layer 20 and the second intrinsic amorphous semiconductor layer 31 are obtained through an integrated formation process.

[0161] In some embodiments of the aforementioned back-contact solar cell, it is mentioned that the second intrinsic amorphous semiconductor layer 31 and the first intrinsic amorphous semiconductor layer 21 disposed in the third region C can be formed using an integrated process.

[0162] In this embodiment, the initial intrinsic amorphous semiconductor layer 20 can be formed in the first region A and a portion of the third region C of the backlight surface 12 by an integrated formation process, such as a chemical vapor deposition process, wherein the portion of the initial intrinsic amorphous semiconductor layer 20 located in the third region C is the second intrinsic amorphous semiconductor layer 31. This helps to simplify the preparation process.

[0163] In some embodiments, the first doped amorphous semiconductor layer 24 and the second doped amorphous semiconductor layer 32 are obtained by an integrated formation process.

[0164] In this embodiment, the first doped amorphous semiconductor layer 24 can be formed on a portion of the initial intrinsic amorphous semiconductor layer 20 corresponding to the first region A and the third region C through an integrated formation process, such as a chemical vapor deposition process, wherein the portion of the first doped amorphous semiconductor layer 24 corresponding to the third region C is the second doped amorphous semiconductor layer 32. This helps to simplify the preparation process.

[0165] When the first doped amorphous semiconductor layer 24 is subjected to local laser modification treatment, the laser acts on the portion of the first doped amorphous semiconductor layer 24 corresponding to the first region A, but does not act on the portion of the first doped amorphous semiconductor layer 24 corresponding to the third region C. In this way, the portion of the first doped amorphous semiconductor layer 24 corresponding to the third region C has not undergone laser modification treatment, and therefore has not been crystallized under the action of the laser, thereby reducing the leakage current of the third region C, which is beneficial to improving the reliability of the solar cell.

[0166] In some embodiments, before the step of forming the second intrinsic amorphous semiconductor layer 31, the preparation method further includes: forming a tunneling passivation layer 41 on the second region B and the portion of the third region C adjacent to the second region B; forming a doped polycrystalline semiconductor layer 42 on the tunneling passivation layer 41, wherein the conductivity type of the doped polycrystalline semiconductor layer 42 is opposite to the conductivity type of the second doped amorphous semiconductor layer 32; wherein another portion of the second intrinsic amorphous semiconductor layer 31 is formed on the doped polycrystalline semiconductor layer 42.

[0167] Specifically, the tunnel passivation layer 41 and the doped polycrystalline semiconductor layer 42 may be grown in sequence by low pressure chemical vapor deposition (LPCVD) or PECVD.

[0168] When forming the tunneling passivation layer 41, the tunneling passivation layer 41 can be formed on the entire backlight surface. Then, the doped polycrystalline semiconductor layer 42 is formed on the entire tunneling passivation layer 41. Then, by removing the material of the tunneling passivation layer 41 and the doped polycrystalline semiconductor layer 42 corresponding to the first region A and the third region C adjacent to the first region A, the material of the tunneling passivation layer 41 and the doped polycrystalline semiconductor layer 42 corresponding to the second region B and the third region C adjacent to the second region B remains.

[0169] After retaining the materials of the tunnel passivation layer 41 and the doped polycrystalline semiconductor layer 42 corresponding to the second region B and the portion of the third region C adjacent to the second region B, an initial intrinsic amorphous semiconductor layer 20 that covers the first region A, the second region B and the third region C as a whole can be obtained through an integrated formation process, and then a first doped amorphous semiconductor layer 24 that covers the first region A, the second region B and the third region C as a whole can be formed on the initial intrinsic amorphous semiconductor layer 20 through an integrated formation process.

[0170] On this basis, the material of the initial intrinsic amorphous semiconductor layer 20 and the portion of the first doped amorphous semiconductor layer 24 corresponding to the second region B can be further removed. This step can be performed before or after the step of performing the laser modification treatment on the first doped amorphous semiconductor layer 24.

[0171] In some embodiments, the preparation method also includes: forming a conductive film layer 50 as a whole on the second doped microcrystalline semiconductor layer 23, the second doped amorphous semiconductor layer 32 and the doped polycrystalline semiconductor layer 42; opening an isolation groove 51 penetrating along the thickness direction z in the portion of the conductive film layer 50 corresponding to the third region C, so as to insulate and isolate the portions of the conductive film layer 50 corresponding to the first region A and the second region B respectively.

[0172] When forming the conductive thin film layer, the conductive thin film layer can be deposited by magnetron sputtering (Physical Vapor Deposition, PVD), reactive plasma deposition (RPD), etc. The isolation trench 51 can be formed by etching using laser etching, printing mask + chemical etching, or printing etching slurry.

[0173] When opening the isolation trench 51, portions of other layers of the conductive film layer 50 adjacent to the semiconductor substrate 10 in the third region C may also be removed. For example, an isolation structure that at least penetrates the conductive film layer 50 may be opened in the third region C between the conductive film layer 50 and the second doped amorphous semiconductor layer 32.

[0174] In some embodiments, the preparation method also includes: forming a first electrode 61 on the side of the second doped microcrystalline semiconductor layer 23 away from the semiconductor substrate 10; forming a second electrode 62 on the side of the doped polycrystalline semiconductor layer 42 away from the semiconductor substrate 10; wherein the first electrode 61 and the second electrode 62 correspond to the first region A and the second region B, respectively, and are respectively used to derive carriers of different conductive types.

[0175] The first electrode 61 can be formed on the portion of the conductive film layer 50 corresponding to the first region A, and the second electrode 62 can be formed on the portion of the conductive film layer 50 corresponding to the second region B. The first electrode 61 and the second electrode 62 can be formed by printing, transfer, evaporation, PVD, electroplating, or a combination thereof.

[0176] In some embodiments, the preparation method further includes: forming a passivation layer 71 on the light-facing surface 11 ; and forming an anti-reflection layer 72 on the passivation layer 71 .

[0177] The light-facing surface 11 can be polished and / or textured as needed, and the passivation layer 71 can be formed on the textured surface 111 of the light-facing surface 11. The passivation layer 71 can be formed using plate-type PECVD or atomic layer deposition (ALD). The anti-reflection layer 72 can be formed using plate-type or tube-type PECVD.

[0178] The step of forming the initial intrinsic amorphous semiconductor layer 20 in the first region A precedes the step of forming the first doped amorphous semiconductor layer 24 on the initial intrinsic amorphous semiconductor layer 20. The step of forming the passivation layer 71 on the light-facing surface 11 precedes the step of forming the anti-reflection layer 72 on the passivation layer 71. The order of forming the passivation layer 71 and the initial intrinsic amorphous semiconductor layer 20 is adjustable; the passivation layer 71 can be formed first, or the initial intrinsic amorphous semiconductor layer 20 can be formed first.

[0179] In the conventional back-contact solar cell fabrication process, the intrinsic amorphous semiconductor layer located in the third region C is typically formed integrally with the intrinsic amorphous semiconductor layer located in the first region A. The intrinsic amorphous semiconductor layer located in the first region A is typically thinner to ensure smooth carrier transmission. This results in the intrinsic amorphous semiconductor layer corresponding to the third region C in conventional back-contact solar cells also being thinner, which in turn does not provide a good isolation effect. In contrast, in the disclosed embodiment, an initial intrinsic amorphous semiconductor layer 20 is first formed. A portion of the initial intrinsic amorphous semiconductor layer 20 corresponding to the first region A along its thickness is then converted into a first doped microcrystalline semiconductor layer 22, with the remaining portion serving as the first intrinsic amorphous semiconductor layer 21. The initial intrinsic amorphous semiconductor layer 20 corresponding to the third region C is retained at its original thickness as the second intrinsic amorphous semiconductor layer 31. This achieves both a thin intrinsic amorphous semiconductor layer in the first region A to ensure carrier transmission and a thick intrinsic amorphous semiconductor layer in the third region C to ensure good isolation.

[0180] Reference below Figure 4-13A plurality of preparation steps of an example of a method for preparing a back-contact solar cell disclosed in the present invention are described.

[0181] Step a: Reference Figure 4 A semiconductor substrate 10 (e.g., an N-type silicon substrate) is provided. The semiconductor substrate 10 has a light-facing surface 11 and a light-repelling surface 12. The light-repelling surface 12 includes a first region A, a second region B, and a third region C. The first region A and the second region B are alternately arranged along at least one direction perpendicular to and parallel to the thickness direction z of the semiconductor substrate 10, and the third region C is located between adjacent first regions A and second regions B.

[0182] exist Figure 4 In FIG, a set of adjacent first region A, third region C, and second region B is indicated by dot-dash lines. The semiconductor substrate 10 is polished to remove the cut damage layer, thereby forming polished surface structures on the light-facing surface 11 and the backlight surface 12 of the semiconductor substrate 10.

[0183] Step b: Reference Figure 5 A tunneling passivation layer 41 (e.g., a silicon oxide film), a doped polycrystalline semiconductor layer 42 (e.g., an N-type doped polycrystalline silicon film), and a mask layer 43 are sequentially formed on the backlight surface 12 of the semiconductor substrate 10. The tunneling passivation layer 41, the doped polycrystalline semiconductor layer 42 (e.g., an N-type doped polycrystalline silicon layer), and the mask layer 43 can cover all areas of the backlight surface 12.

[0184] The mask layer 43 may be one of silicon nitride, silicon oxide, intrinsic amorphous silicon, or a stacked or mixed thin film. The material of the mask layer 43 may also be silicon oxide containing N-type doping elements (such as phosphosilicate glass (PSG)).

[0185] Step c: Reference Figure 6 , the tunneling passivation layer 41, the doped polycrystalline semiconductor layer 42, and the mask layer 43 corresponding to the first region A and part of the second region C are removed, thereby forming the tunneling passivation layer 41, the doped polycrystalline semiconductor layer 42, and the mask layer 43 remaining on the second region B and the portion of the third region C adjacent to the second region B.

[0186] Step d: Reference Figure 7The light-facing surface 11 of the semiconductor substrate 10 is textured to form a textured surface 111, and the mask layer 43 remaining on the portions of the second region B and the third region C adjacent to the second region B is removed, thereby exposing the doped polycrystalline semiconductor layer 42 remaining on the portions of the second region B and the third region C adjacent to the second region B. Furthermore, the material of the semiconductor substrate 10 corresponding to the thickness of the first region A and a portion of the material of the third region C are removed, thereby forming a predetermined height difference between the first region A and the second region B, and forming a height transition between the first region A and the second region B from the third region C.

[0187] Step e: Reference Figure 8 A passivation layer 71 and an anti-reflection layer 72 having substantially the same morphology as the suede surface 111 are formed on the light-facing surface 11 of the semiconductor substrate 10. Furthermore, an initial intrinsic amorphous semiconductor layer 20 (e.g., an intrinsic silicon-containing thin film) and a first doped amorphous semiconductor layer 24 (e.g., a P-type doped silicon-containing thin film) are sequentially formed on the backlight surface 12 of the semiconductor substrate 10. The initial intrinsic amorphous semiconductor layer 20 and the first doped amorphous semiconductor layer 24 can entirely cover all regions of the backlight surface 12, such that the first region A and a portion of the third region C cover the surface of the backlight surface 12, while another portion of the third region C and the second region B cover the surface of the doped polycrystalline semiconductor layer 42.

[0188] Step f: Reference Figure 9 Laser modification treatment is performed on the portion of the first doped amorphous semiconductor layer 24 corresponding to the first region A, converting the portion of the first doped amorphous semiconductor layer 24 (e.g., a P-type doped amorphous silicon thin film) corresponding to the first region A into a second doped microcrystalline semiconductor layer 23 (e.g., a P-type doped microcrystalline silicon thin film with a higher doping concentration). A portion of the initial intrinsic amorphous semiconductor layer 20 is crystallized, and the dopant elements in the first doped amorphous semiconductor layer 24 diffuse into the crystallized portion of the initial intrinsic amorphous semiconductor layer 20, thereby converting the crystallized portion of the initial intrinsic amorphous semiconductor layer 20 into the first doped microcrystalline semiconductor layer 22 (e.g., a P-type doped microcrystalline silicon thin film with a lower doping concentration). The non-crystallized portion of the initial intrinsic amorphous semiconductor layer 20 on the side away from the semiconductor substrate 10 is the first intrinsic amorphous semiconductor layer 21.

[0189] When the laser modification process is performed on the portion of the first doped amorphous semiconductor layer 24 corresponding to the first region A, the laser does not act on the portions of the first doped amorphous semiconductor layer 24 corresponding to the second region B and the third region C.

[0190] Step g: Reference Figure 10, the material of the first doped amorphous semiconductor layer 24 and the portion of the initial intrinsic amorphous semiconductor layer 20 corresponding to the second region B is removed. Accordingly, the portion of the first doped amorphous semiconductor layer 24 corresponding to the third region C becomes the second doped amorphous semiconductor layer 32, and the portion of the initial intrinsic amorphous semiconductor layer 20 corresponding to the third region C becomes the second intrinsic amorphous semiconductor layer 31.

[0191] Step h: Reference Figure 11 A conductive thin film layer 50 is formed integrally on the second doped microcrystalline semiconductor layer 23, the second doped amorphous semiconductor layer 32, and the doped polycrystalline semiconductor layer 42. Before forming the conductive thin film layer 50, a hydrofluoric acid cleaning step may be added to remove oxide layers formed on the second doped microcrystalline semiconductor layer 23, the second doped amorphous semiconductor layer 32, and the doped polycrystalline semiconductor layer 42 due to processes such as laser treatment.

[0192] Step i: Reference Figure 12 An isolation trench 51 is formed in the portion of the conductive film layer 50 corresponding to the third region C, penetrating along the thickness direction, to form an electrical isolation region. Here, at least material of the conductive film layer 50 is removed from the electrical isolation region. For example, the conductive film layer 50 is removed, or the conductive film layer 50 and a portion of the second doped amorphous semiconductor layer 32 are removed.

[0193] Step j: Reference Figure 13 A first electrode 61 is formed on the conductive film layer 50 on the side of the second doped microcrystalline semiconductor layer 23 away from the semiconductor substrate 10, and a second electrode 62 is formed on the conductive film layer 50 on the side of the doped polycrystalline semiconductor layer 42 away from the semiconductor substrate 10.

[0194] Thus far, various embodiments of the present disclosure have been described in detail. To avoid obscuring the concept of the present disclosure, some details known in the art have not been described. Based on the above description, those skilled in the art can fully understand how to implement the technical solutions disclosed herein.

[0195] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art will understand that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. Those skilled in the art will understand that the above embodiments may be modified or some technical features may be replaced with equivalents without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A back-contact solar cell comprising: A semiconductor substrate (10) having a light-facing surface (11) and a backlight surface (12), wherein the backlight surface (12) includes a first region (A); A first intrinsic amorphous semiconductor layer (21) is provided on the backlight surface (12) and is located in the first area (A); A first doped microcrystalline semiconductor layer (22) is provided on the first intrinsic amorphous semiconductor layer (21) and is located on a side of the first intrinsic amorphous semiconductor layer (21) away from the semiconductor substrate (10); and a second doped microcrystalline semiconductor layer (23) disposed on the first doped microcrystalline semiconductor layer (22) and located on a side of the first doped microcrystalline semiconductor layer (22) away from the semiconductor substrate (10); The conductivity type of the first doped microcrystalline semiconductor layer (22) is the same as the conductivity type of the second doped microcrystalline semiconductor layer (23), and the doping concentration of the second doped microcrystalline semiconductor layer (23) is greater than the doping concentration of the first doped microcrystalline semiconductor layer (22).

2. The back contact solar cell according to claim 1, wherein: The doping concentration of the first doped microcrystalline semiconductor layer (22) is less than or equal to 1×10 17 atoms / cm 3 The doping concentration of the second doped microcrystalline semiconductor layer (23) is greater than 1×10 17 atoms / cm 3 , and less than or equal to 1×10 20 atoms / cm 3 .

3. The back contact solar cell according to claim 1, wherein: The thickness of the first doped microcrystalline semiconductor layer (22) is smaller than the thickness of the second doped microcrystalline semiconductor layer (23).

4. The back contact solar cell according to claim 3, wherein: The thickness of the first doped microcrystalline semiconductor layer (22) is greater than or equal to 0.5 nm and less than or equal to 10 nm; the thickness of the second doped microcrystalline semiconductor layer (23) is greater than 10 nm and less than or equal to 50 nm.

5. The back contact solar cell according to claim 1, wherein The backlight surface (12) further includes a second region (B) and a third region (C), the first region (A) and the second region (B) are arranged at intervals along at least one direction perpendicular to the thickness direction of the semiconductor substrate (10), and the third region (C) is located between adjacent first regions (A) and second regions (B); Wherein, the back contact solar cell further comprises: a second intrinsic amorphous semiconductor layer (31), located in the third region (C), and a portion of which is disposed on the backlight surface (12); and A second doped amorphous semiconductor layer (32) is provided on the second intrinsic amorphous semiconductor layer (31) and is located on a side of the second intrinsic amorphous semiconductor layer (31) away from the semiconductor substrate (10); The second doped amorphous semiconductor layer (32) and the second doped microcrystalline semiconductor layer (23) are continuously connected at the boundary between the first region (A) and the third region (C), and the conductivity type of the second doped amorphous semiconductor layer (32) is the same as the conductivity type of the second doped microcrystalline semiconductor layer (23).

6. The back contact solar cell according to claim 5, wherein: The thickness of the second intrinsic amorphous semiconductor layer (31) is greater than the thickness of the first intrinsic amorphous semiconductor layer (21).

7. The back contact solar cell according to claim 6, wherein: The second intrinsic amorphous semiconductor layer (31) is continuously connected to the first intrinsic amorphous semiconductor layer (21) at a boundary position between the first region (A) and the third region (C).

8. The back contact solar cell according to claim 6, wherein: The thickness of the second intrinsic amorphous semiconductor layer (31) is greater than or equal to 7 nm and less than or equal to 20 nm; the thickness of the first intrinsic amorphous semiconductor layer (21) is greater than or equal to 3 nm and less than or equal to 10 nm.

9. The back-contact solar cell according to claim 5, further comprising: a tunneling passivation layer (41), arranged on the backlight surface (12), and located in the second region (B) and a portion of the third region (C) adjacent to the second region (B); and a doped polycrystalline semiconductor layer (42), disposed on the tunneling passivation layer (41) and located on a side of the tunneling passivation layer (41) away from the semiconductor substrate (10); The conductivity type of the doped polycrystalline semiconductor layer (42) is opposite to the conductivity type of the second doped amorphous semiconductor layer (32), and another portion of the second intrinsic amorphous semiconductor layer (31) is arranged on the doped polycrystalline semiconductor layer (42).

10. The back-contact solar cell according to claim 9, further comprising: a conductive thin film layer (50) disposed on the second doped microcrystalline semiconductor layer (23), the second doped amorphous semiconductor layer (32), and the doped polycrystalline semiconductor layer (42); The conductive film layer (50) is provided with an isolation groove (51) penetrating along the thickness direction at least in the third region (C), and the isolation groove (51) is used to insulate and isolate the portions of the conductive film layer (50) corresponding to the first region (A) and the second region (B).

11. The back-contact solar cell according to claim 9, further comprising: a first electrode (61) located on a side of the second doped microcrystalline semiconductor layer (23) away from the semiconductor substrate (10); and a second electrode (62) located on a side of the doped polycrystalline semiconductor layer (42) away from the semiconductor substrate (10); The first electrode (61) and the second electrode (62) correspond to the first region (A) and the second region (B), respectively, and are used to derive carriers of different conductive types.

12. The back-contact solar cell according to any one of claims 1 to 11, further comprising: A passivation layer (71) is provided on the light-facing surface (11); and An anti-reflection layer (72) is provided on the passivation layer (71) and is located on a side of the passivation layer (71) away from the semiconductor substrate (10).

13. A method for preparing a back-contact solar cell according to any one of claims 1 to 12, comprising: A semiconductor substrate (10) is provided, wherein the semiconductor substrate (10) has a light-facing surface (11) and a backlight surface (12), and the backlight surface (12) includes a first region (A); A stacked structure is formed in a first region (A) of the backlight surface (12), in which a first intrinsic amorphous semiconductor layer (21), a first doped microcrystalline semiconductor layer (22), and a second doped microcrystalline semiconductor layer (23) are stacked in sequence, wherein the conductivity type of the first doped microcrystalline semiconductor layer (22) and the conductivity type of the second doped microcrystalline semiconductor layer (23) are the same, and the doping concentration of the second doped microcrystalline semiconductor layer (23) is greater than the doping concentration of the first doped microcrystalline semiconductor layer (22).

14. The preparation method according to claim 13, wherein The steps of forming a stacked structure in which a first intrinsic amorphous semiconductor layer (21), a first doped microcrystalline semiconductor layer (22), and a second doped microcrystalline semiconductor layer (23) are stacked in sequence in a first area (A) of the backlight surface (12) include: forming an initial intrinsic amorphous semiconductor layer (20) in the first region (A); forming a first doped amorphous semiconductor layer (24) on the initial intrinsic amorphous semiconductor layer (20); Performing laser modification treatment on the first doped amorphous semiconductor layer (24); In the process of laser modification treatment of the first doped amorphous semiconductor layer (24), the first doped amorphous semiconductor layer (24) is converted into the second doped microcrystalline semiconductor layer (23) by laser, and a portion of the thickness of the initial intrinsic amorphous semiconductor layer (20) is crystallized, and the doping elements in the first doped amorphous semiconductor layer (24) diffuse into the crystallized portion of the initial intrinsic amorphous semiconductor layer (20), so that the crystallized portion of the initial intrinsic amorphous semiconductor layer (20) is converted into the first doped microcrystalline semiconductor layer (22); the portion of the initial intrinsic amorphous semiconductor layer (20) located on the side of the first doped microcrystalline semiconductor layer (22) adjacent to the semiconductor substrate (10) is defined as the first intrinsic amorphous semiconductor layer (21).

15. The preparation method according to claim 14, wherein The backlight surface (12) further includes a second region (B) and a third region (C), the first region (A) and the second region (B) are arranged at intervals along at least one direction perpendicular to the thickness direction of the semiconductor substrate (10), and the third region (C) is located between adjacent first regions (A) and second regions (B); Wherein, before the step of performing laser modification treatment on the first doped amorphous semiconductor layer (24), the preparation method further comprises: forming a second intrinsic amorphous semiconductor layer (31) on a portion of the third region (C) of the backlight surface (12); forming a second doped amorphous semiconductor layer (32) on the second intrinsic amorphous semiconductor layer (31), wherein the conductivity type of the second intrinsic amorphous semiconductor layer (31) is the same as the conductivity type of the second doped microcrystalline semiconductor layer (23); Wherein, the initial intrinsic amorphous semiconductor layer (20) and the second intrinsic amorphous semiconductor layer (31) are obtained through an integrated formation process.

16. The preparation method according to claim 15, wherein The first doped amorphous semiconductor layer (24) and the second doped amorphous semiconductor layer (32) are obtained through an integrated forming process.

17. The preparation method according to claim 15, wherein Before the step of forming the second intrinsic amorphous semiconductor layer (31), the preparation method further comprises: forming a tunnel passivation layer (41) on the second region (B) and a portion of the third region (C) adjacent to the second region (B); forming a doped polycrystalline semiconductor layer (42) on the tunnel passivation layer (41), wherein the conductivity type of the doped polycrystalline semiconductor layer (42) is opposite to the conductivity type of the second doped amorphous semiconductor layer (32); Another portion of the second intrinsic amorphous semiconductor layer (31) is formed on the doped polycrystalline semiconductor layer (42).

18. The preparation method according to claim 17, further comprising: forming a conductive thin film layer (50) integrally on the second doped microcrystalline semiconductor layer (23), the second doped amorphous semiconductor layer (32), and the doped polycrystalline semiconductor layer (42); An isolation groove (51) is provided in the portion of the conductive film layer (50) corresponding to the third region (C) and extending through the portion in the thickness direction, so as to insulate and isolate the portions of the conductive film layer (50) corresponding to the first region (A) and the second region (B).

19. The preparation method according to claim 17, further comprising: forming a first electrode (61) on a side of the second doped microcrystalline semiconductor layer (23) away from the semiconductor substrate (10); forming a second electrode (62) on a side of the doped polycrystalline semiconductor layer (42) away from the semiconductor substrate (10); The first electrode (61) and the second electrode (62) correspond to the first region (A) and the second region (B), respectively, and are used to derive carriers of different conductive types.

20. The preparation method according to any one of claims 13 to 19, further comprising: forming a passivation layer (71) on the light-facing surface (11); An anti-reflection layer (72) is formed on the passivation layer (71).

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