Back contact battery, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention provides a back contact cell and a preparation method thereof, and a photovoltaic module, and relates to the technical field of solar cells, the back contact cell comprises a silicon substrate, the back surface of the silicon substrate comprises a first region, a second region and a spacer region, and the adjacent first region and second region are separated by the spacer region; the first carrier collection layer has a first conduction type, the first carrier collection layer is arranged on the back surface of the silicon substrate and located in the first region and the spacer region, and the first carrier collection layer comprises a first doped polycrystalline silicon layer with a first crystallization rate; the isolation layer is located in the spacer region and arranged on the surface, away from the silicon substrate, of the first carrier collection layer, the isolation layer comprises a doping layer with a second crystallization rate, and the second crystallization rate is smaller than the first crystallization rate; and the second carrier collection layer has a second conduction type opposite to the first conduction type, and the second carrier collection layer is arranged on the back surface of the silicon substrate, is positioned in the second region and extends to cover the isolation layer. The back contact battery has excellent electrical properties.

Description

Technical Field

[0001] The present disclosure relates to a back-contact cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] In the development of solar cells, interdigitated back contact (IBC) cells have absorbed the amorphous silicon passivation technology of intrinsic thin-layer heterojunction (HJT) and evolved into HBC (Hetero-Junction Back Contact) cells. HBC uses hydrogenated amorphous silicon (a-Si:H) as a double-sided passivation layer, offering excellent passivation, higher open-circuit voltage, and higher efficiency. In the PN junction growth process, regional mask doping is used to reduce carrier recombination losses.

[0003] The prior art provides an HBC battery whose main structure includes: a silicon substrate, the back side of which includes a first region, a second region, and a spacer region, with adjacent first and second regions separated by the spacer region; a first carrier collection layer located on the first region and the spacer region, and a second carrier collection layer located on the second region and the spacer region. The first and second carrier collection layers have opposite conductivity types. In the spacer region, the second carrier collection layer overlies the first carrier collection layer. The second carrier collection layer includes an intrinsic silicon-containing layer and a doped silicon-containing layer disposed on the intrinsic silicon-containing layer.

[0004] In the direction perpendicular to the surface of the silicon substrate, the above-mentioned HBC battery is prone to leakage in the spacer area. Summary of the Invention

[0005] The present disclosure provides a back-contact cell and a preparation method thereof, and a photovoltaic module, which can improve the electrical performance of the back-contact cell.

[0006] A first aspect of the present disclosure provides a back-contact battery, comprising:

[0007] The silicon substrate has a back surface comprising a first region, a second region and a spacer region, wherein adjacent first regions and second regions are separated by the spacer region;

[0008] a first carrier collection layer having a first conductivity type, the first carrier collection layer being disposed on the back side of the silicon substrate and being located in the first region and the spacer region, the first carrier collection layer comprising a first doped polysilicon layer having a first crystallization rate;

[0009] an isolation layer located in the spacer region and disposed on a surface of the first carrier collection layer away from the silicon substrate, the isolation layer comprising a second doped polysilicon layer having a second crystallization rate, the second crystallization rate being less than the first crystallization rate; and

[0010] The second carrier collection layer has a second conductivity type opposite to the first conductivity type. The second carrier collection layer is arranged on the back side of the silicon substrate and is located in the second region and extends to cover the isolation layer.

[0011] In some embodiments, the first carrier collection layer also includes a tunneling layer, which is arranged on the back side of the silicon substrate and is located in the first region and the spacer region. The first doped polysilicon layer is arranged on the surface of the tunneling layer away from the silicon substrate, and the second doped polysilicon layer is arranged on the surface of the first doped polysilicon layer away from the silicon substrate.

[0012] In some embodiments, the second doped polysilicon layer has the same doping element as the first doped polysilicon layer, the first doped polysilicon layer has a first doping concentration, and the second doped polysilicon layer has a second doping concentration that is less than the first doping concentration.

[0013] In some embodiments, the first doping concentration is 1×10 19 ~1×10 21 cm -3 , preferably 1×10 20 ~1×10 21 cm -3 and / or

[0014] The second doping concentration is 1×10 19 ~1×10 20 cm -3 and / or

[0015] The difference between the first doping concentration and the second doping concentration is in the range of 9×10 19 ~9×10 20 cm -3 .

[0016] In some embodiments, the thickness of the tunneling layer ranges from 0.5 nm to 3.0 nm, preferably from 1.0 nm to 1.5 nm; and / or

[0017] The thickness of the first doped polysilicon layer and the second doped polysilicon layer ranges from 50 nm to 300 nm, preferably from 50 nm to 150 nm.

[0018] In some embodiments, the second carrier collection layer comprises:

[0019] An intrinsic silicon-containing layer having a third crystallinity, disposed on the back side of the silicon substrate and located in the second region; and

[0020] The doped silicon-containing layer has a fourth crystallization rate and is disposed on a surface of the intrinsic silicon-containing layer away from the silicon substrate, wherein the fourth crystallization rate is greater than the third crystallization rate and less than the second crystallization rate;

[0021] Wherein, both the intrinsic silicon-containing layer and the doped silicon-containing layer extend to cover the isolation layer.

[0022] In some embodiments, the intrinsic silicon-containing layer has a thickness ranging from 10 nm to 50 nm; and / or

[0023] The thickness of the doped silicon-containing layer ranges from 10 nm to 100 nm.

[0024] In some embodiments, the isolation layer further includes an insulating layer, and the insulating layer is located in the spacer region and disposed between the second doped polysilicon layer and the second carrier collection layer.

[0025] In some embodiments, the insulating layer is at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, and the thickness of the insulating layer ranges from 20 nm to 100 nm, preferably from 40 nm to 60 nm.

[0026] In some embodiments, the back contact cell further includes a conductive layer covering the second carrier collection layer and the first carrier collection layer located in the first region;

[0027] An isolation groove is formed in the spacing area of ​​the conductive layer. The isolation groove at least penetrates the conductive layer and has a depth not exceeding the surface of the isolation layer away from the silicon substrate.

[0028] In some embodiments, the first conductivity type is the same as the conductivity type of the silicon substrate.

[0029] In some embodiments, the back contact cell further comprises a passivation layer and / or an anti-reflection layer disposed on the front side of the silicon substrate.

[0030] A second aspect of the present disclosure provides a photovoltaic module comprising the back-contact cell of the above embodiment.

[0031] A third aspect of the present disclosure provides a method for preparing a back-contact battery, comprising:

[0032] S1. Providing a silicon substrate, wherein the back side of the silicon substrate comprises a first region, a second region, and a spacer region, and adjacent first and second regions are separated by the spacer region;

[0033] S2. forming a first carrier collection layer having a first conductivity type in the first region and the spacer region on the back side of the silicon substrate, and disposing an isolation layer on the entire surface of the first carrier collection layer away from the silicon substrate; wherein the first carrier collection layer comprises a first doped polysilicon layer having a first crystallization rate, and the isolation layer comprises a second doped polysilicon layer having a second crystallization rate, wherein the second crystallization rate is less than the first crystallization rate;

[0034] S3, forming a second carrier collection layer having a second conductivity type on the entire back side of the silicon substrate, where the second conductivity type is opposite to the first conductivity type;

[0035] S4. Remove the isolation layer and the portion of the second carrier collection layer located in the first region.

[0036] In some embodiments, the first carrier collection layer further includes a tunneling layer, S2 including:

[0037] S21, sequentially disposing a tunneling layer, a pre-doped polysilicon layer, and an isolation layer precursor on the entire back surface of the silicon substrate, wherein the isolation layer precursor includes an intrinsic polysilicon layer having a fifth crystallization ratio, and the fifth crystallization ratio is less than the second crystallization ratio;

[0038] S22, removing the isolation layer precursor and a partial thickness of the pre-doped polysilicon layer in the second region by laser;

[0039] S23, annealing the silicon substrate after laser stripping to activate the doping elements in the pre-doped polysilicon layer to form a first doped polysilicon layer, and the intrinsic polysilicon layer to become a second doped polysilicon layer, so that the isolation layer precursor becomes an isolation layer.

[0040] In some embodiments, the deposition temperature of the intrinsic polysilicon layer is lower than the deposition temperature of the pre-doped polysilicon layer.

[0041] In some embodiments, the second carrier collection layer includes an intrinsic silicon-containing layer and a doped silicon-containing layer, and S3 includes:

[0042] S31, cleaning the back surface of the silicon substrate with an alkaline solution to expose the silicon substrate in the second area, and texturing the back surface of the silicon substrate in the second area to form a texturing surface;

[0043] S32 , sequentially forming an intrinsic silicon-containing layer and a doped silicon-containing layer on the back side of the silicon substrate, wherein the intrinsic silicon-containing layer and the doped silicon-containing layer cover the second region and extend to the covering isolation layer.

[0044] In some embodiments, a height difference between the first region and the second region of the back surface of the silicon substrate is in a range of 3 to 10 um.

[0045] In some embodiments, the preparation method further comprises:

[0046] S5. Form a passivation layer and / or an anti-reflection layer on the front surface of the silicon substrate.

[0047] In some embodiments, the preparation method further comprises:

[0048] S6. forming a conductive layer on the back side of the silicon substrate;

[0049] S7. An isolation trench is formed in the spacing area on the conductive layer. The isolation trench at least penetrates the conductive layer and has a depth not exceeding the surface of the isolation layer away from the silicon substrate.

[0050] In the back-contact battery of the embodiment of the present disclosure, a second doped polysilicon layer with a second crystallization rate is provided in the isolation layer of the battery of this embodiment, and the second crystallization rate is less than the first crystallization rate of the first doped polysilicon layer in the first carrier collection layer. The spacer region in the back-contact battery thus obtained includes a first carrier collection layer comprising a first doped polysilicon layer, an isolation layer comprising a second doped polysilicon layer, and a second carrier collection layer, which are sequentially stacked from the inside to the outside on the back side of the silicon substrate. In the back-contact battery provided by the embodiment of the present disclosure, an isolation layer comprising a second doped polysilicon layer with a lower crystallization rate is provided between the first carrier collection layer and the second carrier collection layer, which can play a better isolation role and effectively reduce the leakage problem caused by the recombination of carriers of opposite conductivity types in the first carrier collection layer and the second carrier collection layer in the spacer region.

[0051] The disclosed embodiments also have the following further beneficial effects: During the battery preparation process, when removing excess film layers through a laser process, a low-crystallization-rate polysilicon layer is used as a covering layer. Because this layer has strong light absorption and higher light absorption performance than the first doped polysilicon layer (pre-doped polysilicon layer before the doping concentration is increased), it can serve as a sacrificial layer during the first processing and as a protective layer during the second processing. On the one hand, it can reduce the power of the laser film opening and reduce the damage to the first doped polysilicon layer (or pre-doped polysilicon layer) and the silicon substrate during the laser film opening. On the other hand, it can protect the first doped polysilicon layer during the second laser processing, thereby improving the efficiency of the battery in converting light energy into electrical energy, reducing the impact of damage on the passivation performance of the subsequent passivation layer, and improving the passivation effect of the battery. As a result, the battery can have better electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0053] Figure 1 A schematic structural diagram of a back-contact battery provided in one embodiment of the present disclosure.

[0054] Figure 2 A schematic structural diagram of a silicon substrate provided in one embodiment of the present disclosure.

[0055] Figure 3 This is a structural diagram of an embodiment of the present disclosure in which a tunneling layer, a pre-doped polysilicon layer, an intrinsic polysilicon layer and an insulating layer are sequentially provided on the back side of a silicon substrate.

[0056] Figure 4 This is a schematic diagram of the structure after removing the insulating layer, the intrinsic polysilicon layer and a partial thickness of the pre-doped polysilicon layer in the second region and performing annealing treatment according to an embodiment of the present disclosure.

[0057] Figure 5 This is a structural diagram of an embodiment of the present disclosure in which the second area on the back side of the silicon substrate is exposed, and the second area on the back side and the front side are formed into a textured surface.

[0058] Figure 6 This is a structural schematic diagram of sequentially forming an intrinsic silicon-containing layer and a doped silicon-containing layer on the back side of a silicon substrate according to an embodiment of the present disclosure.

[0059] Figure 7 Schematic diagram of a structure in which a passivation layer is formed on the front surface of a silicon substrate according to an embodiment of the present disclosure.

[0060] Figure 8 Schematic diagram of the structure of forming an anti-reflection layer on the passivation layer on the front surface of a silicon substrate according to an embodiment of the present disclosure.

[0061] Figure 9 This is a structural diagram of removing the intrinsic silicon-containing layer, the doped silicon-containing layer, the insulating layer and the second doped polysilicon layer in the first region according to an embodiment of the present disclosure.

[0062] Figure 10 Schematic diagram of a structure in which a conductive layer is formed on the back side of a silicon substrate according to an embodiment of the present disclosure.

[0063] Figure 11 This is a structural diagram of an isolation trench provided in a spacing region according to an embodiment of the present disclosure.

[0064] Figure 12 A schematic diagram of a structure in which a first electrode and a second electrode are provided in accordance with an embodiment of the present disclosure.

[0065] Figure 13 A schematic flow chart of a method for preparing a back-contact battery according to an embodiment of the present disclosure.

[0066] Description of reference numerals:

[0067] 1. Silicon substrate; 2. Tunneling layer; 3. Pre-doped polysilicon layer; 3-1. First doped polysilicon layer; 4. Intrinsic polysilicon layer; 4-1. Second doped polysilicon layer; 5. Insulating layer; 6. Intrinsic silicon-containing layer; 7. Doped silicon-containing layer; 8. Passivation layer; 9. Anti-reflection layer; 10. Conductive layer; 11. Isolation trench; 12. First electrode; 13. Second electrode; A. First region; B. Second region; C. Spacer region; C1. First spacer region; C2. Second spacer region. DETAILED DESCRIPTION

[0068] The following detailed description of the embodiments of the present disclosure is provided in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of the present disclosure, but are not intended to limit the scope of the present disclosure, that is, the present disclosure is not limited to the described embodiments.

[0069] The main structure of a conventional HBC battery includes: a silicon substrate, the back of which includes an N region, a P region, and a spacer region, with adjacent N and P regions separated by the spacer region; a first carrier collection layer located above the N region and the spacer region, and a second carrier collection layer located above the P region and the spacer region. The first and second carrier collection layers have opposite conductivity types. In the spacer region, the second carrier collection layer overlies the first carrier collection layer. The second carrier collection layer includes an intrinsic silicon-containing layer and a doped silicon-containing layer disposed on the intrinsic silicon-containing layer.

[0070] In existing HBC cells, the doped silicon-containing layers in the first and second carrier-collecting layers of the spacer region are separated only by an intrinsic silicon-containing layer. While the intrinsic silicon-containing layer provides a certain degree of insulation, carriers of opposite conductivity types in the first and second carrier-collecting layers can still pass through the intrinsic silicon-containing layer and recombine, causing leakage in the spacer region perpendicular to the silicon substrate surface.

[0071] Through research, the inventors further discovered that the manufacturing process of HBC batteries includes two laser film opening processes. After the first carrier collection layer is formed on the entire back side of the silicon substrate, the first carrier collection layer located in the P region is removed by the first laser, and then the second carrier collection layer is formed on the entire back side of the silicon substrate, and then the second carrier collection layer located in the N region is removed by the second laser.

[0072] However, due to the high penetration of laser light, the first laser removal of the first carrier collection layer in the P region can cause significant damage to the silicon substrate and the adjacent first carrier collection layer. Furthermore, the second laser removal of the second carrier collection layer in the N region also causes significant damage to the N region's first carrier collection layer, the silicon substrate, and the adjacent second carrier collection layer. If the damage caused by laser ablation is significant, then to minimize the impact of laser damage, the damaged area must be removed. This results in a large height difference between the P and N regions, hindering carrier transport, manifesting as increased string resistance and a reduced fill factor. Furthermore, this results in a large exposed silicon surface area at the edge between the P and N regions, and laser thermal effects can damage the adjacent N region film layer, leading to poor passivation in this area. Furthermore, to minimize laser damage, the laser process window must be strictly controlled during the fabrication process to avoid large fluctuations in laser power, making the fabrication process more complex. Therefore, this structure and corresponding process are not conducive to the production of high-performance back-contact cells.

[0073] Therefore, rational design of the spacer structure and preparation process is crucial to the formation of high-performance back-contact cells.

[0074] Based on the above ideas, the present disclosure provides a back contact battery, hereinafter referred to as "battery", such as Figure 1 As shown, in some embodiments, a back contact cell includes: a silicon substrate 1, a back surface including a first region A, a second region B and a spacer region C, and adjacent first regions A and second regions B are separated by the spacer region C;

[0075] a first carrier collection layer having a first conductivity type, the first carrier collection layer being disposed on the back side of the silicon substrate 1 and located in the first region A and the spacer region C, the first carrier collection layer comprising a first doped polysilicon layer 3-1 having a first crystallization rate;

[0076] an isolation layer located in the spacer region C and disposed on a surface of the first carrier collection layer away from the silicon substrate 1, the isolation layer comprising a second doped polysilicon layer 4-1 having a second crystallization rate, the second crystallization rate being less than the first crystallization rate; and

[0077] The second carrier collection layer has a second conductivity type opposite to the first conductivity type. The second carrier collection layer is provided on the back side of the silicon substrate 1 and is located in the second region B and extends to cover the isolation layer.

[0078] The silicon substrate 1 can be N-type or P-type, for example, an N-type silicon wafer, such as a phosphorus-doped single-crystal silicon wafer. Optionally, the front surface of the silicon substrate 1 has a textured surface to reduce light reflection and increase light absorption, thereby improving the photovoltaic conversion efficiency of the battery.

[0079] The first conductivity type may be N-type, and the corresponding second conductivity type may be P-type, or vice versa. In some embodiments, the first conductivity type is the same as the conductivity type of the silicon substrate 1 .

[0080] Among them, such as Figure 2 As shown, the first region A, second region B, and spacer region C are not physical components, but rather are regions demarcated on the backside of the silicon substrate 1. At least one of each of the first region A, second region B, and spacer region C can be provided. Multiple first regions A and multiple second regions B can be alternately arranged, for example, along a predetermined direction, which can be the length or width of the silicon substrate 1. The spacer region C is located between adjacent first regions A and second regions B. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0081] like Figure 1As shown, a first carrier collection layer is provided on the back side of the silicon substrate 1 in the first region A and the spacer region C. The first carrier collection layer includes a first doped polysilicon layer 3-1 having a first crystallization ratio. The first doped polysilicon layer 3-1 has a first conductivity type, for example, an N-type doped polysilicon layer. The crystallization ratio refers to the volume ratio of the crystalline phase (ordered structure) to the amorphous phase (disordered structure) in a material, and is typically expressed as a percentage.

[0082] The isolation layer is configured to isolate the first carrier collection layer from the second carrier collection layer. One side edge of the isolation layer is aligned with a side edge of the first carrier collection layer proximate to the second region B. If the first region A and the second region B are spaced apart along a predetermined direction, the width of the isolation layer along the predetermined direction is less than the width of the first carrier collection layer along the predetermined direction. The isolation layer includes a second doped polysilicon layer 4-1 having a second crystallinity, or may be superimposed with other insulating layers.

[0083] For example, the first doped polysilicon layer 3-1 is substantially completely crystallized, with a first crystallization ratio ranging from 95% to 100%; a second crystallization ratio ranging from 90% to 95%. The second doped polysilicon layer 4-1 has a higher content of microcrystals, unlike the first doped polysilicon layer 3-1 which is primarily composed of large grains. Large grains have a higher electrical conductivity than microcrystals, but microcrystals have a better ability to absorb laser light.

[0084] The second carrier collection layer has a second conductivity type. The second carrier collection layer is arranged on the back side of the silicon substrate 1 and is located in the second area B and extends to the covering isolation layer, that is, the second carrier collection layer covers the second area B on the back side of the silicon substrate 1, the isolation layer of the spacer area C and the first carrier collection layer on the side of the isolation layer.

[0085] In the isolation layer of the battery of this embodiment, a second doped polysilicon layer 4-1 with a second crystallization rate is provided, and the second crystallization rate is lower than the first crystallization rate of the first doped polysilicon layer 3-1 in the first carrier collection layer. The spacer region C in the battery thus obtained includes a first carrier collection layer comprising a first doped polysilicon layer 3-1, an isolation layer comprising a second doped polysilicon layer 4-1, and a second carrier collection layer, which are sequentially stacked from the inside to the outside on the back of the silicon substrate 1. In the battery provided by the embodiment of the present disclosure, an isolation layer comprising a second doped polysilicon layer 4-1 with a lower crystallization rate is provided between the first carrier collection layer and the second carrier collection layer, which can play a better isolation role and effectively reduce the leakage problem caused by the recombination of carriers of opposite conductivity types in the first carrier collection layer and the second carrier collection layer in the spacer region. For example, as an isolation layer, the lower the doping concentration of the second doped polysilicon layer 4-1, the better the isolation effect.

[0086] Furthermore, a second doped polysilicon layer 4-1 with a second crystallinity lower than the first is provided in the isolation layer of the cell. During the cell fabrication process, when excess film layers are removed via laser processing, the low-crystallization-ratio polysilicon layer is covered. Due to its strong light absorption, which is higher than that of the first doped polysilicon layer 3-1 (pre-doped polysilicon layer 3 before the doping concentration is increased), this layer serves as a sacrificial layer during the first laser processing and as a protective layer during the second laser processing. This reduces the power of the laser ablation process and damage to the underlying film layers, specifically the first doped polysilicon layer 3-1 (or pre-doped polysilicon layer 3) and the silicon substrate 1. Furthermore, it protects the first doped polysilicon layer during the second laser processing, thereby improving the cell's efficiency in converting light energy into electrical energy and reducing the impact of damage on the passivation performance of the subsequent passivation layer, thereby enhancing the cell's passivation effectiveness. This results in a cell with superior electrical performance. If the second doped polysilicon layer 4 - 1 is a doped oxide layer, since the doped oxide layer has a weak light absorption capability, most of the laser light is absorbed by the first doped polysilicon layer 3 - 1 and the silicon substrate 1 , thereby causing greater damage.

[0087] Moreover, since the power parameters of the laser inevitably fluctuate greatly during the processing, when the power parameters are high, it can prevent the first doped polysilicon layer 3-1 (or pre-doped polysilicon layer 3) and the silicon substrate 1 from causing significant damage. When the power parameters are low, the polysilicon layer with a low crystallization rate has a strong light absorption ability, which can also meet the removal requirements of the film layer. This can broaden the process window of laser film opening, reduce the strictness of control over laser processing parameters, thereby reducing processing difficulty, and eliminating the need to use expensive femtosecond lasers, thereby reducing production costs.

[0088] Furthermore, after a single laser process, since the damage to the silicon substrate 1 is minimal, when the film layer on the surface of the second region B is subsequently removed to expose the surface of the silicon substrate 1, there is no need to remove a thicker damaged layer to repair the laser damage. This reduces the height difference between the first region A and the second region B, facilitating carrier transport, reducing string resistance, increasing the battery's fill factor, and improving energy conversion efficiency. Furthermore, during passivation, good passivation effects and mechanical properties can be achieved at the transition junction between the first region A and the second region B. For example, defects in the connection cross-section are reduced, passivation layer coverage is uniform, and stress concentration is reduced, thereby improving the overall passivation effect, stabilizing the preparation process, and increasing the battery yield.

[0089] In some embodiments, the first carrier collection layer also includes a tunneling layer 2, which is arranged on the back side of the silicon substrate 1 and is located in the first region A and the spacer region C. The first doped polysilicon layer 3-1 is arranged on the surface of the tunneling layer 2 away from the silicon substrate 1, and the second doped polysilicon layer 4-1 is arranged on the surface of the first doped polysilicon layer 3-1 away from the silicon substrate 1.

[0090] Among them, the tunneling layer 2 is an ultra-thin dielectric layer that allows electrons to pass through efficiently through the quantum tunneling effect while blocking the recombination loss of other charges (such as holes). It can be made of silicon oxide (SiO2), silicon nitride (SiN x ) or aluminum oxide (Al2O3), etc.

[0091] In some embodiments, the second doped polysilicon layer 4-1 has the same doping element as the first doped polysilicon layer 3-1, the first doped polysilicon layer 3-1 has a first doping concentration, and the second doped polysilicon layer 4-1 has a second doping concentration, which is less than the first doping concentration.

[0092] The doping elements in the second doped polysilicon layer 4-1 can be transferred from the first doped polysilicon layer 3-1 during high temperature annealing, and the second doped polysilicon layer 4-1 is located in the spacer region C, so the second doped polysilicon layer 4-1 is lightly doped polysilicon.

[0093] This embodiment provides the first doped polysilicon layer 3-1 with a higher doping concentration, ensuring efficient carrier transport. The second doped polysilicon layer 4-1 has a lower doping concentration, which improves resistivity. The resistivity of the second doped polysilicon layer 4-1 is significantly higher than that of the first doped polysilicon layer 3-1, effectively blocking lateral leakage between the adjacent first and second regions A and B, thereby improving the operational reliability of the battery.

[0094] In some embodiments, the first doping concentration may be 1×10 19 ~1×10 21 cm -3 , preferably 1×10 20 ~1×10 21 cm -3 The second doping concentration can be 1×10 19 ~1×10 20 cm -3 The difference between the first doping concentration and the second doping concentration may be in the range of 9×10 19 ~9×10 20 cm -3 .

[0095] Although the first doping concentration range and the second doping concentration range have the same lower limit, the range of the first doping concentration is greater than the range of the second doping concentration. When selecting a value, a value within this range where the first doping concentration is greater than the second doping concentration can be selected. Alternatively, more preferably, the entire range of the first doping concentration is greater than the range of the second doping concentration.

[0096] Furthermore, the difference between the first doping concentration and the second doping concentration is limited to a certain range, resulting in a significant concentration difference. During the actual fabrication process, a second doped polysilicon layer 4-1 of a certain thickness (relatively thin) can be retained on the first doped polysilicon layer 3-1 corresponding to the first region A (i.e., the thickness of the second doped polysilicon layer 4-1 corresponding to the first region A is less than the thickness of the second doped polysilicon layer 4-1 corresponding to the spacing region C). This, on the one hand, avoids damage to the first doped polysilicon 3-1 during complete removal of the second doped polysilicon layer 4-1, and on the other hand, helps increase the process window for subsequent deposition of the transparent conductive oxide (TCO) film. This is because the work function of the TCO film must be between that of the first carrier collection layer and the second carrier collection layer, but cannot differ significantly from the work function of either the first or second carrier collection layer. Therefore, if the work function gap between the first and second carrier collection layers can be reduced, the process window for TCO thin film deposition can be increased (because the work function of the TCO is closely related to the deposition process, particularly the oxygen permeability, as the oxygen doping level is closely related to the work function of the TCO film). The second doping concentration is lower than the first doping concentration, meaning that the work function corresponding to the second doping concentration is greater than the work function corresponding to the first doping concentration. Therefore, the work function gap between the second doped polysilicon layer 4-1 and the second carrier collection layer surface is smaller than the work function gap between the first doped polysilicon layer 3-1 and the second carrier collection layer surface. Therefore, retaining a certain thickness of the second doped polysilicon layer 4-1 within the first doped polysilicon layer 3-1 corresponding to the first region A helps increase the process window for TCO thin film deposition.

[0097] In some embodiments, the thickness of the tunneling layer 2 may range from 0.5 nm to 3.0 nm, preferably from 1.0 nm to 1.5 nm; the thickness of the first doped polysilicon layer 3 - 1 and the second doped polysilicon layer 4 - 1 may range from 50 nm to 300 nm, preferably from 50 nm to 150 nm.

[0098] For example, the thickness of the tunneling layer 2 can be: 0.5nm, 0.6nm, 0.7nm, 0.8nm, 0.9nm, 1.0nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm, 2.0nm, 2.1nm, 2.2nm, 2.3nm, 2.4nm, 2.5nm, 2.6nm, 2.7nm, 2.8nm, 2.9nm, 3.0nm, but is not limited thereto.

[0099] For example, the thickness of the first doped polysilicon layer 3-1 and the second doped polysilicon layer 4-1 can be: 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 120nm, 140nm, 160nm, 180nm, 200nm, 220nm, 240nm, 260nm, 280nm, 300nm, but is not limited thereto.

[0100] In some embodiments, as Figure 1 As shown, the second carrier collection layer includes: an intrinsic silicon-containing layer 6, having a third crystallization rate, disposed on the back side of the silicon substrate 1 and located in the second region B; and a doped silicon-containing layer 7, having a fourth crystallization rate, disposed on the surface of the intrinsic silicon-containing layer 6 away from the silicon substrate 1, the fourth crystallization rate being greater than the third crystallization rate but less than the second crystallization rate; wherein both the intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 extend to the covering isolation layer.

[0101] Regarding the relationship between the crystallization rates of each layer, the first crystallization rate, the second crystallization rate, the fourth crystallization rate, and the third crystallization rate decrease in sequence. The first crystallization rate has a first difference with the second crystallization rate, the fourth crystallization rate has a second difference with the third crystallization rate, and the second crystallization rate has a third difference with the fourth crystallization rate. The third difference is greater than the first difference, and the third difference is greater than the second difference. That is, the first crystallization rate is relatively close to the second crystallization rate, the fourth crystallization rate is relatively close to the third crystallization rate, but the difference between the second crystallization rate and the fourth crystallization rate is relatively large.

[0102] The intrinsic silicon-containing layer 6 is an intrinsic low-crystallized silicon-containing layer having very low crystallinity and is almost completely amorphous. The first doped polysilicon layer 3-1 has a first conductivity type, and the doped silicon-containing layer 7 has a second conductivity type.

[0103] In this embodiment, the intrinsic silicon-containing layer 6 contains not only silicon but also other elements (such as oxygen, carbon, or nitrogen). This helps improve the battery's energy band matching, reduces interface band offset, and promotes carrier separation. Furthermore, the mixed elements can saturate silicon dangling bonds, reducing passivation failure at high temperatures. Furthermore, it can reduce parasitic absorption and anti-reflection effects, and lower stress to prevent film cracking or delamination. Thus, the use of the intrinsic silicon-containing layer 6 can simultaneously address passivation, conductivity, optics, and reliability issues, representing a key design breakthrough in heterojunction cell performance. Compared to the use of an intrinsic amorphous silicon layer, the intrinsic amorphous silicon layer contains only pure amorphous silicon, which has a band gap significantly different from that of crystalline silicon, resulting in energy band discontinuity at the interface.

[0104] The doped silicon-containing layer 7 contains both amorphous silicon and microcrystalline silicon. Since microcrystalline silicon has a higher carrier mobility and forms a conductive grid that can provide a low-resistance path, it has better conductivity, is conducive to carrier conduction, and can improve the working efficiency of the battery. Compared with the use of doped amorphous silicon, the resistivity of doped amorphous silicon is higher, which is not conducive to the conduction of carriers. In addition, the doped silicon-containing layer 7 also has a wider spectral transmittance, and due to the transition of microcrystalline silicon, the transition stress at the interface connection can be reduced, thereby improving the reliability of long-term use. Moreover, the hydrogen in amorphous silicon can passivate interface defects, while microcrystalline silicon provides a conductive channel, achieving synergistic optimization of passivation and conductivity.

[0105] In some embodiments, the intrinsic silicon-containing layer 6 may have a thickness ranging from 10 nm to 50 nm, and the doped silicon-containing layer 7 may have a thickness ranging from 10 nm to 100 nm. The doped silicon-containing layer 7 may be thicker than the intrinsic silicon-containing layer 6 .

[0106] For example, the intrinsic silicon-containing layer 6 may have a thickness of 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. The doped silicon-containing layer 7 may have a thickness in the range of 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, or 100 nm.

[0107] In some embodiments, the isolation layer further includes an insulating layer 5, which is located in the spacer region C and disposed between the second doped polysilicon layer 4-1 and the second carrier collection layer in the thickness direction of the silicon substrate 1. Specifically, the insulating layer 5 is located between the second doped polysilicon layer 4-1 and the intrinsic silicon-containing layer 6. The insulating layer 5 can be thicker than the second doped polysilicon layer 4-1 to enhance the insulation effect.

[0108] For example, the insulating layer 5 is at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0109] For example, the thickness of the insulating layer 5 ranges from 20 nm to 100 nm, preferably from 40 nm to 60 nm. For example, the thickness of the insulating layer 5 is 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 100 nm, etc., but is not limited thereto.

[0110] This embodiment can further improve the isolation effect by providing the insulating layer 5, significantly reduce leakage, and improve the performance of the battery.

[0111] In some embodiments, the back contact battery further includes a conductive layer 10, which covers the second carrier collection layer and the first carrier collection layer located in the first area A; the conductive layer 10 opens an isolation groove 11 in the spacing area C, and the isolation groove 11 at least penetrates the conductive layer 10, and the depth does not exceed the isolation layer away from the surface of the silicon substrate 1.

[0112] Among them, such as Figure 1 As shown, in the spacer C, the area where the isolation trench 11 is set is the first spacer C1, and the area outside the isolation trench 11 is the second spacer C2. In a preset direction, the isolation trench 11 can be set in the middle area of ​​the spacer C, or in other areas.

[0113] For example, the conductive layer 10 is a multilayer, stacked layer or mixture of one or more doped metal oxides or nitrides. The metal oxide can be indium oxide, tin oxide, zinc oxide, cadmium oxide, or titanium nitride. The metal nitride can be titanium nitride. The doping elements can be indium, tin, calcium, aluminum, cadmium, zinc, cerium, or fluorine, preferably indium cobalt oxide (full name "Indium Cobalt Oxide", abbreviated as ICO).

[0114] The battery may also include a first electrode 12 and a second electrode 13, both made of metal. The first electrode 12 is located on the conductive layer 10 corresponding to the first region A, and the second electrode 13 is located on the conductive layer 10 corresponding to the second region B. The current in the first carrier collection layer is transmitted to the first electrode 12 through the conductive layer 10, and the current in the second carrier collection layer is transmitted to the second electrode 13 through the conductive layer 10. The first electrode 12 and the second electrode 13 may be formed by at least one of screen printing, electroplating, or transfer printing.

[0115] This embodiment provides an isolation groove 11, the depth of which at least penetrates the conductive layer 10, which can completely cut off the conductive path between the first carrier collection layer and the second carrier collection layer, prevent the first electrode 12 and the second electrode 13 from short-circuiting, and the greater the depth of the isolation groove 11, the better the isolation effect; and the isolation groove 11 does not exceed the distance between the isolation layer and the surface of the silicon substrate 1, that is, it does not exceed the distance between the insulating layer and the surface of the silicon substrate 1, does not touch the isolation layer, and does not affect the insulation of the isolation layer.

[0116] In some embodiments, the back contact cell further includes a passivation layer 8 and / or an anti-reflection layer 9 disposed on the front surface of the silicon substrate 1. The passivation layer 8 or the anti-reflection layer 9 can improve the passivation performance of the cell and reduce or avoid the impact of defects generated during the cell preparation process.

[0117] For example, in the battery of the above embodiment, the intrinsic silicon-containing layer 6 and / or the doped silicon-containing layer 7 is a single layer with the same performance among microcrystalline, nano, amorphous silicon, silicon oxide or silicon carbide thin film layers, or a multilayer with different performance, or a stacked or mixed silicon-containing thin film of several types.

[0118] The passivation layer 8 is one of an intrinsic silicon-containing layer and a doped silicon-containing layer or a stacked layer. The thickness of the intrinsic silicon-containing layer as the passivation layer can be 1-15 nm, and the thickness of the doped silicon-containing layer can be 0-15 nm. Generally, the conductivity type of the doped silicon-containing layer as the passivation layer 8 is the same as the conductivity type of the silicon substrate 1.

[0119] In some specific embodiments of the battery, Figure 1 As shown, a passivation layer 8 and an anti-reflection layer 9 are sequentially provided on the front side of the silicon substrate 1 in a direction away from the silicon substrate 1. A tunneling layer 2, a first doped polysilicon layer 3-1, a conductive layer 10, and a first electrode 12 are sequentially provided on the back side of the silicon substrate 1 in a first region A in a direction away from the silicon substrate 1. An intrinsic silicon-containing layer 6, a doped silicon-containing layer 7, a conductive layer 10, and a second electrode 13 are sequentially provided on the back side of the silicon substrate 1 in a second region B in a direction away from the silicon substrate 1. A tunneling layer 2, a first doped polysilicon layer 3-1, a second doped polysilicon layer 4-1, an insulating layer 5, an intrinsic silicon-containing layer 6, a doped silicon-containing layer 7, and a conductive layer 10 are sequentially provided on the back side of the silicon substrate 1 in an isolation region C in a direction away from the silicon substrate 1. The depth of the isolation trench 11 is such that the intrinsic silicon-containing layer 6, the doped silicon-containing layer 7, and the conductive layer 10 are removed.

[0120] Secondly, the present disclosure provides a photovoltaic module including the back-contact cell of the above embodiment. Exemplarily, the photovoltaic module includes a laminate and a frame assembled to the edge of the laminate, wherein the laminate includes a cover sheet, an adhesive film, a back-contact cell, an adhesive film, and a back sheet stacked in sequence.

[0121] Because the second doped polysilicon layer 4-1 with a second crystallinity lower than the first is included in the isolation layer of the cell, the isolation effect is improved, effectively preventing leakage in the isolation region. Furthermore, during the cell fabrication process, when the laser process removes excess film layers, the low-crystallization-ratio polysilicon layer is used as a covering layer. Due to its strong light absorption, which is higher than that of the first doped polysilicon layer 3-1 (pre-doped polysilicon layer 3 before the doping concentration is increased), this layer serves as a sacrificial layer during the first laser process and a protective layer during the second laser process. This reduces the power of the laser ablation process and minimizes damage to the first doped polysilicon layer 3-1 (or pre-doped polysilicon layer 3) and the silicon substrate 1 during the laser ablation process. This improves the cell's efficiency in converting light energy into electrical energy and minimizes the impact of damage on the subsequent passivation layer, enhancing the cell's passivation effectiveness. This results in a cell with superior electrical performance. This also improves the efficiency of the photovoltaic module in converting light energy into electrical energy, enhancing its overall performance.

[0122] Finally, the present disclosure provides a method for preparing a back contact battery based on the above embodiment. In some embodiments, as Figure 13 As shown, the preparation method comprises:

[0123] S1. Providing a silicon substrate 1, wherein the back surface of the silicon substrate 1 includes a first region A, a second region B, and a spacer region C, and adjacent first region A and second region B are separated by the spacer region C;

[0124] S2. Forming a first carrier collection layer having a first conductivity type in the first region A and the spacer region C on the back side of the silicon substrate 1, and providing an isolation layer on the entire surface of the first carrier collection layer away from the silicon substrate 1; wherein the first carrier collection layer includes a first doped polysilicon layer 3-1 having a first crystallization rate, and the isolation layer includes a second doped polysilicon layer 4-1 having a second crystallization rate, where the second crystallization rate is less than the first crystallization rate;

[0125] S3, forming a second carrier collection layer having a second conductivity type on the entire back side of the silicon substrate 1, where the second conductivity type is opposite to the first conductivity type;

[0126] S4, removing the isolation layer and the portion of the second carrier collection layer located in the first area A.

[0127] Specifically, steps S1 to S4 are executed sequentially.

[0128] In step S1, Figure 2 As shown, the silicon substrate 1 includes a front surface and a back surface, and the back surface includes a first area A, a second area B, and a spacer area C. When multiple first areas A and multiple second areas B are provided, the first areas A and the second areas B are alternately provided, and adjacent first areas A and second areas B are separated by the spacer area C.

[0129] In step S2, a first carrier collection layer and an isolation layer are sequentially stacked on the back side of the silicon substrate 1. For example, the first carrier collection layer may include a tunneling layer 2 and a first doped polysilicon layer 3-1, and the isolation layer may include a second doped polysilicon layer 4-1 and an insulating layer 5. Thus, the tunneling layer 2, the first doped polysilicon layer 3-1, the second doped polysilicon layer 4-1 and the insulating layer 5 are sequentially stacked on the first region A and the isolation region C on the back side of the silicon substrate 1 to form Figure 5 In step S2, a laser process is performed to remove the first carrier collection layer and the isolation layer of the second region B.

[0130] In step S3, a second carrier collection layer is formed on the entire back side of the silicon substrate 1. For example, the second carrier collection layer includes an intrinsic silicon-containing layer 6 having a third crystallization rate and a doped silicon-containing layer 7 having a fourth crystallization rate. It can be understood that the intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 both cover the second region B on the back side of the silicon substrate 1 and the isolation layer located in the first region A and the isolation region C, forming Figure 6 The structure shown.

[0131] In step S4, the isolation layer and the second carrier collection layer located in the first area A can be removed by etching and cleaning or nanosecond, picosecond ultraviolet or green laser, for example, the doped silicon-containing layer 7, the intrinsic silicon-containing layer 6, the insulating layer 5 and the second doped polysilicon layer 4-1 located in the first area A are removed, and the silicon substrate 1 is cleaned to form Figure 9 The structure shown. Retaining a second doped polysilicon layer 4-1 in the spacer region C can enhance the insulation effect of the spacer region C as an isolation region. For example, the isolation layer may further include an insulating layer 5 to further enhance the insulation effect. This significantly reduces leakage, improves the battery's open circuit voltage, fill factor, and conversion efficiency, and enhances process stability. In step S4, if secondary laser processing is involved, the second carrier collection layer and isolation layer in the first region A are removed.

[0132] The fabrication method of this embodiment provides a second doped polysilicon layer 4-1 with a second crystallinity lower than the first crystallinity within the isolation layer. During the battery fabrication process, when removing excess film layers through primary and secondary laser processes, the low-crystallization-ratio polysilicon layer is covered. Due to its strong light absorption, which is higher than that of the first doped polysilicon layer 3-1 (pre-doped polysilicon layer 3 before the doping concentration is increased), this layer serves as a sacrificial layer during the primary laser process and a protective layer during the secondary laser process. This reduces the power of the laser ablation process and minimizes damage to the first doped polysilicon layer 3-1 (or pre-doped polysilicon layer 3) and the silicon substrate 1 during the laser ablation process. This improves the battery's efficiency in converting light energy into electrical energy, minimizes the impact of damage on the subsequent passivation layer's passivation performance, and enhances the battery's passivation effectiveness. Consequently, the battery exhibits superior electrical performance.

[0133] Moreover, since the power parameters of the laser inevitably fluctuate greatly during the processing, when the power parameters are high, it can prevent the first doped polysilicon layer 3-1 (or pre-doped polysilicon layer 3) and the silicon substrate 1 from causing greater damage. When the power parameters are low, the polysilicon layer with a low crystallization rate has a strong light absorption ability, which can also meet the removal requirements of the film layer. This can broaden the process window of laser film opening, reduce the strictness of the control of laser processing parameters, thereby reducing the processing difficulty and thus reducing production costs.

[0134] In some embodiments, the first carrier collection layer further includes a tunneling layer 2, S2 comprising:

[0135] S21, sequentially disposing a tunneling layer 2, a pre-doped polysilicon layer 3, and an isolation layer precursor on the entire back surface of the silicon substrate 1, wherein the isolation layer precursor includes an intrinsic polysilicon layer 4 having a fifth crystallization ratio, wherein the fifth crystallization ratio is less than the second crystallization ratio;

[0136] S22, removing the isolation layer precursor and a partial thickness of the pre-doped polysilicon layer 3 in the second region B by laser;

[0137] S23, annealing the silicon substrate 1 after laser stripping to activate the doping elements in the pre-doped polysilicon layer 3 to form a first doped polysilicon layer 3-1, and the intrinsic polysilicon layer 4 to become a second doped polysilicon layer 4-1, so that the isolation layer precursor becomes an isolation layer.

[0138] Among them, steps S21 to S23 are executed sequentially.

[0139] In S21, the doping concentration of the pre-doped polysilicon layer 3 is lower than that of the first doped polysilicon layer 3-1, the isolation layer precursor includes an intrinsic polysilicon layer 4, and further includes an insulating layer 5, the intrinsic polysilicon layer 4 is undoped, and the isolation layer 4 is formed. Figure 3 For example, the tunneling layer 2, pre-doped polysilicon layer 3, intrinsic polysilicon layer 4, and insulating layer 5 can be sequentially formed on the back side of the silicon substrate 1, for example, using a plate-type or tube-type radio frequency (RF) or very high frequency (VHF) plasma-enhanced chemical vapor deposition (PECVD) device. The pre-doped polysilicon layer 3 can be formed by in-situ doping.

[0140] In S22, the insulating layer 5, the intrinsic polysilicon layer 4 and a portion of the pre-doped polysilicon layer 3 of the second region B are removed by a laser. Figure 4 The structure shown, but the structure formed by S22 is the same as Figure 4 There are still differences in the layer structure materials.

[0141] In S23, the silicon substrate 1, after undergoing a single laser stripping operation in S22, is directly subjected to a high-temperature annealing process at a temperature of 600-1000°C. This annealing process activates the doping elements in the pre-doped polysilicon layer 3 to form a first doped polysilicon layer 3-1, effectively doping it. Furthermore, the doping elements near the surface of the first doped polysilicon layer 3-1 enter the intrinsic polysilicon layer 4, transforming it into a second doped polysilicon layer 4-1, shifting from undoped to a second, lower doping concentration. After annealing, the crystallization rate of the intrinsic polysilicon layer 4 increases, but its crystalline composition remains primarily microcrystals, and its resistance remains higher than that of the doped polysilicon layer 3-1. At this point, the isolation layer precursor becomes the isolation layer. Furthermore, the high-temperature annealing process repairs damage to the silicon substrate 1 and the passivation film caused by the laser stripping process.

[0142] For example, the fifth crystallization rate of the intrinsic polysilicon layer 4 can be 10%~60%, which is a relatively low crystallization rate. After annealing, the second crystallization rate of the intrinsic polysilicon layer 4 is increased to 90%~95%, but at this time the second crystallization rate of the second doped polysilicon layer 4-1 is still lower than the first crystallization rate of the first doped polysilicon layer 3-1, and the first crystallization rate is 95%~100%.

[0143] In step S22 of this embodiment, when the isolation layer precursor and pre-doped polysilicon layer 3 are removed by a single laser, the low-crystallization-rate intrinsic polysilicon layer 4 has strong light absorption and low transmittance. Its light absorption performance is higher than that of the pre-doped polysilicon layer 3, and it can serve as a sacrificial layer, reducing the power of the laser opening and reducing damage to the pre-doped polysilicon layer 3 and the silicon substrate 1 during the laser opening. This reduces the impact of damage on the passivation performance of the subsequent passivation layer, improves the passivation effect of the battery, and thus improves the efficiency of the battery in converting light energy into electrical energy. Moreover, when the isolation layer, the intrinsic silicon-containing layer 6, and the doped silicon-containing layer 7 located in the first area A are removed by a secondary laser in step S4, the second doped polysilicon layer 4-1 with a low crystallization rate can serve as a protective layer for the doped polysilicon layer 3-1, reducing laser damage to the first doped polysilicon layer 3-1 and minimizing the negative impact of laser opening on passivation.

[0144] Moreover, because the power parameters of the laser will inevitably fluctuate greatly during the processing, when the power parameters are high, it can prevent major damage to the pre-doped polysilicon layer 3 and the silicon substrate 1. When the power parameters are low, the intrinsic polysilicon layer 4 with a low crystallization rate has a strong light absorption ability, which can also meet the removal requirements of the film layer. This can broaden the process window of laser film opening, reduce the strictness of control over laser processing parameters, thereby reducing processing difficulty and thus reducing production costs.

[0145] In addition, since the damage to the silicon substrate 1 is relatively small, when the layer structure on the surface of the second area B is subsequently removed to expose the surface of the silicon substrate 1, there is no need to remove a thicker damaged layer to repair the laser damage, thereby reducing the height difference between the first area A and the second area B. During passivation, a good passivation effect can be obtained at the transition connection between the first area A and the second area B, for example, reducing defects in the connection section, uniform coverage of the passivation layer, reducing stress concentration, etc., thereby improving the overall passivation effect and improving the battery operating efficiency.

[0146] Furthermore, in step S23, the process sequence of performing a high-temperature annealing treatment directly after a single laser selective film opening can repair the laser damage inflicted on the film layers and the silicon substrate 1 in the previous process through high-temperature annealing, thereby minimizing and repairing the laser damage, improving the passivation effect, and increasing cell efficiency. Furthermore, repairing the damage inflicted on the silicon substrate 1 through annealing can reduce the height difference between the first region A and the second region B in the subsequent cleaning step, thereby enhancing the passivation effect and reducing recombination. Specifically, it reduces the ineffective consumption of photocarriers (electrons and holes) at the connection interface after they are generated, thereby improving cell efficiency.

[0147] In step 21, the tunneling layer 2, the pre-doped polysilicon layer 3 and the intrinsic polysilicon layer 4 with the fifth crystallinity can be formed only on the back side of the silicon substrate 1. Then, in step 23, high temperature annealing is directly performed after the laser opening, and oxygen is introduced during the annealing to form a silicon oxide layer on the surface of the intrinsic polysilicon layer 4. The silicon oxide layer is used as the insulating layer 5, and there is no need to Figure 3 When depositing the pre-doped polysilicon layer 3 , an additional insulating layer 5 is deposited, thereby reducing the number of process steps.

[0148] In the prior art, annealing is generally performed only after all process steps are completed, that is, after two electrodes are set. This annealing process is low-temperature annealing, and its purpose is to solidify the electrodes, not to achieve the above-mentioned effect.

[0149] Moreover, after high-temperature annealing, a second doped polysilicon layer 4-1 is provided on the doped polysilicon layer 3-1. On the one hand, the resistivity of the second doped polysilicon layer 4-1 is higher than that of the first doped polysilicon layer 3-1, which can enhance isolation and reduce leakage. This can not only significantly reduce leakage, improve the open circuit voltage, fill factor and conversion efficiency of the battery, but also improve the stability of the process.

[0150] In some embodiments, the deposition temperature of the intrinsic polysilicon layer 4 is lower than the deposition temperature of the pre-doped polysilicon layer 3 .

[0151] The deposition temperature of the intrinsic polysilicon layer 4 is low and it has not been annealed at this time. It has low transmittance and strong light absorption ability, so it can be used as a sacrificial layer when the laser removes the film layer, reducing the power of the laser film opening, widening the laser process window, reducing processing costs, and reducing the damage of the laser to the underlying pre-doped polysilicon layer 3 and silicon substrate 1, reducing the impact of damage on the passivation performance of the subsequent passivation layer, improving the passivation effect of the battery, and thus improving the efficiency of the battery in converting light energy into electrical energy.

[0152] In some embodiments, the second carrier collection layer includes an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7, and S3 includes:

[0153] S31, cleaning the back surface of the silicon substrate 1 so that the second area B of the silicon substrate 1 is exposed, and texturing the back surface of the silicon substrate 1 in the second area B to form a texturing surface;

[0154] S32 , forming an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 in sequence on the back side of the silicon substrate 1 , wherein the intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 cover the second region B and extend to cover the isolation layer.

[0155] Among them, S31 is executed after S23. In S31, more specifically, the front and back sides of the silicon substrate 1 can be simultaneously subjected to alkaline solution cleaning, polishing, cleaning, texturing and cleaning steps, so that the second area B on the front and back sides of the silicon substrate 1 is exposed to the silicon substrate 1 and a texturing surface is formed to form. Figure 5 The structure shown.

[0156] S32 is executed after S31. In S32, a plate-type radio frequency (RF) or very high frequency (VHF) plasma-enhanced chemical vapor deposition (PECVD) device is used to sequentially form an intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 on the back side of the silicon substrate 1. The intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 cover the second area B and extend to the isolation layer covering the first area A and the isolation area C, forming Figure 6 The structure shown.

[0157] In this embodiment, the isolation layer and a portion of the pre-doped polysilicon layer 3 of the second region B are first removed by S22. After annealing, an oxide layer is formed on the surface. Then, the oxide layer, the remaining thickness of the doped polysilicon layer 3-1, and the tunneling layer 2 are removed by wet etching and cleaning with an alkaline solution to expose the silicon substrate 1. This not only minimizes the damage to the silicon substrate 1 caused by the laser, but also achieves a smaller amount of removal on the surface of the silicon substrate 1. Moreover, due to the effect of the intrinsic polysilicon layer 4 with a low crystallization rate, the damage to the silicon substrate 1 is relatively small, so the battery performance can still be guaranteed. If the surface of the silicon substrate 1 is directly removed by laser, an additional step of removing the oxide layer is still required because annealing will produce an oxide layer on the exposed silicon substrate surface.

[0158] In some embodiments, the height difference between the first region A and the second region B of the back surface of the silicon substrate 1 is in the range of 3-10 um.

[0159] This embodiment removes excess film layers from the second region B by laser and cleaning, and can set the height difference between the first region A and the second region B within a smaller range. During passivation, a good passivation effect can be obtained at the transition connection between the first region A and the second region B, for example, reducing connection interface defects, ensuring uniform coverage of the passivation layer, reducing stress concentration, etc., thereby improving the overall passivation effect and improving battery operating efficiency.

[0160] In some embodiments, the preparation method of the present disclosure further includes:

[0161] S5 . Form a passivation layer 8 and / or an anti-reflection layer 9 on the front surface of the silicon substrate 1 .

[0162] Among them, S5 is executed after S32, and further, S5 can be executed before S4. Specifically, a passivation layer 8 is first formed on the front surface of the silicon substrate 1 after the texture is formed, and a passivation layer 8 is formed. Figure 7 The structure shown in FIG. 1 is further formed on the passivation layer 8 to form an anti-reflection layer 9. Figure 8 The structure shown.

[0163] In this embodiment, the passivation layer 8 can be an intrinsic silicon-containing layer or a doped silicon-containing layer, or a stack of layers, wherein the conductivity type of the doped silicon-containing layer is the same as the conductivity type of the silicon substrate 1. In step S32, while forming the intrinsic silicon-containing layer 6 on the back side of the silicon substrate 1, an intrinsic silicon-containing layer can also be formed on the front side of the silicon substrate 1 as a passivation layer.

[0164] For example, using tube-type or plate-type plasma-enhanced chemical vapor deposition (PECVD), spin coating, spray coating, or other equipment, an antireflection layer 9 is grown on the surface of the silicon substrate passivation layer 8 using a low-temperature growth method. The antireflection layer 9 has a thickness of 50 to 200 nm. The antireflection layer 9 comprises one or more of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, or magnesium fluoride, and preferably includes a carbon- or silicon quantum dot-encapsulated ultraviolet light-conversion layer. The ultraviolet light-conversion layer can be disposed in the middle, top, or bottom portion of the antireflection layer 9.

[0165] In this embodiment, the passivation layer 8 or the anti-reflection layer 9 can improve the passivation performance of the battery, thereby reducing or avoiding the impact of defects generated during the preparation process of the battery.

[0166] In some embodiments, the preparation method further comprises:

[0167] S6, forming a conductive layer 10 on the back side of the silicon substrate 1;

[0168] S7 . An isolation trench 11 is formed in the spacer region C on the conductive layer 10 . The isolation trench 11 at least penetrates the conductive layer 10 , and its depth does not exceed the surface of the isolation layer away from the silicon substrate 1 .

[0169] Among them, S6 is sequentially performed after S4, and the conductive layer 10 covers the first area A, the second area B and the isolation area C, forming Figure 10 For example, the conductive layer 10 can be formed on the back of the silicon substrate 1 by using equipment such as physical vapor deposition, reactive plasma deposition, magnetron sputtering, etc. The order of S6 and S5 can be interchanged.

[0170] S7 is performed after S6 to form an isolation trench 11 in the isolation region C. The area where the isolation trench 11 is located is the first isolation region C1, and the area outside the isolation trench 11 is the second isolation region C2. For example, nanosecond or picosecond ultraviolet or green laser selective film opening or mask etching can be used to form grooves to insulate the first region A from the second region B.

[0171] This embodiment provides an isolation groove 11, the depth of which at least penetrates the conductive layer 10, thereby completely cutting off the metal conductive path between the first carrier collection layer and the second carrier collection layer, thereby preventing the first electrode 12 and the second electrode 13 from short-circuiting. Moreover, the isolation groove 11 does not exceed the distance between the isolation layer and the surface of the silicon substrate 1, that is, it does not exceed the distance between the insulating layer and the surface of the silicon substrate 1, does not touch the isolation layer, and does not affect the insulation properties of the isolation layer.

[0172] In some embodiments, the preparation method of the present disclosure further includes:

[0173] S8. Dispose a first electrode 12 and a second electrode 13 on the conductive layer 10 at positions corresponding to the first area A and the second area B, respectively.

[0174] Wherein, S8 is performed after S7, the first electrode 12 and the second electrode 13 can be made of metal materials, and the method of forming the first electrode 12 and the second electrode 13 is at least one of screen printing, electroplating or transfer printing, forming Figure 12 The structure shown.

[0175] Some specific examples of the battery preparation method disclosed herein are given below.

[0176] (1) Provide Figure 2 The silicon substrate 1 shown has a back surface including a first region A, a second region B and a spacer region C. The adjacent first region A and second region B are separated by the spacer region C.

[0177] (2) The silicon substrate 1 is polished to remove the cutting damage layer, and a polished structure is formed on the front and back sides of the silicon substrate 1.

[0178] (3) A tunneling layer 2, a pre-doped polysilicon layer 3, an intrinsic polysilicon layer 4 and an insulating layer 5 are sequentially formed on the entire back side of the silicon substrate 1 to form Figure 3 The structure shown.

[0179] The deposition temperature of the intrinsic polysilicon layer 4 is lower than that of the pre-doped polysilicon layer 3. For example, the thickness of the tunneling layer 2 is 0.5 nm to 3.0 nm, preferably 1.0 nm to 1.5 nm; the thickness of the pre-doped polysilicon layer 3 and the intrinsic polysilicon layer 4 is 50 nm to 300 nm, preferably 50 nm to 150 nm; and the thickness of the insulating layer 5 is 20 nm to 100 nm, preferably 40 nm to 60 nm.

[0180] (4) The intrinsic polysilicon layer 4, the insulating layer 5 and a part of the thickness of the pre-doped polysilicon layer 3 of the second region B are removed by a single laser. Then, the silicon substrate 1 with the thickness of the single laser opening is subjected to high temperature annealing. On the one hand, the doping elements in the pre-doped polysilicon layer 3 are activated to form a first doped polysilicon layer 3-1, and the intrinsic polysilicon layer 4 is changed into a second doped polysilicon layer 4-1, changing from undoped to the second doping concentration, to form Figure 4 The structure shown; on the other hand, the damage caused by laser opening to the silicon substrate 1 and the passivation film layer can be repaired by high temperature annealing.

[0181] (5) At the same time, the front and back sides of the silicon substrate 1 are cleaned with an alkaline solution and the second area B on the front and back sides of the silicon substrate 1 is exposed to the silicon substrate 1 and a textured surface is formed. Figure 5 The structure shown.

[0182] (6) An intrinsic silicon-containing layer 6 and a doped silicon-containing layer 7 are sequentially formed on the back of the silicon substrate 1. The intrinsic silicon-containing layer 6 and the doped silicon-containing layer 7 cover the second region B and extend to the isolation layer covering the first region A and the isolation region C, forming Figure 6 The structure shown.

[0183] (7) A passivation layer 8 is formed on the front surface of the silicon substrate 1 after the texture is formed. Figure 7 The structure shown.

[0184] (8) An anti-reflection layer 9 is formed on the passivation layer 8 to form Figure 8 The structure shown.

[0185] (9) The doped silicon-containing layer 7, the intrinsic silicon-containing layer 6, the insulating layer 5 and the second doped polysilicon layer 4-1 located in the first area A are removed by etching slurry cleaning or nanosecond, picosecond ultraviolet or green laser, and the silicon substrate 1 is cleaned. The cleaning here is to achieve the purpose of cleaning, on the one hand, to wash away the etching slurry, and on the other hand, to wash away the powder formed during the laser film opening, forming Figure 9 The structure shown.

[0186] (10) A conductive layer 10 is formed on the back of the silicon substrate 1. The conductive layer 10 covers the first region A, the second region B and the isolation region C, forming Figure 10 The structure shown.

[0187] (11) An isolation trench 11 is formed in the isolation region C. The region where the isolation trench 11 is formed is the first isolation region C1, and the region outside the isolation trench 11 is the second isolation region C2. For example, nanosecond or picosecond ultraviolet or green laser selective film opening or mask etching can be used to form a trench to insulate the first region A from the second region B.

[0188] (12) A first electrode 12 and a second electrode 13 are respectively provided in the first area A and the second area B on the back of the silicon substrate 1 to form Figure 12 The structure shown.

[0189] While the present disclosure has been described with reference to preferred embodiments, various modifications may be made thereto and equivalent components may be substituted without departing from the scope of the present disclosure. In particular, the various technical features described in the various embodiments may be combined in any manner, provided no structural conflicts exist. The present disclosure is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A back contact battery, characterized in that: include: A silicon substrate (1), the back side of which comprises a first region (A), a second region (B) and a spacer region (C), wherein adjacent first region (A) and second region (B) are separated by the spacer region (C); a first carrier collection layer having a first conductivity type, the first carrier collection layer being arranged on the back side of the silicon substrate (1) and located in the first region (A) and the spacer region (C), the first carrier collection layer comprising a first doped polysilicon layer (3-1) having a first crystallization rate; an isolation layer located in the spacer region (C) and provided on a surface of the first carrier collection layer away from the silicon substrate (1), the isolation layer comprising a second doped polysilicon layer (4-1) having a second crystallization rate, the second crystallization rate being less than the first crystallization rate; and The second carrier collection layer has a second conductivity type opposite to the first conductivity type, and the second carrier collection layer is arranged on the back side of the silicon substrate (1) and is located in the second region (B) and extends to cover the isolation layer.

2. The back contact battery according to claim 1, characterized in that The first carrier collection layer further comprises a tunneling layer (2), the tunneling layer (2) being arranged on the back side of the silicon substrate (1) and being located between the first region (A) and the spacer region (C), the first doped polysilicon layer (3-1) being arranged on a surface of the tunneling layer (2) away from the silicon substrate (1), and the second doped polysilicon layer (4-1) being arranged on a surface of the first doped polysilicon layer (3-1) away from the silicon substrate (1).

3. The back contact battery according to claim 2, characterized in that The second doped polysilicon layer (4-1) has the same doping element as the first doped polysilicon layer (3-1), the first doped polysilicon layer (3-1) has a first doping concentration, and the second doped polysilicon layer (4-1) has a second doping concentration, which is less than the first doping concentration.

4. The back contact battery according to claim 3, wherein The first doping concentration is 1×10 19 ~1×10 21 cm -3 , preferably 1×10 20 ~1×10 21 cm -3 and / or The second doping concentration is 1×10 19 ~1×10 20 cm -3 and / or The difference between the first doping concentration and the second doping concentration is in the range of 9×10 19 ~9×10 20 cm -3 .

5. The back contact cell according to claim 2, wherein The thickness of the tunneling layer (2) ranges from 0.5 nm to 3.0 nm, preferably from 1.0 nm to 1.5 nm; and / or The thickness of the first doped polysilicon layer (3-1) and the second doped polysilicon layer (4-1) ranges from 50 nm to 300 nm, preferably from 50 nm to 150 nm.

6. The back contact cell according to claim 1, wherein The second carrier collection layer comprises: an intrinsic silicon-containing layer (6) having a third crystallinity, disposed on the back side of the silicon substrate (1) and located in the second region (B); and a doped silicon-containing layer (7) having a fourth crystallization rate, provided on a surface of the intrinsic silicon-containing layer (6) away from the silicon substrate (1), the fourth crystallization rate being greater than the third crystallization rate and less than the second crystallization rate; Wherein, the intrinsic silicon-containing layer (6) and the doped silicon-containing layer (7) both extend to cover the isolation layer.

7. The back contact battery according to claim 6, characterized in that The thickness of the intrinsic silicon-containing layer (6) is in the range of 10 nm to 50 nm; and / or The thickness of the doped silicon-containing layer (7) ranges from 10 nm to 100 nm.

8. The back contact battery according to any one of claims 1 to 7, characterized in that The isolation layer further comprises an insulating layer (5), wherein the insulating layer (5) is located in the spacer region (C) and is provided between the second doped polysilicon layer (4-1) and the second carrier collection layer.

9. The back contact battery according to claim 8, characterized in that The insulating layer (5) is at least one of silicon oxide, silicon nitride, silicon oxynitride or silicon carbide, and the thickness of the insulating layer (5) ranges from 20 nm to 100 nm, preferably from 40 nm to 60 nm.

10. The back contact battery according to any one of claims 1 to 7, characterized in that: It also includes a conductive layer (10), wherein the conductive layer (10) covers the second carrier collection layer and the first carrier collection layer located in the first area (A); The conductive layer (10) is provided with an isolation groove (11) in the spacer region (C); the isolation groove (11) at least penetrates the conductive layer (10) and has a depth not exceeding the surface of the isolation layer away from the silicon substrate (1).

11. The back contact battery according to any one of claims 1 to 7, characterized in that: The first conductivity type is the same as the conductivity type of the silicon substrate (1).

12. The back contact battery according to any one of claims 1 to 7, characterized in that: It also includes a passivation layer (8) and / or an anti-reflection layer (9) provided on the front side of the silicon substrate (1).

13. A photovoltaic module, characterized in that: A back contact battery comprising the back contact battery according to any one of claims 1 to 12.

14. A method for preparing a back contact battery, characterized in that: include: S1. Providing a silicon substrate (1), wherein the back surface of the silicon substrate (1) comprises a first region (A), a second region (B), and a spacer region (C), and adjacent first regions (A) and second regions (B) are separated by the spacer region (C); S2, forming a first carrier collection layer having a first conductivity type in the first region (A) and the spacer region (C) on the back side of the silicon substrate (1), and providing an isolation layer on the entire surface of the first carrier collection layer away from the silicon substrate (1); wherein the first carrier collection layer includes a first doped polysilicon layer (3-1) having a first crystallization rate, and the isolation layer includes a second doped polysilicon layer (4-1) having a second crystallization rate, and the second crystallization rate is less than the first crystallization rate; S3, forming a second carrier collection layer having a second conductivity type on the entire back side of the silicon substrate (1), wherein the second conductivity type is opposite to the first conductivity type; S4. Remove the isolation layer and the portion of the second carrier collection layer located in the first area (A).

15. The preparation method according to claim 14, characterized in that The first carrier collection layer further includes a tunneling layer (2), and the S2 includes: S21, sequentially arranging the tunneling layer (2), the pre-doped polysilicon layer (3), and the isolation layer precursor on the entire back surface of the silicon substrate (1), wherein the isolation layer precursor comprises an intrinsic polysilicon layer (4) having a fifth crystallization ratio, the fifth crystallization ratio being less than the second crystallization ratio; S22, removing the isolation layer precursor and a portion of the pre-doped polysilicon layer (3) in the second region (B) by laser; S23, annealing the silicon substrate (1) after laser stripping, activating the doping elements in the pre-doped polysilicon layer (3) to form the first doped polysilicon layer (3-1), and the intrinsic polysilicon layer (4) becomes the second doped polysilicon layer (4-1), so that the isolation layer precursor becomes the isolation layer.

16. The preparation method according to claim 15, characterized in that The deposition temperature of the intrinsic polysilicon layer (4) is lower than the deposition temperature of the pre-doped polysilicon layer (3).

17. The preparation method according to claim 15, characterized in that The second carrier collection layer comprises an intrinsic silicon-containing layer (6) and a doped silicon-containing layer (7), and S3 comprises: S31, cleaning the back side of the silicon substrate (1) so that the second area (B) is exposed from the silicon substrate (1), and texturing the back side of the silicon substrate (1) in the second area (B) to form a texturing surface; S32. The intrinsic silicon-containing layer (6) and the doped silicon-containing layer (7) are sequentially formed on the back side of the silicon substrate (1), wherein the intrinsic silicon-containing layer (6) and the doped silicon-containing layer (7) cover the second region (B) and extend to cover the isolation layer.

18. The preparation method according to claim 17, characterized in that: The height difference between the first area (A) and the second area (B) on the back side of the silicon substrate (1) ranges from 3 to 10 μm.

19. The preparation method according to any one of claims 14 to 18, characterized in that: Also includes: S5. Forming a passivation layer (8) and / or an anti-reflection layer (9) on the front surface of the silicon substrate (1).

20. The preparation method according to any one of claims 14 to 18, characterized in that Also includes: S6, forming a conductive layer (10) on the back side of the silicon substrate (1); S7. An isolation groove (11) is formed in the spacer region (C) on the conductive layer (10), wherein the isolation groove (11) at least penetrates the conductive layer (10) and has a depth not exceeding the distance from the isolation layer to the surface of the silicon substrate (1).

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