Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device and a manufacturing method of the electronic device. The electronic device includes an element array substrate, a plurality of bumps, and a scintillator layer. The element array substrate comprises a plurality of photosensitive elements. The plurality of bumps are disposed on the plurality of photosensitive elements and are separated from each other. The scintillator layer is disposed on the plurality of bumps, the scintillator layer has a first portion overlapping the plurality of bumps and a second portion not overlapping the plurality of bumps, and a side of the second portion adjacent to the element array substrate is looser than a side of the second portion away from the element array substrate.

Description

Technical Field

[0001] The present invention relates to an electronic device and a manufacturing method thereof, and in particular to an electronic device with a scintillator layer and a manufacturing method thereof. Background Art

[0002] As electronic devices become increasingly mature, further improving the performance of electronic devices (eg, improving the spatial resolution or sensitivity of imaging) has become one of the current research and development focuses. Summary of the Invention

[0003] The present invention provides an electronic device and a manufacturing method thereof, which are helpful to improve the spatial resolution or sensitivity of imaging.

[0004] According to an embodiment of the present invention, an electronic device includes an element array substrate, a plurality of bumps, and a scintillator layer. The element array substrate includes a plurality of photosensitive elements. The plurality of bumps are disposed on the plurality of photosensitive elements and are separated from each other. The scintillator layer is disposed on the plurality of bumps, wherein the scintillator layer has a first portion overlapping with the plurality of bumps and a second portion not overlapping with the plurality of bumps, and a side of the second portion adjacent to the element array substrate is looser than a side of the second portion distal to the element array substrate.

[0005] According to an embodiment of the present invention, a method for manufacturing an electronic device includes: providing an element array substrate, wherein the element array substrate includes a plurality of photosensitive elements; forming a plurality of bumps on the element array substrate, wherein the plurality of bumps are arranged on the plurality of photosensitive elements and are separated from each other; and forming a scintillator layer on the plurality of bumps, wherein the scintillator layer has a first portion overlapping with the plurality of bumps and a second portion not overlapping with the plurality of bumps, and a side of the second portion adjacent to the element array substrate is looser than a side of the second portion away from the element array substrate.

[0006] To make the above features and advantages of the present disclosure more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 is a partial top view of an electronic device according to one embodiment of the present disclosure;

[0009] Figure 2 It corresponds to Figure 1 Schematic cross-section of the median section line I-I';

[0010] Figure 3 It corresponds to Figure 2 A schematic cross-sectional view of an electronic device irradiated by X-rays;

[0011] Figure 4 is a schematic flow chart of a method for manufacturing an electronic device according to one embodiment of the present disclosure;

[0012] Figure 5 is a simplified schematic diagram of the steps for forming a scintillator layer;

[0013] Figure 6 yes Figure 5 A partial enlarged schematic diagram;

[0014] Figure 7 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0015] Explanation of Figure Numbers

[0016] 1. 1A: electronic device;

[0017] 5: Evaporation source;

[0018] 10: Component array substrate;

[0019] 12, 12A: bump;

[0020] 14: scintillator layer;

[0021] 100: photosensitive element;

[0022] 102: active components;

[0023] 140: needle-like structure;

[0024] 400, 402, 404: steps;

[0025] AR: arrowhead;

[0026] BE: lower electrode;

[0027] BL: bias line;

[0028] C1, C2, C3: conductive layers;

[0029] CH: semiconductor pattern;

[0030] D1, D2, D3: direction;

[0031] DE: drain;

[0032] DL: data line;

[0033] G: gap;

[0034] GE: gate;

[0035] GL: gate line;

[0036] IN1, IN2, IN3, IN4: dielectric layer;

[0037] IT1, IT2: spacing;

[0038] L1: X-ray;

[0039] L2: visible light;

[0040] N5, N10: normal;

[0041] P1: Part I;

[0042] P2: Part II;

[0043] PC: photosensitive structure;

[0044] S1: first surface;

[0045] S2: second surface;

[0046] S3: third surface;

[0047] S4: fourth surface;

[0048] SCL: semiconductor layer;

[0049] SE: source;

[0050] SUB: substrate;

[0051] T12: thickness;

[0052] TE: upper electrode;

[0053] TH1: through hole;

[0054] TH2: open hole;

[0055] U: scintillator unit;

[0056] W1, W2, W3, W4: width;

[0057] I-I': section line;

[0058] θ: angle. DETAILED DESCRIPTION

[0059] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0060] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, the words "including" and "comprising" are open-ended and should be interpreted as meaning "including, but not limited to..."

[0061] Directional terms used herein, such as "up," "down," "front," "back," "left," "right," etc., are used only with reference to the directions in the accompanying drawings. Therefore, the directional terms used are intended to illustrate, not to limit, this disclosure. In the accompanying drawings, each figure illustrates the general characteristics of the methods, structures, and / or materials used in particular embodiments. However, these figures should not be construed as defining or limiting the scope or nature of the embodiments. For example, the relative sizes, thicknesses, and positions of various layers, regions, and / or structures may be reduced or exaggerated for clarity.

[0062] A structure (or layer, element, substrate) described in the present disclosure is located on / above another structure (or layer, element, substrate), which may mean that the two structures are adjacent and directly connected, or it may mean that the two structures are adjacent but not directly connected. Indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate element, intermediate substrate, intermediate gap) between the two structures, and the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure. The intermediate structure can be composed of a single-layer or multi-layer physical structure or a non-physical structure, without limitation. In the present disclosure, when a certain structure is disposed "on" another structure, it may mean that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0063] The terms "approximately," "substantially," or "approximately" are generally interpreted as being within 10% of a given value or range, or within 5%, 3%, 2%, 1%, or 0.5% of a given value or range. In addition, the phrases "a range from a first value to a second value" and "a range between a first value and a second value" indicate that the range includes the first value, the second value, and other values ​​therebetween.

[0064] The use of ordinal numbers such as "first" and "second" in the specification and claims to modify an element does not, by itself, imply or indicate any prior ordinal number of the element(s), nor does it indicate the order of one element relative to another, or the order of manufacturing methods. Such ordinal numbers are used solely to clearly distinguish one element from another with the same name. The claims and the specification may not use the same terminology; thus, the first element in the specification may be the second element in the claim.

[0065] In some embodiments of the present disclosure, terms related to joining and connecting, such as "connected" and "interconnected," unless otherwise specified, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with another structure disposed between the two structures. Furthermore, such terms related to joining and connecting may also include situations where both structures are movable or both structures are fixed. Furthermore, the term "coupled" includes any direct and indirect electrical connection means. Furthermore, the term "linked" includes any signal communication means whereby two elements or devices can directly or indirectly receive and / or transmit wireless signals.

[0066] The electrical connection or coupling described in this disclosure may refer to a direct connection or an indirect connection. In the case of a direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment. In the case of an indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited thereto.

[0067] In the present disclosure, the thickness, length and width can be measured using an optical microscope (OM), and the thickness or width can be measured from a cross-sectional image in an electron microscope, but the present disclosure is not limited thereto. In addition, any two values ​​or directions used for comparison may have a certain error. In addition, the terms "a given range is from a first value to a second value", "a given range falls within the range from a first value to a second value", or "a given range is between a first value and a second value" indicate that the given range includes the first value, the second value, and other values ​​therebetween. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0068] It should be noted that the following embodiments may be implemented by replacing, recombining, or combining features from several different embodiments to create other embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meanings as commonly understood by those skilled in the art in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of this disclosure.

[0070] In this document, the types and types of electronic devices are not limited. For example, the electronic device may include a display device, a backlight device, an antenna device, a detection device, a splicing device, or any device that requires charging. In addition, the electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The display device may, for example, include liquid crystal, a light-emitting diode, fluorescence, phosphor, quantum dot (QD), other suitable display media, or a combination of the foregoing. The antenna device may be a liquid crystal antenna device or a non-liquid crystal antenna device. The detection device may be a detection device that senses capacitance, light (such as visible light or X-rays), heat energy, or ultrasound, but is not limited thereto. In some embodiments, the electronic device may include electronic components. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light emitting diode may include, but is not limited to, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, or a quantum dot LED. The splicing device may be, but is not limited to, a display splicing device, a detection splicing device, or an antenna splicing device.

[0071] It should be noted that the electronic device may be any of the aforementioned arrangements and combinations, but is not limited thereto. Furthermore, the electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may include peripheral systems such as a drive system, a control system, and a light source system to support a display device, an antenna device, a wearable device (e.g., including augmented reality or virtual reality), an in-vehicle device (e.g., including a car windshield), or a splicing device.

[0072] Figure 1 is a partial top view of an electronic device according to an embodiment of the present disclosure. Figure 2 It corresponds to Figure 1 Schematic diagram of the cross section along the midline I-I'. Figure 1In order to clearly show the relative arrangement relationship between the multiple bumps and other components (such as multiple photosensitive components, multiple active components, multiple gate lines, multiple scan lines, and multiple bias lines), some film layers in the electronic device (such as scintillator layers and multiple dielectric layers, etc.) are omitted. For these omitted film layers, please refer to Figure 2 and its related instructions. In addition, for easy identification, Figure 1 The edges of the plurality of bumps are indicated by thick lines, and the shading of the plurality of bumps is omitted to clearly show the components located under the plurality of bumps.

[0073] Please refer to Figure 1 as well as Figure 2 The electronic device 1 may include an element array substrate 10, a plurality of bumps 12, and a scintillator layer 14. The element array substrate 10 may include a plurality of photosensitive elements 100. The plurality of bumps 12 are disposed on the plurality of photosensitive elements 100 and are separated from each other. The scintillator layer 14 is disposed on the plurality of bumps 12, wherein the scintillator layer 14 has a first portion P1 overlapping with the plurality of bumps 12 and a second portion P2 not overlapping with the plurality of bumps 12, and the second portion P2 is looser on a side adjacent to the element array substrate 10 (e.g., the lower side) than on a side of the second portion P2 away from the element array substrate 10 (e.g., the upper side).

[0074] Specifically, the plurality of bumps 12 and the scintillator layer 14 are sequentially arranged on the element array substrate 10 along the direction D3, for example. Figure 2 For example, the device array substrate 10 may include a substrate SUB, a conductive layer C1, a dielectric layer IN1, a semiconductor layer SCL, a conductive layer C2, a dielectric layer IN2, a dielectric layer IN3, a plurality of photosensitive elements 100, a dielectric layer IN4, and a conductive layer C3, but the present invention is not limited thereto. Depending on different needs, the device array substrate 10 may include one or more film layers.

[0075] The substrate SUB can be a rigid substrate or a flexible substrate. Materials for the substrate SUB include, but are not limited to, glass, quartz, ceramic, sapphire, or plastic. Plastics include, but are not limited to, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), other suitable flexible materials, or combinations thereof.

[0076] The conductive layer C1 is disposed on the substrate SUB. The material of the conductive layer C1 includes, for example, a transparent conductive material or an opaque conductive material. The transparent conductive material may include metal oxide, graphene, other suitable transparent conductive materials, or a combination thereof. The metal oxide may include indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other metal oxides. The opaque conductive material may include a metal, an alloy, or a combination thereof. The metal may be a single layer of metal or a metal stack, such as aluminum, molybdenum, or titanium / aluminum / titanium, but is not limited thereto. The conductive layer C1 may be a patterned conductive layer, and the conductive layer C1 may include a plurality of gates GE, a plurality of gate lines GL (refer to Figure 1 ) and other circuits (not shown), but are not limited to these.

[0077] like Figure 1 As shown, each gate GE is electrically connected to a corresponding gate line GL. For example, the plurality of gate lines GL extend along direction D1 and are arranged along direction D2. Directions D1 and D2 intersect with each other and are both perpendicular to the stacking direction (e.g., direction D3) of the device array substrate 10, the plurality of bumps 12, and the scintillator layer 14. In some embodiments, directions D1 and D2 are perpendicular to each other, but are not limited thereto.

[0078] Refer again Figure 2 The dielectric layer IN1 is disposed on the conductive layer C1 and the substrate SUB. The dielectric layer IN1 may be a single layer or multiple layers. The material of the dielectric layer IN1 includes, for example, an organic insulating material, an inorganic insulating material, or a combination thereof. Organic insulating materials include, but are not limited to, polymethyl methacrylate (PMMA), epoxy resin, acrylic resin, silicone, polyimide polymer, perfluoroalkoxy alkane resin (PFA), or a combination thereof. Inorganic insulating materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0079] A semiconductor layer SCL is disposed on the dielectric layer IN1. The material of the semiconductor layer SCL includes, but is not limited to, amorphous silicon, polysilicon, or a metal oxide such as indium gallium zinc oxide (IGZO). The semiconductor layer SCL may be a patterned semiconductor layer and may include a plurality of semiconductor patterns CH. The plurality of semiconductor patterns CH overlap with the plurality of gate electrodes GE in a direction D3.

[0080] A conductive layer C2 is disposed on the semiconductor layer SCL and the dielectric layer IN1. The material of the conductive layer C2 can refer to the material of the conductive layer C1 described above and will not be repeated here. The conductive layer C2 can be a patterned conductive layer and may include, but is not limited to, a plurality of source electrodes SE, a plurality of drain electrodes DE, a plurality of data lines DL, and other circuits (not shown).

[0081] like Figure 1 As shown, each source electrode SE can be electrically connected to a corresponding data line DL. In addition, each source electrode SE and a corresponding drain electrode DE can be located on opposite sides of a corresponding semiconductor pattern CH. For example, a plurality of data lines DL extend along a direction D2 and are arranged along a direction D1. In a top view, as shown in FIG. Figure 1 As shown, the plurality of data lines DL and the plurality of gate lines GL are interlaced with each other, and the plurality of data lines DL and the plurality of gate lines GL pass through the dielectric layer IN1 (see Figure 2 ) and are electrically insulated from each other. The device array substrate 10 may further include a plurality of active devices 102. Each active device 102 includes, for example, a gate GE, a semiconductor pattern CH, a source SE, and a drain DE, but is not limited thereto. Figure 1 as well as Figure 2 In the embodiment, a bottom-gate thin film transistor is used as an example of the active element 102. However, it should be understood that the type of the active element 102, the relative arrangement relationship and / or shape of the electrodes in the active element 102, etc. can be changed according to actual needs. Figure 1 as well as Figure 2 Shown are limited.

[0082] Refer again Figure 2 The dielectric layer IN2 is disposed on the conductive layer C2, the semiconductor layer SCL, and the dielectric layer IN1. The dielectric layer IN2 may be a single layer or multiple layers, and the material of the dielectric layer IN2 may refer to the material of the dielectric layer IN1, which will not be repeated here.

[0083] A dielectric layer IN3 is disposed on dielectric layer IN2. Dielectric layer IN3 can be used to provide a flat surface for supporting multiple photosensitive elements 100. The material of dielectric layer IN3 includes, but is not limited to, an organic insulating material. The details regarding organic insulating materials are described above and will not be repeated here.

[0084] A plurality of photosensitive elements 100 are disposed on the dielectric layer IN3. Figure 1 As shown, a plurality of photosensitive elements 100 can be arranged in an array in the direction D1 and the direction D2. Figure 2Each photosensitive element 100, for example, includes a lower electrode BE, a photosensitive structure PC, and an upper electrode TE, and the lower electrode BE, the photosensitive structure PC, and the upper electrode TE are, for example, stacked in sequence on the dielectric layer IN3. The lower electrode BE is, for example, electrically connected to a corresponding drain electrode DE via a through hole TH1 penetrating the dielectric layer IN3 and the dielectric layer IN2. The material of the lower electrode BE may, for example, include a transparent conductive material or an opaque conductive material. The material of the upper electrode TE may, for example, include a transparent conductive material, so that the light beam incident on the photosensitive element 100 can penetrate the upper electrode TE and be transmitted to the photosensitive structure PC. The material of the photosensitive structure PC includes, for example, silicon, germanium, indium gallium arsenide, lead sulfide, or other suitable semiconductor materials.

[0085] exist Figure 1 In the embodiment, the area of ​​the lower electrode BE is larger than the area of ​​the photosensitive structure PC and the area of ​​the upper electrode TE, and the area of ​​the photosensitive structure PC is equal to the area of ​​the upper electrode TE, but the present disclosure is not limited thereto. Alternatively, the area of ​​the lower electrode BE may be equal to the area of ​​the photosensitive structure PC and the area of ​​the upper electrode TE to facilitate manufacturing. Alternatively, the area of ​​the lower electrode BE, the area of ​​the photosensitive structure PC, and the area of ​​the upper electrode TE may be changed according to actual needs. In addition, in Figure 1 In the embodiment, the plurality of photosensitive elements 100 do not overlap with the plurality of gate lines GL, the plurality of data lines DL, and the plurality of active elements 102 in direction D3, but the present disclosure is not limited thereto. Alternatively, the plurality of photosensitive elements 100 may overlap with the plurality of gate lines GL, the plurality of data lines DL, and / or the plurality of active elements 102 in direction D3 to increase the area of ​​the photosensitive elements 100 and thereby improve conversion efficiency.

[0086] A dielectric layer IN4 is disposed on the plurality of photosensitive elements 100 and the dielectric layer IN2. The dielectric layer IN4 can provide a flat surface for supporting the conductive layer C3 and / or the plurality of bumps 12. The material of the dielectric layer IN4 may include, but is not limited to, an organic insulating material. The dielectric layer IN4 may include a plurality of openings TH2. Each opening TH2 exposes a portion of the top electrode TE of a corresponding photosensitive element 100.

[0087] Conductive layer C3 is disposed on dielectric layer IN4. The material of conductive layer C3 can refer to the material of conductive layer C1 described above and will not be repeated here. Conductive layer C3 can be a patterned conductive layer and may include, but is not limited to, a plurality of bias lines BL and other circuits (not shown).

[0088] Each bias line BL is electrically connected to a corresponding top electrode TE through a corresponding opening TH2, for example. Figure 1As shown, the bias lines BL extend along a direction D2 and are arranged along a direction D1. In addition, the bias lines BL and the data lines DL are alternately arranged along a direction D1.

[0089] It should be understood that Figure 2 The device array substrate 10 in FIG. 1 is merely an example and is not intended to limit the embodiment of the device array substrate 10 . For example, although not shown, the source electrode SE, the drain electrode DE, and / or the data line DL may include multiple conductive layers. In other embodiments, another conductive layer (not shown) may be provided between the second conductive layer C2 and the bottom electrode BE, and the conductive pattern or connecting line structure (not shown) in the other conductive layer that electrically connects the drain electrode DE to the bottom electrode BE may be considered part of the drain electrode DE. Similarly, the conductive pattern or connecting line structure (not shown) in the other conductive layer that is electrically connected to the source electrode SE may be considered part of the source electrode SE.

[0090] A plurality of bumps 12 are disposed on the conductive layer C3 and the dielectric layer IN4. The bumps 12 may be made of a transparent material having a light transmittance greater than 70%, such as, but not limited to, a transparent material having a light transmittance greater than 98% or 99%. For example, the bumps 12 may be made of a transparent organic polymer material such as, but not limited to, polymethyl methacrylate, epoxy resin, acrylic resin, silicone, polyimide polymer, perfluoroalkoxyalkane resin, positive-type photosensitive material, negative-type photosensitive material, or a combination thereof.

[0091] In some embodiments, the thickness T12 of the plurality of bumps 12 is, for example, greater than 0.5 μm and less than 30 μm. Figure 1 As shown, the plurality of bumps 12 and the plurality of photosensitive elements 100 may be arranged in a one-to-one relationship. In a top view, the area of ​​at least one of the plurality of bumps 12 may be larger or smaller than the area of ​​at least one of the plurality of photosensitive elements 100. Figure 1 For example, the areas of the plurality of bumps 12 are larger than the areas of the plurality of photosensitive elements 100, and each bump 12 covers, for example, a corresponding photosensitive element 100 and a corresponding active element 102, but the present invention is not limited thereto. In some embodiments, the area of ​​at least one of the plurality of bumps 12 may be 0.7 to 1.3 times the area of ​​at least one of the plurality of photosensitive elements 100.

[0092] In some embodiments, the pitch of the plurality of bumps 12 is, for example, greater than 1 μm. Figure 1 For example, the bumps 12 may have a pitch IT1 in direction D1, and the bumps 12 may have a pitch IT2 in direction D2. Both pitch IT1 and pitch IT2 may be, for example, greater than 1 μm. Pitch IT1 and pitch IT2 may be the same or different. In some embodiments, pitch IT1 is, for example, greater than pitch IT2, but this is not limiting.

[0093] The scintillator layer 14 is, for example, a columnar crystal scintillator layer. Figure 2 As shown, the scintillator layer 14 may have an optical fiber-like needle-like structure 140. The material of the scintillator layer 14 includes, for example, cesium iodide (CsI), cesium bromide (CsBr), cesium copper iodide (Cs3Cu2I5), other types of inorganic scintillator materials, or organic scintillator materials.

[0094] The plurality of bumps 12 can shield the material of the scintillator layer when forming the scintillator layer 14, so that the growth rate of the scintillator layer 14 on the plurality of bumps 12 is faster than the growth rate between two adjacent bumps 12, thereby changing the area density of the scintillator layer 14. Figure 2 As shown, the scintillator layer 14 may have a first portion P1 that overlaps with the plurality of bumps 12 and a second portion P2 that does not overlap with the plurality of bumps 12. The density of the first portion P1 is greater than that of the second portion P2. For example, the density difference between the first portion P1 and the second portion P2 may be greater than or equal to 2%. If the density of the first portion P1 is 100%, the density of the second portion P2 may be 98% or less.

[0095] Furthermore, the plurality of needle-like structures 140 of the scintillator layer 14 extend / grow upward from the plurality of bumps 12, wherein the spacing between the plurality of bumps 12 is greater than 1 μm (refer to Figure 1 The spacing IT1 and IT2 in the scintillator layer 140 result in a gap G between the bottoms of two adjacent needle-like structures 140 located on two adjacent bumps 12. As the needle-like structures 140 grow upward, the two adjacent needle-like structures 140 become closer and closer to each other, that is, the gap G gradually becomes smaller. The gap G, for example, divides the scintillator layer 14 into a plurality of scintillator units U. Figure 2 As shown, the scintillator layer 14 may include a plurality of scintillator units U (only one is shown), with a gap G between adjacent two of the plurality of scintillator units U. The gap G gradually decreases in the stacking direction (e.g., direction D3) of the device array substrate 10, the plurality of bumps 12, and the scintillator layer 14. Because the gap G is provided corresponding to the second portion P2 of the scintillator layer 14 and the gap G gradually decreases from bottom to top, the side of the second portion P2 adjacent to the device array substrate 10 (e.g., the lower side) is looser than the side of the second portion P2 away from the device array substrate 10 (e.g., the upper side).

[0096] In addition, one of the plurality of scintillator units U overlaps with a corresponding one of the bumps 12 and has a first surface S1 adjacent to the corresponding one of the bumps 12 and a second surface S2 away from the corresponding one of the bumps 12 (e.g., a virtual plane formed by a plurality of vertices of the plurality of needle-like structures 140), and in the cross-sectional view, as shown in FIG. Figure 2As shown, the width W2 of the second surface S2 is greater than the width W1 of the first surface S1. In addition, the corresponding one protrusion 12 has a third surface S3 adjacent to the scintillator unit U and a fourth surface S4 away from the scintillator unit U, wherein in the cross-sectional view, as shown Figure 2 As shown, the width W3 of the third surface S3 is less than or equal to the width W1 of the first surface S1, and the width W3 of the third surface S3 may be different from the width W4 of the fourth surface S4. For example, the width W3 may be less than the width W4, but is not limited thereto. In other embodiments, the width W3 may be greater than or equal to the width W4.

[0097] Figure 3 It corresponds to Figure 2 A cross-sectional diagram of an electronic device being irradiated by X-rays. Figure 3 When the electronic device 1 is irradiated by X-rays L1, the scintillator layer 14 in the electronic device 1 converts the X-rays L1 into visible light L2. Because the refractive index of the needle-like structures 140 in the scintillator layer 14 is greater than that of air, the visible light L2 is transmitted through the needle-like structures 140 toward the photosensitive element 100 via total internal reflection (TIR). The photosensitive element 100 receives the visible light L2 emitted from the needle-like structures 140 and generates an image corresponding to the light intensity distribution of the visible light L2.

[0098] By designing that the side of the second portion P2 of the scintillator layer 14 adjacent to the element array substrate 10 is looser than the side of the second portion P2 away from the element array substrate 10, the multiple needle-like structures 140 in the scintillator layer 14 are distributed more evenly and tightly on the side away from the multiple bumps 12 (the gap G is smaller), while the multiple needle-like structures 140 are concentrated on the multiple bumps 12 on the side adjacent to the multiple bumps 12, forming a plurality of inverted trapezoidal scintillator units U. The inverted trapezoidal scintillator units U help to increase the light-collecting area of ​​the scintillator layer 14. In addition, guiding the visible light L2 converted from the X-ray L1 to the corresponding photosensitive element 100 through total reflection helps to improve the sensitivity of imaging. In addition, since the multiple inverted trapezoidal scintillator units U are distributed more loosely on the side adjacent to the multiple bumps 12 (the gap G is larger), the light interference (such as X-talk) between the multiple scintillator units U can be reduced, which helps to improve the spatial resolution of imaging.

[0099] Figure 4 It is a schematic flow chart of a method for manufacturing an electronic device according to one embodiment of the present disclosure. Figure 5 is a simplified schematic diagram of the steps for forming a scintillator layer. Figure 6 yes Figure 5 For easier viewing, Figure 6The electronic device in the scintillator layer is rotated by an angle (the incident direction of the material of the scintillator layer is also rotated by the same angle), so that the electronic device is arranged at an angle equal to Figure 2 same.

[0100] Please refer to Figure 2 and Figure 4 , a manufacturing method of the electronic device 1 may include: providing an element array substrate 10, wherein the element array substrate 10 includes a plurality of photosensitive elements 100 (step 400); forming a plurality of bumps 12 on the element array substrate 10, wherein the plurality of bumps 12 are arranged on the plurality of photosensitive elements 100 and are separated from each other (step 402); and forming a scintillator layer 14 on the plurality of bumps 12, wherein the scintillator layer 14 has a first portion P1 overlapping with the plurality of bumps 12 and a second portion P2 not overlapping with the plurality of bumps 12, and a side of the second portion P2 adjacent to the element array substrate 10 is looser than a side of the second portion P2 away from the element array substrate 10 (step 404).

[0101] The details of the element array substrate 10 can be referred to above and will not be repeated here. In addition, the material of the plurality of bumps 12 can be a transparent organic polymer material to save process time and / or reduce the plurality of bumps 12 for the visible light L2 incident on the plurality of photosensitive elements 100 (refer to Figure 3 ). In addition, based on considerations such as process time, process limits, and / or effectiveness of the shielding effect, the thickness T12 of the plurality of bumps 12 is, for example, greater than 0.5 μm and less than 30 μm, so that the scintillator layer 14 grows faster on the plurality of bumps 12 than between two adjacent bumps 12.

[0102] In detail, Figure 5 as well as Figure 6 As shown, the scintillator layer 14 is, for example, a columnar crystal scintillator layer, and the method of forming the scintillator layer 14 includes evaporation. During the evaporation, the device array substrate 10 having a plurality of bumps 12 is obliquely positioned above the evaporation source 5, so that the material of the scintillator layer 14 obliquely impinges on the plurality of bumps 12 and the device array substrate 10. Figure 5 as well as Figure 6 The arrow AR in FIG. 1 shows the incident direction of the material of the scintillator layer 14. Oblique incidence means that the angle θ between the normal line N10 of the element array substrate 10 (e.g., a line perpendicular to the surface of the element array substrate 10) and the normal line N5 of the evaporation source 5 (e.g., a line perpendicular to the surface of the evaporation source 5) is greater than 0.

[0103] Under the design of the element array substrate 10 in which the material of the scintillator layer 14 is obliquely incident on the multiple bumps 12 and the multiple bumps 12 will shield the obliquely incident material of the scintillator layer 14, so that the growth rate of the scintillator layer 14 on the multiple bumps 12 is faster than the growth rate between two adjacent bumps 12. Figure 6 The schematic diagram shows that a needle-like structure 140 is formed between two adjacent bumps 12. However, the growth rate of the needle-like structure 140 between the two adjacent bumps 12 is slower than that of the needle-like structure 140 on the bump 12. Therefore, the needle-like structure 140 between the two adjacent bumps 12 is shorter than the needle-like structure 140 on the bump 12. The length difference becomes more significant as the growth time increases. Figure 2 As shown, when the scintillator layer 14 is manufactured, the needle-like structure 140 between two adjacent bumps 12 is so small that it can be almost ignored.

[0104] The thickness T12 of the plurality of bumps 12 can be increased and / or the distance between two adjacent bumps 12 can be increased (e.g. Figure 1 The spacing IT1 and / or spacing IT2 shown in the figure is used to improve the degree of shielding of the obliquely incident scintillator layer 14 by the multiple bumps 12 during evaporation. However, the process time and / or cost will increase with the increase of the thickness T12 of the bump 12, and the thickness T12 of the bump 12 has a process limit. Therefore, based on considerations such as process time, process limit and / or effectiveness of the shielding effect, the thickness T12 of the multiple bumps 12 is, for example, greater than 0.5 μm and less than 30 μm. In addition, considering the loosening effect of the scintillator layer 14 on the side adjacent to the multiple bumps, the spacing of the multiple bumps 12 (such as Figure 1 The distance IT1 and / or the distance IT2 shown are, for example, greater than 1 μm.

[0105] Figure 7 is a partial cross-sectional diagram of an electronic device according to another embodiment of the present disclosure. Figure 7 , the electronic device 1A and Figure 2 The main difference of the electronic device 1 is that the width W3 of the third surface S3 of the bump 12A is greater than the width W4 of the fourth surface S4. Figure 2 The plurality of bumps 12 in the embodiment are formed by patterning a positive photosensitive material, for example. Figure 7 The plurality of bumps 12A are formed by patterning a negative photosensitive material, for example, but not limited thereto.

[0106] In summary, in the embodiments disclosed herein, the spatial resolution or sensitivity of imaging can be improved by designing the second portion of the scintillator layer adjacent to the device array substrate to be looser than the second portion away from the device array substrate.

[0107] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0108] Although the embodiments and advantages of the present disclosure have been disclosed above, it should be understood that those skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure, and the features between the embodiments may be arbitrarily mixed and replaced with each other to form other new embodiments. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Those skilled in the art can understand from the content of the present disclosure that the processes, machines, manufacturing, material compositions, devices, methods and steps currently or in the future developed can be used according to the present disclosure as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present disclosure also includes the combination of each claim and embodiment. The scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. An electronic device, characterized in that: include: An element array substrate comprising a plurality of photosensitive elements; a plurality of bumps, disposed on the plurality of photosensitive elements and separated from each other; as well as A scintillator layer is arranged on the multiple bumps, wherein the scintillator layer has a first portion overlapping with the multiple bumps and a second portion not overlapping with the multiple bumps, and the side of the second portion adjacent to the element array substrate is looser than the side of the second portion away from the element array substrate.

2. The electronic device according to claim 1, wherein: The material of the plurality of bumps is a transparent material with a light transmittance greater than 70%.

3. The electronic device according to claim 1, wherein: The thickness of the bumps is greater than 0.5 μm and less than 30 μm.

4. The electronic device according to claim 1, wherein: A pitch between the plurality of bumps is greater than 1 μm.

5. The electronic device according to claim 1, wherein: In a top view, an area of ​​at least one of the plurality of bumps is larger or smaller than an area of ​​at least one of the plurality of photosensitive elements.

6. The electronic device according to claim 1, wherein: The density of the first portion is greater than the density of the second portion.

7. The electronic device according to claim 1, wherein: The scintillator layer includes a plurality of scintillator units, which are respectively arranged on the plurality of bumps, wherein there is a gap between two adjacent scintillator units in the plurality of scintillator units, and the gap gradually becomes smaller in the stacking direction of the element array substrate, the plurality of bumps and the scintillator layer.

8. The electronic device according to claim 7, wherein: One of the plurality of scintillator units overlaps a corresponding one of the bumps and has a first surface adjacent to the corresponding one of the bumps and a second surface away from the corresponding one of the bumps. In a cross-sectional view, a width of the second surface is greater than a width of the first surface.

9. The electronic device according to claim 8, wherein: The corresponding one protrusion has a third surface adjacent to the one scintillator unit and a fourth surface away from the one scintillator unit, wherein in the cross-sectional view, the width of the third surface is less than or equal to the width of the first surface, and the width of the third surface is different from the width of the fourth surface.

10. The electronic device according to claim 1, wherein: The scintillator layer is a columnar crystal scintillator layer.

11. A method for manufacturing an electronic device, characterized in that: include: Providing an element array substrate, wherein the element array substrate includes a plurality of photosensitive elements; forming a plurality of bumps on the element array substrate, wherein the plurality of bumps are disposed on the plurality of photosensitive elements and are separated from each other; as well as A scintillator layer is formed on the multiple bumps, wherein the scintillator layer has a first portion overlapping with the multiple bumps and a second portion not overlapping with the multiple bumps, and a side of the second portion adjacent to the element array substrate is looser than a side of the second portion layer away from the element array substrate.

12. The method for manufacturing an electronic device according to claim 11, wherein: The scintillator layer is a columnar crystal scintillator layer, and a method of forming the scintillator layer includes evaporation.

13. The method for manufacturing an electronic device according to claim 12, wherein: During the evaporation, the element array substrate on which the plurality of bumps are formed is obliquely disposed above an evaporation source, so that the material of the scintillator layer is obliquely incident on the plurality of bumps and the element array substrate.

14. The method for manufacturing an electronic device according to claim 11, wherein: The material of the plurality of bumps is a transparent organic polymer material.

15. The method for manufacturing an electronic device according to claim 11, wherein: The thickness of the plurality of bumps is greater than 0.5 μm and less than 30 μm, so that the growth rate of the scintillator layer on the plurality of bumps is faster than the growth rate between two adjacent bumps.

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