Double-sided TOPCon battery and preparation method thereof

Abstract

The invention provides a double-sided TOPCon battery and a preparation method thereof, the double-sided TOPCon battery comprises an N-type silicon wafer, the front surface of the N-type silicon wafer is divided into a suede structure region and a P-poly structure region, and the suede structure region is sequentially provided with a first passivation layer and a first anti-reflection layer from inside to outside; the P-poly structure region sequentially comprises a first dielectric layer, a boron doping layer, a first passivation layer and a first anti-reflection layer from inside to outside, the boron doping layer comprises a first P + doping layer and a second P + + doping layer, the first P + doping layer is arranged on the circumferential edge of the second P + + doping layer, and the second P + + doping layer is connected with a first electrode. According to the invention, the second P + + doping layer is formed in the P-poly region on the front surface of the silicon wafer, so that low contact resistance is realized, a fill factor is improved, a flat interface is provided, and good passivation is realized; meanwhile, a PN junction structure is directly removed in a non-metal region, the boron doping area is reduced, front recombination is reduced, the passivation quality of the front is improved, the textured structure can maintain the high light trap capacity, optical loss is reduced, and short-circuit current is not damaged.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a double-sided TOPCon cell and a preparation method thereof. Background Art

[0002] The TOPCon (Tunnel Oxide Passivated Contact) cell is a new type of passivated contact cell. This cell achieves passivation by depositing an ultra-thin silicon oxide layer and doping polysilicon on the surface of the cell's silicon substrate. This structure enables excellent surface passivation and selective carrier collection, making bifacial Topcon photovoltaic cells a future technology path for next-generation N-type silicon wafers. Although bifacial Topcon photovoltaic cells offer excellent passivation performance and high open-circuit voltage, and the P-poly structure significantly reduces metal recombination on the front side while maintaining front contact resistivity, the use of thick polysilicon on the front side of the solar cell results in significant current loss due to parasitic light absorption, limiting further improvements in cell efficiency.

[0003] There are already some invention patents for solving the problem of improving the efficiency of solar cells. For example: Patent CN117334788A discloses a double-sided passivated battery prepared based on physical deposition technology and its preparation method, which provides a double-sided passivated battery prepared based on physical deposition technology and its preparation method, realizing a full passivation on the back and a localized passivation contact structure on the front, which satisfies the purpose of improving the passivation ability and increasing the battery efficiency, and effectively avoids the optical loss caused by the parasitic absorption of light by the Poly layer. However, this solution forms multiple layers of boron-doped layers in succession, and requires multiple precise control of the alignment problem. The steps are cumbersome and introduces potential yield limiting factors.

[0004] Patent CN118198180A provides a method for preparing a high-yield Poly-finger structured battery and a battery. Compared to other Poly-Finger technology routes, this reduces the finger area width, improves the yield, and reduces parasitic absorption losses in the P-poly layer, thereby improving battery mass production efficiency. However, this invention forms a p⁺-doped layer on the entire surface of the textured silicon through boron diffusion, which leads to high surface recombination. In addition, the p⁺-poly has a higher contact resistance than n⁺-poly, which may limit the fill factor. Although the front-side fully planar polysilicon structure can reduce contact resistance, the polysilicon layer has a severe parasitic absorption effect. When used on the front of the silicon wafer, it absorbs sunlight of a certain wavelength, resulting in severe optical losses and a decrease in short-circuit current. Summary of the Invention

[0005] The purpose of the present invention is to provide a double-sided TOPCon battery to overcome the above-mentioned technical problems existing in the prior art.

[0006] The purpose of the present invention is to provide a method for preparing a double-sided TOPCon cell, which reduces the recombination loss in the front metal-semiconductor contact area and significantly reduces the resistance by controlling the local area of ​​high-concentration boron doping.

[0007] To this end, the technical solutions provided by the present invention are as follows:

[0008] A bifacial TOPCon cell, comprising an N-type silicon wafer, wherein the front side of the N-type silicon wafer is divided into a textured structure region and a P-poly structure region, wherein the textured structure region is sequentially provided with a first passivation layer and a first anti-reflection layer from the inside out;

[0009] The P-poly structure area is composed of a first dielectric layer, a boron-doped layer, a first passivation layer and a first anti-reflection layer from the inside to the outside. The boron-doped layer includes a first P+ doped layer and a second P++ doped layer. The first P+ doped layer is arranged at the circumferential edge of the second P++ doped layer. The second P++ doped layer is connected to the first electrode. The concentration of the second P++ doped layer is greater than that of the first P+ doped layer.

[0010] The volume of the second P++ layer accounts for 2% to 100% of the boron-doped layer.

[0011] The concentration of the first P+ doped layer is 1E*18 cm -3 ~1E*19cm -3 , junction depth 0.1-0.5μm.

[0012] The concentration of the second P++ layer is 1E*19 cm -3 ~1E*20 cm -3 , junction depth 0.05-0.45μm.

[0013] The back side of the N-type silicon wafer is sequentially provided with a second dielectric layer, a first N+ doped layer, and a second anti-reflection layer from the inside out, and the first N+ doped layer is connected to a second electrode.

[0014] The width of the first P+ doped layer is greater than that of the second P++ doped layer, and the width of the second P++ doped layer is greater than that of the gate line.

[0015] A method for preparing a double-sided TOPCon battery comprises the following steps:

[0016] Step 1) Raw silicon polishing: Place the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0017] Step 2) Forming a first P+ doped layer: First, a first dielectric layer is formed on the front side of the N-type silicon wafer. Then, an amorphous silicon layer, a polysilicon layer, or a mixed layer of amorphous silicon and polysilicon is formed on the first dielectric layer. Then, boron doping is performed to form the first P+ doped layer.

[0018] Step 3) Backside etching: Remove the BSG and the first P+ doped layer on the back and edge of the N-type silicon wafer;

[0019] Step 4) Local etching: Perform local laser patterning on the preset textured area on the front surface to remove the local surface BSG, and then perform alkaline etching to remove the doped layer below the laser area, so that only the first dielectric layer and the first P+ doped polysilicon layer remain in the P-poly area;

[0020] Step 5) Local heavy doping: Use the BSG on the surface of the P-poly area as a doping source, and through local doping, advance the BSG boron source to form a local heavy doping second P++ doping layer

[0021] Step 6) Forming a first N+ doped layer: forming a second dielectric layer and an amorphous silicon layer or a polysilicon layer or a mixed layer of amorphous silicon and polysilicon on the back side of the N-type silicon wafer, and doping this area with phosphorus to form a doped first N+ doped layer;

[0022] Step 7) Front etching: remove the PSG and N+ doping layers on the front and edge;

[0023] Step 8) Local texturing: forming a local pyramid structure on the front side and removing residual BSG and PSG;

[0024] Step 9) Deposition of the first passivation layer: ALD atomic layer deposition is used to deposit the first passivation layer on the front of the silicon wafer with a thickness of 1 nm to 10 nm.

[0025] Step 10) Deposition of anti-reflection layer: Deposit the first anti-reflection layer and the second anti-reflection layer on the front and back sides of the silicon wafer respectively using PECVD, with a thickness of 20nm to 200nm;

[0026] Step 11) Screen printing: Screen print the first electrode and the second electrode on the front and back of the silicon wafer respectively, and then sinter them.

[0027] When boron doping is performed in step 2), LPCVD technology is used, BCl3 is used as a boron source for surface doping to form a first P+ doping layer, and the diffusion temperature is 800°C to 950°C; or PECVD technology is used, BH3 or TMB is used as a boron source for surface doping to form a first P+ doping layer, and the diffusion temperature is 200°C to 600°C.

[0028] During the local laser patterning process in step 4), the operating power of the optical device is 1 W ~ 25 W, the scanning speed is 5 m / s ~ 50 m / s, and the frequency is 200 kHz ~ 2000 kHz.

[0029] The local doping method in step 5) is a local laser thermal effect, screen printing doping paste or local ion implantation.

[0030] The beneficial effects of the present invention are:

[0031] The present invention forms a second P++ doped layer (high-concentration boron doping) in the P-poly area on the front side of the silicon wafer to optimize the contact between metal and polysilicon, achieve low contact resistance, reduce recombination, improve the fill factor, and provide a smooth interface for good passivation. At the same time, the PN junction structure is directly removed in the non-metallic area, reducing the area of ​​boron doping on the front side, which can reduce front recombination and improve the passivation quality of the front side. The velvet structure is designed to maintain a high light trapping ability, reduce optical loss, and not damage the short-circuit current.

[0032] The present invention breaks through the mutually exclusive limitations of optical and electrical performance by combining planar polysilicon finger contacts and velvet light absorption area structures, while improving the passivation effect of the front surface of the battery, minimizing the parasitic light absorption of the polysilicon layer and ensuring good contact performance. The width of the second P++ doped layer is greater than the gate line width, which can reduce contact resistance, improve current distribution, enhance carrier collection efficiency, and improve the electrical performance of the photovoltaic cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic structural diagram of an embodiment of the battery of the present invention. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the invention from the contents disclosed in this specification.

[0035] Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings. However, the invention may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so as to provide a thorough and complete disclosure of the invention and fully convey the scope of the invention to those skilled in the art. The terms used in the exemplary embodiments shown in the drawings are not intended to limit the invention.

[0036] Unless otherwise specified, the terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have meanings consistent with the context of their relevant fields and should not be interpreted as idealized or overly formal.

[0037] Example 1

[0038] The present invention provides a bifacial TOPCon cell, comprising an N-type silicon wafer, wherein the front side of the N-type silicon wafer is divided into a suede structure region and a P-poly structure region, wherein the suede structure region is sequentially provided with a first passivation layer and a first anti-reflection layer from the inside to the outside;

[0039] The P-poly structure area is composed of a first dielectric layer, a boron-doped layer, a first passivation layer and a first anti-reflection layer from the inside to the outside. The boron-doped layer includes a first P+ doped layer and a second P++ doped layer. The first P+ doped layer is arranged at the circumferential edge of the second P++ doped layer. The second P++ doped layer is connected to the first electrode. The concentration of the second P++ doped layer is greater than that of the first P+ doped layer.

[0040] The P-poly structure on the front side of the silicon wafer provides a smooth interface for excellent passivation. In the non-metallized area, the PN junction structure is eliminated, reducing the boron doping area on the front side, thereby minimizing front-side recombination and improving front-side passivation quality. The textured (pyramid) structure maintains high light trapping capacity, reducing optical losses and maintaining short-circuit current. The second P++ doped layer in the P-poly structure optimizes the contact between metal and polysilicon, achieving low contact resistance, reducing recombination, and improving fill factor.

[0041] The present invention combines planar polysilicon finger contacts (the electrode portion is heavily doped with boron) with a suede-like light absorption region structure to break through the mutually exclusive limitations of optical and electrical performance. While improving the passivation effect of the front surface of the battery, it minimizes the parasitic light absorption of the polysilicon layer and ensures good contact performance.

[0042] Example 2

[0043] Based on Example 1, this embodiment provides a double-sided TOPCon cell, in which the volume proportion of the second P++ layer in the boron-doped layer is 2% to 100%.

[0044] Taking laser doping as an example, the laser's application range in the first P+ doped layer (BSG) can be set as required. When the laser is applied only to the predetermined gate line area, the second P++ layer accounts for 2% of the total boron-doped layer volume. When the laser is applied to the entire P region, the second P++ layer accounts for 100% of the total boron-doped layer volume.

[0045] The concentration of the first P+ doped layer is 1E*18 cm -3 ~1E*19cm -3 , junction depth 0.1-0.5μm.

[0046] The concentration of the second P++ layer is 1E*19 cm -3 ~1E*20 cm -3 , junction depth 0.05-0.45μm.

[0047] The doping concentration reaches 10 19 cm -3 It can provide a large number of free electrons or holes, significantly improving the conductivity.

[0048] Example 3

[0049] Based on Example 1, this embodiment provides a double-sided TOPCon battery, such as Figure 1 As shown, the back side of the N-type silicon wafer is composed of a second dielectric layer, a first N+ doped layer, and a second anti-reflection layer from the inside to the outside, and the first N+ doped layer is connected to a second electrode.

[0050] When the tunneling passivation layer is used on the back of the battery, it can provide excellent back surface passivation and carrier collection capabilities.

[0051] Furthermore, the width of the first P+ doped layer is greater than that of the second P++ doped layer, and the width of the second P++ doped layer is greater than that of the gate line.

[0052] The width of the second P++ doped layer is greater than the gate line width, which can reduce contact resistance, improve current distribution, enhance carrier collection efficiency, and improve the electrical performance of the photovoltaic cell.

[0053] Example 4

[0054] This embodiment provides a method for preparing a double-sided TOPCon battery, comprising the following steps:

[0055] Step 1) Raw silicon polishing: Place the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0056] Step 2) Forming a first P+ doped layer: First, a first dielectric layer is formed on the front side of the N-type silicon wafer. Then, an amorphous silicon layer, a polysilicon layer, or a mixed layer of amorphous silicon and polysilicon is formed on the first dielectric layer. Then, boron doping is performed to form the first P+ doped layer.

[0057] Step 3) Backside etching: Remove the BSG and the first P+ doped layer on the back and edge of the N-type silicon wafer;

[0058] Step 4) Local etching: Perform local laser patterning on the preset textured area on the front surface to remove the local surface BSG, and then perform alkaline etching to remove the doped layer below the laser area, so that only the first dielectric layer and the first P+ doped polysilicon layer remain in the P-poly area;

[0059] Step 5) Local heavy doping: Use the BSG on the surface of the P-poly area as a doping source, and through local doping, advance the BSG boron source to form a local heavy doping second P++ doping layer

[0060] Step 6) Forming a first N+ doped layer: forming a second dielectric layer and an amorphous silicon layer or a polysilicon layer or a mixed layer of amorphous silicon and polysilicon on the back side of the N-type silicon wafer, and doping this area with phosphorus to form a doped first N+ doped layer;

[0061] Step 7) Front etching: remove the PSG and N+ doping layers on the front and edge;

[0062] Step 8) Local texturing: forming a local pyramid structure on the front side and removing residual BSG and PSG;

[0063] Step 9) Deposition of the first passivation layer: ALD atomic layer deposition is used to deposit the first passivation layer on the front of the silicon wafer with a thickness of 1 nm to 10 nm.

[0064] Step 10) Deposition of anti-reflection layer: Deposit the first anti-reflection layer and the second anti-reflection layer on the front and back sides of the silicon wafer respectively using PECVD, with a thickness of 20nm to 200nm;

[0065] Step 11) Screen printing: Screen print the first electrode and the second electrode on the front and back of the silicon wafer respectively, and then sinter them.

[0066] When boron doping is performed in step 2), LPCVD technology is used, and BCl3 is used as a boron source for surface doping to form a first P+ doping layer, and the diffusion temperature is 800°C to 950°C.

[0067] The method of the present invention controls the local area of ​​high-concentration boron doping, optimizes the front optical absorption and electrical contact performance at the same time, reduces the recombination loss of the front metal-semiconductor contact area, and improves the battery efficiency.

[0068] Example 5

[0069] Based on Example 4, this example provides a method for preparing a double-sided TOPCon cell, comprising the following steps:

[0070] Step 1) Place the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0071] Step 2) Forming the first P+ doped layer: First, the first dielectric layer is formed on the front side of the silicon wafer, and then an amorphous silicon layer is formed on the first dielectric layer, and then boron doping is performed to obtain the first P+ doped layer; the ECV surface concentration is 1E*19cm -3 , junction depth 0.5μm;

[0072] Step 3) Clean the back surface to remove the back and edge BSG and the first P+ doping layer;

[0073] Step 4) performing local laser patterning on the front surface of the preset textured area to remove the local surface BSG, and then performing alkaline etching to remove the doped layer below the laser area, so that the P-poly area of ​​the non-preset textured area remains with the first dielectric layer and the first P+ doped layer, forming a P-poly area structure;

[0074] The operating parameters of the laser are: power 20W, scanning speed 30m / s, frequency 1000kHz;

[0075] Step 5) Local heavy doping: The BSG on the surface of the first P+ doped layer in the P-poly region is used as a doping source. Through laser doping technology, the laser power is 70W, the wavelength is 500nm, the scanning speed is 32500mm / s, and the frequency is 1100kHz. The boron source is advanced twice, and then heat treatment is performed at 900℃ for 10min. A second P++ doped layer is formed inside the first P+ lightly doped polysilicon layer. The ECV surface concentration is 1E20cm -3 , the junction depth is 0.45 μm, and the volume of the second P++ doped layer accounts for 50% of the first P+ doped layer, the width of the first P+ doped layer region is 500 μm, the width of the second P++ region is 280 μm, and the gate line width is 40 μm;

[0076] Step 6) Deposit a second dielectric layer and an amorphous silicon layer on the back of the silicon wafer. Phosphorus is doped in this area to obtain the first N+ doped layer with an ECV surface concentration of 5E*20cm -3 , junction depth 0.3μm;

[0077] Step 7) Clean the front surface to remove the PSG and the first N+ doping layer on the front and edge;

[0078] Step 8) Texturing the silicon wafer to form a local pyramid and a local P-poly area structure on the front side, and then remove the residual BSG on the P-poly area structure and the PSG on the back side;

[0079] Step 9) depositing a first passivation layer on the front side of the silicon wafer with a thickness of 5 nm;

[0080] Step 10) depositing a first anti-reflection layer and a second anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 80 nm each;

[0081] Step 11) preparing a first electrode and a second electrode on the second P++P-poly region and the first N+P-poly region respectively, and sintering them.

[0082] Comparative Example 1

[0083] Compared with Example 5, this comparative example does not have heavy doping. The specific preparation process is as follows:

[0084] Step 1: Place the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0085] Step 2: Form the first P+ doped layer. First, form the first dielectric layer on the front of the silicon wafer. Then form an amorphous silicon layer on the first dielectric layer. Then, dope it with boron to obtain the first P+ doped layer. The ECV surface concentration is 1E*19cm -3 , junction depth 0.5μm;

[0086] Step 3: Clean the back of the silicon wafer to remove the BSG and the first P+ doped layer on the back and edge.

[0087] Step 4: Perform local laser patterning on the front surface of the preset textured area to remove the local surface BSG, and then perform alkaline etching to remove the doped layer below the laser area, so that the P-poly area of ​​the non-preset textured area remains with the first dielectric layer and the first P+ doped layer, forming a Poly finger structure;

[0088] The operating parameters of the laser are: power 20W, scanning speed 30m / s, frequency 1000kHz;

[0089] Step 5: Deposit a second dielectric layer and an amorphous silicon layer on the back of the silicon wafer, and dope this area with phosphorus to obtain the first N+ doped layer with an ECV surface concentration of 5E*20cm -3 , junction depth 0.3μm;

[0090] Step 6: Clean the front surface to remove the PSG and the first N+ doping layer on the front and edge.

[0091] Step 7: Texturing the silicon wafer to form a local pyramid and a local poly finger structure on the front side, and then remove the residual BSG on the poly finger structure and the PSG on the back side;

[0092] Step eight, depositing the first passivation layer on the front side of the silicon wafer with a thickness of 5 nm;

[0093] Step 9: depositing a first anti-reflection layer and a second anti-reflection layer on the front and back sides of the silicon wafer, respectively, with a thickness of 80 nm each.

[0094] Step 10: Prepare a first electrode and a second electrode on the first P+ doping region and the first N+ doping region respectively, and sinter them.

[0095] Comparative Example 2

[0096] Compared with Example 5, this comparative example has heavy doping, but is a full-surface structure (not a partial suede structure or a partial poly structure). The specific preparation process is as follows:

[0097] Step 1: Place the N-type silicon wafer into a tank-type alkaline solution for texturing;

[0098] Step 2: Form the first doped P+ layer: First, form a first dielectric layer on the front of the silicon wafer, then form an amorphous silicon layer on the first dielectric layer, and then dope it with boron to obtain the first P+ doped layer. The ECV surface concentration is 1E*19cm -3 , junction depth 0.5μm;

[0099] Step 3: Clean the back surface, remove the BSG on the back surface and then perform alkaline polishing;

[0100] Step 4: The BSG on the surface of the local first P+ doped layer is used as a doping source. Through laser doping technology, the laser power is 70W, the wavelength is 500nm, the scanning speed is 32500mm / s, and the frequency is 1100kHz. The boron source is secondary promoted and then heat treated at 900℃ for 10min to form a local second P++ doped layer with an ECV surface concentration of 1E20cm -3 , junction depth 0.45μm, second P++ doped layer width 280μm, gate line width 40μm;

[0101] Step 5: Deposit a second dielectric layer and an amorphous silicon layer on the back of the silicon wafer, and dope this area with phosphorus to obtain the first N+ doped layer with an ECV surface concentration of 5E*20cm -3 , junction depth 0.3μm;

[0102] Step 6: Clean the front surface to remove the PSG and the first N+ doping layer on the front and edge.

[0103] Step 7: Remove the residual BSG on the front and PSG on the back;

[0104] Step 8: depositing a first passivation layer on the front side of the silicon wafer with a thickness of 5 nm;

[0105] Step nine, depositing a first anti-reflection layer and a second anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 80 nm each;

[0106] Step 10: Prepare the first electrode and the second electrode on the second P++ doped region and the first N+ doped region respectively, and sinter them.

[0107] Comparative Example 3:

[0108] The structural design in this comparative example is compared with Example 5, with finger contacts and heavy doping, but the width of the first P+ doped layer region = the width of the second P++ doped layer region = the gate line width.

[0109] Step 1: Place the N-type silicon wafer in a tank-type alkaline solution for polishing;

[0110] Step 2: Form the first P+ doped layer. First, form the first dielectric layer on the front of the silicon wafer. Then form an amorphous silicon layer on the first dielectric layer. Then, dope it with boron to obtain the first P+ doped layer. The ECV surface concentration is 1E*19cm -3 , junction depth 0.5μm;

[0111] Step 3: Clean the back surface to remove the back and edge BSG and the first P+ doped layer;

[0112] Step 4: Perform local laser patterning on the preset textured area on the front side to remove the local surface BSG, and then perform alkaline etching to remove the doped layer below the laser area, so that only the first dielectric layer and the first P+ doped layer remain in the finger area;

[0113] The operating parameters of the laser are: power 20W, scanning speed 30m / s, frequency 1000kHz;

[0114] Step 5: The BSG on the surface of the first P+ doped layer is used as a doping source. Through laser doping technology, the laser power is 70W, the wavelength is 500nm, the scanning speed is 32500mm / s, and the frequency is 1100kHz. The boron source is secondary promoted and then heat treated at 900℃ for 10min to form a second P++ doped layer inside the first P+ doped layer. The ECV surface concentration is 1E20cm -3 , the junction depth is 0.45 μm, and the volume of the second P++ doped layer accounts for 50% of the first P+ doped layer, the width of the first P+ doped layer area is 40 μm, the width of the second P++ doped layer area is 40 μm, and the gate line width is 40 μm;

[0115] Step 6: Deposit a second dielectric layer and an amorphous silicon layer on the back of the silicon wafer, and dope this area with phosphorus to obtain the first N+ doped layer with an ECV surface concentration of 5E*20cm -3 , junction depth 0.3μm;

[0116] Step 7: Clean the front surface to remove the PSG and N+ doping layers on the front and edge.

[0117] Step 8: Texturing the silicon wafer to form a local pyramid and a local Poly finger structure on the front side, and then remove the residual BSG on the Poly finger structure and the PSG on the back side;

[0118] Step nine, depositing a first passivation layer on the front side of the silicon wafer with a thickness of 5 nm;

[0119] Step 10: depositing a first anti-reflection layer and a second anti-reflection layer on the front and back surfaces of the silicon wafer, respectively, with a thickness of 80 nm each;

[0120] Step eleven: prepare a first electrode and a second electrode on the first P++ doped layer region and the first N+ doped layer region respectively, and sinter them.

[0121] In order to further illustrate and verify the effects of the present invention, the following electrical performance tests were conducted on the cells prepared in Example 5, Comparative Example 1, Comparative Example 2, and Comparative Example 3. The results are shown in Table 1.

[0122] Reflectivity was tested using a D8 reflectometer, measuring the front side of the cell. Contact resistance was tested using a TLM, with all measured values ​​averaged. IV testing (current-voltage characteristics testing) was performed using an IV tester.

[0123] Table 1 TOPCon battery performance test results of examples and comparative examples

[0124]

[0125] As shown in Table 1, Comparative Example 1 lacks heavy doping (a second P++ doped layer) and has high contact resistance, while Comparative Example 2 has heavy doping and a full-surface velvet finish, resulting in significant parasitic absorption. Compared to Comparative Examples 1 and 2, Example 5 employs a combination of planar polysilicon finger contacts (heavily boron-doped in the electrode area) and a velvet-finger light absorption region structure, overcoming the mutually exclusive limitations of optical and electrical performance. While enhancing the passivation effect on the front surface of the cell, it also minimizes parasitic light absorption in the polysilicon layer and ensures good contact performance, thereby improving the electrical performance of the photovoltaic cell. Furthermore, the cell produced in Example 5 exhibits both low reflectivity and low contact resistance, and its conversion efficiency is significantly higher than that of the cell produced in the comparative example.

[0126] Compared with Example 3, Example 5 has a first P++ doped layer width greater than the second P++ doped layer width, and a second P++ doped layer width greater than the gate line width, which can reduce contact resistance, improve current distribution, enhance carrier collection efficiency, and improve the electrical performance of the photovoltaic cell.

[0127] In summary, the present invention forms a second P++ doped layer (high-concentration boron doping) in the P-poly region on the front side of the silicon wafer, thereby optimizing the contact between metal and polysilicon, achieving low contact resistance, reducing recombination, and improving the fill factor. It can also provide a smooth interface and achieve good passivation. At the same time, the PN junction structure is directly removed in the non-metallic region, reducing the boron-doped area on the front side, which can reduce front-side recombination and improve the passivation quality of the front side. In addition, the velvet structure is designed to maintain a high light trapping capability, reduce optical loss, and not damage the short-circuit current.

[0128] The present invention breaks through the mutually exclusive limitations of optical and electrical performance by combining planar polysilicon finger contacts and velvet light absorption area structures, while improving the passivation effect of the front surface of the battery, minimizing the parasitic light absorption of the polysilicon layer and ensuring good contact performance. The width of the second P++ doped layer is greater than the gate line width, which can reduce contact resistance, improve current distribution, enhance carrier collection efficiency, and improve the electrical performance of the photovoltaic cell.

[0129] The above examples are merely illustrative of the invention and do not constitute a limitation on the scope of protection of the invention. Any design that is identical or similar to the invention falls within the scope of protection of the invention.

Claims

1. A double-sided TOPCon battery, characterized by: An N-type silicon wafer is included, wherein the front surface of the N-type silicon wafer is divided into a suede structure area and a P-poly area, and the suede structure area is sequentially provided with a first passivation layer and a first anti-reflection layer from the inside to the outside; The P-poly region comprises, from the inside to the outside, a first dielectric layer, a boron-doped layer, a first passivation layer, and a first anti-reflection layer. The boron-doped layer includes a first P+ doped layer and a second P++ doped layer. The first P+ doped layer is arranged at the circumferential edge of the second P++ doped layer. The second P++ doped layer is connected to a first electrode, and the concentration of the second P++ doped layer is greater than that of the first P+ doped layer.

2. A double-sided TOPCon battery according to claim 1, characterized in that: The volume of the second P++ layer accounts for 2% to 100% of the boron-doped layer.

3. The double-sided TOPCon battery according to claim 1, characterized in that: The concentration of the first P+ doped layer is 1E*18 cm -3 ~1E*19 cm -3 , junction depth 0.1-0.5 μm.

4. The double-sided TOPCon battery according to claim 1, characterized in that: The concentration of the second P++ layer is 1E*19 cm -3 ~1E*20 cm -3 , junction depth 0.05-0.45μm.

5. A double-sided TOPCon cell according to any one of claims 1 to 4, characterized in that: The back side of the N-type silicon wafer is sequentially provided with a second dielectric layer, a first N+ doped layer, and a second anti-reflection layer from the inside out, and the first N+ doped layer is connected to a second electrode.

6. A double-sided TOPCon cell according to any one of claims 1 to 4, characterized in that: The width of the first P+ doped layer is greater than that of the second P++ doped layer, and the width of the second P++ doped layer is greater than that of the gate line.

7. The method for preparing a double-sided TOPCon cell according to any one of claims 1 to 4, characterized in that: The following steps are involved: Step 1) Raw silicon polishing: Place the N-type silicon wafer in a tank-type alkaline solution for polishing; Step 2) Forming a first P+ doped layer: First, a first dielectric layer is formed on the front side of the N-type silicon wafer. Then, an amorphous silicon layer, a polysilicon layer, or a mixed layer of amorphous silicon and polysilicon is formed on the first dielectric layer. Then, boron doping is performed to form the first P+ doped layer. Step 3) Backside etching: Remove the BSG and the first P+ doped layer on the back and edge of the N-type silicon wafer; Step 4) Local etching: Perform local laser patterning on the preset textured area on the front surface to remove the local surface BSG, and then perform alkaline etching to remove the doped layer below the laser area, so that only the first dielectric layer and the first P+ doped polysilicon layer remain in the P-poly area; Step 5) Local heavy doping: Use the BSG on the surface of the P-poly area as a doping source, and through local doping, advance the BSG boron source to form a local heavy doped second P++ doping layer; Step 6) Forming a first N+ doped layer: forming a second dielectric layer and an amorphous silicon layer or a polysilicon layer or a mixed layer of amorphous silicon and polysilicon on the back side of the N-type silicon wafer, and doping this area with phosphorus to form a doped first N+ doped layer; Step 7) Front etching: remove the PSG and N+ doping layers on the front and edge; Step 8) Local texturing: forming a local pyramid structure on the front side and removing residual BSG and PSG; Step 9) Deposition of the first passivation layer: ALD atomic layer deposition is used to deposit the first passivation layer on the front of the silicon wafer with a thickness of 1 nm to 10 nm. Step 10) Deposition of anti-reflection layer: Deposit the first anti-reflection layer and the second anti-reflection layer on the front and back sides of the silicon wafer respectively using PECVD, with a thickness of 20nm to 200nm; Step 11) Screen printing: Screen print the first electrode and the second electrode on the front and back of the silicon wafer respectively, and then sinter them.

8. The method for preparing a double-sided TOPCon battery according to claim 7, characterized in that: When boron doping is performed in step 2), LPCVD technology is used, BCl3 is used as a boron source for surface doping to form a first P+ doping layer, and the diffusion temperature is 800°C to 950°C; or PECVD technology is used, BH3 or TMB is used as a boron source for surface doping to form a first P+ doping layer, and the diffusion temperature is 200°C to 600°C.

9. The method for preparing a double-sided TOPCon battery according to claim 7, wherein: During the local laser patterning process in step 4), the operating power of the optical device is 1 W ~ 25 W, the scanning speed is 5 m / s ~ 50 m / s, and the frequency is 200 kHz ~ 2000 kHz.

10. The method for preparing a double-sided TOPCon battery according to claim 7, characterized in that: The local doping method in step 5) is a local laser thermal effect, screen printing doping paste or local ion implantation.

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