Display panel and manufacturing method thereof

Abstract

The embodiment of the invention provides a display panel and a manufacturing method thereof. The display panel has a display area and a transparent area. The display panel comprises a substrate, an active layer, a gate insulating layer, a first metal layer, an interlayer insulating layer, a contact hole and a first opening. The active layer is arranged on the substrate and located in the display area. The gate insulating layer covers the active layer and the substrate. The first metal layer is located on the side, away from the substrate, of the gate insulation layer and comprises a gate located in the display area and overlapped with the active layer. The interlayer insulating layer is located on the side, away from the substrate, of the first metal layer. The contact hole is located in the display area, penetrates through the interlayer insulating layer and the gate insulating layer and extends into the active layer. The first opening is located in the transparent area and penetrates through the interlayer insulating layer and the gate insulating layer. Thus, the same photomask can be used for exposure to form the contact hole of the display area and the first opening of the transparent area, and the number of photomasks needed for manufacturing the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] Micro Light Emitting Diode (Micro-LED) refers to a light-emitting diode device in which the distance between pixels is at the micron level. As a new generation of display technology, Micro LED display devices have the advantages of small size, wide color gamut, high brightness and long life, and their operating voltage is low, luminous efficiency is high, response speed is fast, performance is stable and reliable, and operating temperature range is wide. They can well meet various needs and are the mainstream development direction of micro-display technology in the future. A transparent display means that the display itself has a certain degree of light transmittance, and you can see both the image displayed on the display and the information behind the display. Transparent displays have been used in high-end display fields such as car window glass, shopping mall windows, AR (Augmented Reality), VR (Virtual Reality). At present, the production process of transparent display screens based on Micro Light Emitting Diode (Micro-LED) is complicated and requires a large number of masks. Summary of the Invention

[0003] The embodiments of the present application provide a display panel and a method for manufacturing the same, which are beneficial for reducing the number of masks required for manufacturing the display panel, thereby at least partially solving the above-mentioned technical problems.

[0004] To achieve the above-mentioned object, according to a first aspect of the present application, a display panel is provided, wherein the display panel has a display area and a transparent area, and includes:

[0005] substrate;

[0006] an active layer, disposed on the substrate and located in the display area;

[0007] a gate insulating layer, covering the active layer and the substrate;

[0008] a first metal layer, located on a side of the gate insulating layer facing away from the substrate, and comprising a gate, wherein the gate is located in the display area and overlaps with the active layer;

[0009] an interlayer insulating layer, located on a side of the first metal layer facing away from the substrate;

[0010] a contact hole, located in the display area, penetrating the interlayer insulating layer and the gate insulating layer, and extending into the active layer;

[0011] The first opening is located in the transparent area and penetrates the interlayer insulating layer and the gate insulating layer.

[0012] Optionally, the display panel further includes:

[0013] a second metal layer, located on a side of the interlayer insulating layer facing away from the substrate, and comprising a contact electrode, wherein the contact electrode is located in the contact hole and contacts a sidewall of the active layer;

[0014] a flat layer, located on a side of the second metal layer facing away from the substrate;

[0015] a passivation layer, located on a side of the planar layer facing away from the substrate;

[0016] The second opening is located in the transparent area and penetrates the passivation layer, and also overlaps with the first opening.

[0017] Optionally, the display panel further includes a third opening, which is located in the transparent area and passes through the flat layer, and is also connected to the first opening and the second opening.

[0018] Optionally, the passivation layer includes a first sidewall defining the second opening, the planarization layer includes a second sidewall defining the third opening, and the first sidewall is coplanar with the second sidewall.

[0019] Optionally, the light transmittance of the planar layer is greater than or equal to 90%, and the planar layer is located in the display area and the transparent area and fills the first opening.

[0020] Optionally, the passivation layer includes a first passivation layer, the display panel also includes a third metal layer and a light-emitting device, the third metal layer is located on the side of the flat layer away from the substrate and includes a binding electrode located in the display area, the first passivation layer covers the third metal layer and the flat layer and is provided with a fourth opening, the fourth opening is located in the display area and exposes the binding electrode, the light-emitting device is located in the display area and bound to the binding electrode, and the binding electrode is electrically connected to the contact electrode.

[0021] Optionally, the passivation layer further includes a second passivation layer, and the second passivation layer is located between the third metal layer and the planar layer.

[0022] According to a second aspect of the present application, a method for manufacturing a display panel is provided, wherein the display panel has a display area and a transparent area, the method comprising:

[0023] forming an active layer on a substrate, wherein the active layer is located in the display area;

[0024] forming a gate insulating layer, wherein the gate insulating layer covers the active layer and the substrate;

[0025] forming a first metal layer, the first metal layer being located on a side of the gate insulating layer facing away from the substrate and comprising a gate, the gate being located in the display area and overlapping the active layer;

[0026] forming an interlayer insulating layer, wherein the interlayer insulating layer is located on a side of the first metal layer facing away from the substrate;

[0027] A single exposure and development process, as well as a single etching process, are used to remove part of the gate insulating layer, the interlayer insulating layer, and part of the active layer to form a contact hole and a first opening. The contact hole is located in the display area and passes through the interlayer insulating layer and the gate insulating layer and extends into the active layer. The first opening is located in the transparent area and passes through the interlayer insulating layer and the gate insulating layer.

[0028] Optionally, the method further comprises:

[0029] forming a second metal layer, the second metal layer being located on a side of the interlayer insulating layer facing away from the substrate and comprising a contact electrode, the contact electrode being located in the contact hole and contacting a sidewall of the active layer;

[0030] A planar layer is formed. The planar layer is located on a side of the second metal layer facing away from the substrate, is also located in the display area, and fills the first opening.

[0031] Optionally, the method further comprises:

[0032] forming a passivation layer, wherein the passivation layer is located on a side of the planar layer facing away from the substrate;

[0033] performing a patterning process on the passivation layer to form a remaining passivation layer and a second opening penetrating the passivation layer, wherein the second opening is located in the transparent region, penetrates the passivation layer, and overlaps with the first opening;

[0034] The remaining passivation layer is used as a mask, and the planar layer is patterned through the second opening to form a third opening penetrating the planar layer. The third opening is located in the transparent area and communicates with the second opening and the first opening.

[0035] In the display panel and its manufacturing method according to the embodiments of the present application, the contact hole in the display area penetrates the interlayer insulating layer and the gate insulating layer and extends into the active layer, and the first opening in the transparent area penetrates the interlayer insulating layer and the gate insulating layer. This allows the use of a single photomask for exposure, development, and a single etching of the gate insulating layer, interlayer insulating layer, and active layer to form the contact hole in the display area and the first opening in the transparent area, thereby reducing the number of photomasks required to manufacture the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic cross-sectional view of a display panel provided in an exemplary embodiment of the present application;

[0037] Figure 2 is another schematic cross-sectional view of a display panel provided in an exemplary embodiment of the present application;

[0038] Figure 3 is a schematic diagram of another cross-sectional structure of a display panel provided in an exemplary embodiment of the present application;

[0039] Figure 4 is a schematic diagram of another cross-sectional structure of a display panel provided in an exemplary embodiment of the present application;

[0040] Figure 5 A schematic flow chart of a method for manufacturing a display panel provided in an exemplary embodiment of the present application;

[0041] Figures 6 and 7 The production process provided in the exemplary embodiment of this application Figure 1 A schematic diagram of the process is displayed on the panel.

[0042] Description of reference numerals:

[0043] 100, display panel; 100A, display area; 100B, transparent area;

[0044] 11. Base;

[0045] 12. Active layer;

[0046] 13. Gate insulation layer;

[0047] 141. First metal layer; 142. Gate; 143. Second metal layer; 144. Contact electrode; 145. Third metal layer; 146. Binding electrode; 147. Fourth metal layer; 148. Electrode plate;

[0048] 15. Interlayer insulating layer; 151. First interlayer insulating layer; 152. Second interlayer insulating layer;

[0049] 16, flat layer; 161, first flat layer; 162, second flat layer; 163, third flat layer; 16A, second side wall;

[0050] 17, passivation layer; 17A, first sidewall; 171, first passivation layer; 171A, third sidewall; 172, second passivation layer; 172A, fourth sidewall;

[0051] 18. Shading layer;

[0052] 19. Buffer layer;

[0053] 201, first conductive layer; 202, first bonding electrode; 203, second conductive layer; 204, second bonding electrode;

[0054] H1, contact hole; O1, first opening; O2, second opening; O21, first sub-opening; O22, second sub-opening; O3, third opening; O4, fourth opening;

[0055] 21. Light-emitting device. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0057] Figure 1 A schematic cross-sectional structure diagram of a display panel provided in an exemplary embodiment of the present application.

[0058] like Figure 1 As shown, the display panel 100 has a display area 100A and a transparent area 100B. The portion of the display panel 100 corresponding to the display area 100A can emit light to achieve display. The portion of the display panel 100 corresponding to the transparent area 100B has a high transmittance to light, so that the back side of the display side of the display panel 100 can be seen when the display panel 100 is displaying.

[0059] The display area 100A may include a plurality of light-emitting areas, and the transparent area 100B may be located between adjacent light-emitting areas.

[0060] The display panel 100 includes a substrate 11 , a driving circuit layer, and a light emitting device 21 .

[0061] The substrate 11 is used to support the light-emitting devices 21 of the display area 100A and the driving circuit connected to the light-emitting devices 21, and is also used to support the light-transmitting structure of the transparent area 100B. The substrate 11 can include a glass substrate, but is not limited to this. The substrate 11 can also include a flexible substrate.

[0062] The driving circuit layer includes an active layer 12 , a gate insulating layer 13 , a first metal layer 141 and an interlayer insulating layer 15 .

[0063] Active layer 12 is disposed on substrate 11 and located in display area 100A. In some embodiments, active layer 12 may include at least one of a low-temperature polysilicon active layer and a metal oxide active layer. For example, active layer 12 may include a low-temperature polysilicon active layer. In some embodiments, active layer 12 may have a thickness of 450 to 500 angstroms.

[0064] The gate insulating layer 13 covers the active layer 12 and the substrate 11 to isolate the active layer 12 from the first metal layer 141. In some embodiments, the gate insulating layer 13 may include a silicon oxide layer (SiO2), a silicon nitride layer (SiN x ) and at least one of a silicon oxynitride layer. Exemplarily, the gate insulating layer 13 may include a silicon oxide layer. In some embodiments, the thickness of the gate insulating layer 13 may be 1200 angstroms to 1400 angstroms.

[0065] The first metal layer 141 is located on the side of the gate insulating layer 13 facing away from the substrate 11. The first metal layer 141 includes a gate 142, which is located in the display area 100A and overlaps with the active layer 12. In this way, when a gate voltage is applied to the gate 142, the electric field generated by the gate voltage can act on the active layer 12. In some embodiments, the first metal layer 141 may also include, but is not limited to, a scan line. In some embodiments, the first metal layer 141 may include at least one of molybdenum, aluminum, titanium, copper, and silver. For example, the first metal layer 141 includes molybdenum, which has a low resistivity and helps reduce the resistance loss of the gate 142. In some embodiments, the thickness of the first metal layer 141 may be 2700 angstroms to 3000 angstroms.

[0066] Interlayer insulating layer 15 is located on a side of first metal layer 141 facing away from substrate 11 to isolate first metal layer 141 from other conductive layers on first metal layer 141. In some embodiments, interlayer insulating layer 15 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In some embodiments, interlayer insulating layer 15 may have a thickness of 4000 angstroms to 8000 angstroms.

[0067] The display panel 100 is also provided with a contact hole H1 and a first opening O1. The contact hole H1 is provided in the display area 100A, penetrates the interlayer insulating layer 15 and the gate insulating layer 13, and extends into the active layer 12. The first opening O1 is provided in the transparent area 100B, penetrates the interlayer insulating layer 15 and the gate insulating layer 13. That is, the interlayer insulating layer 15 and the gate insulating layer 13 in the transparent area 100B are removed to improve the transmittance of the transparent area 100B of the display panel 100. In this way, during the process of manufacturing the display panel 100, the same photomask can be used for exposure, followed by development and a single etching process of the gate insulating layer 13, the interlayer insulating layer 15, and the active layer 12 to form the contact hole H1 in the display area 100A and the first opening O1 in the transparent area 100B, thereby reducing the number of photomasks required to manufacture the display panel 100.

[0068] It should be noted that in some technologies, the contact hole only penetrates the gate insulating layer and the interlayer insulating layer and does not extend into the active layer. Furthermore, the first opening only penetrates the interlayer insulating layer. Therefore, the contact hole and the first opening have different depths and need to be produced using two separate photomasks.

[0069] However, in some embodiments of the present application, the contact hole H1 and the first opening O1 both penetrate the interlayer insulating layer 15 and the gate insulating layer 13, and the contact hole H1 further extends to the active layer 12, so that the contact hole H1 and the first opening O1 can be formed by sharing a mask and undergoing exposure, development and etching.

[0070] During the process of etching to form the contact hole H1 and the first opening O1, the depth of the contact hole H1 in the active layer 12 can be adjusted by adjusting the etching selectivity. In some embodiments, the contact hole H1 can penetrate a portion of the active layer 12. In other embodiments, the contact hole H1 can penetrate the entire active layer 12.

[0071] In some embodiments, the display panel 100 further includes a buffer layer 19. The buffer layer 19 is located between the substrate 11 and the active layer 12. The first opening O1 also penetrates the buffer layer 19 to remove the buffer layer 19 in the transparent area 100B, thereby further improving the light transmittance of the transparent area 100B.

[0072] In some embodiments, the contact hole H1 further extends into the buffer layer 19. The depth of the contact hole H1 in the buffer layer 19 is less than the thickness of the buffer layer 19.

[0073] In some embodiments, the display panel 100 further includes a light shielding layer 18, which is located between the buffer layer 19 and the substrate 11. The light shielding layer 18 overlaps the active layer 12 to shield the active layer 12 from light. In some embodiments, the light shielding layer 18 includes at least one of a metal and a black organic material. For example, the light shielding layer 18 may include molybdenum. In some embodiments, the thickness of the light shielding layer 18 may be 500 to 1000 angstroms.

[0074] In some embodiments, the driving circuit layer further includes a second metal layer 143. The second metal layer 143 is located on a side of the interlayer insulating layer 15 facing away from the substrate 11 and includes a contact electrode 144. The contact electrode 144 is located in the contact hole H1 and contacts the sidewalls of the active layer 12. The contact electrode 144 may include a source electrode and a drain electrode, each of which contacts the sidewalls of the active layer 12 through the two contact holes H1. In some embodiments, the second metal layer 143 may also include, but is not limited to, a data line.

[0075] In some embodiments, the second metal layer 143 may include at least one of molybdenum, aluminum, titanium, copper, and silver. For example, the second metal layer 143 may include a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence. In some embodiments, the second metal layer 143 may have a thickness of 6000 angstroms to 9000 angstroms.

[0076] It should be noted that the driving circuit layer includes a transistor, and the transistor includes a gate 142 , an active layer 12 and a contact electrode 144 .

[0077] In some embodiments, the display panel 100 further includes a planarization layer 16 , which is located on the side of the second metal layer 143 facing away from the substrate 11 to planarize the drive circuit layer. In some embodiments, the planarization layer 16 comprises an organic material, including but not limited to at least one of polyimide, acrylic resin, epoxy resin, polyester, and polyurethane. For example, the planarization layer 16 may comprise yellow or light yellow polyimide. In some embodiments, each planarization layer 16 may have a thickness of 15,000 to 20,000 angstroms.

[0078] In some embodiments, the display panel 100 further includes a passivation layer 17. The passivation layer 17 is located on the side of the planar layer 16 facing away from the substrate 11 to protect the film layer below the passivation layer 17. In some embodiments, the passivation layer 17 may include a silicon oxide layer (SiO2), a silicon nitride layer (SiN x ) and at least one of a silicon oxynitride layer.

[0079] In some embodiments, the display panel 100 is further provided with a second opening O2. The second opening O2 is located in the transparent region 100B and penetrates the passivation layer 17, overlapping the first opening O1. Thus, the passivation layer 17 located in the transparent region 100B is removed, further improving the light transmittance of the transparent region 100B of the display panel 100.

[0080] In some embodiments, the orthographic projection of the first opening O1 on the substrate 11 is located within the orthographic projection of the second opening O2 on the substrate 11 , that is, the size of the second opening O2 is larger than that of the first opening O1 .

[0081] In some embodiments, the display panel 100 is further provided with a third opening O3. The third opening O3 is located in the transparent region 100B and penetrates the planar layer 16. The third opening O3 is also connected to the first opening O1 and the second opening O2. Thus, the planar layer 16 located in the transparent region 100B is also removed, further improving the light transmittance of the transparent region 100B of the display panel 100.

[0082] In some embodiments, the orthographic projection of the third opening O3 on the substrate 11 is located within the orthographic projection of the second opening O2 on the substrate 11 , that is, the size of the third opening O3 is smaller than that of the second opening O2 .

[0083] In some embodiments, in a direction from the substrate 11 to the active layer 12 , ie, a thickness direction of the display panel 100 , an opening area of ​​each of the first opening O1 , the second opening O2 , and the third opening O3 increases gradually.

[0084] In some embodiments, the passivation layer 17 includes a first sidewall 17A defining the second opening O2. The planarization layer 16 includes a second sidewall 16A defining the third opening O3. The first sidewall 17A and the second sidewall 16A are coplanar. In this manner, the second opening O2 and the third opening O3 can be formed continuously. For example, after forming the second opening O2, the planarization layer 16 is etched using the passivation layer 17 as a mask to form the third opening O3, further reducing the number of photomasks required to manufacture the display panel 100.

[0085] The first side wall 17A and the second side wall 16A are both curved surfaces. When the first side wall 17A and the second side wall 16A are coplanar, they are co-curved surfaces.

[0086] In some embodiments, the angle a1 between the first sidewall 17A and the substrate 11 and the angle a2 between the second sidewall 16A and the substrate 11 are 70° to 85°. Thus, the first sidewall 17A and the second sidewall 16A both have appropriate angles with the substrate 11, thereby improving the light transmittance of both and reducing the difficulty of manufacturing the second opening O2 and the third opening O3.

[0087] It should be noted that in some technologies, since the second opening and the third opening are formed using two independent masks, the first sidewall and the second sidewall are staggered. In some embodiments of the present application, the third opening O3 is formed by etching using the passivation layer 17 as a mask, which can reduce one mask.

[0088] In some embodiments, the passivation layer 17 includes a first passivation layer 171. The display panel 100 also includes a third metal layer 145. The third metal layer 145 is located on the side of the planar layer 16 facing away from the substrate 11 and includes a binding electrode 146 located in the display area 100A. The first passivation layer 171 covers the third metal layer 145 and the planar layer 16 and is provided with a fourth opening O4. The fourth opening O4 is located in the display area 100A and exposes the binding electrode 146. The binding electrode 146 is electrically connected to the contact electrode 144. In this way, the first passivation layer 171 protects the binding electrode 146. At the same time, the fourth opening O4 on the first passivation layer 171 can also ensure that the binding electrode 146 is connected to the light-emitting device 21, so that the light-emitting device 21 is connected to the transistor in the driving circuit through the binding electrode 146.

[0089] In some embodiments, the first passivation layer 171 may include a silicon oxide layer (SiO2), a silicon nitride layer (SiN x ) and at least one of a silicon oxynitride layer. For example, the first passivation layer 171 may include a silicon nitride layer. In some embodiments, the thickness of the first passivation layer 171 may be 2000 angstroms to 3000 angstroms.

[0090] In some embodiments, the passivation layer 17 further includes a second passivation layer 172, which is located between the third metal layer 145 and the planar layer 16. During the etching process of the third metal layer 145, the second passivation layer 172 protects the planar layer 16, reducing the risk of damage to the planar layer 16 caused by the etching solution.

[0091] In some embodiments, the second passivation layer 172 may include a silicon oxide layer (SiO2), a silicon nitride layer (SiN x ) and at least one of a silicon oxynitride layer. For example, the second passivation layer 172 may include a silicon nitride layer. In some embodiments, the thickness of the second passivation layer 172 may be 1000 angstroms to 3000 angstroms.

[0092] The light emitting device 21 is located in the display area 100A and is bonded to the bonding electrode 146. The light emitting device 21 may include at least one of an inorganic light emitting diode, a micro light emitting diode (Micro-LED), and a sub-millimeter light emitting diode (Mini-LED). Exemplarily, the light emitting device 21 includes a micro light emitting diode.

[0093] In some embodiments, the interlayer insulating layer 15 includes a first interlayer insulating layer 151 and a second interlayer insulating layer 152. The display panel 100 also includes a fourth metal layer 147. The first interlayer insulating layer 151 covers the first metal layer 141 and the gate insulating layer 13. The fourth metal layer 147 is located on the side of the first interlayer insulating layer 151 facing away from the substrate 11 and includes an electrode plate 148. The electrode plate 148 overlaps with the gate 142. The second interlayer insulating layer 152 covers the fourth metal layer 147 and the first interlayer insulating layer 151. In this way, the electrode plate 148 and the gate 142 respectively constitute two electrode plates 148 of a capacitor. As a component of the driving circuit, the capacitor can improve the display effect of the display panel 100.

[0094] In some embodiments, the first interlayer insulating layer 151 may include a silicon oxide layer (SiO2), a silicon nitride layer (SiN x ) and at least one of a silicon oxynitride layer. Exemplarily, the first interlayer insulating layer 151 may include a silicon nitride layer. In some embodiments, the thickness of the first interlayer insulating layer 151 may be 1000 angstroms to 1400 angstroms.

[0095] In some embodiments, the second interlayer insulating layer 152 may include a silicon oxide layer (SiO2), a silicon nitride layer (SiN x ) and at least one of a silicon oxynitride layer. For example, the first interlayer insulating layer 151 may include a silicon nitride layer and a silicon oxide layer stacked in sequence. In some embodiments, the thickness of the second interlayer insulating layer 152 may be 4000 angstroms to 6000 angstroms.

[0096] In some embodiments, the planarization layer 16 includes a first planarization layer 161, a second planarization layer 162, and a third planarization layer 163. The display panel 100 also includes a first conductive layer 201 and a second conductive layer 203. The first planarization layer 161 covers the second metal layer 143 and the interlayer insulating layer 15. The first conductive layer 201 is located on the side of the first planarization layer 161 facing away from the substrate 11. The second planarization layer 162 covers the first conductive layer 201 and the first planarization layer 161. The second conductive layer 203 is located on the side of the second planarization layer 162 facing away from the substrate 11. The third planarization layer 163 covers the second conductive layer 203 and the second planarization layer 162.

[0097] Furthermore, the first conductive layer 201 may include a first strapping electrode 202, which is connected to the contact electrode 144 via a first strapping hole in the first planar layer 161. The second conductive layer 203 may include a second strapping electrode 204, which may be connected to the first strapping electrode 202 via a second strapping hole in the second planar layer 162. The binding electrode 146 may be connected to the second strapping electrode 204 via a third strapping hole. The third strapping hole penetrates the third planar layer 163 and the second passivation layer 172.

[0098] In some embodiments, the first conductive layer 201 may further include a first power line, and the second conductive layer 203 may further include a second power line. The first power line may be used to transmit a first power voltage, which may be a positive voltage such as VDD. The second power line may be used to transmit a second power voltage, which may be a negative voltage such as VSS.

[0099] Combining the above content, it can be seen that for the embodiments of this application Figure 1 In the display panel 100 shown in FIG, since the formation process of the contact hole H1 and the first opening O1 uses a common photomask, and etching the remaining passivation layer as a mask layer to form the third opening O3 can also save a photomask. Figure 1 The display panel 100 shown can save two photomasks.

[0100] Figure 2 This is another schematic cross-sectional view of a display panel provided in an exemplary embodiment of the present application.

[0101] Figure 2 The display panel 100 is shown with Figure 1 The display panel 100 shown is substantially similar, and similarities are not further described. Differences include: the transmittance of the planar layer 16 is greater than or equal to 90%. The planar layer 16 is located in the display area 100A and the transparent area 100B, and fills the first opening O1. As such, due to the high transmittance of the planar layer 16, even if the planar layer 16 in the transparent area 100B is retained to fill the first opening O1, the transmittance of the transparent area 100B is not significantly affected. Furthermore, since the planar layer 16 in the transparent area 100B is retained, the etching process of the planar layer 16 in the transparent area 100B can be omitted, thereby eliminating the photomask exposure process prior to the etching process, thereby saving a photomask.

[0102] In some embodiments, the light transmittance of the planar layer 16 may be greater than or equal to 95%, so as to further improve the light transmittance of the planar layer 16 .

[0103] In some embodiments, the planar layer 16 may include transparent polyimide, such that the light transmittance of the planar layer 16 is greater than or equal to 90%. The transparent polyimide may be chemically modified based on ordinary polyimide to reduce the conjugated structure within the molecule and add transparent groups (such as fluoride or other low refractive index groups) to improve the transparency of the material.

[0104] Exemplarily, the display panel includes two or more planar layers, and each planar layer includes transparent polyimide.

[0105] It should be noted that the test conditions for the transmittance of the flat layer 16 include: (1) using a light source to emit visible light with a wavelength of 380nm to 780nm to vertically irradiate the flat layer 16, that is, the visible light is perpendicular to the surface of the flat layer 16; (2) using a photometer to measure the intensity of the incident light before the visible light passes through the flat layer 16; (3) using a photometer to measure the intensity of the transmitted light after the visible light passes through the flat layer 16; (4) dividing the transmitted light intensity by the incident light intensity, and then multiplying the result by 100% to obtain the transmittance.

[0106] In some embodiments, Figure 2 The display panel 100 shown also differs in that the second opening O2 may include a first sub-opening O21 and a second sub-opening O22 that are interconnected. The first sub-opening O21 penetrates the first passivation layer 171, which includes a third sidewall 171A that defines the first sub-opening O21. The second sub-opening O22 penetrates the second passivation layer 172, which includes a fourth sidewall 172A that defines the second sub-opening O22. The third sidewall 171A and the fourth sidewall 172A are offset. In this way, two photomasks can be used to form the first sub-opening O21 and the fourth opening O4, respectively. For example, the first sub-opening O21 and the fourth opening O4 can be formed using a common photomask, while the second sub-opening O22 and the overlap hole provided in the second passivation layer 172 in the display area 100A can be formed using a common photomask. In other words, there is no need to use separate photomasks to form the first sub-opening O21 and the second sub-opening O22, thereby reducing the number of photomasks required to manufacture the display panel 100.

[0107] It can be seen from this that for the embodiments of this application Figure 2 In the display panel 100 shown, since the formation process of the contact hole H1 and the first opening O1 uses the same mask, the planar layer 16 of the transparent area 100B does not need to be etched, and the first sub-opening O21 and the second sub-opening O22 of the second opening O2 do not need additional independent masks. Figure 2 The display panel 100 shown can save three photomasks.

[0108] Figure 3This is another schematic cross-sectional structure diagram of a display panel provided in an exemplary embodiment of the present application.

[0109] Figure 3 The display panel 100 is shown with Figure 2 The display panel 100 shown is basically similar, and the similarities are not repeated here. The differences include that the third opening O3 passes through the flat layer 16, that is, the flat layer 16 in the transparent area 100B is removed to improve the transmittance of the transparent area 100B and ensure the transparent display function of the display panel 100.

[0110] In some embodiments, the transparent polyimide of the planar layer 16 may further include a photosensitive group. Thus, by exposing and developing the planar layer 16 , the planar layer 16 in the transparent area 100B is removed, thereby forming the third opening O3 .

[0111] It should be noted that when planarization layer 16 includes first to third planarization layers 161, 163, overexposure compensation is required during exposure of each layer. This compensation is typically set to greater than 0.5 μm, meaning that the difference between the actual opening size in the planarization layer and the opening size on the mask is greater than 0.5 μm. This can be adjusted based on the actual film thickness, opening size, and opening depth of each layer in planarization layer 16 to avoid residual planarization layer 16 residue at the third opening O3.

[0112] Figure 4 This is another schematic cross-sectional structure diagram of a display panel provided in an exemplary embodiment of the present application.

[0113] Figure 4 The display panel 100 is shown with Figure 3 The display panel 100 shown is substantially similar except that: Figure 4 The passivation layer 17 of the display panel 100 shown does not include the second passivation layer 172. As such, a photomask required for patterning the second passivation layer 172 can be omitted.

[0114] Figure 5 Schematic diagram of a process for manufacturing a display panel provided in an exemplary embodiment of the present application.

[0115] like Figure 5 and Figure 6 As shown, the display panel has a display area 100A and a transparent area 100B. The manufacturing method of the display panel includes:

[0116] Step S101 , forming an active layer 12 on a substrate 11 , wherein the active layer 12 is located in the display area 100A;

[0117] Step S102 , forming a gate insulating layer 13 , wherein the gate insulating layer 13 covers the active layer 12 and the substrate 11 ;

[0118] Step S103 , forming a first metal layer 141 , the first metal layer 141 is located on a side of the gate insulating layer 13 facing away from the substrate 11 and includes a gate 142 , the gate 142 is located in the display area 100A and overlaps with the active layer 12 ;

[0119] Step S104 , forming an interlayer insulating layer 15 , the interlayer insulating layer 15 being located on a side of the first metal layer 141 facing away from the substrate 11 ;

[0120] In step S105, a single exposure and development process and a single etching process are used to remove part of the gate insulating layer 13, part of the interlayer insulating layer 15, and part of the active layer 12 to form a contact hole H1 and a first opening O1. The contact hole H1 is located in the display area 100A and penetrates the interlayer insulating layer 15 and the gate insulating layer 13, and extends into the active layer 12; the first opening O1 is located in the transparent area 100B and penetrates the interlayer insulating layer 15 and the gate insulating layer 13.

[0121] In some embodiments of the present application, after the active layer 12, the gate insulating layer 13, the first metal layer 141 and the interlayer insulating layer 15 are formed, the same mask can be used for exposure, and then the gate insulating layer, the interlayer insulating layer and the active layer are developed and etched once to form the contact hole H1 of the display area 100A and the first opening O1 of the transparent area 100B, thereby saving the mask required to independently form the first opening O1 and reducing the production cost of the display panel 100.

[0122] In some embodiments, before step S101, the method for manufacturing the display panel 100 further includes: step S100, forming a light shielding layer 18 on the substrate 11, and forming a buffer layer 19 covering the light shielding layer 18 and the substrate 11. In this way, the light shielding layer 18 is used to shield the subsequently formed active layer 12 from light, thereby improving the problem of leakage of the active layer 12 due to light exposure.

[0123] In some embodiments, after step S105, as Figure 7 As shown, the method for manufacturing the display panel 100 further includes step S106, i.e., forming a second metal layer 143. The second metal layer 143 is located on a side of the interlayer insulating layer 15 facing away from the substrate 11 and includes a contact electrode 144. The contact electrode 144 is located in the contact hole H1 and contacts the sidewall of the active layer 12. In this way, the connection between the contact electrode 144 and the active layer 12 is achieved.

[0124] In some embodiments, after step S106, as Figure 7As shown, the manufacturing method of the display panel 100 further includes step S107, that is, forming a planar layer 16. The planar layer 16 is located on the side of the second metal layer 143 facing away from the substrate 11, is also located in the display area 100A and fills the first opening O1. In this way, the planar layer 16 plays a planarizing role.

[0125] In some embodiments, after step S107, as Figure 7 As shown, the manufacturing method of the display panel 100 further includes step S108, i.e. forming a passivation layer 17. The passivation layer 17 is located on the side of the flat layer 16 facing away from the substrate 11 and is located in the display area 100A and the transparent area 100B. In this way, the passivation layer 17 plays a protective role for the film layers below it.

[0126] In some embodiments, after step S108, as Figure 7 As shown, the manufacturing method of the display panel 100 further includes:

[0127] Step S109 , patterning the passivation layer 17 to form a remaining passivation layer 17 and a second opening O2 penetrating the passivation layer 17 . The second opening O2 is located in the transparent region 100B and penetrates the passivation layer 17 , and overlaps with the first opening O1 .

[0128] Step S110 : Using the remaining passivation layer 17 as a mask, the planar layer 16 is patterned through the second opening O2 to form a third opening O3 penetrating the planar layer 16 . The third opening O3 is located in the transparent region 100B and communicates with the second opening O2 and the first opening O1 .

[0129] In some embodiments of the present application, after the passivation layer 17 is patterned to form the second opening O2, the planar layer 16 is patterned using the remaining passivation layer 17 as a mask to remove the planar layer 16 from the transparent region 100B. This eliminates the need for a mask to form the third opening O3, thereby reducing the manufacturing cost of the display panel 100.

[0130] In some embodiments, after step S110, as Figure 1 As shown, the method for manufacturing the display panel 100 further includes step S111, namely, patterning the first passivation layer 171 of the display area 100A to form a fourth opening O4 penetrating the first passivation layer 171, wherein the fourth opening O4 exposes the binding electrode 146. Thus, when the passivation layer 17 is used as a mask, the second opening O2 and the third opening O3 need to be formed first, and then the fourth opening O4 is formed, to reduce the risk of damage to the third metal layer 145 caused by forming the second opening O2 and the third opening O3.

[0131] It should be noted that for Figure 1In the display panel 100 shown, each of the light shielding layer 18, the active layer 12, the first metal layer 141 to the fourth metal layer 147, and the first conductive layer 201 to the second conductive layer 203 requires a separate photomask. Furthermore, each of the first flat layer 161 to the third flat layer 163, the first passivation layer 171, and the second passivation layer 172 in the display area 100A requires a separate photomask. Furthermore, the first opening O1 and the contact hole H1 share a photomask. The second opening O2 requires a separate photomask. Therefore, Figure 1 The number of photomasks required for the display panel 100 shown may be fifteen.

[0132] In some embodiments, as Figure 2 As shown, after step S106, the method for manufacturing the display panel 100 may include:

[0133] A planar layer 16 is formed. The transmittance of the planar layer 16 is greater than or equal to 90%. The planar layer 16 is located on the side of the second metal layer 143 facing away from the substrate 11 , and is also located in the display area 100A and the transparent area 100B and fills the first opening O1 .

[0134] In some embodiments of the present application, when the transmittance of the flat layer 16 is high, the flat layer 16 of the transparent area 100B is retained, so the etching process of the flat layer 16 of the transparent area 100B can be omitted, and then the mask exposure process before the etching process can be omitted, thereby saving a mask.

[0135] In some embodiments, as Figure 3 As shown, after forming the second opening O2 , the manufacturing method of the display panel 100 may further include: removing the planar layer 16 of the transparent area 100B to form a third opening O3 .

[0136] In some embodiments, the planar layer 16 in the transparent area 100B can be removed by performing an exposure and development process on the planar layer 16. During the exposure process of the planar layer 16 in the transparent area 100B, it is necessary to compensate for the overexposure of the planar layer 16 to improve the problem of the planar layer 16 remaining in the third opening O3.

[0137] In summary, in the display panel and its manufacturing method according to the embodiments of the present application, the contact hole in the display area penetrates the interlayer insulating layer and the gate insulating layer and extends into the active layer, and the first opening in the transparent area penetrates the interlayer insulating layer and the gate insulating layer. This allows the same photomask to be used for exposure to form the contact hole in the display area and the first opening in the transparent area, reducing the number of photomasks required to manufacture the display panel.

[0138] The description of the above embodiments is only used to help understand the technical solutions and core ideas of this application; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that: The display panel has a display area and a transparent area, and includes: substrate; an active layer, disposed on the substrate and located in the display area; a gate insulating layer, covering the active layer and the substrate; a first metal layer, located on a side of the gate insulating layer facing away from the substrate, and comprising a gate, wherein the gate is located in the display area and overlaps with the active layer; an interlayer insulating layer, located on a side of the first metal layer facing away from the substrate; a contact hole, located in the display area, penetrating the interlayer insulating layer and the gate insulating layer, and extending into the active layer; The first opening is located in the transparent area and penetrates the interlayer insulating layer and the gate insulating layer.

2. The display panel according to claim 1, wherein: Also includes: a second metal layer, located on a side of the interlayer insulating layer facing away from the substrate, and comprising a contact electrode, wherein the contact electrode is located in the contact hole and contacts a sidewall of the active layer; a flat layer, located on a side of the second metal layer facing away from the substrate; a passivation layer, located on a side of the planar layer facing away from the substrate; The second opening is located in the transparent area and penetrates the passivation layer, and also overlaps with the first opening.

3. The display panel according to claim 2, wherein: Also includes: The third opening is located in the transparent area and passes through the flat layer, and is also communicated with the first opening and the second opening.

4. The display panel according to claim 3, wherein: The passivation layer includes a first sidewall defining the second opening, the planarization layer includes a second sidewall defining the third opening, and the first sidewall is coplanar with the second sidewall.

5. The display panel according to claim 2, wherein: The light transmittance of the planar layer is greater than or equal to 90%. The planar layer is located in the display area and the transparent area and fills the first opening.

6. The display panel according to claim 2, wherein: The passivation layer includes a first passivation layer, and the display panel also includes a third metal layer and a light-emitting device. The third metal layer is located on the side of the flat layer away from the substrate and includes a binding electrode located in the display area. The first passivation layer covers the third metal layer and the flat layer and is provided with a fourth opening. The fourth opening is located in the display area and exposes the binding electrode. The light-emitting device is located in the display area and bound to the binding electrode. The binding electrode is electrically connected to the contact electrode.

7. The display panel according to claim 6, wherein: The passivation layer further includes a second passivation layer, and the second passivation layer is located between the third metal layer and the planar layer.

8. A method for manufacturing a display panel, characterized in that: The display panel has a display area and a transparent area, and the method includes: forming an active layer on a substrate, wherein the active layer is located in the display area; forming a gate insulating layer, wherein the gate insulating layer covers the active layer and the substrate; forming a first metal layer, the first metal layer being located on a side of the gate insulating layer facing away from the substrate and comprising a gate, the gate being located in the display area and overlapping the active layer; forming an interlayer insulating layer, wherein the interlayer insulating layer is located on a side of the first metal layer facing away from the substrate; A single exposure and development process, as well as a single etching process, are used to remove part of the gate insulating layer, part of the interlayer insulating layer, and part of the active layer to form a contact hole and a first opening. The contact hole is located in the display area and passes through the interlayer insulating layer and the gate insulating layer and extends into the active layer. The first opening is located in the transparent area and passes through the interlayer insulating layer and the gate insulating layer.

9. The method for manufacturing a display panel according to claim 8, wherein: Also includes: forming a second metal layer, the second metal layer being located on a side of the interlayer insulating layer facing away from the substrate and comprising a contact electrode, the contact electrode being located in the contact hole and contacting a sidewall of the active layer; A planar layer is formed. The planar layer is located on a side of the second metal layer facing away from the substrate, is also located in the display area, and fills the first opening.

10. The method for manufacturing a display panel according to claim 9, wherein: Also includes: forming a passivation layer, wherein the passivation layer is located on a side of the planar layer facing away from the substrate; performing a patterning process on the passivation layer to form a remaining passivation layer and a second opening penetrating the passivation layer, wherein the second opening is located in the transparent region, penetrates the passivation layer, and overlaps with the first opening; The remaining passivation layer is used as a mask, and the planar layer is patterned through the second opening to form a third opening penetrating the planar layer. The third opening is located in the transparent area and communicates with the second opening and the first opening.

Images