Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a manufacturing method thereof. The display panel comprises a substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, a common line, an interlayer insulating layer, a pixel electrode, a source electrode, a drain electrode, a passivation layer and a common electrode. The interlayer insulating layer is provided with a first through hole, and the first through hole penetrates through the interlayer insulating layer and exposes the common line. A second through hole is formed in the position, corresponding to the first through hole, of the passivation layer, and the second through hole is connected with the first through hole in a sleeving mode. The display panel further comprises a metal pad arranged in the first through hole, the metal pad, the source electrode and the drain electrode are arranged on the same layer, the metal pad is arranged on the bottom face and the side wall of the first through hole and the periphery of the opening of the first through hole, and the metal pad makes contact with the common line. The second through hole exposes a part of the metal pad, and the common electrode is in contact with the metal pad through the second through hole. By adding the metal pad between the passivation layer and the interlayer insulating layer sleeve hole, the yield of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] Low-temperature polysilicon (LTPS) thin-film transistors (TFTs) are key components of display panels such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays. To save manufacturing costs and lower product costs, the industry has been working to reduce the number of process steps.

[0003] Currently, display panel manufacturing often uses the 9-mask process. While this process is mature and reliable, it has many steps and high manufacturing costs. To simplify the process and reduce costs, the industry has proposed a 6-mask process. This process eliminates the light shielding layer and planarization layer processes and utilizes halftone mask technology to form the pixel electrode and interlayer insulation layer in the same process, thus reducing the number of masks.

[0004] In the 6 Mask process, in order to make the common voltage in the display panel more uniform, a common line set on the same layer as the gate is usually used to provide a common voltage signal to the common electrode. However, there is a situation where the common line and the common electrode cannot be properly connected. This technical problem reduces the yield of the display panel product.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a display panel and a manufacturing method thereof, aiming to improve the yield of the display panel.

[0007] An embodiment of the present application provides a display panel, comprising: a gate; a common line, the common line and the gate being located in the same film layer; an interlayer insulating layer arranged on the gate, the interlayer insulating layer being provided with a first through hole, the first through hole penetrating the interlayer insulating layer and exposing at least a portion of the common line; a pixel electrode, a source electrode, and a drain electrode arranged on the interlayer insulating layer; a passivation layer arranged on the source electrode, the drain electrode, the pixel electrode, and the interlayer insulating layer, the passivation layer being provided with a second through hole at a position corresponding to the first through hole, the second through hole being connected to the first through hole; a common electrode arranged on the passivation layer; and a metal pad arranged in the first through hole, the metal pad being located in the same film layer as the source electrode and the drain electrode, the metal pad being arranged on the bottom surface and sidewalls of the first through hole, and on the periphery of the opening of the first through hole, the metal pad being in contact with the common line; wherein the second through hole exposes a portion of the metal pad, and the common electrode is in contact with the metal pad through the second through hole.

[0008] In the above-mentioned display panel, the display panel also includes an annular metal component, which is arranged on the periphery of the opening of the first through hole, the annular metal component surrounds the opening of the first through hole, the annular metal component is arranged on the interlayer insulating layer, and the part of the metal pad located outside the first through hole is arranged on the annular metal component.

[0009] In the above display panel, a ratio of an area of ​​the annular metal member to an area of ​​a portion of the metal pad located outside the first through hole is less than 1.

[0010] In the above display panel, an inner edge of the annular metal member is flush with an edge of the opening of the first through hole.

[0011] In the above display panel, the annular metal component and the pixel electrode are located in the same film layer, and the pixel electrode and the annular metal component are made of the same material.

[0012] In the above display panel, the metal pad is disposed on the interlayer insulating layer at the periphery of the opening of the first through hole.

[0013] In the above display panel, the source electrode, the drain electrode and the metal pad are located in the same film layer, and the source electrode, the drain electrode and the metal pad are made of the same material.

[0014] In the above display panel, when looking down at the display panel, the metal pad is located between the main portion of the common line and the gate line electrically connected to the gate.

[0015] In the above-mentioned display panel, when looking down at the display panel, in a direction perpendicular to the length direction of the common line, the size of the metal pad is larger than half the width of the gap between the main body of the common line and the gate line, and smaller than the width of the gap.

[0016] In the above display panel, when looking down at the display panel, in a direction perpendicular to the length direction of the common line, the size of the metal pad is larger than the width of the main body of the common line or the width of the gate line.

[0017] An embodiment of the present application also provides a method for manufacturing a display panel, the manufacturing method comprising: forming a gate and a common line on a gate insulating layer; forming an interlayer insulating layer on the gate insulating layer, the gate and the common line; forming a pixel electrode on the interlayer insulating layer; forming a first through hole in the interlayer insulating layer, the first through hole penetrating the interlayer insulating layer and exposing the common line; forming a source, a drain and a metal pad in the first through hole and on the interlayer insulating layer, the metal pad being arranged on the bottom surface and side walls of the first through hole, and on the periphery of the opening of the first through hole, the metal pad being in contact with the common line; forming a passivation layer on the source, the drain, the metal pad, the pixel electrode and the interlayer insulating layer; forming a second through hole on the passivation layer at a position corresponding to the first through hole, the second through hole exposing a portion of the metal pad; and forming a common electrode on the passivation layer, the common electrode being in contact with the metal pad through the second through hole.

[0018] In the above-mentioned manufacturing method, the step of forming a source, a drain and a metal pad in the first through hole and on the interlayer insulating layer includes: forming a source-drain metal layer in the first through hole and on the interlayer insulating layer; and patterning the source-drain metal layer to form the source, the drain and the metal pad.

[0019] In the above manufacturing method, the manufacturing method further includes: forming an annular metal component on the same layer as the pixel electrode during the process of forming the pixel electrode, and the annular metal component is arranged on the interlayer insulating layer at the periphery of the opening of the first through hole.

[0020] In the above manufacturing method, the step of forming the first through hole in the interlayer insulating layer includes: etching the interlayer insulating layer at the hollowed portion of the annular metal member serving as a mask to form the first through hole.

[0021] The display panel and its manufacturing method of the present application include a metal pad disposed within a first through-hole provided in the interlayer insulating layer. The metal pad is formed from the same layer and material as the source and drain electrodes. This structural design enables the metal pad to be formed simultaneously with the source and drain electrodes in the same process step, eliminating the need for additional process steps. Furthermore, because the metal pad is disposed on the bottom surface and sidewalls of the first through-hole, as well as around the opening of the first through-hole, it fully covers and protects the underlying common line, preventing it from being etched during wet etching of the source and drain metal layers, thereby ensuring a reliable electrical connection between the common line and the common electrode.

[0022] The display panel and its manufacturing method provided in the present application adopt a technical solution of adding a metal pad between the passivation layer and the interlayer insulating layer sleeve hole. While maintaining the simplified advantage of the 6 Mask process, it effectively solves the problem of common lines being etched during the wet etching process, ensures reliable electrical connection between the common lines and the common electrodes, improves the manufacturing yield and product reliability of the display panel, and achieves the goals of reducing manufacturing costs, improving production efficiency and display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram illustrating the phenomenon of common lines being etched in a traditional display panel.

[0024] Figure 2 This is a block diagram of the display panel provided in this application.

[0025] Figure 3 is a schematic diagram of a first embodiment of a display panel provided in this application.

[0026] Figure 4 This is a layout of a partial area of ​​the first embodiment of the display panel provided in this application.

[0027] Figure 5 is a schematic diagram of a second embodiment of a display panel provided in this application.

[0028] Figures 6 to 11 It is a schematic diagram of the method for manufacturing a display panel provided in this application. DETAILED DESCRIPTION

[0029] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0030] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0031] The embodiments of the present application may be combined with each other.

[0032] The display panel provided in the embodiments of the present application may be, for example, a liquid crystal display panel.

[0033] like Figure 2 As shown, the display panel includes a display area and a non-display area, and the display area is provided with m×n pixels arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of gate lines, a plurality of data lines and a gate drive circuit. The plurality of gate lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit is provided in the non-display area and is electrically connected to the plurality of gate lines. The source drive circuit is electrically connected to the plurality of data lines through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit, respectively.

[0034] The display panel includes a thin-film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin-film transistor array substrate includes a glass substrate, a first metal layer disposed on the glass substrate, a gate insulating layer disposed on the first metal layer, a semiconductor layer disposed on the gate insulating layer, a second metal layer disposed on the semiconductor layer, a passivation layer disposed on the second metal layer, and a pixel electrode disposed on the passivation layer. The first metal layer includes gate lines and gate electrodes. The second metal layer includes data lines, source electrodes, drain electrodes, etc. The opposing substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0035] Each pixel includes at least one thin-film transistor and a pixel electrode. The thin-film transistor's gate is electrically connected to the corresponding gate line, its source is electrically connected to the corresponding data line, and its drain is electrically connected to the corresponding pixel electrode. When the gate line outputs a high-level scanning signal, the thin-film transistor turns on, and the data signal on the data line is transmitted to the pixel electrode through the thin-film transistor. When the gate line outputs a low-level scanning signal, the thin-film transistor turns off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0036] The gate drive circuit includes n cascaded gate drive sub-circuits, each of which is electrically connected to a gate line. Under the control of a timing controller, the gate drive sub-circuits sequentially output scanning signals to scan each row of pixels in the display area row by row.

[0037] In one embodiment of the present application, a display panel is provided. The display panel is manufactured using a 6-mask process. Compared with the traditional 9-mask process, the light shielding layer (LS) process and the planarization layer (PLN) process are omitted, and the pixel electrode and the interlayer insulating layer are formed in the same process through the halftone mask technology, thereby reducing the number of masks and lowering the manufacturing cost.

[0038] Specifically, if Figure 3 、 Figure 4 and Figure 5 As shown, the thin-film transistor array substrate of the display panel includes a substrate 301, a buffer layer 302, a semiconductor layer 303, a gate insulating layer 304, a gate electrode 305, a common line 307, an interlayer insulating layer 306, a pixel electrode 312, a source electrode 313, a drain electrode 314, a passivation layer 315, and a common electrode 317. Substrate 301 is a glass substrate, and buffer layer 302 is disposed on substrate 301. Semiconductor layer 303 is disposed on buffer layer 302 and is made of low-temperature polysilicon (LTPS). After doping, semiconductor layer 303 forms a source region, a drain region, and a channel region. Gate insulating layer 304 is disposed on semiconductor layer 303 and buffer layer 302 to insulate semiconductor layer 303 from gate electrode 305. The gate 305 and common line 307 are disposed on the gate insulating layer 304. The common line 307 and the gate 305 are located in the same film layer and are made of the same material (molybdenum (Mo)). An interlayer insulating layer 306 is disposed on the gate 305 and the gate insulating layer 304 to insulate the gate 305 from the source 313 and the drain 314.

[0039] The source electrode 313, drain electrode 314, and pixel electrode 312 are disposed on the interlayer insulating layer 306. The source electrode 313 and drain electrode 314 are made of a multilayer metal material: molybdenum-aluminum-molybdenum (MoAlMo). The pixel electrode 312 is made of a transparent conductive material, such as indium tin oxide (ITO). In this embodiment, the pixel electrode 312 is a bottom transparent electrode (BITO). A passivation layer 315 is disposed on the source electrode 313, drain electrode 314, pixel electrode 312, and interlayer insulating layer 306. A common electrode 317 is disposed on the passivation layer 315 and is made of a transparent conductive material, such as indium tin oxide. In this embodiment, the common electrode 317 is a top transparent electrode (TITO).

[0040] In this display panel, the interlayer insulating layer 306 is provided with a first through-hole 309, which penetrates the interlayer insulating layer 306 and exposes at least a portion of the protrusion 3072 of the common line 307. The passivation layer 315 is provided with a second through-hole 316 at a position corresponding to the first through-hole 309. The second through-hole 316 is nested with the first through-hole 309 to form a nested hole. The display panel also includes a metal pad 308 disposed within the first through-hole 309. The metal pad 308 is located on the same film layer as the source electrode 313 and the drain electrode 314. The metal pad 308 is disposed on the bottom surface and sidewalls of the first through-hole 309, as well as around the opening of the first through-hole 309. The metal pad 308 is in contact with (electrically connected to) the protrusion 3072 of the common line 307. The second through-hole 316 exposes a portion of the metal pad 308. The common electrode 317 contacts the metal pad 308 through the second through-hole 316, thereby achieving electrical connection between the common electrode 317 and the common line 307. The metal pad 308 protects the protrusion 3072 of the common line 307, preventing the protrusion 3072 of the common line 307 from being etched away during the wet etching process.

[0041] In this display panel, the drain electrode 314 is electrically connected to the pixel electrode 312. Because the pixel electrode 312 is formed before the source electrode 313 and the drain electrode 314, at least a portion of the drain electrode 314 overlaps at least a portion of the pixel electrode 312. The source electrode 313 is electrically connected to the semiconductor layer 303 via a third through-hole 310 that penetrates the gate insulating layer 304 and the interlayer insulating layer 306. The drain electrode 314 is electrically connected to the semiconductor layer 303 via a fourth through-hole 311 that penetrates the gate insulating layer 304 and the interlayer insulating layer 306. The first through-hole 309, the third through-hole 310, and the fourth through-hole 311 are formed in the same manufacturing process.

[0042] In order to make the common voltage in the display panel more uniform, the present application provides a common voltage signal to the common electrode 317 through the common line 307 provided in the same layer as the gate 305 in the display panel. This design can reduce the signal transmission path, reduce signal delay, and improve display quality. However, in the actual production process, it was found that Figure 1 As shown, during the wet etching of the source and drain metal (made of MoAlMo) to form the source and drain electrodes, the common line 101 (made of Mo) beneath the via 102 is also etched away, resulting in a loss of connection between the common line 101 and the common electrode. This is because the wet etchant used to etch MoAlMo also etches the Mo material. When the two materials are in direct contact and exposed to the same etching environment, it is impossible to selectively etch only the MoAlMo without affecting the Mo.

[0043] In order to solve the above problems, Figure 3 、 Figure 4 and Figure 5As shown, the display panel of the present application adds a metal pad 308 between the passivation layer 315 and the interlayer insulating layer 306. The metal pad 308 is on the same layer as the source 313 and the drain 314, and is made of the same material (MoAlMo). The metal pad 308 is arranged on the bottom surface and sidewall of the first through hole 309, as well as on the periphery of the opening of the first through hole 309. The metal pad 308 contacts the protrusion 3072 of the common line 307, and a portion of the passivation layer 315 is arranged on the metal pad 308. The second through hole 316 exposes a portion of the metal pad 308, while no longer exposing a portion of the protrusion 3072 of the common line 307. The common electrode 317 contacts the metal pad 308 through the second through hole 316, thereby being electrically connected to the protrusion 3072 of the common line 307. During the wet etching process for forming the source 313 and drain 314, the metal pad 308 covers and protects the protruding portion 3072 of the common line 307, preventing the protruding portion 3072 of the common line 307 from being etched away. Furthermore, because the metal pad 308 is formed in the same layer and material as the source 313 and drain 314, it can be formed in the same process step, without adding additional manufacturing cost or process complexity.

[0044] When looking down at the display panel, the metal pad 308 is located between the main portion 3071 of the common line 307 and the gate line electrically connected to the gate 305. Specifically, the main portion 3071 of the common line 307 extends along a first direction, the gate line extends along the first direction and is arranged parallel to the main portion 3071 of the common line 307, and the metal pad 308 is arranged in the gap area between the main portion 3071 of the common line 307 and the adjacent gate line. This can make full use of the space between the gate line and the common line 307 in the display panel, avoid the metal pad 308 occupying the opening area of ​​the pixel, and thus will not affect the transmittance and display effect of the display panel. At the same time, this can also enable the metal pad 308 to effectively form a reliable electrical connection with the protrusion 3072 of the common line 307, ensure the stable transmission of the common voltage signal, and improve the electrical performance and display uniformity of the display panel.

[0045] When looking down at the display panel, in a direction perpendicular to the length of the common line 307, the size W1 of the metal pad 308 is greater than half the width W2 of the gap between the main portion 3071 of the common line 307 and the gate line, and is less than the width W2 of the gap. This ensures that the metal pad 308 has sufficient area to form good electrical contact with the protrusion 3072 of the common line 307, reducing contact resistance, while not excessively occupying the gap space, avoiding the risk of short circuits with adjacent gate lines. In addition, this is also conducive to maintaining good process tolerances during the manufacturing process. Even in the case of slight deviations in the photolithography alignment, it can ensure reliable connection between the metal pad 308 and the common line 307, thereby improving the manufacturing yield and product reliability of the display panel.

[0046] When looking down at the display panel, in a direction perpendicular to the length direction of the common line 307, the size W1 of the metal pad 308 is greater than the width W3 of the main portion 3071 of the common line 307 or the width W4 of the gate line. This ensures that the metal pad 308 has a sufficiently large contact area, which can effectively reduce the contact resistance between the metal pad 308 and the common line 307 and improve the reliability of the electrical connection. The larger size of the metal pad 308 can also provide better current carrying capacity, reduce electromigration caused by excessive current density, and extend the service life of the display panel. At the same time, this also enhances the protective effect of the metal pad 308 on the common line 307, and can more comprehensively cover and protect the protrusion 3072 of the common line 307 during the wet etching process, preventing the infiltration of the etching solution and accidental etching of the common line 307.

[0047] This application provides two embodiments. Figure 3 and Figure 4As shown, in the first embodiment, the display panel also includes an annular metal member 318, which is arranged at the periphery of the opening of the first through hole 309, the annular metal member 318 surrounds the opening of the first through hole 309, the annular metal member 318 is arranged on the interlayer insulating layer 306, and the portion of the metal pad 308 located outside the first through hole 309 is arranged on the annular metal member 318, that is, the annular metal member 318 is located between the metal pad 308 and the interlayer insulating layer 306, and the annular metal member 318 and the pixel electrode 312 are located in the same film layer. The ratio of the area of ​​the annular metal member 318 to the area of ​​the portion of the metal pad 308 located outside the first through hole 309 is less than 1. Specifically, the ratio of the areas of the two is between 0.3 and 0.9. This ensures that the annular metal member 318 can provide the necessary support and positioning functions for the metal pad 308 without excessively occupying the space of the pixel area. Since the annular metal member 318 is made of a transparent conductive material, although it has a certain degree of light transmittance, its excessive area will still affect the light transmittance of the area. By controlling the area of ​​the annular metal member 318 to be less than a certain proportion of the area of ​​the outer part of the metal pad 308, the impact on the transmittance of the pixel opening area can be minimized, ensuring that the brightness and display effect of the display panel are not significantly affected. While ensuring the reliability of the electrical connection, the high transmittance and excellent optical performance of the display panel are maintained. The inner edge of the annular metal member 318 is flush with the edge of the opening of the first through hole 309, that is, the annular metal member 318 is not arranged on the side wall or bottom surface of the first through hole 309. The annular metal member 318 and the pixel electrode 312 are located in the same film layer, and the material of the pixel electrode 312 and the annular metal member 318 is the same, which is a transparent conductive material such as indium tin oxide. The annular metal member 318 and the pixel electrode 312 are formed in the same process and act as a mask for forming the first through hole 309. When forming the first through hole 309, the annular metal member 318 allows the etching liquid to etch the interlayer insulating layer 306 only at the location where the first through hole 309 is to be formed, thereby improving the position accuracy and size controllability of the through hole. In this way, the shape and position of the through hole can be precisely controlled.

[0048] The second embodiment of the present application is similar to the first embodiment, except that: Figure 5 As shown, in the second embodiment, the metal pad 308 is directly disposed on the interlayer insulating layer 306 around the opening of the first through hole 309. No annular metal member 318, located on the same layer as the pixel electrode 312, is disposed between the metal pad 308 and the interlayer insulating layer 306. The source electrode 313, drain electrode 314, and metal pad 308 are located on the same film layer and are made of the same material: MoAlMo multilayer metal. This design is relatively simple, eliminates a layer of structure, and reduces manufacturing complexity.

[0049] This application also provides a method for manufacturing a display panel. Figures 6 to 11 As shown, the method includes the following steps: Step 1: forming a buffer layer 302 on a substrate 301. The substrate 301 is a glass substrate, and the buffer layer 302 is made of silicon nitride (SiNx) or silicon oxide (SiOx) and can be deposited by plasma enhanced chemical vapor deposition (PECVD).

[0050] Step 2: Form a semiconductor layer 303 on the buffer layer 302. The semiconductor layer 303 is made of low-temperature polysilicon. First, an amorphous silicon film is deposited, and then the amorphous silicon is converted into polysilicon through an excimer laser annealing (ELA) process.

[0051] Step 3: Process the semiconductor layer 303 so that it includes a channel region, a lightly doped region, and a heavily doped region. The heavily doped region includes a source region and a drain region. This step is achieved through ion implantation, using different dopant types, dosages, and energies depending on the doping requirements of different regions.

[0052] Step 4: Form a gate insulating layer 304 on the semiconductor layer 303 and the buffer layer 302. The gate insulating layer 304 is made of silicon nitride or silicon oxide, and can also be deposited by PECVD.

[0053] Step 5: Form gate 305 and common line 307 on gate insulating layer 304. This step is accomplished by depositing a metal layer (e.g., molybdenum), photolithography, and dry etching. Forming gate 305 and common line 307 in the same metal layer ensures that common line 307 and gate 305 have the same electrical characteristics.

[0054] Step 6: An interlayer insulating layer 306 is formed on the gate insulating layer 304, the gate 305 and the common line 307. The interlayer insulating layer 306 is made of silicon nitride or silicon oxide and can also be deposited by PECVD.

[0055] Step 7: Form a pixel electrode 312 on the interlayer insulating layer 306 and simultaneously form a through hole in the interlayer insulating layer 306. This step utilizes halftone mask technology to simultaneously complete the formation of the pixel electrode 312 and the etching of the first through hole 309 in the interlayer insulating layer 306 in a single photolithography process. A halftone mask is a special photomask in which the patterned areas have different transmittances, typically divided into fully transparent areas, semi-transparent areas, and completely opaque areas. During the exposure process, areas of different transmittance cause the photoresist to receive different doses of exposure, resulting in photoresist patterns of different thicknesses after development. Specifically, the photoresist corresponding to the fully transparent areas is completely removed after development to form the through hole; the photoresist corresponding to the semi-transparent areas is partially retained after development and is thinner, used to form the pixel electrode 312 pattern; and the photoresist corresponding to the completely opaque areas is completely retained after development to protect other areas.

[0056] In this step, a layer of transparent conductive material (such as ITO) is first deposited on the interlayer insulating layer 306. Then, photoresist is applied and exposed using a halftone mask. After development, a photoresist pattern of varying thickness is formed. Next, a first etching step is performed to etch the transparent conductive material layer, forming the pattern for the pixel electrode 312. Then, an ashing step is performed to remove the thin layer of photoresist corresponding to the semi-transparent area, exposing the interlayer insulating layer 306 underneath. Finally, a second etching step is performed to etch the interlayer insulating layer 306, forming a through hole. In this way, the formation of the pixel electrode 312 and the etching of the through hole in the interlayer insulating layer 306 are completed in a single photolithography process, saving a photomask and the corresponding process steps.

[0057] In this embodiment, a half-tone mask technique is used to form the pixel electrode 312 while simultaneously forming an annular metal member 318 on the same layer as the pixel electrode 312. A first through-hole 309, a third through-hole 310, and a fourth through-hole 311 are formed in the interlayer insulating layer 306. The first through-hole 309 penetrates the interlayer insulating layer 306 and exposes the common line 307. The third through-hole 310 and the fourth through-hole 311 penetrate the gate insulating layer 304 and the interlayer insulating layer 306 and expose the heavily doped region of the semiconductor layer 303. If the design of the first embodiment is adopted, the annular metal member 318 on the same layer as the pixel electrode 312 can be used as a mask to etch the interlayer insulating layer 306 at the hollowed-out portion of the annular metal member 318 to form the first through-hole 309.

[0058] Step 8: Form a source electrode 313, a drain electrode 314, and a metal pad 308 within the first through-hole 309 and on the interlayer insulating layer 306. This step includes two sub-steps: first, a source and drain metal layer is formed within the first through-hole 309 and on the interlayer insulating layer 306. A MoAlMo multilayer metal structure is used, which can be deposited by methods such as magnetron sputtering; then, the source and drain metal layer is patterned to form the source electrode 313, the drain electrode 314, and the metal pad 308. The metal pad 308 is disposed on the bottom surface and sidewalls of the first through-hole 309, as well as on the periphery of the opening of the first through-hole 309. The metal pad 308 contacts the common line 307 and serves to protect the common line 307.

[0059] Step 9: Form a passivation layer 315 on the source electrode 313, the drain electrode 314, the metal pad 308, the pixel electrode 312 and the interlayer insulating layer 306. The passivation layer 315 is made of silicon nitride or silicon oxide and can also be deposited by PECVD.

[0060] Step 10: A second through-hole 316 is formed in the passivation layer 315 at a position corresponding to the first through-hole 309. Second through-hole 316 exposes a portion of the metal pad 308. This step is accomplished through photolithography and dry etching. Because the metal pad 308 covers the common line 307, the second through-hole 316 only exposes the metal pad 308 and does not directly expose the common line 307, thus avoiding damage to the common line 307 in subsequent processes.

[0061] Step 11: Common electrode 317 is formed on passivation layer 315. Common electrode 317 contacts metal pad 308 through second through-hole 316. This step includes two sub-steps: first, a common electrode layer is formed on the surface of passivation layer 315 and within second through-hole 316. A transparent conductive material such as ITO can be deposited by magnetron sputtering or other methods. Then, the common electrode layer is patterned to form a desired pattern for common electrode 317.

[0062] Through the above-described technical solution, the display panel of the present application adds a metal pad 308 between the passivation layer 315 and the interlayer insulating layer 306 through the hole. This effectively solves the problem of common line 307 being etched during wet etching of the source and drain metal layers, ensuring a reliable electrical connection between common line 307 and common electrode 317, thereby improving the manufacturing yield and product reliability of the display panel. Furthermore, the display panel of the present application utilizes a six-mask process, reducing the number of masks and process steps, lowering manufacturing costs, and improving production efficiency.

[0063] In practical applications, if the contact area between the metal pad 308 and the common line 307 is insufficient, the contact resistance will be too large, affecting the uniform distribution of the common voltage, thereby causing display defects such as uneven display and flickering.

[0064] To address the above technical issues, the embodiments of the present application provide first through-holes 309 in the form of elongated strips or a combination of multiple small through-holes, thereby maximizing the contact area between metal pad 308 and common line 307. Furthermore, a raised structure can be provided on common line 307 to increase the contact area with metal pad 308.

[0065] When the display panel operates for a long time or in a high temperature environment, metal interdiffusion or oxidation may occur at the interface between the metal pad 308 (MoAlMo) and the common line 307 (Mo), resulting in increased contact resistance and affecting the reliability of the electrical connection.

[0066] To address these technical issues, a transition layer, such as a thin layer of titanium (Ti) or titanium nitride (TiN), is introduced between metal pad 308 and common line 307 to act as a diffusion barrier, preventing interdiffusion between the two metals. This is achieved by depositing a thin layer of titanium or titanium nitride within first via 309 before forming the source and drain metal layers. This is followed by the MoAlMo multilayer metal deposition.

[0067] During the wet etching of the source and drain metal layers, if the etching solution penetrates through the tiny gap between the metal pad 308 and the sidewall of the first through hole 309 , the common line 307 may still be partially etched, affecting the reliability of the electrical connection.

[0068] To address the aforementioned technical issues, a multi-angle deposition technique is employed to ensure that the metal pad 308 uniformly covers the sidewalls of the first through-hole 309. Simultaneously, the thickness of the metal pad 308 can be appropriately increased to enhance its protective capability for the common line 307. Furthermore, the wet etching process can be optimized, such as by adjusting the etching solution composition and controlling the etching time and temperature, to reduce the etching rate for the Mo material and improve the selectivity for MoAlMo. Furthermore, after the metal pad 308 is formed, a short heat treatment can be performed to promote interfacial bonding between the metal pad 308 and the common line 307 and reduce the possibility of etching solution infiltration.

[0069] In practical applications, if the contact area between the metal pad 308 and the common line 307 is insufficient, the contact resistance will be too large, affecting the uniform distribution of the common voltage, thereby causing display defects such as uneven display and flickering.

[0070] To solve the above technical problems, the embodiment of the present application sets 3 to 5 small circular through holes with a diameter of 2μm to 3μm on the common line 307, and the spacing between the small through holes is 5μm to 10μm, ensuring that the metal pads 308 at each small through hole can form a continuous electrical connection. In addition, the embodiment of the present application sets a protrusion on the common line 307, the height of these protrusions is 50nm to 100nm, the width is 1μm to 3μm, and one is set every 10μm to 15μm along the length direction of the common line 307, so that the metal pad 308 and the common line 307 form a closer contact at the protrusion, increasing the contact area while reducing the contact resistance. This protrusion can be achieved by using a specially designed mask pattern in the process of forming the common line 307, without the need for additional process steps.

[0071] When the display panel operates for a long time or in a high temperature environment, metal interdiffusion or oxidation may occur at the interface between the metal pad 308 (MoAlMo) and the common line 307 (Mo), resulting in increased contact resistance and affecting the reliability of the electrical connection.

[0072] To address the aforementioned technical issues, embodiments of the present application introduce a transition layer, such as a thin layer of titanium (Ti) or titanium nitride (TiN), between the metal pad 308 and the common line 307 as a diffusion barrier to prevent interdiffusion between the two metals. The thickness of this transition layer ranges from 5nm to 20nm, preventing interdiffusion without significantly increasing contact resistance. Specifically, before forming the source and drain metal layers, a thin layer of titanium or titanium nitride is deposited within the first via 309, followed by a multilayer MoAlMo metal deposition. The titanium layer can be deposited via magnetron sputtering in an argon atmosphere for 30 to 60 seconds; the titanium nitride layer can be deposited via reactive magnetron sputtering in an argon and nitrogen mixed atmosphere with an argon to nitrogen flow ratio of 4:1 to 2:1 for 40 to 80 seconds. This transition layer not only prevents interdiffusion but also improves adhesion between the metal pad 308 and the common line 307, enhancing interfacial bonding strength and improving the reliability and stability of the electrical connection.

[0073] During the wet etching of the source and drain metal layers, if the etching solution penetrates through the tiny gap between the metal pad 308 and the sidewall of the first through hole 309 , the common line 307 may still be partially etched, affecting the reliability of the electrical connection.

[0074] In order to solve the above technical problems, the embodiment of the present application adopts multi-angle deposition technology to ensure that the metal pad 308 evenly covers the side wall of the first through hole 309. Specifically, when depositing the source and drain metal layer, the substrate 301 is rotated and deposited at an inclination angle of 15° to 30°, with the rotation angles of 0°, 90°, 180°, and 270° in four directions. The deposition thickness in each direction is 1 / 4 of the total thickness, ensuring that the coverage rate of the metal pad 308 on the side wall of the first through hole 309 reaches more than 95%, forming a continuous and seamless protective layer. At the same time, the embodiment of the present application appropriately increases the thickness of the metal pad 308 from the conventional 200nm to 300nm to 300nm to 500nm, so as to improve its protection ability for the common line 307 and enhance its ability to resist the penetration of the etching solution.

[0075] In addition, the embodiments of the present application optimize the wet etching process by adjusting the etching solution composition. By adding 0.5% to 1% of a corrosion inhibitor, such as benzotriazole or thiourea, to the conventional mixture of phosphoric acid, nitric acid, and acetic acid, the etching rate of the Mo material is selectively reduced, while the selectivity for MoAlMo is improved. The etching rate ratio of MoAlMo to Mo is increased from the original 3:1 to over 8:1. At the same time, the etching temperature is reduced from the conventional 40°C to 25°C to 30°C, and the etching time is extended from 60 seconds to 90 seconds to 120 seconds. By reducing the etching rate, the process control accuracy is improved, and the accidental etching of the common line 307 is reduced.

[0076] Furthermore, in the embodiment of the present application, a short heat treatment is performed after the metal pad 308 is formed to promote interfacial bonding between the metal pad 308 and the common line 307 and reduce the possibility of etching solution infiltration. This heat treatment is performed in a nitrogen or argon protective atmosphere at a temperature of 250°C to 350°C for 10 to 30 minutes. This moderate heat treatment allows for a tighter bond between the metal pad 308 and the common line 307 interface, while also preventing metal interdiffusion issues caused by excessively high temperatures.

[0077] The display panel of this application can be applied to various types of liquid crystal display panels, such as FFS (Fringe Field Switching) liquid crystal display panels or IPS (In-Plane Switching) liquid crystal display panels. In addition, this technology can also be extended to other types of display panels such as OLED (Organic Light-Emitting Diode) display panels.

[0078] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: gate; A common line, wherein the common line and the gate are located in the same film layer; an interlayer insulating layer disposed on the gate, wherein the interlayer insulating layer is provided with a first through hole, the first through hole penetrating the interlayer insulating layer and exposing at least a portion of the common line; A pixel electrode, a source electrode, and a drain electrode are provided on the interlayer insulating layer; a passivation layer provided on the source electrode, the drain electrode, the pixel electrode and the interlayer insulating layer, wherein the passivation layer is provided with a second through hole at a position corresponding to the first through hole, and the second through hole is connected to the first through hole; a common electrode disposed on the passivation layer; as well as a metal pad disposed in the first through hole, the metal pad being located in the same film layer as the source electrode and the drain electrode, the metal pad being disposed on the bottom surface and sidewalls of the first through hole, and being disposed around the periphery of the opening of the first through hole, and the metal pad being in contact with the common line; The second through hole exposes a portion of the metal pad, and the common electrode contacts the metal pad through the second through hole.

2. The display panel according to claim 1, wherein: The display panel also includes an annular metal component, which is arranged at the periphery of the opening of the first through hole, the annular metal component surrounds the opening of the first through hole, the annular metal component is arranged on the interlayer insulating layer, and the part of the metal pad located outside the first through hole is arranged on the annular metal component.

3. The display panel according to claim 2, wherein: A ratio of an area of ​​the annular metal member to an area of ​​a portion of the metal pad located outside the first through hole is less than 1.

4. The display panel according to claim 2, wherein: An inner edge of the annular metal member is flush with an edge of the opening of the first through hole.

5. The display panel according to claim 2, wherein: The annular metal component and the pixel electrode are located in the same film layer, and the pixel electrode and the annular metal component are made of the same material.

6. The display panel according to claim 1, wherein: The metal pad is disposed on the interlayer insulating layer at a periphery of an opening of the first through hole.

7. The display panel according to claim 1, wherein: The source electrode, the drain electrode, and the metal pad are located in the same film layer, and the source electrode, the drain electrode, and the metal pad are made of the same material.

8. The display panel according to claim 1, wherein: In a top-view of the display panel, the metal pad is located between the main body of the common line and a gate line electrically connected to the gate.

9. The display panel according to claim 8, wherein: When looking down at the display panel, in a direction perpendicular to the length direction of the common line, the size of the metal pad is larger than half the width of the gap between the main portion of the common line and the gate line, and smaller than the width of the gap.

10. The display panel according to claim 8, wherein In a perspective of looking down at the display panel, in a direction perpendicular to the length direction of the common line, a size of the metal pad is larger than a width of a main portion of the common line or a width of the gate line.

11. A method for manufacturing a display panel, characterized in that: The production method comprises: forming a gate and a common line on the gate insulating layer; forming an interlayer insulating layer on the gate insulating layer, the gate and the common line; forming a pixel electrode on the interlayer insulating layer; forming a first through hole in the interlayer insulating layer, wherein the first through hole penetrates the interlayer insulating layer and exposes the common line; forming a source electrode, a drain electrode, and a metal pad in the first through hole and on the interlayer insulating layer, wherein the metal pad is arranged on the bottom surface and sidewalls of the first through hole and on the periphery of the opening of the first through hole, and the metal pad is in contact with the common line; forming a passivation layer on the source electrode, the drain electrode, the metal pad, the pixel electrode, and the interlayer insulating layer; forming a second through hole on the passivation layer at a position corresponding to the first through hole, wherein the second through hole exposes a portion of the metal pad; and A common electrode is formed on the passivation layer, and the common electrode contacts the metal pad through the second through hole.

12. The production method according to claim 11, characterized in that The step of forming a source electrode, a drain electrode and a metal pad in the first through hole and on the interlayer insulating layer comprises: forming a source-drain metal layer in the first through hole and on the interlayer insulating layer; and The source and drain metal layer is patterned to form the source, the drain and the metal pad.

13. The manufacturing method according to claim 11, characterized in that: The production method further comprises: A ring-shaped metal member is formed in the same layer as the pixel electrode during the process of forming the pixel electrode. The ring-shaped metal member is disposed on the interlayer insulating layer at the periphery of the opening of the first through hole.

14. The manufacturing method according to claim 13, characterized in that: The step of forming a first through hole in the interlayer insulating layer comprises: The interlayer insulating layer is etched at the hollow portion of the ring-shaped metal member serving as a mask to form the first through hole.

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