Quantum bit room temperature resistance measurement system, test circuit and related method

Abstract

The invention discloses a room temperature resistance measuring system of quantum bits, a testing circuit and a related method. The preparation method of the quantum bit test circuit comprises the following steps: carrying out metal coating, first photoetching and photoresist cleaning and removing treatment on a pre-treated wafer to obtain a wafer prepared with a bottom layer circuit; a shielding object is attached to the pin of the bottom layer circuit; carrying out second photoetching and metal evaporation treatment on the wafer attached with the shielding object so as to prepare a Josephson junction connected with the bottom layer circuit on the wafer; the shielding object attached to the pin of the bottom layer circuit is removed, a test circuit exposed out of the pin of the bottom layer circuit is obtained, the test circuit comprises the bottom layer circuit and a Josephson junction connected with the bottom layer circuit, and the pin of the bottom layer circuit is used for being connected with resistance measuring equipment. The preparation time of the quantum bit test circuit can be saved.

Description

Technical Field

[0001] The present invention relates to the field of quantum technology, and in particular to a room temperature resistance measurement system, a test circuit and related methods for a quantum bit. Background Art

[0002] As the core platform for the development of practical quantum computers, the performance of superconducting quantum chips is directly related to the computing performance of superconducting quantum computers. The core component of superconducting quantum chips is superconducting qubits, which play a role similar to transistors in classical chips. Setting more qubits on superconducting quantum chips means more powerful computing power. However, with the increase in superconducting qubits, the production cost of superconducting quantum chips is also gradually increasing. Reducing the scrap rate of superconducting quantum chips is one of the means to reduce the production cost of superconducting quantum chips.

[0003] In the existing technology, the reason for the scrapping of superconducting quantum chips is mostly due to the fact that the quantum bit frequency of the superconducting quantum bits processed on the chip does not match the designed frequency. Therefore, in order to ensure the performance of superconducting quantum chips and reduce the scrap rate of superconducting quantum chips, the frequency parameters of the superconducting quantum bits must be strictly controlled. The Josephson junction is a key structure of the superconducting quantum bit, and the characterization of the room temperature resistance of the Josephson junction is an important means to reflect the quantum bit frequency. Therefore, the room temperature resistance of the Josephson junction needs to be measured during the preparation process of the superconducting quantum bit.

[0004] In the existing technology, after the wafer is subjected to double-angle evaporation treatment, a stripping process is required to expose the pads (pins) of the bottom circuit in the test circuit before the room temperature resistance of the Josephson junction can be measured. The stripping process generally takes 3-5 hours, which is relatively time-consuming. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a room temperature resistance measurement system, test circuit and related methods of quantum bits that overcome the above problems or at least partially solve the above problems.

[0006] In a first aspect, an embodiment of the present invention provides a method for preparing a quantum bit test circuit, comprising:

[0007] Performing metal coating, first photolithography, and photoresist cleaning and removal on the pre-treated wafer to obtain a wafer with bottom layer circuits prepared;

[0008] Attaching shielding objects to the pins of the bottom circuit;

[0009] Performing a second photolithography and metal evaporation process on the wafer with the shield attached thereto to prepare a Josephson junction on the wafer connected to the bottom layer circuit;

[0010] The shielding material attached to the pins of the bottom circuit is removed to obtain a test circuit exposing the pins. The test circuit includes the bottom circuit and a Josephson junction connected to the bottom circuit. The pins of the bottom circuit are used to connect to a resistance measuring device.

[0011] In an optional embodiment, metal coating, first photolithography, and photoresist cleaning and removal are performed on the pre-treated wafer to obtain a wafer with bottom-layer circuits, including:

[0012] Performing metal coating on the pre-treated wafer to form a first metal layer on the surface of the wafer;

[0013] forming a first photoresist coating on the surface of the first metal layer of the wafer;

[0014] Based on the preset pattern of the bottom layer circuit, the wafer with the first photoresist coating is exposed and developed for the first time to perform patterning processing, and the wafer after patterning processing is etched to expose the preset area of ​​the bottom layer circuit;

[0015] The first photoresist coating remaining after etching on the wafer is cleaned and removed to expose the first metal layer in a preset area of ​​the bottom circuit to obtain the bottom circuit.

[0016] In an optional embodiment, attaching a shield to the pin of the bottom circuit includes:

[0017] A shield is attached to the pin area of ​​the bottom circuit, or a shield is attached to the pin area of ​​the bottom circuit and the wafer substrate area exposed outside the pin area.

[0018] In an optional embodiment, a second photolithography and metal evaporation process is performed on the wafer with the shield attached thereto to prepare a Josephson junction connected to the bottom layer circuit on the wafer, comprising:

[0019] forming a second photoresist coating and a third photoresist coating on the surface of the wafer with the shield attached thereto, and performing a second exposure and development process on the wafer with the second photoresist coating and the third photoresist coating to perform patterning processing to expose a predetermined area on the wafer surface where the Josephson junction is to be arranged;

[0020] The wafer surface after the second exposure and development is subjected to a double-angle evaporation process to form a second metal layer on the wafer surface to obtain a Josephson junction connected to the bottom layer circuit.

[0021] In an optional embodiment, the bottom layer circuit includes a first pin, a second pin, a first lead for connecting the first pin and a first electrode of the Josephson junction, and a second lead for connecting the second pin and a second electrode of the Josephson junction;

[0022] After removing the shielding attached to the pins of the bottom circuit, the pins of the bottom circuit are exposed, and the first lead and the second lead are covered by the second photoresist coating, the third photoresist coating and the second metal layer.

[0023] In an optional embodiment, the shielding material is an adhesive tape with a temperature resistance greater than 200 degrees.

[0024] In an optional embodiment, the tape is made of a polyimide film substrate.

[0025] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a method for measuring the room temperature resistance of a quantum bit, comprising:

[0026] Prepare a test circuit using the above-mentioned method for preparing a quantum bit test circuit;

[0027] applying a test current to the Josephson junction based on the test circuit, and measuring the applied test current;

[0028] measuring a voltage between a first electrode and a second electrode of the Josephson junction when the test current is applied to the Josephson junction;

[0029] A room temperature resistance of the qubit is determined based on the voltage and the test current.

[0030] In a third aspect, based on the same inventive concept, an embodiment of the present invention further provides a circuit for testing the room temperature resistance of a quantum bit, comprising: a Josephson junction and an underlying circuit disposed on a wafer;

[0031] The bottom circuit includes a pin and a lead connecting the pin and an electrode of the Josephson junction;

[0032] The pins include: a first pin and a second pin, and correspondingly, the leads include: a first lead connecting the first pin and a first electrode of the Josephson junction, and a second lead connecting the second pin and a second electrode of the Josephson junction;

[0033] The bottom layer circuit is prepared by performing metal coating, first photolithography and photoresist cleaning and removal on the pre-processed wafer;

[0034] The Josephson junction is prepared by performing a second photolithography and metal evaporation process on a wafer prepared with a bottom layer circuit and attached with a shield; the shield is attached to the pins of the bottom layer circuit and is removed after the preparation of the Josephson junction is completed to expose the covered pins.

[0035] In a fourth aspect, based on the same inventive concept, an embodiment of the present invention further provides a system for measuring the room temperature resistance of a quantum bit, comprising: a resistance measuring device and a test circuit for the room temperature resistance of the quantum bit described above;

[0036] The resistance measuring device comprises: a first probe assembly, a second probe assembly, a power supply, a voltage measuring device and a current measuring device;

[0037] The first probe assembly includes: a first probe and a second probe;

[0038] The second probe assembly includes: a third probe and a fourth probe;

[0039] The first probe and the third probe are connected to the first pin of the bottom layer circuit, and the second probe and the fourth probe are connected to the second pin of the bottom layer circuit;

[0040] The power supply and the current measuring device are arranged between the first probe and the second probe, the power supply is used to apply a test current to the Josephson junction, and the current measuring device is used to detect the test current;

[0041] The voltage measuring device is used to detect the voltage between the first electrode and the second electrode of the Josephson junction.

[0042] The beneficial effects of the above technical solutions provided by the embodiments of the present invention include at least:

[0043] A method for preparing a test circuit for a quantum bit according to an embodiment of the present invention comprises the following steps: after preparing an underlying circuit, a shield is attached to the pin of the underlying circuit, and then a second photolithography and metal evaporation process is performed on the wafer with the shield attached to prepare a Josephson junction connected to the underlying circuit on the wafer with the underlying circuit. Since the shield has been used to shield the pin of the underlying circuit before the Josephson junction is prepared on the wafer, the photoresist and the evaporated metal layer set during the second photolithography and metal evaporation process when preparing the Josephson junction are all covered on the shield. After the Josephson junction is prepared, it is only necessary to remove the shield attached to the pin of the underlying circuit to expose the pin of the underlying circuit, and then the pin of the underlying circuit can be measured by connecting the pin of the underlying circuit to the external resistance. The device is connected to measure the room temperature resistance of the Josephson junction; that is, the preparation method provided by the embodiment of the present invention, by attaching a shielding material to the pins of the bottom circuit after preparing the bottom circuit and before preparing the Josephson junction, so that after the preparation of the Josephson junction is completed, only the step of removing the shielding material attached to the pins of the bottom circuit needs to be performed to measure the room temperature resistance of the Josephson junction. Compared with the existing technology, when measuring the room temperature resistance of the Josephson junction, no stripping process is required, which can save the measurement time of the room temperature resistance of the Josephson junction; and if the room temperature resistance measurement of the Josephson junction fails, there is no need to perform a subsequent photoresist stripping process on the quantum chip, which can save stripping materials and further reduce the production cost and time cost of the quantum chip.

[0044] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0045] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0047] Figure 1 Schematic diagram of a process for preparing a quantum bit test circuit in Example 1 of the present invention;

[0048] Figure 2 Schematic diagram of the structure of the test circuit in Example 1 of the present invention;

[0049] Figure 3This is a structural diagram of a case where a shield is provided at the pin of the bottom circuit in the first embodiment of the present invention;

[0050] Figure 4 for Figure 2 Cross-sectional view along AA direction;

[0051] Figure 5 for Figure 4 A magnified diagram of the pin at position B in the middle;

[0052] Figure 6 A system for measuring the room temperature resistance of a quantum bit in the second embodiment of the present invention;

[0053] Figure 7 Schematic diagram of the flow of the method for measuring the room temperature resistance of a quantum bit in Example 3 of the present invention. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the present invention, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0055] In the prior art, when measuring the room temperature resistance of a quantum bit, after obtaining the underlying circuit, the Josephson junction of the quantum bit is prepared, and the general process flow for measuring the room temperature resistance of the quantum bit is as follows:

[0056] 1. Apply two layers of photoresist on the wafer substrate of the chip, and expose and develop a cross-structured groove.

[0057] 2. According to the preset evaporation angle, two layers of superconducting metal are evaporated in sequence at an oblique angle, and an oxidation process is added for a certain period of time before the two evaporation processes.

[0058] 3. After evaporation, some of the deposited metal is deposited in the grooves and attached to the chip substrate, becoming part of the qubit. The remaining excess metal is deposited on the two layers of photoresist. The chip is then soaked or cleaned with an organic solvent such as acetone to remove the photoresist, separating the metal deposited on the two layers of photoresist from the wafer substrate along with the photoresist. This is known as the lift-off process.

[0059] 4. After the stripping process is performed to expose the pins of the underlying circuit, the room temperature resistance of the quantum bit is measured.

[0060] That is, in the existing process, when performing room temperature measurement of quantum bits, it is necessary to wait for the stripping process to complete and remove the photoresist covering the pins in the underlying circuit before measuring the room temperature resistance.

[0061] In order to solve the problem in the prior art that when measuring the room temperature resistance of a quantum bit, a stripping process needs to be performed after the dual-angle evaporation process, which leads to a high time cost for measuring the room temperature resistance, an embodiment of the present invention provides a system, a test circuit and related methods for measuring the room temperature resistance of a quantum bit. The core of the system is to provide a method for preparing a test circuit for a quantum bit, wherein a shield is attached to the pins of the underlying circuit after preparing the underlying circuit and before preparing the Josephson junction, so that the photoresist coating formed by the photolithography process and the metal layer formed by the metal evaporation process when preparing the Josephson junction are covered on the shield at the pins. After the preparation of the Josephson junction is completed, only the shield attached to the pins of the underlying circuit needs to be removed to expose the pins of the underlying circuit for measuring the room temperature resistance of the Josephson junction. Compared with the prior art, there is no need to wait for the photoresist stripping process, which can save the overall measurement time of the room temperature resistance of the quantum bit.

[0062] The following describes in detail the room temperature resistance measurement system, test circuit, and related methods of the quantum bits provided in the embodiments of the present invention through specific examples; wherein, the quantum bits described in the embodiments include but are not limited to superconducting quantum bits, etc.

[0063] Example 1

[0064] The method for preparing a test circuit of a quantum bit provided by an embodiment of the present invention has a flow chart referring to Figure 1 Shown, including:

[0065] Step S101: performing metal coating, first photolithography, and photoresist cleaning and removal processing on the pre-treated wafer to obtain a wafer with bottom layer circuits prepared thereon;

[0066] Step S102: attaching a shield to the pins of the bottom circuit;

[0067] Step S103: performing a second photolithography and metal evaporation process on the wafer with the shield attached thereto, so as to prepare a Josephson junction on the wafer connected to the bottom layer circuit;

[0068] Step S104: removing the shielding attached to the pins of the bottom circuit to obtain a test circuit exposing the pins of the bottom circuit, wherein the test circuit includes the bottom circuit and a Josephson junction connected to the bottom circuit, and the pins of the bottom circuit are used to connect to a resistance measuring device.

[0069] Optionally, the preparation method provided by an embodiment of the present invention includes, in step S101, performing metal coating, first photolithography, and photoresist cleaning and removal on the pre-treated wafer to obtain a wafer with bottom-layer circuits, including:

[0070] Performing metal coating on the pre-treated wafer to form a first metal layer on the surface of the wafer;

[0071] forming a first photoresist coating on the surface of the first metal layer of the wafer;

[0072] Based on the preset pattern of the bottom layer circuit, the wafer with the first photoresist coating is exposed and developed for the first time to perform patterning processing, and the wafer after patterning processing is etched to expose the preset area of ​​the bottom layer circuit;

[0073] The first photoresist coating remaining after etching on the wafer is cleaned and removed to expose the first metal layer in a preset area of ​​the bottom circuit to obtain the bottom circuit.

[0074] The embodiment of the present invention does not specifically limit the material of the wafer substrate, which can be selected according to actual needs. For example, the material of the wafer substrate includes but is not limited to sapphire, high-resistance silicon, etc. When pre-treating the wafer substrate, it can specifically include: soaking in piranha solution for a first preset time, ultrasonic cleaning using IPA (using isopropyl alcohol as the cleaning solution for ultrasonic cleaning) for a second preset time, and ultrasonic cleaning using deionized water for a third preset time; the specific values ​​of the first preset time, the second preset time, and the third preset time can be selected according to actual processing needs and are not specifically limited in the embodiment of the present invention; optionally, the first preset time can be 10-20 minutes; the second preset time can be 10-15 minutes, and the third preset time can be 5-10 minutes.

[0075] The pre-treated wafer is subjected to metal coating treatment to form a first metal layer on the surface of the wafer. Specifically, the process may include: using electron beam evaporation equipment to perform metal coating treatment on the pre-treated wafer under preset vacuum conditions, and passivating the pre-treated wafer with pure oxygen in an oxidation chamber after metal coating to form a protective layer. The preset vacuum conditions and the coating conditions during the metal coating treatment are not specifically limited in the embodiments of the present invention and can be set based on actual needs. For example, the preset vacuum conditions can be 1E-9torr to 2E-10torr. When the coating treatment is performed, the coating rate can be selected to be 6-7A / s. The coating thickness can be selected to be 100±10nm, and when the coating treatment is performed, it can be specifically an aluminum-plated film.

[0076] A first photoresist coating is formed on the surface of the first metal layer of the wafer; specifically, the method may include: applying a layer of the first photoresist to the plated first metal layer based on a preset first photoresist processing condition to form the first photoresist coating. The first photoresist may be a positive photoresist, specifically a photoresist with a thickness of 500 nm. The first photoresist processing conditions include a coating speed and time, and a baking temperature and time, which may be selected based on actual needs. For example, when the first photoresist is an S1805 series photoresist, the coating speed may be 3000-3500 rpm, the coating time may be 50s-55s, the baking temperature may be 90-115°, and the baking time may be 90s-100s.

[0077] The wafer having the first photoresist coating formed thereon is exposed and developed for the first time based on the preset pattern of the underlying circuit to perform patterning processing, and the wafer after patterning processing is etched to expose the preset area of ​​the underlying circuit. Specifically, the process may include:

[0078] Using a mask exposure machine, a wafer with a first photoresist coating is exposed to a pattern based on the preset pattern of the underlying circuitry and the preset exposure conditions. After pattern exposure, a development process is performed. During exposure, the exposure mode can be selected as a vacuum mode, and the exposure time can be selected as 1-2 seconds. During development, the developer and development time can be selected based on actual needs. For example, the developer can be ZX-238 solution, and the development time can be selected as 50-60 seconds. After development, a fixing process is performed, specifically in deionized water for approximately 1 minute. A nitrogen gun is then used to blow dry the wafer to complete the fixing process.

[0079] The wafer after the first development is then etched using an etching solution based on preset etching conditions, and then blown dry after being soaked in deionized water for a preset time. Optionally, the etching process is specifically to etch away the first metal layer in the area outside the preset pattern of the bottom layer circuit on the wafer to expose the wafer substrate in the area; wherein, when etching, the etching solution and etching time can be specifically selected according to the plated first metal layer, for example: when the first metal layer is an aluminum layer, the selected etching solution can be selected as an aluminum etching solution, and the specific etching time can be selected as 2min±30s; when soaking in deionized water after etching, the soaking time can be 3-5min, and when blowing dry, a nitrogen chamber can be used for blowing dry.

[0080] Optionally, the preparation method of the test circuit provided in an embodiment of the present invention cleans and removes the first photoresist coating remaining on the wafer after etching to expose the first metal layer of a preset area of ​​the underlying circuit. When the underlying circuit is obtained, the specific process of removing the first photoresist includes but is not limited to: placing the etched wafer in methyl pyrrolidone (NMP) or the degumming solution RemovePG, heating it to 80-85°C and soaking it for 1-2 hours, then switching to IPA and soaking it for 5-10 minutes, and then blowing it dry with a nitrogen gun.

[0081] Optionally, in the method for preparing a qubit test circuit according to an embodiment of the present invention, in step S102, attaching a shielding object to the pins of the bottom circuit may specifically include:

[0082] A shield is attached to the pin area of ​​the bottom circuit, or a shield is attached to the pin area of ​​the bottom circuit and the wafer substrate area 105 exposed outside the pin area. That is, in the preparation method provided by the embodiment of the present invention, when setting a shield at the pin of the bottom circuit, the shield can be attached only to the pin area of ​​the bottom circuit, or the shield can be attached together with the wafer substrate exposed outside the pin area. Figure 2 and Figure 3 As shown, Figure 3 The figure shows a schematic diagram of a structure in which a shield 13 is attached to the pin (101, 103) area of ​​the bottom circuit and the wafer substrate area 105 exposed outside the pin area. In order to avoid the second photolithography forming a photoresist coating on the wafer substrate area exposed outside the pin area and the metal evaporation process forming a second metal layer on the photoresist coating, the second metal layer is connected to the first metal layer of the pin after the attached shield is removed, thereby causing a short circuit in the test circuit, it is preferred to attach a shield to the pin area of ​​the bottom circuit and the wafer substrate area exposed outside the pin area.

[0083] Optionally, in the preparation method provided by the embodiment of the present invention, in step S103, a second photolithography and metal evaporation process is performed on the wafer with the shield attached thereto to prepare a Josephson junction connected to the bottom layer circuit on the wafer with the bottom layer circuit prepared thereon, comprising:

[0084] forming a second photoresist coating and a third photoresist coating on the surface of the wafer with the shield attached thereto, and performing a second exposure and development process on the wafer with the second photoresist coating and the third photoresist coating to perform patterning processing to expose a predetermined area on the wafer surface where the Josephson junction is to be arranged;

[0085] The wafer surface after the second exposure and development is subjected to a double-angle evaporation process to form a second metal layer on the wafer surface to obtain a Josephson junction connected to the bottom layer circuit.

[0086] Specifically, forming a second photoresist coating and a third photoresist coating on the surface of the wafer with the shield attached thereto may specifically include: on the surface of the wafer with the shield attached thereto, based on a preset second photoresist processing condition, evenly coating two layers of photoresist, namely a second photoresist and a third photoresist, to form the second photoresist coating and the third photoresist coating. The types of the second photoresist and the third photoresist and the corresponding processing conditions may be selected based on actual needs. For example, when the second photoresist and the third photoresist are PMMA (polymethyl methacrylate) & MMA (methyl methacrylate) electron beam photoresists, the coating speed may be selected to be 1000 rpm-1500 rpm, the coating time may be selected to be 1 min-1 m30 s, the baking temperature may be selected to be 90-100°, and the baking time may be 1 min-1 m30 s.

[0087] The wafer provided with the second photoresist coating and the third photoresist coating is subjected to a second exposure and development process for patterning to expose a preset area on the wafer surface where the Josephson junction is provided. Specifically, the process includes: using an electron beam exposure machine to expose the second photoresist coating and the third photoresist coating based on the preset area of ​​the Josephson junction and preset exposure conditions, wherein the preset exposure conditions include: an exposure dose of 200-300 uc / square centimeter. When performing the development process, the developer and development time can be selected according to actual needs; for example, MIBK (methyl isobutyl ketone): IPA (isopropyl alcohol) 1:3 can be used for development, and the development time is 50-70 seconds; when performing the fixing process, the fixing can be carried out in deionized water, and the fixing time can be selected to be about 1 minute, and then a nitrogen gun is used to blow dry to complete the fixing.

[0088] Optionally, when performing dual-angle evaporation treatment on the wafer after the second exposure and development, the specific coating rate can be selected to be 3-5 A / s.

[0089] In one embodiment, the preparation method provided by the embodiment of the present invention, the test circuit prepared is referenced Figures 2 to 4 As shown, the bottom line 10 includes: a first pin 101, a second pin 103, a first lead 102 for connecting the first pin 101 and a first electrode of the Josephson junction 11 (not shown in the figure), and a second lead 104 for connecting the second pin 103 and a second electrode of the Josephson junction 11 (not shown in the figure);

[0090] After removing the shield 13 attached to the pin of the bottom circuit 10, refer to Figure 4 and Figure 5As shown, the first pin 101 and the second pin 103 of the bottom circuit 10 are in an exposed state, and the first lead 102 and the second lead 104 are in a state covered by the second photoresist coating 12, the third photoresist coating 13 and the second metal layer 14. That is, the test circuit obtained by the preparation method provided by the embodiment of the present invention, after removing the shielding 13 attached to the pins of the bottom circuit 10, the first pin 101 and the second pin 103 of the bottom circuit 10 are exposed, but the first lead 102 and the second lead 104 of the bottom circuit 10 are still in a state where the photoresist is not stripped. Since the first pin 101 and the second pin 103 of the bottom circuit 10 can be directly connected to the resistance measuring device, the bottom circuit 10 can realize the measurement of the room temperature resistance of the quantum bit without stripping the photoresist.

[0091] In one embodiment, the shielding material 13 disposed at the pins of the bottom circuit 10 can be a tape with a temperature resistance greater than 200°C to accommodate the high-temperature processing environment during subsequent electron beam photoresist preparation during Josephson junction fabrication. Specifically, the tape can be made of, but not limited to, a polyimide film substrate. Parameters such as the thickness of the high-temperature tape can be selected based on actual needs; optionally, the tape can be 50 μm to 80 μm thick.

[0092] Based on the same inventive concept, the embodiment of the present invention also provides a test circuit for the room temperature resistance of a quantum bit, referring to Figures 2 to 5 As shown, it includes: a Josephson junction 11 and a bottom circuit 10 arranged on a wafer 15;

[0093] The bottom circuit 10 includes a pin and a lead connecting the pin and an electrode of the Josephson junction 11;

[0094] The pins include: a first pin 101 and a second pin 103. Correspondingly, the leads include: a first lead 102 connecting the first pin 101 and a first electrode (not shown in the figure) of the Josephson junction 11, and a second lead 104 connecting the second pin 103 and a second electrode (not shown in the figure) of the Josephson junction 11.

[0095] The bottom circuit 10 is prepared by performing metal coating, first photolithography and photoresist cleaning and removal on a pre-processed wafer;

[0096] The Josephson junction 11 is prepared by performing a second photolithography and metal evaporation process on a wafer prepared with a bottom layer circuit 10 and attached with a shield 13; the shield 13 is attached to the pins of the bottom layer circuit 10 and is removed after the preparation of the Josephson junction 11 is completed to expose the covered pins.

[0097] In the test circuit provided by the embodiment of the present invention, after the bottom layer circuit 10 is prepared and before the Josephson junction 11 is prepared, a shield 13 is attached to the pins (first pin 101 and second pin 103). This allows the photoresist coating formed during the second photolithography process on the wafer and the metal layer formed during the metal evaporation process to cover the shield 13 at the pins. After the Josephson junction 11 is prepared, the shield 13 attached to the pins is removed to expose the pins. Compared to the prior art, the exposure process of the first pin 101 and the second pin 103 of the bottom layer circuit 10 does not require stripping the photoresist after the second photolithography process, which can save preparation time for the test circuit 1 and, in turn, can save time for measuring the room temperature resistance of the quantum bit.

[0098] Among them, the specific instructions for metal coating, the first photolithography and photoresist cleaning and removal treatment on the pre-treated wafer, attaching the shield 13 at the first pin 101 and the second pin 103, and performing the second photolithography and metal evaporation treatment on the wafer prepared with the bottom layer circuit 10 and attached with the shield 13 have been described in detail in the preparation method of the test circuit in this embodiment and will not be elaborated here.

[0099] Example 2

[0100] The embodiment of the present invention also provides a system for measuring the room temperature resistance of a quantum bit, referring to Figure 6 As shown, it includes: a resistance measuring device 2 and a test circuit 1 for the room temperature resistance of a quantum bit in the first embodiment;

[0101] The resistance measuring device 2 includes: a first probe assembly, a second probe assembly, a power supply 25, a voltage measuring device 26 and a current measuring device 27;

[0102] The first probe assembly includes: a first probe 21 and a second probe 22;

[0103] The second probe assembly includes: a third probe 23 and a fourth probe 24;

[0104] The first probe 21 and the third probe 23 are connected to the first pin 101 of the bottom line 10 , and the second probe 22 and the fourth probe 24 are connected to the second pin 103 of the bottom line 10 ;

[0105] A power supply 25 and a current measuring device 27 are provided between the first probe 21 and the second probe 22 . The power supply 25 is used to apply a test current to the Josephson junction 11 , and the current measuring device 27 is used to detect the test current.

[0106] The voltage measuring device 26 is used to detect the voltage between the first electrode and the second electrode of the Josephson junction 11 .

[0107] Compared with the prior art, the system for measuring the room temperature resistance of a quantum bit provided in an embodiment of the present invention does not require a photoresist stripping process after the Josephson junction 11 is prepared during the preparation of the test circuit 1. It is only necessary to remove the shielding material 13 attached to the pins of the underlying circuit 10 before preparing the Josephson junction 11 to expose the pins of the underlying circuit 10, thereby saving the preparation time of the test circuit 1. Based on this, the system for measuring the room temperature resistance of a quantum bit provided in this embodiment, when applied to the measurement of the room temperature resistance of a quantum bit, has the characteristic of being able to save the overall measurement time of the room temperature resistance of the quantum bit.

[0108] The specific preparation process of the test circuit 1 has been described in detail in the above-mentioned embodiment 1, and will not be described in detail in this embodiment of the present invention.

[0109] Example 3

[0110] The embodiment of the present invention also provides a method for measuring the room temperature resistance of a quantum bit, the flow chart of which is shown in FIG. Figure 7 Shown, including:

[0111] Step S201: preparing a test circuit using the method for preparing a qubit test circuit in Example 1;

[0112] Step S202: applying a test current to the Josephson junction based on the test circuit, and measuring the applied test current;

[0113] Step S203: measuring the voltage between the first electrode and the second electrode of the Josephson junction when the test current is applied to the Josephson junction;

[0114] Step S204: determining the room temperature resistance of the quantum bit based on the voltage and the test current.

[0115] Regarding the method for measuring the room temperature resistance of the quantum bit in the above embodiment, compared with the existing technology, during the preparation process of its test circuit 1, no photoresist stripping process is required after the Josephson junction 11 is prepared. It is only necessary to remove the shielding material 13 attached to the pin of the underlying circuit 10 before preparing the Josephson junction 11 to expose the pin of the underlying circuit 10, which can save the preparation time of the test circuit 1. Based on this, the method for measuring the room temperature resistance of the quantum bit provided in this embodiment has the characteristic of being able to save the overall measurement time of the room temperature resistance of the quantum bit.

[0116] Optionally, the method for measuring the room temperature resistance of a quantum bit in an embodiment of the present invention, after preparing a test circuit, applies a test current to the Josephson junction in step S202 and measures the applied test current, and measures the voltage between the first electrode and the second electrode of the Josephson junction when the test current is applied to the Josephson junction in step S203. Specifically, it can be implemented based on the room temperature resistance measurement system of the quantum bit in Example 2.

[0117] Among them, the specific preparation process of the test circuit has been described in detail in the above embodiment 1, and the specific structure of the room temperature resistance measurement system of the quantum bit has been described in detail in the above embodiment 2, which will not be described in detail in this embodiment of the present invention.

[0118] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention.

[0119] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0120] In the present invention, unless otherwise specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication between them; direct connections or indirect connections through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0121] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0122] In the present invention, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0123] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for preparing a quantum bit test circuit, characterized in that: include: Performing metal coating, first photolithography, and photoresist cleaning and removal on the pre-treated wafer to obtain a wafer with bottom layer circuits prepared; Attaching shielding objects to the pins of the bottom circuit; Performing a second photolithography and metal evaporation process on the wafer with the shield attached thereto to prepare a Josephson junction on the wafer connected to the bottom layer circuit; The shielding material attached to the pins of the bottom circuit is removed to obtain a test circuit exposing the pins. The test circuit includes the bottom circuit and a Josephson junction connected to the bottom circuit. The pins of the bottom circuit are used to connect to a resistance measuring device.

2. The preparation method according to claim 1, wherein Metal coating, first photolithography, and photoresist cleaning and removal are performed on the pre-treated wafer to obtain a wafer with bottom-layer circuits, including: Performing metal coating on the pre-treated wafer to form a first metal layer on the surface of the wafer; forming a first photoresist coating on the surface of the first metal layer of the wafer; Based on the preset pattern of the bottom layer circuit, the wafer with the first photoresist coating is exposed and developed for the first time to perform patterning processing, and the wafer after patterning processing is etched to expose the preset area of ​​the bottom layer circuit; The first photoresist coating remaining after etching on the wafer is cleaned and removed to expose the first metal layer in a preset area of ​​the bottom circuit to obtain the bottom circuit.

3. The preparation method according to claim 1, wherein Attaching a shield to the pins of the bottom circuit, including: A shield is attached to the pin area of ​​the bottom circuit, or a shield is attached to the pin area of ​​the bottom circuit and the wafer substrate area exposed outside the pin area.

4. The preparation method according to claim 1, wherein Performing a second photolithography and metal evaporation process on the wafer with the shield attached to prepare a Josephson junction connected to the bottom layer circuit on the wafer, including: forming a second photoresist coating and a third photoresist coating on the surface of the wafer with the shield attached thereto, and performing a second exposure and development process on the wafer with the second photoresist coating and the third photoresist coating to perform patterning processing to expose a predetermined area on the wafer surface where the Josephson junction is to be arranged; The wafer surface after the second exposure and development is subjected to a double-angle evaporation process to form a second metal layer on the wafer surface to obtain a Josephson junction connected to the bottom layer circuit.

5. The preparation method according to claim 4, wherein The bottom circuit includes a first pin, a second pin, a first lead for connecting the first pin and a first electrode of the Josephson junction, and a second lead for connecting the second pin and a second electrode of the Josephson junction; After removing the shielding attached to the pins of the bottom circuit, the pins of the bottom circuit are exposed, and the first lead and the second lead are covered by the second photoresist coating, the third photoresist coating and the second metal layer.

6. The preparation method according to any one of claims 1 to 5, characterized in that The shielding material is an adhesive tape with a temperature resistance greater than 200 degrees.

7. The preparation method according to claim 6, wherein The material of the adhesive tape is a polyimide film substrate.

8. A method for measuring the room temperature resistance of a quantum bit, characterized in that: include: Prepare a test circuit using the method for preparing a quantum bit test circuit according to any one of claims 1 to 7; applying a test current to the Josephson junction based on the test circuit, and measuring the applied test current; measuring a voltage between a first electrode and a second electrode of the Josephson junction when the test current is applied to the Josephson junction; A room temperature resistance of the qubit is determined based on the voltage and the test current.

9. A test circuit for room temperature resistance of a quantum bit, characterized in that: include: Josephson junction and underlying circuits provided on the wafer; The bottom circuit includes a pin and a lead connecting the pin and an electrode of the Josephson junction; The pins include: a first pin and a second pin, and correspondingly, the leads include: a first lead connecting the first pin and a first electrode of the Josephson junction, and a second lead connecting the second pin and a second electrode of the Josephson junction; The bottom layer circuit is prepared by performing metal coating, first photolithography and photoresist cleaning and removal on the pre-processed wafer; The Josephson junction is prepared by performing a second photolithography and metal evaporation process on a wafer prepared with a bottom layer circuit and attached with a shield; the shield is attached to the pins of the bottom layer circuit and is removed after the preparation of the Josephson junction is completed to expose the covered pins.

10. A system for measuring room temperature resistance of a quantum bit, characterized in that: include: A resistance measuring device and a circuit for testing the room temperature resistance of a quantum bit as claimed in claim 9; The resistance measuring device comprises: a first probe assembly, a second probe assembly, a power supply, a voltage measuring device and a current measuring device; The first probe assembly includes: a first probe and a second probe; The second probe assembly includes: a third probe and a fourth probe; The first probe and the third probe are connected to the first pin of the bottom layer circuit, and the second probe and the fourth probe are connected to the second pin of the bottom layer circuit; The power supply and the current measuring device are arranged between the first probe and the second probe, the power supply is used to apply a test current to the Josephson junction, and the current measuring device is used to detect the test current; The voltage measuring device is used to detect the voltage between the first electrode and the second electrode of the Josephson junction.

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