Task scheduling method and device

Abstract

The invention discloses a task scheduling method and device, relates to the technical field of computers, and gives consideration to task affinity and load balance while performing task scheduling based on a multi-core architecture. The method is applied to a task scheduling device comprising a plurality of processing cores, and each processing core is provided with a plurality of queues with different priorities. The method comprises the steps that a first processing core schedules a first task in a first queue of the first processing core in a first period of the first processing core, and the first queue of the first processing core and a second queue of a second processing core both comprise the first task in the first period of the first processing core; if the execution of the first task in the first period of the first processing core is not finished, the first processing core executes the following operations: the first task is added to the tail of a first queue of the first processing core for scheduling of a second period of the first processing core, and the first period of the first processing core is earlier than the second period of the first processing core; and moving the first task to the tail of the second queue of the second processing core.

Description

Task scheduling method and device Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a task scheduling method and device. Background Art

[0002] As modern computer hardware evolves from single-core processors to multi-core processors, processor architectures become increasingly complex. Simultaneously, the scheduling algorithms within operating system kernels have evolved significantly, resulting in the emergence of a variety of scheduler types.

[0003] Symmetric multiprocessing (SMP), a modern mainstream processor architecture, uses a scheduling algorithm primarily to address the fairness and efficiency of task execution, specifically addressing affinity and load balancing. Affinity refers to the efficiency with which a task runs on a particular core. The closer the task was to its last execution on that core, the higher the affinity, and vice versa. Load balancing ensures that tasks are evenly distributed across cores in a multi-core architecture, preventing some cores from being extremely busy while others are idle. Good load balancing can significantly improve hardware utilization, thereby increasing task efficiency.

[0004] In the scheduling algorithms of the prior art, when performing task scheduling based on a multi-core architecture, it is impossible to take into account both task affinity and load balancing at the same time.

[0005] Summary of the Invention

[0006] The present application provides a task scheduling method and device for taking into account both task affinity and load balancing when scheduling tasks based on a multi-core architecture.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a task scheduling method is provided, which is applied to a task scheduling device including multiple processing cores, each of the multiple processing cores is provided with multiple queues, the multiple processing cores include a first processing core and a second processing core, the multiple queues include a first queue and a second queue, and the priority of the first queue is higher than the priority of the second queue; the method includes: the first processing core schedules the first task in the first queue of the first processing core in the first cycle of the first processing core, and the first queue of the first processing core and the second queue of the second processing core both include the first task in the first cycle of the first processing core, and the first cycle is a scheduling cycle of the first processing core; if the first task is not completed in the first cycle of the first processing core, the first processing core performs the following operations: adding the first task to the end of the first queue of the first processing core for scheduling the second cycle of the first processing core, the first cycle of the first processing core is earlier than the second cycle of the first processing core, that is, for the first processing core to schedule the first task at a subsequent time; moving the first task to the end of the second queue of the second processing core, that is, for the first processing core to schedule the first task at a subsequent time.

[0009] In the above technical solution, each of the multiple processing cores is provided with multiple queues with different priorities, and the same task is simultaneously deployed in different priority queues of different processing cores. After scheduling a task from its own queue, any one of the multiple processing cores still adds the task to its own first queue with the highest priority. For example, the multiple processing cores include a first processing core and a second processing core, and the multiple queues include a first queue and a second queue. In the first cycle of the first processing core, the first queue of the first processing core and the second queue of the second processing core both include the first task, so that the first processing core schedules the first task in the first queue of the first processing core in the first cycle of the first processing core. If the first task is not completed in the first cycle of the first processing core, the first processing core adds the first task to the end of the first queue of the first processing core and moves the first task to the end of the second queue of the second processing core for scheduling the first processing core and the second processing core at a subsequent time. Therefore, this method ensures the affinity of tasks and the load balancing of multiple processing cores.

[0010] Optionally, queue indication information may be provided corresponding to the first task, and the queue indication information may be used to indicate the queue in which the first task is located. For example, the queue indication information of the first task may be used to indicate that the first task is in the first queue of the first processing core, and to indicate that the first task is in the second queue of the second processing core. The first processing core may determine that the first task is in the second queue of the second processing core based on the queue indication information corresponding to the first task, and may move the first task to the end of the second queue of the second processing core.

[0011] In one possible implementation of the first aspect, moving the first task to the end of the second queue of the second processing core includes: deleting the first task from the second queue of the second processing core; and adding the first task to the end of the second queue of the second processing core for subsequent scheduling by the second processing core. In this possible implementation, by moving the first task to the end of the second queue of the second processing core, repeated scheduling of the first task by the second processing core can be avoided. Furthermore, if the first processing core does not schedule the first task at a later time, the second processing core can directly schedule the first task without requiring additional load balancing computational overhead.

[0012] In a possible implementation of the first aspect, the method further includes: when the first processing core does not schedule the first task, the second processing core schedules the first task in the second queue of the second processing core in the first cycle of the second processing core; if the first task is not completed in the first cycle of the second processing core, the second processing core performs the following operations: adding the first task to the end of the first queue of the second processing core for scheduling the second cycle of the second processing core, the first cycle of the second processing core being earlier than the second cycle of the second processing core; and moving the first task to the end of the second queue of the first processing core. In the above possible implementation, when the first processing core does not schedule the first task, the second processing core can directly schedule the first task in the second queue of the second processing core, thereby performing load balancing by default between the first processing core and the second processing core, without the need for additional load balancing computational overhead.

[0013] In a possible implementation of the first aspect, the multiple processing cores further include a third processing core, the multiple queues further include a third queue, the second queue has a higher priority than the third queue, and the third queue of the third processing core further includes a first task. The method further includes: when the first processing core and the second processing core have not scheduled the first task, the third processing core schedules the first task in the third queue of the third processing core in the first cycle of the third processing core; if the first task has not been completed in the first cycle of the third processing core, the third processing core performs the following operations: adding the first task to the end of the first queue of the third processing core for scheduling the second cycle of the third processing core, the first cycle of the third processing core being earlier than the second cycle of the third processing core; moving the first task to the end of the second queue of the first processing core, and moving the first task to the end of the third queue of the second processing core. In the above possible implementation, when the first processing core and the second processing core have not scheduled the first task, the third processing core can directly schedule the first task in the third queue of the third processing core, thereby performing load balancing by default between the first processing core and the third processing core, without the need for additional load balancing computational overhead. In addition, by adding the first task to the end of the first queue of the third processing core, moving the first task to the end of the second queue of the first processing core, and moving the first task to the end of the third queue of the second processing core, it is also possible to avoid the first task being repeatedly scheduled by the second processing core and the first processing core.

[0014] In a possible implementation of the first aspect, the multiple queues of the same processing core among the multiple processing cores constitute a logical queue in order of priority. In the above possible implementation, the multiple queues of the same processing core are logically connected in series to form a queue, that is, to form a logical queue. Taking 3 queues set up for each processing core as an example, if each scheduling needs to traverse the 3 queues, the performance of the scheduling will be relatively poor. In the embodiment of the present application, the 3 queues can actually be connected in series to form a logical queue. Then, when selecting a task, the processing core can proceed in the order of the first queue, the second queue, and the third queue, that is, if the first queue is not empty, the tasks in the second queue and the third queue are not considered. If the second queue is not empty, the tasks in the third queue are not considered, thereby greatly improving the scheduling performance.

[0015] Optionally, multiple queues of the same processing core may constitute a logical queue, and the logical queue may further correspond to at least two pieces of indication information, each of which may be used to indicate the head of each of the multiple queues. For example, the multiple queues include a first queue, a second queue, and a third queue. The logical queue may correspond to first indication information, second indication information, and third indication information. The first indication information may be used to indicate the head of the first queue, the second indication information may be used to indicate the head of the second queue, and the third indication information may be used to indicate the head of the third queue. Optionally, each of the at least two pieces of indication information may be a pointer.

[0016] In a possible implementation of the first aspect, the method further includes: each of the multiple processing cores sequentially executing tasks in the multiple queues according to the priority order of the multiple queues of the processing core. That is, each processing core can schedule tasks in its corresponding multiple queues in descending order of priority within its respective scheduling cycle. The scheduling cycles of different processing cores can be independent of each other. Taking the first processing core as an example, the first cycle of the first processing core can refer to a scheduling cycle of the first processing core. The first processing core can sequentially schedule tasks in the multiple queues of the first processing core in descending order of priority within the first cycle of the first processing core. In the above possible implementation, when selecting tasks, the processing core can select in the order of the first queue, the second queue, and the third queue. That is, if the first queue is not empty, tasks in the second and third queues are not considered. If the second queue is not empty, tasks in the third queue are not considered, thereby greatly improving scheduling performance.

[0017] In a possible implementation of the first aspect, the multiple processing cores further include a fourth processing core, and the method further includes: the fourth processing core assigning the multiple tasks to be scheduled to the multiple queues of the multiple processing cores; wherein, for any one of the multiple tasks, the task is included in queues of different priorities of different processing cores within the multiple processing cores. In the above possible implementation, by assigning the multiple tasks to be scheduled to the multiple queues of the multiple processing cores, the affinity of the tasks and the load balancing of the multiple processing cores can be ensured when the tasks are subsequently scheduled.

[0018] In a second aspect, a task scheduling device is provided, comprising a plurality of processing cores, each of the plurality of processing cores being provided with a plurality of queues, the plurality of processing cores comprising a first processing core and a second processing core, the plurality of queues comprising a first queue and a second queue, the priority of the first queue being higher than the priority of the second queue; the first processing core being configured to schedule a first task in the first queue of the first processing core in a first cycle of the first processing core, wherein both the first queue of the first processing core and the second queue of the second processing core include the first task in the first cycle of the first processing core; if the first task has not been completed in the first cycle of the first processing core, the first processing core is further configured to perform the following operations: adding the first task to the end of the first queue of the first processing core for scheduling in the second cycle of the first processing core, wherein the first cycle of the first processing core is earlier than the second cycle of the first processing core; and moving the first task to the end of the second queue of the second processing core.

[0019] In a possible implementation of the second aspect, the first processing core is further used to: delete the first task from the second queue of the second processing core; and add the first task to the end of the second queue of the second processing core for scheduling by the second processing core at a subsequent time.

[0020] In a possible implementation of the second aspect, the second processing core is used to schedule the first task in the second queue of the second processing core in the first cycle of the second processing core when the first processing core has not scheduled the first task; if the first task has not been completed in the first cycle of the second processing core, the second processing core is further used to perform the following operations: add the first task to the end of the first queue of the second processing core for scheduling in the second cycle of the second processing core, the first cycle of the second processing core being earlier than the second cycle of the second processing core; and move the first task to the end of the second queue of the first processing core.

[0021] In a possible implementation of the second aspect, the multiple processing cores also include a third processing core, the multiple queues also include a third queue, the second queue has a higher priority than the third queue, and the third queue of the third processing core also includes the first task; the third processing core is used to schedule the first task in the third queue of the third processing core in the first cycle of the third processing core when the first processing core and the second processing core have not scheduled the first task; if the first task is not completed in the first cycle of the third processing core, the third processing core is also used to perform the following operations: add the first task to the end of the first queue of the third processing core for scheduling the second cycle of the third processing core, the first cycle of the third processing core being earlier than the second cycle of the third processing core; move the first task to the end of the second queue of the first processing core, and move the first task to the end of the third queue of the second processing core.

[0022] In a possible implementation of the second aspect, the multiple queues of the same processing core among the multiple processing cores form a logical queue in order of priority. For example, the first queue, the second queue, and the third queue of the first processing core may form a logical queue in order of high to low priority; the first queue, the second queue, and the third queue of the second processing core may also form a logical queue in order of high to low priority; and the first queue, the second queue, and the third queue of the third processing core may also form a logical queue in order of high to low priority.

[0023] In a possible implementation of the second aspect, each of the multiple processing cores is further configured to execute tasks in the multiple queues in sequence according to the priority order of the multiple queues of the processing core. That is, each processing core can schedule tasks in the multiple queues corresponding to it in order of priority from high to low within its respective scheduling cycle. The scheduling cycles of different processing cores can be independent of each other. Taking the first processing core as an example, the first cycle of the first processing core can refer to a scheduling cycle of the first processing core, and the first processing core can schedule tasks in the multiple queues of the first processing core in sequence according to priority from high to low within the first cycle of the first processing core.

[0024] In a possible implementation of the second aspect, the multiple processing cores also include a fourth processing core; the fourth processing core is used to allocate the multiple tasks to be scheduled to the multiple queues of the multiple processing cores; wherein, for any one of the multiple tasks, the task is included in queues of different priorities of different processing cores in the multiple processing cores.

[0025] In a third aspect, a task scheduling device is provided, which includes a multi-core processor and a memory, in which instructions are stored. When the multi-core processor executes the instruction, the task processing device executes the task scheduling method provided in the first aspect or any possible implementation of the first aspect.

[0026] In a fourth aspect, a vehicle is provided, which includes the task scheduling device provided by the second aspect or any possible implementation of the second aspect, or includes the task scheduling device provided by the third aspect.

[0027] In a fifth aspect, a readable storage medium is provided, in which instructions are stored. When the instructions are executed by a device, the device executes the task scheduling method provided in the first aspect or any possible implementation of the first aspect.

[0028] In a sixth aspect, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute a task scheduling method as provided in the first aspect or any possible implementation of the first aspect.

[0029] It can be understood that the beneficial effects that can be achieved by any of the task scheduling devices, vehicles, readable storage media and computer program products provided above can correspond to the beneficial effects of the task scheduling method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a CFS scheduling architecture provided in an embodiment of the present application;

[0031] FIG2 is a schematic diagram of a single processing core rotating processing tasks provided by an embodiment of the present application;

[0032] FIG3 is a schematic diagram of load balancing tasks among multiple cores provided by an embodiment of the present application;

[0033] FIG4 is a schematic diagram of a scheduling architecture of BFS and MuqSS provided in an embodiment of the present application;

[0034] FIG5 is a schematic diagram of a BFS scheduling method provided in an embodiment of the present application;

[0035] FIG6 is a schematic structural diagram of a vehicle provided in an embodiment of the present application;

[0036] FIG7 is a schematic diagram of the structure of a task scheduling device provided in an embodiment of the present application;

[0037] FIG8 is a schematic diagram of a software architecture in a task scheduling device provided in an embodiment of the present application;

[0038] FIG9 is a flowchart of a task scheduling method provided in an embodiment of the present application;

[0039] FIG10 is a schematic diagram of a task scheduling method provided by an embodiment of the present application;

[0040] FIG11 is a flow chart of another task scheduling method provided in an embodiment of the present application;

[0041] FIG12 is a schematic diagram of another task scheduling provided in an embodiment of the present application;

[0042] FIG13 is a schematic diagram of another task scheduling provided in an embodiment of the present application;

[0043] FIG14 is a flow chart of another task scheduling method provided in an embodiment of the present application;

[0044] FIG15 is a flow chart of another task scheduling method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following sections discuss the making and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use this description and technology and do not limit the scope of this application.

[0046] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0047] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0048] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0049] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0050] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] Before introducing the embodiments of the present application, the relevant application scenarios involved in the present application are first introduced and explained.

[0052] With the advancement of modern computer hardware, single-core processors have gradually evolved into multi-core processors, and processor architectures have become increasingly complex. Symmetric multiprocessing (SMP), a mainstream modern processor architecture, features shared and non-shared L1, L2, and L3 caches between cores. Meanwhile, the corresponding kernel scheduling algorithms have evolved from O(1) to O(N), from rotating staircase deadline (RSDL) scheduling to brain-fuck scheduling (BFS), and finally to complete fair scheduling (CFS). Furthermore, several deadline scheduler variants have emerged, including first-input first-output (FIFO / RR) real-time schedulers and earliest eligible virtual deadline first (EEVDF). However, CFS remains the mainstream task scheduling algorithm in the Linux kernel.

[0053] Scheduling algorithms in SMP systems primarily address the fairness and efficiency of task execution, essentially addressing two core issues: affinity and load balancing. Affinity refers to the efficiency with which tasks are executed on a particular core. Complex cache mechanisms in processor architectures can cause a pattern of hot and cold tasks. If a task has just run on a core, the cached information is not immediately overwritten. When it runs on the same core again, the memory does not need to be re-read and written, significantly accelerating the task's execution rate. This is task affinity. The closer the execution time of a task on the same core, the higher the affinity; vice versa. Load balancing aims to evenly distribute tasks across cores in a multi-core architecture, preventing some cores from being extremely busy while others are idle. Good load balancing significantly improves hardware utilization and thus task efficiency. Generally, a good general-purpose scheduler must address both affinity and load balancing to maximize hardware performance and improve program efficiency.

[0054] In order to solve the above-mentioned problem of balancing affinity and load balancing, the following solutions are usually adopted in related technologies.

[0055] The first is a scheduling architecture that uses fully fair scheduling (CFS). As shown in Figure 1, in a multi-core architecture, each of the multiple processing cores (for example, processing core 0 to processing core 3) is provided with a runnable queue, and each processing core can schedule tasks in the runnable queue through the scheduler. The running time of the same task is divided into multiple time slices, and the time slices of different tasks can be arranged into the runnable queues of different processing cores through load balancing. Multiple time slices corresponding to the same task can be arranged into the runnable queue of the same processing core. In addition, as shown in Figure 2, for a single processing core, the processing core can process different tasks in multiple time slices in a round-robin manner, for example, processing task 1 in time slices T0 and T4, processing task 2 in time slices T1 and T5, processing task 3 in time slices T2 and T6, and processing task 4 in time slices T3 and T7.

[0056] The above solution can ensure the affinity of tasks to the greatest extent possible. However, it is easy for one processing core to be extremely busy while others are relatively idle. Therefore, a load balancing solution is needed to balance the tasks among multiple cores.

[0057] For example, FIG3 is a schematic diagram of load balancing tasks among multiple cores. The multiple cores may include processing cores 0 to 3. The runnable queues of each processing core may include queues corresponding to different scheduling strategies (e.g., stop scheduling, real-time (RT) scheduling, CFS scheduling, and idle scheduling). FIG3 takes four queues as an example and represents them as queues a to d. Among them, queue a of processing core 0 is empty, queue b includes 3 tasks, queue c includes 4 tasks, and queue d includes 1 task; queue a of processing core 1 is empty, queue b includes 2 tasks, queue c includes 3 tasks, and queue d includes 1 task; queue a of processing core 2 is empty, queue b is empty, queue c includes 2 tasks, and queue d includes 1 task; queue a of processing core 3 is empty, queue b is empty, queue c is empty, and queue d includes 1 task. That is, processing core 1 is busy, processing core 2 is relatively idle, and processing core 3 is idle.

[0058] In Figure 3 above, the task scheduling method may include: setting up a separate runnable queue for each processing core; adding ready tasks to the runnable queue of a processing core; calculating the virtual runtime (vruntime) for each task based on the task's elapsed time; sorting tasks in ascending order of vruntime; allocating equal time slices to each task in the runnable queue; and recalculating the vruntime after a processing core has completed its time slice and placing it at the end of the ready queue. Load balancing in Figure 3 above can be achieved in the following three ways: first, active balancing, where a busy processing core actively searches for an idle processing core to transfer tasks to, for example, processing core 1 transfers tasks to processing cores 2 and 3; second, idle balancing, where a processing core enters an idle state, triggering load balancing and stealing tasks from adjacent processing cores, for example, processing cores 2 and 3 steal tasks from processing core 1; and third, timed balancing, where a timer triggers the load balancing module to perform task balancing.

[0059] While the above methods can achieve load balancing, they are relatively costly. Active balancing requires additional load balancing overhead on already busy cores, making them even busier. Idle balancing requires weighing the load balancing overhead against the cost of idle waiting, resulting in discontinuous, small, fragmented idle time, which underutilizes core resources. Furthermore, the load balancing algorithm relies on the non-uniform memory access (NUMA) framework to determine affinity and steal tasks from adjacent cores. Timed balancing also introduces unnecessary balancing overhead. These shortcomings are primarily due to the fact that CFS, when designed, focused on task affinity across the entire system, while relatively neglecting load balancing design. This necessitates additional measures to compensate, but these measures cannot offset the additional overhead incurred by load balancing.

[0060] The second type is a scheduling architecture that uses brain-dead scheduling (BFS) or multiple queue skiplist scheduling (MuqSS).

[0061] As shown in (a) of Figure 4, when the BFS scheduling architecture is adopted, there is only one global run queue (or called the global run queue), and all processing cores (for example, processing cores 0 to 3) share the same run queue. The tasks in this run queue constitute a global linked list. This design takes into account the natural load balancing of tasks and does not require additional load balancing costs. When a processing core enters the idle state, the scheduler automatically assigns running tasks to the processing core, thereby utilizing the hardware capabilities of multiple cores. MuqSS scheduling is an extension of BFS, mainly used to solve the problem of concurrent locks in the global run queue in BFS. As shown in (b) of Figure 4, in the MuqSS scheduling architecture, the global linked list of the global queue is split into multiple skiplists, each of which is set with a lock. Multiple processing cores dispatch running tasks from these multiple queues in a decentralized manner through a try lock mechanism.

[0062] Specifically, as shown in Figure 5, the scheduling method using BFS can include: multiple processing cores share a global run queue based on a lock mechanism, that is, a shared global linked list; tasks in the global run queue are sorted according to a certain priority; when a scheduling point arrives, the main scheduler retrieves the task from the head of the global run queue for the corresponding processing core and dispatches the task to a specific processing core through process switching; after the task's time slice expires, the task is placed back into the global run queue. In addition, during the task scheduling process, the following operations can be performed on the global run queue: modifying scheduling parameters, performing state migration, creating and exiting, and updating the time slices of tasks in the queue through interrupt processing. Figure 5 uses multiple processing cores, including processing cores 0 to n, as an example for explanation.

[0063] The above solution uses a global shared queue for scheduling, naturally solving the problem of load balancing across multiple cores. This eliminates idle cores and introduces no additional load balancing costs. However, this design completely ignores task affinity. Tasks are assigned to different cores completely randomly, completely ignoring the cache of previous tasks. Therefore, each scheduling operation may require a cache refresh, resulting in low efficiency per core. Furthermore, multiple cores competing for the global queue require a locking mechanism. If the number of cores exceeds 16, the overhead caused by lock contention becomes unbearable. The MuqSS scheduling architecture optimizes the locking problem in BFS by using a skip table and a trial lock mechanism. However, this design also inherently randomly assigns tasks to different cores, thus failing to effectively address the task affinity issue. These shortcomings are primarily due to the fact that architectures such as BFS and MuqSS focus on task load balancing while neglecting affinity design, resulting in insufficient task affinity and low efficiency per core.

[0064] Based on this, an embodiment of the present application provides a task scheduling method, which can be used to solve multiple problems in the above-mentioned related technologies, such as ensuring high affinity of tasks, making full use of the hardware cache architecture of the processor, taking into account the natural load balancing, making full use of multiple processing cores to reduce or eliminate fragmented idleness, and minimizing the overhead of lock contention during load balancing. Among them, the task scheduling method can be applied to a task scheduling device including multiple processing cores, each of the multiple processing cores is provided with multiple queues with different priorities, and the same task is simultaneously deployed in different priority queues of different processing cores. Any one of the multiple processing cores, after scheduling a task from its own queue, still adds the task to its own first queue with the highest priority, thereby ensuring the affinity of the task and the load balancing of multiple processing cores.

[0065] The technical solutions provided in the embodiments of the present application can be applied to various terminal devices of multi-core processors. The terminal device may include, but is not limited to, a mobile phone, a tablet computer, a computer, a laptop computer, an ultra-mobile personal computer (umPC), a netbook, a camera, a camera, a wearable device, a vehicle, an in-vehicle device, a virtual reality (VR) device, an augmented reality (AR) device, or an intelligent robot. Optionally, the above-mentioned vehicle may include, but is not limited to, a road vehicle, a water vehicle, an air vehicle, an industrial device, an agricultural device, or an entertainment device. The vehicle can be a vehicle in a broad sense, for example, the vehicle can be a vehicle (such as a commercial vehicle, a passenger car, a car, an electric vehicle, a ship, an airplane, a train, a high-speed rail, etc.), an industrial vehicle (such as a forklift, a trailer, a tractor, etc.), an engineering vehicle (such as an excavator, a bulldozer, a crane, etc.), agricultural equipment (such as a mower, a harvester, etc.), amusement equipment, a toy vehicle, etc. For the convenience of description, the structure of the terminal device is illustrated below using a vehicle as an example.

[0066] Figure 6 is a structural schematic diagram of a vehicle 100 provided in an embodiment of the present application, and the vehicle 100 may have an automatic driving function. In one possible embodiment, the vehicle 100 is configured to be in a fully or partially automatic driving mode. For example, the vehicle 100 can control itself while being in the automatic driving mode, and can determine the current state of the vehicle and its surrounding environment through human operation, determine the possible behavior of at least one other vehicle in the surrounding environment, and determine the confidence level corresponding to the possibility of the other vehicle performing the possible behavior, and control the vehicle 100 based on the determined information. When the vehicle 100 is in the automatic driving mode, the vehicle 100 can be set to operate without human interaction. In another embodiment, the vehicle 100 can be a vehicle with the P gear locking mechanism canceled, and / or a vehicle that supports remote parking assist (RPB) function.

[0067] The vehicle 100 may include various subsystems, such as a travel system 102, a sensor system 104, a control system 106, one or more peripheral devices 108, a power source 110, a computer system 112, and a user interface 116. Alternatively, the vehicle 100 may include more or fewer subsystems, and each subsystem may include multiple components. In addition, each subsystem and component of the vehicle 100 may be interconnected via wired or wireless connections.

[0068] Propulsion system 102 may include components that provide powered motion for vehicle 100. In one embodiment, propulsion system 102 may include engine 118, energy source 119, transmission 120, and wheels 121 (or tires). Engine 118 may be an internal combustion engine, an electric motor, an air compression engine, or other engine combinations, such as a hybrid engine consisting of a gasoline engine and an electric motor, or a hybrid engine consisting of an internal combustion engine and an air compression engine. Engine 118 converts energy source 119 into mechanical energy.

[0069] Examples of energy source 119 include gasoline, diesel, other petroleum-based fuels, propane, other compressed gas-based fuels, ethanol, solar panels, batteries, and other sources of electricity. Energy source 119 may also provide energy to other systems of vehicle 100.

[0070] The transmission 120 can transmit mechanical power from the engine 118 to the wheels 121. The transmission 120 may include a gearbox, a differential, and a drive shaft. In some embodiments, the transmission 120 may also include other components, such as a clutch. The drive shaft may include one or more shafts that can be coupled to one or more wheels 121.

[0071] The sensor system 104 may include several sensors that sense information about the environment surrounding the vehicle 100. For example, the sensor system 104 may include a positioning system 122 (the positioning system may be a global positioning system (GPS) system, a BeiDou system, or other positioning systems), an inertial measurement unit (IMU) 124, a radar 126, a laser rangefinder 128, and a camera 130. The sensor system 104 may also include sensors for the internal systems of the monitored vehicle 100 (e.g., an in-vehicle air quality monitor, a fuel gauge, an oil temperature gauge, etc.). Sensor data from one or more of these sensors may be used to detect objects and their corresponding characteristics (position, shape, direction, speed, etc.). This detection and recognition is a key function for the safe operation of the autonomous vehicle 100.

[0072] Positioning system 122 may be used to estimate the geographic location of vehicle 100. IMU 124 may be used to sense changes in position and orientation of vehicle 100 based on inertial acceleration. In some embodiments, IMU 124 may be a combination of an accelerometer and a gyroscope.

[0073] Radar 126 may utilize radio signals to sense objects within the surrounding environment of vehicle 100. In some embodiments, in addition to sensing objects, radar 126 may also be used to sense the speed and / or heading of the objects.

[0074] The laser rangefinder 128 may utilize laser light to sense objects in the environment in which the vehicle 100 is located. In some embodiments, the laser rangefinder 128 may include one or more laser sources, a laser scanner, and one or more detectors, among other system components.

[0075] The camera 130 may be used to capture multiple images of the surrounding environment of the vehicle 100. The camera 130 may be a still camera or a video camera.

[0076] Control system 106 controls the operation of vehicle 100 and its components. Control system 106 may include various elements, including a steering system 132 , a throttle 134 , a braking system 136 , a sensor fusion algorithm 138 , a computer vision system 140 , a path control system 142 , and an obstacle avoidance system 144 .

[0077] The steering system 132 is operable to adjust the forward direction of the vehicle 100. For example, in one embodiment, the steering system 132 may be a steering wheel system.

[0078] The throttle 134 is used to control the operating speed of the engine 118 and, in turn, the speed of the vehicle 100 .

[0079] The braking system 136 is a system for applying a certain braking force to the wheels 121, thereby forcibly braking them to a certain extent. The function of the braking system 136 is to force the moving vehicle 100 to slow down or even stop according to the requirements of the driver or the controller, or to stabilize the stopped vehicle 100 under various road conditions (for example, on a slope), or to maintain a stable speed of the vehicle 100 traveling downhill. In one embodiment, the braking system 136 can use friction to slow down the wheels 121. In other embodiments, the braking system 136 can convert the kinetic energy of the wheels 121 into electric current, and the braking system 136 can also take other forms to slow down the rotation speed of the wheels 121 to control the speed of the vehicle 100.

[0080] The computer vision system 140 can be operated to process and analyze images captured by the camera 130 to identify objects and / or features in the environment surrounding the vehicle 100. The objects and / or features may include traffic signs, road boundaries, and obstacles. The computer vision system 140 can use object recognition algorithms, structure from motion (SFM) algorithms, video tracking, and other computer vision techniques. In some embodiments, the computer vision system 140 can be used to map the environment, track objects, estimate the speed of objects, and so on.

[0081] The route control system 142 is used to determine the driving route of the vehicle 100. In some embodiments, the route control system 142 may combine data from the sensors 138, the GPS 122, and one or more predetermined maps to determine the driving route for the vehicle 100.

[0082] The obstacle avoidance system 144 is used to identify, assess, and avoid or otherwise negotiate potential obstacles in the environment of the vehicle 100 .

[0083] Of course, in one example, the control system 106 may include additional or alternative components other than those shown and described, or may include fewer than some of the components shown.

[0084] Vehicle 100 interacts with external sensors, other vehicles, other computer systems, or users via peripherals 108. Peripherals 108 may include a wireless communication system 146, an onboard computer 148, a microphone 150, and / or a speaker 152.

[0085] In some embodiments, peripheral devices 108 provide a means for a user of vehicle 100 to interact with user interface 116. For example, onboard computer 148 can provide information to the user of vehicle 100. User interface 116 can also operate onboard computer 148 to receive user input. Onboard computer 148 can be operated via a touch screen. In other cases, peripheral devices 108 can provide a means for vehicle 100 to communicate with other devices located within the vehicle. For example, microphone 150 can receive audio (e.g., voice commands or other audio input) from the user of vehicle 100. Similarly, speaker 152 can output audio to the user of vehicle 100.

[0086] The wireless communication system 146 can communicate wirelessly with one or more devices directly or via a communication network. For example, the wireless communication system 146 can use 3G cellular communication, such as code division multiple access (CDMA), EVDO, global system for mobile communications (GSM) / general packet radio service (GPRS), or 4G cellular communication, such as long term evolution (LTE), or 5G cellular communication. The wireless communication system 146 can use WiFi to communicate with a wireless local area network (WLAN). In some embodiments, the wireless communication system 146 can use an infrared link, Bluetooth or ZigBee to communicate directly with the device. Other wireless protocols, such as various vehicle communication systems, for example, the wireless communication system 146 may include one or more dedicated short range communications (DSRC) devices, which may include public and / or private data communications between vehicles and / or roadside stations.

[0087] Power source 110 can provide power to various components of vehicle 100. In one embodiment, power source 110 can be a rechargeable lithium-ion or lead-acid battery. One or more battery packs of such batteries can be configured as a power source to provide power to various components of vehicle 100. In some embodiments, power source 110 and energy source 119 can be implemented together, such as in some all-electric vehicles.

[0088] Some or all functions of the vehicle 100 are controlled by a computer system 112. The computer system 112 may include at least one processor 113 that executes instructions 115 stored in a non-transitory computer-readable medium, such as a memory 114. The computer system 112 may also be a plurality of computing devices that control individual components or subsystems of the vehicle 100 in a distributed manner.

[0089] The processor 113 may include one or more processing units, which may include, but are not limited to, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), a network processing unit (NPU), a graphics processing unit (GPU), an image signal processor (ISP), a microcontroller, or a microprocessor. Furthermore, the processor 113 may also include other hardware circuits or accelerators, such as application-specific integrated circuits, field-programmable gate arrays or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Alternatively, the processor 113 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, or the like. In one possible embodiment, the processor 113 may include a multi-core processor, which may include a quad-core processor, an octa-core processor, a hexa-core processor, or the like. Although the figure functionally illustrates the processor, memory, and other components of a computer in the same block, those skilled in the art should understand that the processor, computer, or memory may actually include multiple processors, computers, or memories that may or may not be stored in the same physical housing. For example, the memory may be a hard drive or other storage medium located in a housing distinct from the computer. Thus, references to a processor or computer will be understood to include references to a collection of processors or computers or memories that may or may not operate in parallel. Rather than using a single processor to perform the steps described herein, some components, such as the steering assembly and the reduction assembly, may each have their own processor that performs only calculations related to the functionality of the component.

[0090] In various aspects described herein, the processor can be located remotely from the vehicle and in wireless communication with the vehicle. In other aspects, some of the processes described herein are performed on a processor disposed within the vehicle while others are performed by a remote processor, including taking the necessary steps to perform a single maneuver.

[0091] In some embodiments, memory 114 may contain instructions 115 (e.g., program logic) that are executable by processor 113 to perform various functions of vehicle 100, including those described above. Memory 114 may also contain additional instructions, including instructions for transmitting data to, receiving data from, interacting with, and / or controlling one or more of travel system 102, sensor system 104, control system 106, and peripherals 108.

[0092] In addition to the instructions 115, the memory 114 may also store data such as road maps, route information, the vehicle's location, direction, speed, and other such vehicle data, as well as other information. This information may be used by the vehicle 100 and the computer system 112 during operation of the vehicle 100 in autonomous, semi-autonomous, and / or manual modes.

[0093] User interface 116 is used to provide information to or receive information from a user of vehicle 100. Optionally, user interface 116 may include one or more input / output devices within the set of peripherals 108, such as wireless communication system 146, onboard computer 148, microphone 150, and speaker 152.

[0094] Computer system 112 may control functions of vehicle 100 based on input received from various subsystems (e.g., travel system 102, sensor system 104, and control system 106) and from user interface 116. For example, computer system 112 may utilize input from control system 106 in order to control steering system 132 to avoid obstacles detected by sensor system 104 and obstacle avoidance system 144. In some embodiments, computer system 112 may be operable to provide control over many aspects of vehicle 100 and its subsystems.

[0095] Alternatively, one or more of the above components may be installed or associated separately from the vehicle 100. For example, the memory 114 may be partially or completely separate from the vehicle 100. The above components may be communicatively coupled together in a wired and / or wireless manner.

[0096] Optionally, the above components are only an example. In actual applications, the components in the above modules may be added or deleted according to actual needs. The above examples should not be understood as limitations on the embodiments of the present application.

[0097] An autonomous vehicle, such as vehicle 100 above, traveling on a road can identify objects in its surroundings to determine adjustments to its current speed. The objects can be other vehicles, traffic control devices, or other types of objects. In some examples, each identified object can be considered independently, and the speed adjustment to be made to the autonomous vehicle can be determined based on its respective characteristics, such as its current speed, acceleration, and distance from the vehicle.

[0098] Optionally, the autonomous vehicle 100 or a computing device associated with the autonomous vehicle 100 (e.g., computer system 112, computer vision system 140, memory 114) can predict the behavior of the identified objects based on their characteristics and the state of the surrounding environment (e.g., traffic, rain, ice on the road, etc.). Optionally, the behavior of each identified object depends on the behavior of each other, so the behavior of all identified objects can be considered together to predict the behavior of a single identified object. The vehicle 100 can adjust its speed based on the predicted behavior of the identified objects. In other words, the autonomous vehicle can determine what stable state the vehicle will need to adjust to (e.g., accelerate, decelerate, or stop) based on the predicted behavior of the objects. Other factors can also be considered in determining the speed of the vehicle 100, such as the lateral position of the vehicle 100 on the road, the curvature of the road, the proximity of static and dynamic objects, etc.

[0099] In addition to providing instructions to adjust the speed of the autonomous vehicle, the computing device may also provide instructions to modify the steering angle of vehicle 100 so that the autonomous vehicle follows a given trajectory and / or maintains a safe lateral and longitudinal distance from objects near the autonomous vehicle (e.g., cars in adjacent lanes on the road).

[0100] It is understood that the structure of the vehicle 100 shown in the figure does not constitute a limitation on the vehicle 100, and the vehicle 100 may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0101] FIG7 is a schematic diagram of the structure of a task scheduling device provided in an embodiment of the present application, wherein the task scheduling device may include multiple processing cores, each of which may be provided with multiple queues (or referred to as multiple volunteer queues), and the priorities of the multiple queues are different. For example, the multiple processing cores include 8 processing cores and are represented as processing core 0 to processing core 7, respectively. Each processing core is provided with 3 queues and are represented as a first queue Q1, a second queue Q2, and a third queue Q3, respectively. The priority of the first queue Q1 may be level 0, the priority of the second queue Q2 may be level 1, and the priority of the third queue Q3 may be level 2, that is, the priority of the first queue Q1 is greater than the priority of the second queue Q2, and the priority of the second queue Q2 is greater than the priority of the third queue Q3.

[0102] In the task scheduling device, the multiple queues of each processing core can be used to mount (or be called deploying) tasks with different affinities, and the different affinities can be distinguished by the distance of the task from the last scheduled processing core. The multiple queues of each processing core can form a logical queue in order of priority, and the tasks in each queue of the multiple queues can be sorted in a certain order, such as sorting by virtual running time. Each processing core can schedule the tasks in the multiple queues in sequence according to the priority order of the multiple queues corresponding to each of them. If the high-priority queue is not empty, the low-priority queue will not be considered. For example, if the first queue Q1 is not empty, the tasks in the second queue Q2 and the third queue Q3 will not be considered. If the second queue Q2 is not empty, the tasks in the third queue Q3 will not be considered. Among them, the same task can be deployed in queues of different priorities of different processing cores at the same time. Exemplarily, the tasks to be scheduled include task 1 and task 2. Task 1 is simultaneously deployed in the first queue Q1 of processing core 0, the second queue Q2 of processing core 1, and the third queue Q3 of processing core 3. Task 2 is simultaneously deployed in the first queue Q1 of processing core 7, the second queue Q2 of processing core 6, and the third queue Q3 of processing core 4.

[0103] Optionally, the multiple processing cores in the task scheduling device may be further divided into multiple clusters, each of which may include a portion of the processing cores, and different processing cores in the same cluster may share an L2 cache. Exemplarily, the multiple processing cores include processing cores 0 through 7, where processing cores 0 through 3 may be located in a first cluster, and processing cores 4 through 7 may be located in a second cluster.

[0104] It can be understood that the above Figure 7 is used as an example to illustrate that the task scheduling device includes 8 processing cores, and each processing core is provided with 3 queues. In actual applications, the task scheduling device can also include a greater or lesser number of processing cores, and each processing core can be provided with 2 or 4 queues of different numbers. The above example does not constitute a limitation to the embodiments of the present application.

[0105] Figure 8 is a schematic diagram of a software architecture in a task scheduling device provided in an embodiment of the present application. The software architecture runs on the hardware resources of the task scheduling device. For example, the hardware resources may include a processor. The processor may be a central processing unit (CPU). The software architecture may run on the CPU. The software architecture may include a general scheduler and a scheduler class. The general scheduler may include a main scheduler and a periodic scheduler. The scheduler class may include schedulers corresponding to different scheduling strategies. For example, the different scheduling strategies may include real-time scheduling, voluntary scheduling, and stop scheduling. Each scheduler in the scheduler class may be provided with a corresponding scheduling queue, which may be used to store multiple tasks that the scheduler needs to schedule for execution.

[0106] The processor can execute context switching when it needs to run the main scheduler and the periodic scheduler. The main scheduler, the periodic scheduler, and the scheduler class can be used to manage kernel scheduling of the task scheduling device. In one embodiment, the main scheduler can be used to select a scheduler from the scheduler class, and the selected scheduler can be used to schedule the execution of tasks in the corresponding scheduling queue.

[0107] It is understood that in the embodiments of the present application, a scheduler can be provided in the scheduler class of the above-mentioned software architecture to support the task scheduling device in executing the task scheduling method provided below. For example, the volunteer scheduler in the above-mentioned scheduler class can be used to support the task scheduling device in executing the task scheduling method provided in the embodiments of the present application. Specifically, this can be achieved by having the corresponding processing core run the volunteer scheduler to schedule the corresponding task.

[0108] After introducing the structure and software architecture of the task scheduling device, the task scheduling method provided in the embodiment of the present application is described in detail below.

[0109] Figure 9 is a flow chart of a task scheduling method provided in an embodiment of the present application. The task scheduling method can be applied to the task scheduling device provided above, which includes multiple processing cores, and each of the multiple processing cores is provided with multiple queues. The multiple processing cores include a first processing core and a second processing core, and the multiple queues include a first queue and a second queue, and the priority of the first queue is higher than the priority of the second queue. In the first cycle of the first processing core, the first queue of the first processing core and the second queue of the second processing core both include the first task. At this time, the first task can be scheduled according to the following method steps. For ease of description, the first queue of the first processing core is represented as Q11, the second queue of the first processing core is represented as Q12, the first queue of the second processing core is represented as Q21, and the second queue of the second processing core is represented as Q22.

[0110] S201 : A first processing core schedules a first task in a first queue Q11 of the first processing core in a first cycle of the first processing core.

[0111] Among them, any queue of any processing core among the multiple processing cores can be empty or include one or more tasks. Each processing core can schedule tasks in its corresponding multiple queues in descending order of priority within its respective scheduling cycle. The scheduling cycles of different processing cores can be independent of each other. Taking the first processing core as an example, the first cycle of the first processing core can refer to a scheduling cycle of the first processing core. The first processing core can schedule tasks in its multiple queues in descending order of priority within the first cycle of the first processing core.

[0112] Furthermore, taking the first processing core as an example, the first queue Q11 of the first processing core may include one or more tasks, and the first task may be any one of the one or more tasks. When the first queue Q11 of the first processing core includes multiple tasks, the first processing core may schedule and execute the multiple tasks sequentially in the order of the multiple tasks within the first processing core's first cycle. If the first processing core does not schedule all the tasks in the first queue Q11 of the first processing core within the first processing core's first cycle, the unscheduled tasks will continue to be scheduled at a later time.

[0113] Similarly, the second queue Q11 of the first processing core may also include one or more tasks. If the first processing core completes scheduling the tasks in the first queue Q11 of the first processing core within the first processing cycle of the first processing core, the first processing core may continue to schedule tasks in the second queue Q12 of the first processing core. If the first processing core does not complete scheduling the tasks in the first queue Q11 of the first processing core within the first processing cycle of the first processing core, the first processing core ignores the tasks in the second queue Q12 of the first processing core.

[0114] Optionally, the multiple queues corresponding to each processing core may further include a third queue, and the second queue has a higher priority than the third queue. For ease of description, the third queue of the first processing core may be represented as Q13 below. Taking the first processing core as an example, if the first processing core completes scheduling of tasks in the second queue Q12 of the first processing core within the first cycle of the first processing core, the first processing core may continue to schedule tasks in the third queue Q13 of the first processing core. If the first processing core has not completed scheduling of tasks in the first queue Q11 of the first processing core within the first cycle of the first processing core, the first processing core ignores tasks in the second queue Q12 and the third queue Q13 of the first processing core. If the first processing core has not completed scheduling of tasks in the second queue Q12 of the first processing core within the first cycle of the first processing core, the first processing core ignores tasks in the third queue Q13 of the first processing core.

[0115] Exemplarily, as shown in Figure 10, the first queue Q11 of the first processing core includes 6 tasks and are respectively represented as tasks a to task f, the second queue Q12 of the first processing core includes 3 tasks and are respectively represented as tasks g to task i, and the third queue Q13 of the first processing core includes 3 tasks and are respectively represented as tasks j to task l. Then: the first processing core schedules tasks a to task f in the first queue Q11 within the first cycle of the first processing core, and ignores tasks g to task i in the second queue Q12 of the first processing core, and tasks j to task l in the third queue Q13 of the first processing core.

[0116] The above Figure 10 shows the high-affinity operation process on a single processing core, that is, when there are many tasks in multiple queues of a certain processing core or the task execution time is long, causing the processing core to be busy, then the processing core can give priority to selecting tasks from the first queue. If all tasks in the first queue are not executed within a scheduling cycle, the tasks in the second and third queues are ignored.

[0117] In one possible embodiment, when the first queue Q11 of the first processing core and the second queue Q22 of the second processing core both include a first task, the first processing core may schedule the first task in the first queue Q11 of the first processing core within the first cycle of the first processing core. For example, the first processing core may wake up the first task in the first queue Q11 within the first cycle of the first processing core, select the first task from the first queue Q11, and execute it. The specific execution time may be equal to the time slice allocated to the first task. The time slice may refer to the runtime allocated by the processing core to a task, and the time slices corresponding to different tasks may be the same or different.

[0118] After the first processing core schedules the first task in the first queue Q11 of the first processing core, if the first task has completed its first cycle on the first processing core, the first processing core may delete the first task from the queues of other processing cores or invalidate the first task in the queues of other processing cores to prevent the other processing cores from repeatedly scheduling the first task. For example, if the second queue Q22 of the second processing core includes the first task, the first processing core may delete the first task from the second queue Q22 of the second processing core to prevent the second processing core from repeatedly scheduling the first task.

[0119] After the first processing core schedules the first task in the first queue Q11 of the first processing core, if the first task has not yet completed its first cycle, the first processing core executes the following steps: S202 and S203. S202 and S203 may be performed in any order. FIG9 illustrates the example of S203 being performed after S202.

[0120] S202 : The first processing core adds the first task to the tail of the first queue Q11 of the first processing core for scheduling in the second cycle of the first processing core. The first cycle of the first processing core is earlier than the second cycle of the first processing core.

[0121] The second cycle of the first processing core may refer to a scheduling cycle after the first cycle of the first processing core. For example, the second cycle of the first processing core may be the first scheduling cycle after the first cycle of the first processing core, or the second or third scheduling cycle after the first cycle of the first processing core. When the number of tasks in the first queue Q11 of the first processing core is small, the first processing core may reschedule the first task added in S202 after the first cycle of the first processing core and in a scheduling cycle that is closer to the first cycle of the first processing core. When the number of tasks in the first queue Q11 of the first processing core is large, the first processing core may reschedule the first task added in S202 after the first cycle of the first processing core and in a scheduling cycle that is farther away from the first cycle of the first processing core.

[0122] S203 : The first processing core moves the first task to the end of the second queue Q22 of the second processing core.

[0123] The first task may be provided with queue indication information corresponding to it, and the queue indication information may be used to indicate the queue in which the first task is located. For example, the queue indication information of the first task may be used to indicate that the first task is in the first queue Q11 of the first processing core, and to indicate that the first task is in the second queue Q22 of the second processing core. The first processing core may determine the position of the first task in the queues of other processing cores based on the queue indication information corresponding to the first task.

[0124] In one possible embodiment, the first processing core moving the first task to the end of the second queue Q22 of the second processing core may include: the first processing core deleting the first task from the second queue Q22 of the second processing core; and the first processing core adding the first task to the end of the second queue of the second processing core for subsequent scheduling by the second processing core. Optionally, the first processing core deleting the first task from the second queue Q22 of the second processing core may be replaced by the first processing core marking the first task in the second queue Q22 of the second processing core as invalid.

[0125] That is, if the first task has not been completed in the first cycle of the first processing core, the first processing core can delete the first task in the second queue Q22 of the second processing core to avoid repeated scheduling of the first task by the second processing core; in addition, the first processing core adds the first task to the end of the second queue Q22 of the second processing core for scheduling by the second processing core at a subsequent time, so as to reallocate the first task to the second queue Q22 of the second processing core.

[0126] Optionally, the multiple processing cores further include a third processing core, and the multiple queues corresponding to each processing core further include a third queue, and the second queue has a higher priority than the third queue. For ease of description, hereinafter, the first queue of the third processing core is represented as Q31, the second queue of the third processing core is represented as Q32, the third queue of the third processing core is represented as Q33, the third queue of the first processing core is represented as Q13, and the third queue of the second processing core is represented as Q23.

[0127] In one possible embodiment, if the third queue Q33 of the third processing core still includes the first task, and after S201, the first task has not yet completed execution in the first cycle of the first processing core, the method further includes: the first processing core moving the first task to the end of the third queue Q33 of the third processing core. Furthermore, if the first task has completed execution in the first cycle of the first processing core, the first processing core may delete the first task from the third queue Q33 of the third processing core, so that the third processing core no longer schedules the first task repeatedly.

[0128] It can be understood that the relevant description of the first processing core moving the first task to the end of the third queue Q33 of the third processing core is similar to the description of the first processing core moving the first task to the end of the second queue Q22 of the second processing core in the above S203. Please refer to the detailed description in the above S203 for details, and the embodiments of the present application will not be repeated here.

[0129] Furthermore, after S202-S203, if, during a subsequent scheduling cycle of the first processing core, the first processing core is able to schedule the first task again according to the priority order of the first processing core's multiple queues, the first processing core may continue to execute the above steps S201-S203. If, during a subsequent scheduling cycle of the first processing core, the first processing core is busy and cannot schedule the task added to the first queue Q11 of the first processing core in S202, and the second processing core is able to schedule the first task, then, as shown in FIG11 , the method may further include S204a-S206a.

[0130] S204a: When the first processing core does not schedule the first task, the second processing core schedules the first task in the second queue of the second processing core in the first cycle of the second processing core.

[0131] The first cycle of the second processing core may refer to a scheduling cycle of the second processing core. The second processing core may schedule tasks in multiple queues of the second processing core in descending order of priority within the first cycle of the second processing core.

[0132] In addition, the first queue Q21 of the second processing core can be empty or include at least one task. When the first queue Q21 of the second processing core includes at least one task, the first processing core can schedule execution in sequence according to the order of the at least one task within the first cycle of the second processing core. The second queue Q11 of the second processing core can include one or more tasks, and the first task can be any one of the one or more tasks. If the first queue Q21 of the second processing core is empty, or the second processing core has scheduled the tasks in the first queue Q21 of the second processing core within the first cycle of the second processing core, the second processing core can continue to schedule tasks in the second queue Q22 of the second processing core, for example, scheduling the first task in the second queue Q22 of the second processing core.

[0133] For example, as shown in Figure 12, the first queue Q21 of the second processing core includes 2 tasks and are represented as tasks a to b respectively, the second queue Q22 of the second processing core includes 2 tasks and are represented as tasks c to d respectively, and the third queue Q23 of the second processing core includes 3 tasks and are represented as tasks e to g respectively. Then: the second processing core schedules tasks a to b in the first queue Q21, tasks c to d in the second queue Q22, and task e in the third queue Q23 within the first cycle of the second processing core, and ignores tasks f to g in the third queue Q23 of the second processing core.

[0134] In one possible embodiment, when both the first queue Q11 of the first processing core and the second queue Q22 of the second processing core include the first task, if the first processing core has not scheduled the first task, the second processing core may schedule the first task in the second queue Q22 of the second processing core in the first cycle of the second processing core. Exemplarily, the second processing core may wake up the first task in the second queue Q22 during the first cycle of the second processing core, select the first task from the second queue Q22, and execute it. The specific execution time may be equal to the time slice allocated to the first task.

[0135] After the second processing core schedules the first task in the second processing core's second queue Q22, if the first task has completed its first cycle on the second processing core, the second processing core may delete the first task from the queues of other processing cores, or invalidate the first task in the queues of other processing cores, so that other processing cores no longer schedule the first task. For example, if the first processing core's first queue Q11 includes the first task, the second processing core may delete the first task from the first processing core's first queue Q11, so that the first processing core no longer schedules the first task. If the third processing core's third queue Q33 also includes the first task, the second processing core may also delete the first task from the third processing core's third queue Q33, so that the third processing core no longer schedules the first task.

[0136] After the second processing core schedules the first task in the second queue Q22 of the second processing core, if the first task has not yet completed its first cycle in the second processing core, the second processing core executes the following steps: S205a and S206a. S205a and S206a may be executed in any order. The figure illustrates this by assuming that S206a occurs after S205a.

[0137] S205a: The second processing core adds the first task to the tail of the first queue Q21 of the second processing core for scheduling in the second cycle of the second processing core. The first cycle of the second processing core is earlier than the second cycle of the second processing core.

[0138] The second cycle of the second processing core may refer to a scheduling cycle after the first cycle of the second processing core. For example, the second cycle of the second processing core may be the first scheduling cycle after the first cycle of the second processing core, or the second or third scheduling cycle after the first cycle of the second processing core. When the number of tasks in the first queue Q21 of the second processing core is small, the second processing core may reschedule the first task added in S205a after the first cycle of the second processing core and in a scheduling cycle that is closer to the first cycle of the second processing core. When the number of tasks in the first queue Q21 of the second processing core is large, the second processing core may reschedule the first task added in S205a after the first cycle of the second processing core and in a scheduling cycle that is farther away from the first cycle of the second processing core.

[0139] For example, as shown in FIG13 , the first queue Q11 of the first processing core includes tasks a through c, the second queue Q12 of the first processing core is empty, the first queue Q21 of the second processing core includes tasks d through e, and the second queue Q22 of the second processing core includes task c. Assuming that the first processing core schedules tasks a and b within one of the first processing core's scheduling cycles, and the second processing core schedules tasks d, e, and c within one of the second processing core's scheduling cycles, then: after scheduling tasks a and b for execution, the first processing core adds tasks a and b to the first queue Q11 of the first processing core; after scheduling tasks d, e, and c for execution, the second processing core adds tasks d, e, and c to the first queue Q21 of the second processing core, and adds task c to the first queue Q11 of the first processing core.

[0140] S206a: The second processing core moves the first task to the end of the second queue Q12 of the first processing core.

[0141] In one possible embodiment, the second processing core moving the first task to the end of the second queue Q12 of the first processing core may include: the second processing core deleting the first task from the first queue Q12 of the first processing core; and the second processing core adding the first task to the end of the second queue Q12 of the first processing core for subsequent scheduling by the first processing core. Optionally, the second processing core deleting the first task from the first queue Q11 of the first processing core may be replaced by the second processing core marking the first task in the first queue Q11 of the first processing core as invalid.

[0142] That is, if the first task has not been completed in the first cycle of the first processing core, the second processing core can delete the first task in the first queue Q11 of the first processing core to avoid repeated scheduling of the first task by the first processing core; in addition, the second processing core adds the first task to the end of the second queue Q12 of the first processing core for scheduling by the first processing core at a subsequent time, so as to reallocate the first task to the second queue Q12 of the first processing core.

[0143] Optionally, if the third queue Q33 of the third processing core also includes the first task, and after S204, the first task has not yet completed execution in the first cycle of the second processing core, the method further includes: the second processing core moving the first task to the end of the third queue Q33 of the third processing core. Furthermore, if the first task has completed execution in the first cycle of the first processing core, the second processing core may delete the first task from the third queue Q33 of the third processing core, so that the third processing core no longer schedules the first task repeatedly.

[0144] It can be understood that the relevant description of the second processing core moving the first task to the end of the third queue Q33 of the third processing core is similar to the description of the second processing core moving the first task to the end of the second queue Q22 of the first processing core in the above S206a. Please refer to the detailed description in the above S206a for details, and the embodiments of the present application will not be repeated here.

[0145] Furthermore, if the third queue Q33 of the third processing core also includes the first task, and after S202-S203, the first processing core has not scheduled the first task, the second processing core has not scheduled the first task, and the third processing core is able to schedule the first task, then, as shown in FIG14 , the method may further include S204b-S206b.

[0146] S204b: When the first processing core and the second processing core have not scheduled the first task, the third processing core schedules the first task in the third queue Q33 of the third processing core in the first cycle of the third processing core.

[0147] The first cycle of the third processing core may refer to a scheduling cycle of the third processing core. The third processing core may schedule tasks in multiple queues of the third processing core in descending order of priority within the first cycle of the third processing core.

[0148] In addition, the first queue Q31 and the second queue Q32 of the third processing core can be empty or include at least one task. When the first queue Q31 and the second queue Q32 of the third processing core include at least one task, the third processing core can schedule execution in sequence according to the order of the at least one task within the first cycle of the third processing core. The third queue Q33 of the third processing core can include one or more tasks, and the first task can be any one of the one or more tasks. If the first queue Q31 and the second queue Q32 of the third processing core are empty, or the third processing core has scheduled the tasks in the first queue Q31 and the second queue Q32 of the third processing core within the first cycle of the third processing core, the third processing core can continue to schedule tasks in the third queue Q33 of the third processing core, for example, scheduling the first task in the third queue Q33 of the third processing core.

[0149] In one possible embodiment, when the first queue Q11 of the first processing core, the second queue Q22 of the second processing core, and the third queue Q33 of the third processing core all include the first task, if neither the first processing core nor the second processing core has scheduled the first task, the third processing core may schedule the first task in the third queue Q33 of the third processing core in the first cycle of the third processing core. Exemplarily, the third processing core may wake up the first task in the third queue Q33 during the first cycle of the third processing core, select the first task from the third queue Q33, and execute it. The specific execution time may be equal to the time slice allocated to the first task.

[0150] After the third processing core schedules the first task in its third queue Q33, if the first task has completed execution in the third processing core's first cycle, the third processing core may delete the first task from the queues of other processing cores, or invalidate the first task in the queues of other processing cores, so that other processing cores no longer schedule the first task. For example, if the first task is included in the first queue Q11 of the first processing core, the third processing core may delete the first task from the first queue Q11 of the first processing core, so that the first processing core no longer schedules the first task. If the second queue Q22 of the second processing core also includes the first task, the third processing core may also delete the first task from the second queue Q22 of the second processing core, so that the second processing core no longer schedules the first task.

[0151] After the third processing core schedules the first task in its third queue Q33, if the first task has not yet completed execution within the first cycle of the third processing core, the third processing core performs the following operations: S205b and S206b. S205b and S206b may be executed in any order; in the figure, S206b is used as an example to illustrate the sequence.

[0152] S205b: The third processing core adds the first task to the end of the first queue Q31 of the third processing core for scheduling in the second cycle of the third processing core. The first cycle of the third processing core is earlier than the second cycle of the third processing core.

[0153] The second cycle of the third processing core may refer to a scheduling cycle after the first cycle of the third processing core. For example, the second cycle of the third processing core may be the first scheduling cycle after the first cycle of the third processing core, or the second or third scheduling cycle after the first cycle of the third processing core. When the number of tasks in the first queue Q31 of the third processing core is small, the third processing core may reschedule the first task added in S205b after the first cycle of the third processing core and in a scheduling cycle that is closer to the first cycle of the third processing core. When the number of tasks in the first queue Q31 of the third processing core is large, the third processing core may reschedule the first task added in S205b after the first cycle of the third processing core and in a scheduling cycle that is farther away from the first cycle of the third processing core.

[0154] S206b: The third processing core moves the first task to the end of the second queue Q12 of the first processing core, and moves the first task to the end of the third queue Q23 of the second processing core.

[0155] In one possible embodiment, the third processing core moving the first task to the end of the second queue Q12 of the first processing core may include: the third processing core deleting the first task from the first queue Q12 of the first processing core; and, the third processing core adding the first task to the end of the second queue Q12 of the first processing core for subsequent scheduling by the first processing core. Optionally, the third processing core deleting the first task from the first queue Q11 of the first processing core may be replaced by the third processing core marking the first task in the first queue Q11 of the first processing core as invalid.

[0156] Similarly, the third processing core moving the first task to the end of the third queue Q23 of the second processing core may include: the third processing core deleting the first task from the second queue Q22 of the second processing core; and, the third processing core adding the first task to the end of the third queue Q23 of the second processing core for subsequent scheduling by the second processing core. Optionally, the third processing core deleting the first task from the second queue Q22 of the second processing core may be replaced by the third processing core marking the first task in the second queue Q22 of the second processing core as invalid.

[0157] It will be appreciated that the above embodiment is described using as an example an example where the multiple processing cores include three processing cores, each processing core is assigned three queues with different priorities, and the same task is deployed in the queues of the three processing cores with different priorities. In actual applications, the multiple processing cores may also include a larger number of processing cores, and each processing core may be assigned a larger number of queues. The above example does not limit the embodiments of the present application.

[0158] Optionally, multiple queues of the same processing core among the multiple processing cores form a logical queue in order of priority. For example, the first queue Q11, the second queue Q12, and the third queue Q13 of the first processing core can form a logical queue in order of priority from high to low; the first queue Q21, the second queue Q22, and the third queue Q23 of the second processing core can also form a logical queue in order of priority from high to low; the first queue Q31, the second queue Q32, and the third queue Q33 of the third processing core can also form a logical queue in order of priority from high to low.

[0159] In particular, multiple queues of the same processing core can constitute a logical queue, and the logical queue can also correspond to at least two indication information, and the at least two indication information can be used to indicate the head of each queue in the multiple queues. For example, the multiple queues include a first queue, a second queue, and a third queue. The logical queue can correspond to first indication information, second indication information, and third indication information. The first indication information can be used to indicate the head of the first queue, the second indication information can be used to indicate the head of the second queue, and the third indication information can be used to indicate the head of the third queue. Optionally, each of the at least two indication information can be a pointer.

[0160] Furthermore, before the multiple processing cores in the task scheduling device schedule tasks in their respective multiple queues, the method further includes: any one of the multiple processing cores initializes the multiple queues of each of the multiple processing cores; the processing core assigns the multiple tasks to be scheduled to the multiple queues of each of the multiple processing cores, wherein the same task can be assigned to queues of different priorities of different processing cores. Exemplarily, the multiple processing cores also include a fourth processing core, which randomly assigns the multiple tasks to be scheduled to the multiple queues of each of the multiple processing cores. For example, the multiple tasks include a first task, and the fourth processing core assigns the first task to the first queue Q11 of the first processing core, the second queue Q22 of the second processing core, and the third queue Q33 of the third processing core.

[0161] For ease of understanding, the task scheduling method provided in the embodiment of the present application is illustrated below with reference to FIG15. As shown in FIG15, the method may include: S1. A certain processing core initializes multiple queues of multiple processing cores; S2. The processing core randomly assigns multiple tasks to different queues of different processing cores, such as the first task is assigned to the first queue Q11 of the first processing core, the second queue Q22 of the second processing core, and the third queue Q33 of the third processing core; S3. Whether a certain task is awakened by the processing core corresponding to the first queue where the task is located, such as whether the first task is awakened by the first processing core, if so, execute S4a, if not, execute S4b; S4a. Whether the time slice allocated to the task is used up, if so, execute S5a, if not, execute S5b; S5a. Insert the task into the first queue where the task is located, such as inserting the first task into the first queue Q11 of the first processing core; S5b. Insert the task into the processing core corresponding to the task ; S4b. Whether the task is awakened by the processing core corresponding to the second queue where the task is located, for example, whether the first task is awakened by the second processing core. If so, execute S6a, if not, execute S6b; S6a. Switch the first queue and the second queue where the task is located, for example, add the first task to the first queue Q21 of the second processing core and the second queue Q12 of the first processing core; S6b. Switch the first queue, the second queue and the third queue where the task is located, for example, add the first task to the first queue Q31 of the third processing core, the second queue Q12 of the first processing core and the third queue Q23 of the second processing core; wherein after steps S5a, S5b, S6a and SS6b, execute S7; S7. Execute the task, for example, execute the first task; S8. Delete the task from the queue where the task is located.

[0162] In summary, the task scheduling method mentioned above may include the following three core processes. 1. Tasks are initially randomly assigned to different queues of different processing cores. For example, the first task can be randomly assigned to the first queue Q11 of the first processing core, the second queue Q22 of the second processing core, and the third queue Q33 of the third processing core during initialization. 2. When a task is scheduled by different processing cores, the queue where the task is located can be updated synchronously. For example, when the first task is scheduled by the first processing core, the queue where the first task is located does not switch; if the first task is scheduled by the second processing core, it indicates that the first processing core is in a busy state, and load balancing is performed by default. At this time, the first task is switched to the first queue Q21 of the second processing core and the second queue Q12 of the first processing core; similarly, if the first task is scheduled by the third processing core, it indicates that the first processing core and the second processing core are in a busy state, and load balancing is performed by default. At this time, the first task also needs to switch to different queues of different cores accordingly. 3. After the task is scheduled, the task is deleted from the corresponding queue to avoid being scheduled multiple times. For example, after the first processing core schedules the first task in the first queue Q11 of the first processing core, the first processing core deletes the first task in the second queue Q22 of the second processing core and the first task in the third queue Q33 of the third processing core.

[0163] The task scheduling method provided by the embodiment of the present application has the characteristic of high affinity on a single processing core. Among them, the high affinity on a single processing core is mainly manifested in the following points. First, the tasks to be scheduled are respectively assigned to different queues of the processing core according to affinity. For example, before starting scheduling, when initializing the three queues of the processing core, the vruntime of the tasks to be scheduled can be calculated separately, and sorted from small to large, and correspondingly assigned to the first queue, second queue and third queue of the processing core. Second, when scheduling the processing core, tasks are selected in the order of the first queue, the second queue and the third queue. For example, the processing core selects tasks from the first queue first. If there are more tasks in the first queue, then within this scheduling cycle, the processing core has not completed the scheduling of all tasks in the first queue. Even if there are tasks with smaller vruntime or higher priority in the second and third queues, they will not be considered. Third, after being scheduled for execution by the processing core corresponding to the first queue where the task is located, the task continues to be added to the first queue of the processing core, specifically to the end of the first queue of the processing core, to facilitate subsequent scheduling of the processing core. In this way, over time, a binding effect between the task and the processing core will gradually be formed, thereby improving the operating performance of a single processing core.

[0164] The task scheduling method provided in the embodiment of the present application can ensure the affinity of tasks while also ensuring the load balancing of multiple processing cores. The main reasons for this are as follows.

[0165] First, affinity is designed for individual tasks rather than processor architectures. In the CFS algorithm, task affinity is divided according to the NUMA architecture (i.e., the physical organizational structure of the processor). This design distinguishes task affinity from the hardware cache sharing architecture, which is a relatively rough division method. However, the embodiment of the present application directly distinguishes affinity based on the distance between the task and the last scheduled processing core. Compared with the above-mentioned physical organizational structure of the processor, the affinity of the task is more accurate and reasonable.

[0166] Secondly, affinity distance is used to directly participate in the design of the queues (or scheduling queues) of the processing cores. Among them, multiple queues with different affinities are set for each processing core. For example, three queues are set for each processing core, named the first queue, the second queue, and the third queue. The tasks to be scheduled are assigned to different queues in the multiple queues according to the distance from the last time they ran on the processing core. For example, if a task was scheduled to run on processing core 0, processing core 1, and processing core 2 respectively in the last three times, then the task will be in the third queue of processing core 0, the second queue of processing core 1, and the first queue of processing core 2 at the same time when it is scheduled next time.

[0167] Third, multiple queues of the same processing core are logically connected in series to form a single queue, i.e., a logical queue. For example, if each processing core has three queues, and each scheduling operation requires traversing these three queues, the scheduling performance will be relatively poor. In the embodiment of the present application, these three queues can actually be connected in series to form a single logical queue. Then, when selecting tasks, the processing core can select tasks in the order of the first queue, the second queue, and the third queue. That is, if the first queue is not empty, tasks in the second and third queues are not considered. If the second queue is not empty, tasks in the third queue are not considered, thereby greatly improving scheduling performance.

[0168] Fourthly, the same task is set in different queues based on the affinity of the tasks. This design naturally satisfies the load balancing of multiple processing cores. Among them, the same task can be assigned to different queues of different processing cores. For example, the first task is assigned to the first queue Q11 of the first processing core, the second queue Q22 of the second processing core, and the third queue Q33 of the third processing core. Then, the three processing cores can all have the opportunity to schedule the first task, so that in this case, the first task has a natural load balancing feature. For example, if the first processing core is very busy and the third processing core is very idle, and the first task is not scheduled on the first processing core for a long time, the third processing core can seamlessly schedule the first task from the third queue Q33 of the third processing core and execute it, thus eliminating the need for other additional load balancing computational overhead (or load balancing cost). Compared with the load balancing in BFS, this design is not a completely random load balancing, but a load balancing that takes affinity into consideration. Therefore, it has a natural performance advantage over BFS.

[0169] In addition, by testing and comparing this method with CFS, the test parameters corresponding to different scheduling methods are shown in Table 1 below. As can be seen from Table 1, the scheduling method of the embodiment of the present application improves the number of instructions per clock (IPC), instruction cache miss rate (iTLB miss), instruction translation look-aside buffer miss rate (iTLB miss), data cache miss rate (dcache miss), retirement rate, front-end blocking rate (fronted bound), bad speculation rate, and back-end blocking rate (back bound) compared to CFS. Among them, the test parameters corresponding to the front-end blocking rate include: instruction fetch latency rate (latency bound), L2 cache translation cache miss rate (L2 TLB-miss), L2 cache instruction miss rate (L2 i-miss), and instruction fetch bandwidth blocking rate (bandwidth bound). Test parameters for the misprediction rate may include: branch mispredicts (BP mispred), machine clears (machine clears), nuke flushes, and other flushes caused by instruction retirement. Test parameters for the backend stall rate may include: resource bound, core bound, divide, fsu_stall, other execution port stalls (execution port util), memory bound, and L1 cache bound.

[0170] Table 1

[0171] In an embodiment of the present application, each of the multiple processing cores is provided with multiple queues of different priorities, and the same task is simultaneously deployed in queues of different priorities of different processing cores. For example, the multiple processing cores include a first processing core and a second processing core, and the multiple queues include a first queue and a second queue. The first queue of the first processing core and the second queue of the second processing core both include a first task. The first processing core schedules the first task in the first queue of the first processing core in the first cycle of the first processing core. If the first task is not completed in the first cycle of the first processing core, the first processing core adds the first task to the end of the first queue of the first processing core and moves the first task to the end of the second queue of the second processing core for scheduling the first processing core and the second processing core at subsequent times, thereby ensuring the affinity of the tasks and the load balancing of the multiple processing cores.

[0172] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the interaction between different processing cores. It can be understood that, in order to realize the above functions, the above-mentioned task scheduling device, etc. includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0173] The embodiment of the present application can divide the task scheduling device into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. In actual implementation, there may be other division methods.

[0174] The present application also provides a task scheduling device, which includes multiple processing cores, each of the multiple processing cores is provided with multiple queues, the multiple processing cores include a first processing core and a second processing core, the multiple queues include a first queue and a second queue, and the priority of the first queue is higher than the priority of the second queue.

[0175] In a possible embodiment, the first processing core is used to schedule the first task in the first queue of the first processing core in the first cycle of the first processing core. In the first cycle of the first processing core, the first queue of the first processing core and the second queue of the second processing core both include the first task. If the first task has not been completed in the first cycle of the first processing core, the first processing core is further used to perform the following operations: add the first task to the end of the first queue of the first processing core for scheduling in the second cycle of the first processing core, the first cycle of the first processing core being earlier than the second cycle of the first processing core; and move the first task to the end of the second queue of the second processing core.

[0176] Specifically, the first processing core is used to move the first task to the end of the second queue of the second processing core, which may include: deleting the first task from the second queue of the second processing core; adding the first task to the end of the second queue of the second processing core for scheduling by the second processing core at a subsequent time.

[0177] Furthermore, in another possible embodiment, the second processing core is used to schedule the first task in the second queue of the second processing core in the first cycle of the second processing core when the first processing core has not scheduled the first task; if the first task has not been completed in the first cycle of the second processing core, the second processing core is further used to perform the following operations: add the first task to the end of the first queue of the second processing core for scheduling in the second cycle of the second processing core, the first cycle of the second processing core being earlier than the second cycle of the second processing core; and move the first task to the end of the second queue of the first processing core.

[0178] Optionally, the multiple processing cores further include a third processing core, the multiple queues further include a third queue, the second queue has a higher priority than the third queue, and the third queue of the third processing core further includes the first task. In one possible embodiment, the third processing core is configured to schedule the first task in the third queue of the third processing core in the first cycle of the third processing core when the first processing core and the second processing core have not scheduled the first task; if the first task has not been completed in the first cycle of the third processing core, the third processing core is further configured to perform the following operations: add the first task to the end of the first queue of the third processing core for scheduling in the second cycle of the third processing core, where the first cycle of the third processing core is earlier than the second cycle of the third processing core; move the first task to the end of the second queue of the first processing core, and move the first task to the end of the third queue of the second processing core.

[0179] Optionally, the multiple queues of the same processing core among the multiple processing cores form a logical queue in order of priority.

[0180] Optionally, each of the multiple processing cores is further configured to execute tasks in the multiple queues in sequence according to the priority order of the multiple queues of the processing core.

[0181] Furthermore, the multiple processing cores also include a fourth processing core; the fourth processing core is used to allocate multiple tasks to be scheduled to the multiple queues of the multiple processing cores; wherein, for any one of the multiple tasks, the task is included in queues of different priorities of different processing cores in the multiple processing cores.

[0182] In another aspect of the present application, a task scheduling device is provided. The task scheduling device includes a multi-core processor and a memory. The memory stores instructions. When the multi-core processor executes the instructions in the processor, the task scheduling device performs the steps of the task scheduling method provided in the above method embodiment. In one example, the task scheduling device can be a terminal device or a chip used in the terminal device.

[0183] In another aspect of the present application, a vehicle is also provided, which includes the task scheduling device provided by the above-mentioned device embodiment, or is used to execute the task scheduling method provided by the above-mentioned method embodiment.

[0184] The present application also provides a readable storage medium having instructions stored therein. When the instructions are executed on a device (e.g., a single-chip microcomputer, a chip, a computer, or a processor), the device executes the steps of the above-described method embodiments. If the components of the task scheduling device are implemented as software functional units and sold or used as independent products, they can be stored in the readable storage medium.

[0185] Based on this understanding, the embodiments of the present application also provide a computer program product containing instructions. The technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or terminal device, etc.) or the processor therein to execute all or part of the steps of the method of each embodiment of the present application.

[0186] In another aspect of the present application, a computer program product is provided, which includes computer instructions. When the computer instructions are run on a device (for example, the device can be a single-chip microcomputer, chip, computer or processor, etc.), the device executes the steps in the above method embodiments.

[0187] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0188] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0189] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0190] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the part of the technical solution of the embodiment of the present application that contributes in essence or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method of each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0191] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A task scheduling method, characterized in that: Applied to a task scheduling device including a plurality of processing cores, each of the plurality of processing cores is provided with a plurality of queues, the plurality of processing cores include a first processing core and a second processing core, the plurality of queues include a first queue and a second queue, and the priority of the first queue is higher than the priority of the second queue; the method includes: The first processing core schedules a first task in a first queue of the first processing core in a first cycle of the first processing core, wherein in the first cycle of the first processing core, the first queue of the first processing core and the second queue of the second processing core both include the first task; If the first task is not completed in the first cycle of the first processing core, the first processing core performs the following operations: adding the first task to the end of the first queue of the first processing core for scheduling the second cycle of the first processing core, wherein the first cycle of the first processing core is earlier than the second cycle of the first processing core; The first task is moved to the end of the second queue of the second processing core.

2. The method according to claim 1, characterized in that The step of moving the first task to the tail of the second queue of the second processing core includes: Deleting the first task from the second queue of the second processing core; The first task is added to the end of the second queue of the second processing core for scheduling the second processing core at a subsequent time.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: When the first processing core does not schedule the first task, the second processing core schedules the first task in the second queue of the second processing core in a first cycle of the second processing core; If the first task is not completed in the first cycle of the second processing core, the second processing core performs the following operations: adding the first task to the end of the first queue of the second processing core for scheduling the second cycle of the second processing core, wherein the first cycle of the second processing core is earlier than the second cycle of the second processing core; The first task is moved to the end of the second queue of the first processing core.

4. The method according to any one of claims 1 to 3, characterized in that: The multiple processing cores further include a third processing core, the multiple queues further include a third queue, the second queue has a higher priority than the third queue, the third queue of the third processing core further includes the first task, and the method further includes: When the first processing core and the second processing core do not schedule the first task, the third processing core schedules the first task in the third queue of the third processing core in the first cycle of the third processing core; If the first task is not completed in the first cycle of the third processing core, the third processing core performs the following operations: Adding the first task to the tail of the first queue of the third processing core for scheduling the second cycle of the third processing core, wherein the first cycle of the third processing core is earlier than the second cycle of the third processing core; The first task is moved to the end of the second queue of the first processing core, and the first task is moved to the end of the third queue of the second processing core.

5. The method according to any one of claims 1 to 4, characterized in that: The multiple queues of the same processing core among the multiple processing cores form a logical queue in order of priority.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: Each of the multiple processing cores executes the tasks in the multiple queues in sequence according to the priority order of the multiple queues of the processing core.

7. The method according to any one of claims 1 to 6, characterized in that: The plurality of processing cores further include a fourth processing core, and the method further includes: The fourth processing core distributes the multiple tasks to be scheduled to the multiple queues of the multiple processing cores; wherein, for any one of the multiple tasks, queues of different priorities of different processing cores in the multiple processing cores include the task.

8. A task scheduling device, characterized in that: comprising a plurality of processing cores, each of the plurality of processing cores being provided with a plurality of queues, the plurality of processing cores comprising a first processing core and a second processing core, the plurality of queues comprising a first queue and a second queue, the priority of the first queue being higher than the priority of the second queue; The first processing core is configured to schedule a first task in a first queue of the first processing core in a first cycle of the first processing core, wherein in the first cycle of the first processing core, the first queue of the first processing core and the second queue of the second processing core both include the first task; If the first task is not completed in the first cycle of the first processing core, the first processing core is further configured to perform the following operations: adding the first task to the end of the first queue of the first processing core for scheduling the second cycle of the first processing core, wherein the first cycle of the first processing core is earlier than the second cycle of the first processing core; The first task is moved to the end of the second queue of the second processing core.

9. The device according to claim 8, characterized in that The first processing core is further configured to: Deleting the first task from the second queue of the second processing core; The first task is added to the end of the second queue of the second processing core for scheduling the second processing core at a subsequent time.

10. The device according to claim 8 or 9, characterized in that the second processing core is configured to schedule the first task in a second queue of the second processing core in a first cycle of the second processing core when the first processing core has not scheduled the first task; If the first task is not completed in the first cycle of the second processing core, the second processing core is further configured to perform the following operations: adding the first task to the end of the first queue of the second processing core for scheduling the second cycle of the second processing core, wherein the first cycle of the second processing core is earlier than the second cycle of the second processing core; The first task is moved to the end of the second queue of the first processing core.

11. The device according to any one of claims 8 to 10, characterized in that: The multiple processing cores further include a third processing core, the multiple queues further include a third queue, the second queue has a higher priority than the third queue, and the third queue of the third processing core further includes the first task; The third processing core is configured to schedule the first task in the third queue of the third processing core in the first cycle of the third processing core when the first processing core and the second processing core have not scheduled the first task; If the first task is not completed in the first cycle of the third processing core, the third processing core is further configured to perform the following operations: Adding the first task to the tail of the first queue of the third processing core for scheduling the second cycle of the third processing core, wherein the first cycle of the third processing core is earlier than the second cycle of the third processing core; The first task is moved to the end of the second queue of the first processing core, and the first task is moved to the end of the third queue of the second processing core.

12. The device according to any one of claims 8 to 11, characterized in that: The multiple queues of the same processing core among the multiple processing cores form a logical queue in order of priority.

13. The device according to any one of claims 8 to 12, characterized in that: Each of the multiple processing cores is further configured to sequentially execute tasks in the multiple queues according to the priority order of the multiple queues of the processing core.

14. The device according to any one of claims 8 to 13, characterized in that: The plurality of processing cores further includes a fourth processing core; The fourth processing core is used to allocate multiple tasks to be scheduled to the multiple queues of the multiple processing cores; wherein, for any one of the multiple tasks, queues of different priorities of different processing cores in the multiple processing cores include the task.

15. A task scheduling device, characterized in that: The task scheduling device includes a multi-core processor and a memory, wherein instructions are stored in the memory. When the multi-core processor executes the instructions, the task processing device executes the task scheduling method according to any one of claims 1 to 7.

16. A readable storage medium, characterized in that: The readable storage medium stores instructions, and when the instructions are executed by a device, the device executes the task scheduling method according to any one of claims 1 to 7.

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