Semiconductor memory device

Abstract

A semiconductor memory device (MD) includes a memory cell (11) and a sense amplifier circuit (32). The memory cell includes P-type driving transistors (TPM0, TPM1), N-type load transistors (TNM0, TNM1), and P-type access transistors (TPM2, TPM3) connected to a bit line pair (BL, BLB). The sense amplifier circuit (32) includes P-type transistors (TP0, TP1, TP2) and N-type transistors (TN4, TN5).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and in particular to an SRAM (Static Random Access Memory). Background Art

[0002] SRAM is widely used as a type of main memory mounted in semiconductor integrated circuit devices.

[0003] As a conventional technique, for example, as shown in Patent Document 1, there is disclosed a semiconductor memory device in which a transfer gate (access transistor) among transistors constituting an SRAM memory cell is constituted by a P-type transistor.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2009-176407 Summary of the Invention

[0007] -Technical problem to be solved by the invention-

[0008] However, prior art documents including Patent Document 1 show circuit diagrams of memory cells whose transfer gates are formed of P-type transistors, but do not disclose peripheral circuits of an SRAM using the memory cells.

[0009] The present disclosure discloses a peripheral circuit of an SRAM using an SRAM memory cell, particularly a circuit related to SRAM readout, wherein the SRAM memory cell uses a P-type transistor as an access transistor.

[0010] -Technical solutions for solving technical problems-

[0011] In a first aspect of the present disclosure, a semiconductor memory device includes a memory cell and a sense amplifier circuit. The memory cell includes a first P-type transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, a third P-type transistor, and a fourth P-type transistor, wherein the gate of the first P-type transistor is connected to a first node, the source of the first P-type transistor is connected to a first power supply, and the drain of the first P-type transistor is connected to a second node. The gate of the first N-type transistor is connected to the first node, the source of the first N-type transistor is connected to a second power supply, and the drain of the first N-type transistor is connected to the second node. The gate of the second P-type transistor is connected to the second node, the source of the second P-type transistor is connected to the first power supply, and the drain of the second P-type transistor is connected to the first node. The gate of the second N-type transistor is connected to the second node, the source of the second N-type transistor is connected to the second power supply, and the drain of the second N-type transistor is connected to the first node. The third P-type transistor is arranged between the second node and a first bit line, and the gate of the third P-type transistor is connected to a word line. The fourth P-type transistor is arranged between the first node and a second bit line, and the gate of the fourth P-type transistor is connected to the word line. The sense amplifier circuit includes a fifth P-type transistor, a sixth P-type transistor, a third N-type transistor, a seventh P-type transistor, and a fourth N-type transistor. The source of the fifth P-type transistor is connected to the first power supply. The fifth P-type transistor is turned on or off based on a sense amplifier enable signal. The gate of the sixth P-type transistor is connected to the second bit line via a third node. The source of the sixth P-type transistor is connected to the drain of the fifth P-type transistor. The drain of the sixth P-type transistor is connected to a fourth node. The fourth node is connected to the first bit line. The gate of the third N-type transistor is connected to the third node. The source of the third N-type transistor is connected to the second power supply. The drain of the third N-type transistor is connected to the fourth node. The gate of the seventh P-type transistor is connected to the fourth node. The source of the seventh P-type transistor is connected to the drain of the fifth P-type transistor. The drain of the seventh P-type transistor is connected to the third node. The gate of the fourth N-type transistor is connected to the fourth node. The source of the fourth N-type transistor is connected to the second power supply. The drain of the fourth N-type transistor is connected to the third node.

[0012] In a second aspect of the present disclosure, a semiconductor memory device includes a memory cell and a word line driver, wherein the memory cell is connected to a word line, the word line driver receives a clock signal and an address signal as input, and sets the word line to a low level according to the clock signal and the address signal, the memory cell includes a first P-type transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, a third P-type transistor, and a fourth P-type transistor, wherein the gate of the first P-type transistor is connected to a first node, the source of the first P-type transistor is connected to a first power supply, the drain of the first P-type transistor is connected to a second node, the gate of the first N-type transistor is connected to the first node, the source of the first N-type transistor is connected to the second power supply, and the drain of the first P-type transistor is connected to a second node. The first bit line driver includes a first N-type transistor and a second P-type transistor. The first N-type transistor has a drain connected to the second node, the second P-type transistor has a gate connected to the second node, the second P-type transistor has a source connected to the first power supply, the drain of the second P-type transistor is connected to the first node, the gate of the second N-type transistor is connected to the second node, the source of the second N-type transistor is connected to the second power supply, and the drain of the second N-type transistor is connected to the first node. The third P-type transistor is arranged between the second node and the first bit line, and the gate of the third P-type transistor is connected to a word line. The fourth P-type transistor is arranged between the first node and the second bit line, and the gate of the fourth P-type transistor is connected to the word line. The word line driver includes a fifth P-type transistor, the source of the fifth P-type transistor is connected to the first power supply, and the gate and drain of the fifth P-type transistor are connected to the word line.

[0013] -Effects of the Invention-

[0014] According to the present disclosure, a peripheral circuit of an SRAM using an SRAM memory cell is provided, wherein the SRAM memory cell adopts a P-type transistor as an access transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a diagram showing a configuration example of a memory cell array and a driver circuit constituting the semiconductor memory device according to the first embodiment;

[0016] Figure 2 FIG. 1 is a diagram showing a configuration example of a readout circuit constituting the semiconductor memory device according to the first embodiment;

[0017] Figure 3 is a timing chart showing an example of the operation of the semiconductor memory device according to the first embodiment;

[0018] Figure 4 is a diagram showing a modified example of the driver circuit according to the first embodiment;

[0019] Figure 5 is a diagram for explaining the operation of a driver circuit according to a modification of the first embodiment;

[0020] Figure 6 FIG. 1 is a diagram showing a configuration example of a memory cell array and a driver circuit constituting a semiconductor memory device according to a second embodiment;

[0021] Figure 7 FIG. 1 is a diagram showing a configuration example of a readout circuit constituting a semiconductor memory device according to a second embodiment;

[0022] Figure 8 This is a timing chart showing an operation example of the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0023] Below, the embodiments are described with reference to the accompanying drawings. It should be noted that in the following description, the same symbols are sometimes used to describe the signal line (node) and the signal passing through the signal line (node). Similarly, the same symbols are sometimes used to describe the power supply node and the voltage supplied to the power supply node. In addition, in this disclosure, the term "connection" is used as the following concept: this concept includes not only the case where there is a direct connection between each other, but also the case where there is an indirect connection between each other via elements such as transistors.

[0024] <First embodiment>

[0025] Figure 1 and Figure 2 The following is a structural example of the semiconductor memory device MD according to this embodiment. The semiconductor memory device MD includes Figure 1 The memory cell array 1 and word line driver 2 shown, and Figure 2 The readout circuit 3 is shown.

[0026] [Memory Cell Array]

[0027] In this embodiment, the memory cell array 1 includes a plurality of memory cells 11 arranged in an array of n rows (n is a natural number) × m groups (m is a natural number). In addition, each row of memory cells 11 is connected to a different word line WLB[0] to WLB[n-1]. In other words, in this example, the memory cell array 1 is composed of n word lines WLB[0] to WLB[n-1] and n×m memory cells 11. It should be noted that in Figure 1 The middle figure shows one set of memory cells 11 among the m sets of memory cells 11. In the following description, when word lines WLB[0] to WLB[n-1] are not distinguished from each other, they may be simply referred to as "word lines WLB".

[0028] [Storage Unit]

[0029] The memory cell 11 includes P-type drive transistors TPM0 and TPM1 , N-type load transistors TNM0 and TNM1 , and P-type access transistors TPM2 and TPM3 .

[0030] The gate of the driver transistor TPM0 (equivalent to the first P-type transistor) is connected to the node DB (equivalent to the first node), the drain of the driver transistor TPM0 is connected to the node D (equivalent to the second node), and the source of the driver transistor TPM0 is connected to the power supply VDD (equivalent to the first power supply node). The gate of the load transistor TNM0 (equivalent to the first N-type transistor) is connected to the node DB, the drain of the load transistor TNM0 is connected to the node D, and the source of the load transistor TNM0 is connected to the ground VSS (equivalent to the second power supply node). In other words, the driver transistor TPM0 and the load transistor TNM0 are connected in series between the power supply VDD and the ground VSS.

[0031] The gate of the driver transistor TPM1 (equivalent to the second P-type transistor) is connected to node D, the drain of the driver transistor TPM1 is connected to node DB, and the source of the driver transistor TPM1 is connected to power supply VDD. The gate of the load transistor TNM1 (equivalent to the second N-type transistor) is connected to node D, the drain of the load transistor TNM1 is connected to node DB, and the source of the load transistor TNM1 is connected to ground VSS. In other words, the driver transistor TPM1 and the load transistor TNM1 are connected in series between power supply VDD and ground VSS. Furthermore, the driver transistors TPM0 and TPM1 and the load transistors TNM0 and TNM1 form a latch.

[0032] Access transistor TPM2 (equivalent to the third P-type transistor) is provided between node D and bit line BL (equivalent to the first bit line), with its gate connected to word line WLB. Access transistor TPM3 (equivalent to the fourth P-type transistor) is provided between node DB and bit line BLB (equivalent to the second bit line), with its gate connected to word line WLB. It should be noted that in the following description, the pair consisting of bit line BL and bit line BLB is sometimes referred to as "bit line pair BL, BLB."

[0033] In memory cell 11, data is stored at nodes D and DB via a latch structure consisting of driver transistors TPM0 and TPM1 and load transistors TNM0 and TNM1. Furthermore, when word line WLB is 'L' (low level), the data stored at nodes D and DB is read out to bit line pair BL and BLB via access transistors TPM2 and TPM3. Hereinafter, low-level signals are sometimes abbreviated as 'L', and high-level signals are sometimes abbreviated as 'H'.

[0034] [Word line driver]

[0035] The word line driver 2 receives the clock signal RDCLK and the address signal AD as input, and sets the target word line WLB to 'L' according to the clock signal RDCLK and the address signal AD.

[0036] exist Figure 1 FIG2 shows an example in which the word line driver 2 is composed of a NAND circuit 21 and two-stage inverters 22 and 23. The NAND circuit 21 receives the clock signal RDCLK and the address signal AD as inputs, and the two-stage inverters 22 and 23 are connected in series between the output of the NAND circuit 21 and the word line WLB. Figure 1 In addition to the structure in FIG. 1 , other circuit structures may be used to realize the function of “setting the target word line WLB to 'L' according to the clock signal RDCLK and the address signal AD”.

[0037] [Readout circuit]

[0038] The bit line pair BL, BLB of the memory cell array 1 and Figure 2 The readout circuit 3 shown is connected. The readout circuit 3 is provided for each group of memory cells constituting the memory cell array 1. That is, in this example, m readout circuits 3 are provided for m groups of memory cells 11. It should be noted that Figure 2 In FIG, a readout circuit 3 is shown as an example.

[0039] The readout circuit 3 includes a discharge circuit 31 , a sense amplifier circuit 32 , a data line discharge circuit 33 , and an output circuit 34 .

[0040] [Discharge circuit]

[0041] When the discharge signal NPCG is 'H', the discharge circuit 31 discharges the bit line pair BL, BLB.

[0042] Discharge circuit 31 includes N-type transistors TNEQ1, TN0, and TN1 (equivalent to a fifth N-type transistor). Transistor TNEQ1 is provided between bit line BL and bit line BLB. Transistor TN0 is provided between the node connecting bit line BL and transistor TNEQ1 and ground VSS. Transistor TN1 is provided between the node connecting bit line BLB and transistor TNEQ1 and ground VSS. A discharge signal NPCG is applied to the gates of transistors TNEQ1, TN0, and TN1.

[0043] [Sense amplifier circuit]

[0044] The sense amplifier circuit 32 amplifies data read out to the data line pair RDL, RDLB connected to the bit line pair BL, BLB according to the sense amplifier enable signal SAE. When the sense amplifier enable signal SAE is 'H', the sense amplifier circuit 32 is enabled.

[0045] Sense amplifier circuit 32 includes P-type transistors TP0, TP1, and TP2, and N-type transistors TN4 and TN5. The source of transistor TP0 (equivalent to the fifth P-type transistor) is connected to power supply VDD, and the inverted signal of sense amplifier enable signal SAE is applied to the gate of transistor TP0. The gate of transistor TP1 (equivalent to the sixth P-type transistor) is connected to data line RDLB (equivalent to the second data line) via node NB (equivalent to the third node), the source of transistor TP1 is connected to the drain of transistor TP0, and the drain of transistor TP1 is connected to data line RDL (equivalent to the first data line) via node N (equivalent to the fourth node). Transistor TN4 (equivalent to the third N-type transistor) has a gate connected to node NB, a source connected to ground VSS, and a drain connected to node N. Transistor TP2 (equivalent to the seventh P-type transistor) has a gate connected to node N, a source connected to the drain of transistor TP0, and a drain connected to node NB. The gate of the transistor TN5 (corresponding to a fourth N-type transistor) is connected to the node N, the source of the transistor TN5 is connected to the ground VSS, and the drain of the transistor TN5 is connected to the node NB.

[0046] The signal amplified by sense amplifier circuit 32 is read from output terminal RD by output circuit 34. Specifically, when D = 'H' and DB = 'L', a 'L' signal is read from output terminal RD; when D = 'L' and DB = 'H', a 'H' signal is read from output terminal RD. Here, D represents the signal at node D, and DB represents the signal at node DB. These terms will sometimes be used interchangeably in the following descriptions.

[0047] [Data line discharge circuit]

[0048] When the data line discharge signal NPCGSA is 'H', the data line discharge circuit 33 discharges the data line pair RDL, RDLB to 'L'.

[0049] Data line discharge circuit 33 includes N-type transistors TNEQ2, TN6, and TN7. Transistor TNEQ2 is disposed between data line RDL and data line RDLB. Transistor TN6 is disposed between the node connecting data line RDL and transistor TNEQ2 and ground VSS. Transistor TN7 is disposed between the node connecting data line RDLB and transistor TNEQ2 and ground VSS. A discharge signal NPCGSA is applied to the gates of transistors TNEQ2, TN6, and TN7.

[0050] [Output circuit]

[0051] Output circuit 34 includes inverters INV1 and INV2, a P-type transistor TP3, and an N-type transistor TN8. Transistors TP3 and TN8 are connected in series between a power supply VDD and a ground VSS. Data line RDL is connected to the gate of transistor TP3 via inverter INV1. Data line RDLB is connected to the gate of transistor TN8. Furthermore, the node connecting transistors TP3 and TN8 is connected to output terminal RD via inverter INV2.

[0052] The bit line BL is connected to the node N via the N-type transistor TN2 (equivalent to the fifth N-type transistor) and the data line RDL. The transistor TN2 switches between the bit line BL and the data line RDL based on the sense amplifier enable signal SAE and the NREAD signal (equivalent to the read signal).

[0053] Bit line BLB is connected to node NB via N-type transistor TN3 (equivalent to the sixth N-type transistor) and data line RDLB. Transistor TN3 switches between bit line BLB and data line RDLB based on sense amplifier enable signal SAE and NREAD signal.

[0054] Furthermore, the gates of the transistor TN2 and the transistor TN3 are connected to the output terminals of a two-input NOR circuit NOR0 , which receives the sense amplifier enable signal SAE and the NREAD signal as inputs.

[0055] (Data reading operation)

[0056] Next, refer to Figure 3 , the data reading operation of the memory cell 11 is described. Below, for convenience, signals are sometimes described using only symbols. For example, the signal of the bit line BL is sometimes described using only the symbol "BL." The same applies to other signals.

[0057] First, from Figure 1 The operation of reading "0" from the memory cell 11 in the upper section will be described (refer to Figure 3left).

[0058] In the state before reading, D='H' and DB='L' in the memory cell 11. In addition, NPCG=NPCGSA=H, and under the action of the discharge circuit 31 and the data line discharge circuit 33, BL=BLB=RDL=RDLB=L.

[0059] At the start of a read operation, NPCG = NPCGSA = L, releasing the discharge state of discharge circuit 31 and data line discharge circuit 33. Furthermore, WLB[n-1] = 'L' and NREAD = 'L'. Consequently, the output signal of NOR circuit NORO becomes 'H', connecting bit line BL to data line RDL, and bit line BLB to data line RDLB. Consequently, the potentials of bit line BL and data line RDL begin to rise due to the 'H' signal previously stored at node D.

[0060] Next, SAE is set to 'H', and the output of NOR circuit NORO goes 'L'. This disconnects bit line BL from data line RDL, and bit line BLB from data line RDLB. Furthermore, transistor TPO of sense amplifier circuit 32 turns on, amplifying the RDL and RDLB signals. Consequently, the RDL signal rises to power supply voltage VDD, causing the output of output terminal RD to go 'L', and a "0" is read from memory cell 11, the target memory cell.

[0061] Furthermore, as SAE is set to 'H', WLB[n-1]=NPCG=H. Then, the discharge circuit 31 returns to the state of BL=BLB=L.

[0062] After data is read from the output terminal RD, SAE is set to L, and the sense amplifier circuit 32 is in a non-operating state. NPCGSA is set to H, and the data line discharge circuit 33 returns to the state of RDL=RDLB=L.

[0063] Next, the operation of reading "1" from the memory cell 11 in the upper row will be described (see FIG. Figure 3 Here, the explanation focuses on the differences from the operation of reading "0".

[0064] First, in the state before reading, D='L' and DB='H' in the memory cell 11. The settings of other signals are the same as the operation of reading "0".

[0065] Next, when the discharge states of the discharge circuit 31 and the data line discharge circuit 33 are released and WLB[n-1]='L' and NREAD='L', the potentials of the bit line BLB and the data line RDLB start to rise due to the 'H' signal originally stored in the node DB.

[0066] Then, when SAE='H' is set, the RDL and RDLB signals are amplified, whereby the RDLB signal rises to the power supply voltage VDD, and the output of the output terminal RD becomes 'H', and "1" is read from the memory cell 11 to be read.

[0067] The operation after this is the same as the operation of reading "0".

[0068] -Modifications-

[0069] Here, Modification 1 of the semiconductor memory device MD according to the first embodiment will be described.

[0070] Figure 4 This modification is equivalent to Figure 1 Here, with Figure 1 The following description focuses on the differences.

[0071] exist Figure 4 In the word line driver 2, a P-type transistor 24 (equivalent to a fifth P-type transistor) is included. The source of the transistor 24 is connected to the power supply VDD, and the gate and drain of the transistor 24 are connected to the word line WLB. Figure 1 More specifically, each of the word lines WLB[0] to [n-1] is connected to the transistor 24. In other words, the word line driver 2 includes n transistors 24.

[0072] Reference Figure 5 , the function and effect of this modification are explained. Figure 5 , an example in which D=H and DB=L are stored is shown.

[0073] Here, in semiconductor memory device MD, as clock signal RDCLK changes from 'L' to 'H', the signal of word line WLB corresponding to address signal AD changes from 'H' to 'L', thereby performing a read operation.

[0074] During this read operation, when word line WLB goes 'L', charge is supplied from power supply VDD to the pre-discharged bit line BL along a path (hereinafter referred to as the "charge supply path") consisting of the driver transistor TPM0, access transistor TPM2, bit line BL, and data line RDL. Consequently, a voltage drop occurs at node D due to resistor voltage division in the path from driver transistor TPM0 to bit line BL, or due to resistor voltage division in the path from driver transistor TPM0 to data line RDL. This voltage drop at node D is eliminated when the signal on word line WLB returns to 'H'.

[0075] Here, when the ratio of the resistance of the driving transistor TPM0 to the resistance of the entire charge supply path is relatively small, Figure 1 It can also work without any problems under the structure (see Figure 5 "Normal operation").

[0076] On the other hand, if the resistance of the drive transistor TPMO is relatively large relative to the resistance of the entire charge supply path, the voltage drop at the node D becomes larger when the word line WLB goes 'L'. As a result, in the latch structure of the memory cell 11, the signal at the node D may invert from 'H' to 'L', and the signal at the node DB may invert from 'L' to 'H', causing malfunction (see Figure 5 "When the wrong action is taken").

[0077] Therefore, by adopting the structure of this modification, when the word line WLB is at 'L', the potential of the word line WLB can be made higher than the ground potential VSS (see Figure 5 Thus, the resistance value of the access transistor TPM2 can be made smaller than Figure 1 As a result, the ratio of the resistance of the driving transistor TPMO to the resistance of the entire charge supply path can be reduced to Figure 1 Therefore, the voltage drop at the node D is reduced, and thus normal operation can be achieved even when the resistance of the driving transistor TPMO accounts for a relatively large proportion of the resistance of the entire charge supply path.

[0078] <Second embodiment>

[0079] Figure 6 and Figure 7 The following is a structural example of the semiconductor memory device MD according to this embodiment. The semiconductor memory device MD includes Figure 6 The memory cell array 1 and word line driver 2 shown, and Figure 7 The readout circuit 3 shown in FIG. Figure 6In the Figure 1 The corresponding structure, annotation and Figure 1 The same symbol. Similarly, Figure 7 In the Figure 2 The corresponding structure, annotation and Figure 2 The same reference numerals are used. In addition, the following description will focus on the differences from the first embodiment.

[0080] In this embodiment, the memory cell array 1 includes a plurality of memory cells 11 arranged in an array of n rows (n is a natural number)×c columns (c is a natural number)×m groups (m is a natural number). Figure 6 The middle diagram shows one group of memory cells 11 among the m groups of memory cells 11 .

[0081] like Figure 6 As shown, each row of memory cells 11 is connected to a different word line WLB[0] to WLB[n-1]. Furthermore, each column of memory cells 11 is connected to a different bit line pair BL[0] to BL[c-1], BLB[0] to BLB[c-1]. In other words, the memory cell array 1 is composed of n word lines WLB[0] to WLB[n-1], c pairs of bit line pairs BL[0] to BL[c-1], BLB[0] to BLB[c-1], and n×c×m memory cells 11.

[0082] In the following description, when word lines WLB[0] to WLB[n-1] are not distinguished from each other, they may be simply referred to as “word lines WLB.” The same applies to bit lines BL, bit lines BLB, and bit line pairs BL and BLB.

[0083] like Figure 7 As shown in FIG. 1 , in the readout circuit 3 of this embodiment, a discharge circuit 31 is provided for each column. That is, the readout circuit 3 includes c discharge circuits 31. For each c column, a sense amplifier circuit 32, a data line discharge circuit 33, and an output circuit 34 are provided. Figure 2 In addition to the structure of , it also includes a column selector circuit 35 set for each column.

[0084] [Column selector circuit]

[0085] The column selector circuit 35 selects a column from which data is to be read from a plurality of columns, and data from the bit line pair BL, BLB of the column (0 to c-1) selected by the column select signal NCAD[0:c-1] is read from the output terminal RD.

[0086] Specifically, the column selector circuit 35 includes N-type transistors TN2 , TN3 , and TN9 , a P-type transistor TP4 , and a NOR circuit NORO.

[0087] Transistor TN2 (equivalent to the fifth N-type transistor) is provided between bit line BL[x] (0 ≤ x ≤ c-1) and data line RDL. Transistor TN3 (equivalent to the fifth N-type transistor) is provided between bit line BLB[x] and data line RDLB. The source of transistor TP4 is connected to power supply VDD, and the drain of transistor TP4 is connected to the drain of transistor TN9 and one input terminal of NOR circuit NORO. The source of transistor TN9 is connected to column select signal NCAD[x]. Furthermore, the gates of transistor TP4 and transistor TN9 are connected to the READ signal. The other input terminal of NOR circuit NORO is connected to sense amplifier enable signal SAE. The output of NOR circuit NORO is connected to the gates of transistor TN2 and transistor TN3.

[0088] (Data reading operation)

[0089] Next, refer to Figure 8 , the data reading operation of the memory cell 11 is described. In this example, the memory cell 11 ( Figure 6 The data reading example of the storage unit 11 shown in the upper left corner is described. Figure 3 ) is explained with the focus on the differences. Figure 3 In FIG, the inverted NREAD signal is shown as the read signal, while in Figure 8 , the READ signal is shown as it is as the read signal, which is different from the first embodiment.

[0090] First, the operation of reading "0" from the memory cell 11 as the read target will be described (see Figure 8 left).

[0091] In the state before reading, Figure 3 Based on the status, NCAD[0:c-1]='H'.

[0092] To start a read operation, WLB[n-1] = 'L', READ = 'H', and NCAD[0] = 'L'. This causes the output signal of the NOR circuit NORO in column [0] to become 'H', connecting bit line BL[0] to data line RDL, and bit line BLB[0] to data line RDLB. Consequently, the potentials of bit line BL[0] and data line RDL begin to rise due to the 'H' signal previously stored at node D.

[0093] At this time, for the other columns [1:c-1], NCAD[1:c-1]='H' is maintained, and the bit lines BL[1:c-1] and data lines RDL, and the bit lines BLB[1:c-1] and data lines RDLB are disconnected.

[0094] Next, SAE is set to 'H', and the output of NOR circuit NORO goes 'L'. This disconnects bit line BL[0] from data line RDL, and bit line BLB[0] from data line RDLB. Furthermore, transistor TPO of sense amplifier circuit 32 turns on, amplifying the RDL and RDLB signals. Consequently, the RDL signal rises to power supply voltage VDD, causing the output of output terminal RD to go 'L', and a "0" is read from memory cell 11, the target memory cell.

[0095] The subsequent operation is the same as that of the first embodiment, and the discharge circuit 31 returns to the state of BL[0]=BLB[0]=L. The data line discharge circuit 33 also returns to the state of RDL=RDLB=L.

[0096] Next, the operation of reading "1" from the memory cell 11 as the read target will be described (see FIG. Figure 8 right).

[0097] First, in the state before reading, D='L' and DB='H' in the memory cell 11. The settings of other signals are the same as the operation of reading "0".

[0098] Next, when the discharge states of the discharge circuit 31 and the data line discharge circuit 33 are released and WLB[n-1] = 'L', READ = 'H', and NCAD[0] = 'L', the potentials of the bit line BLB[0] and the data line RDLB begin to rise due to the 'H' signal originally stored in the node DB.

[0099] Then, when SAE='H' is set, the RDL and RDLB signals are amplified, whereby the RDLB signal rises to the power supply voltage VDD, and the output of the output terminal RD becomes 'H', and "1" is read from the memory cell 11 to be read.

[0100] The operation after this is the same as the operation of reading "0".

[0101] It should be noted that the technology disclosed herein is not limited to the configurations described in the above embodiments, but can be applied to embodiments in which appropriate changes, substitutions, additions, omissions, etc. are made. In addition, the components described in the above embodiments can be combined to form new embodiments.

[0102] For example, the word line driver 2 of the second embodiment may be replaced with the word line driver 2 shown in the first modification of the first embodiment, thereby achieving the same effects as those of the first embodiment.

[0103] -Industrial Applicability-

[0104] According to the present disclosure, it is possible to provide a peripheral circuit of an SRAM using an SRAM memory cell which uses a P-type transistor as an access transistor and is therefore very useful.

[0105] -Explanation of symbols-

[0106] MD semiconductor memory device

[0107] 1 Memory cell array

[0108] 2 word line drivers

[0109] 11 Storage Unit

[0110] 24 transistors (fifth P-type transistors)

[0111] 31 Discharge circuit

[0112] 32 Sense Amplifier Circuit

[0113] 35 Column Selector Circuit

[0114] AD address signal

[0115] BL bit line (first bit line)

[0116] BLB bit line (second bit line)

[0117] D node (second node)

[0118] DB node (first node)

[0119] N node (fourth node)

[0120] NB node (third node)

[0121] RDL data line (first data line)

[0122] RDLB data line (second data line)

[0123] SAE sense amplifier enable signal

[0124] TN0 transistor (fifth N-type transistor)

[0125] TN1 transistor (fifth N-type transistor)

[0126] TN2 transistor (fifth N-type transistor)

[0127] TN3 transistor (fifth N-type transistor, sixth N-type transistor)

[0128] TN4 transistor (third N-type transistor)

[0129] TN5 transistor (fourth N-type transistor)

[0130] TNEQ1 transistor (fifth N-type transistor)

[0131] TNM0 load transistor (first N-type transistor)

[0132] TNM1 load transistor (second N-type transistor)

[0133] TP0 transistor (fifth P-type transistor)

[0134] TP1 transistor (sixth P-type transistor)

[0135] TP2 transistor (the seventh P-type transistor)

[0136] TPM0 driver transistor (first P-type transistor)

[0137] TPM1 driver transistor (second P-type transistor)

[0138] TPM2 access transistor (third P-type transistor)

[0139] TPM3 access transistor (fourth P-type transistor)

[0140] RDCLK clock signal

[0141] VDD power supply (first power supply)

[0142] VSS ground (second power supply)

[0143] WLB word line.

Claims

1. A semiconductor memory device, characterized in that: The semiconductor memory device includes a memory cell and a sense amplifier circuit. The memory cell includes a first P-type transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, a third P-type transistor, and a fourth P-type transistor. The gate of the first P-type transistor is connected to the first node, the source of the first P-type transistor is connected to the first power supply, and the drain of the first P-type transistor is connected to the second node. The gate of the first N-type transistor is connected to the first node, the source of the first N-type transistor is connected to the second power supply, and the drain of the first N-type transistor is connected to the second node. The gate of the second P-type transistor is connected to the second node, the source of the second P-type transistor is connected to the first power supply, and the drain of the second P-type transistor is connected to the first node. The gate of the second N-type transistor is connected to the second node, the source of the second N-type transistor is connected to the second power supply, and the drain of the second N-type transistor is connected to the first node. The third P-type transistor is arranged between the second node and the first bit line, and the gate of the third P-type transistor is connected to the word line. The fourth P-type transistor is provided between the first node and the second bit line, and the gate of the fourth P-type transistor is connected to the word line. The sense amplifier circuit includes a fifth P-type transistor, a sixth P-type transistor, a third N-type transistor, a seventh P-type transistor, and a fourth N-type transistor. The source of the fifth P-type transistor is connected to the first power supply, and the fifth P-type transistor is turned on or off based on a sense amplifier enable signal. The gate of the sixth P-type transistor is connected to the second bit line via the third node, the source of the sixth P-type transistor is connected to the drain of the fifth P-type transistor, the drain of the sixth P-type transistor is connected to the fourth node, and the fourth node is connected to the first bit line. The gate of the third N-type transistor is connected to the third node, the source of the third N-type transistor is connected to the second power supply, and the drain of the third N-type transistor is connected to the fourth node. The gate of the seventh P-type transistor is connected to the fourth node, the source of the seventh P-type transistor is connected to the drain of the fifth P-type transistor, and the drain of the seventh P-type transistor is connected to the third node. A gate of the fourth N-type transistor is connected to the fourth node, a source of the fourth N-type transistor is connected to the second power supply, and a drain of the fourth N-type transistor is connected to the third node.

2. The semiconductor memory device according to claim 1, wherein: The semiconductor memory device includes a memory cell array, the memory cell array being composed of a plurality of columns, each of the plurality of columns being composed of a plurality of memory cells connected to a common first bit line and a common second bit line as a group. The semiconductor memory device includes a column selector circuit configured to select a column from which data is to be read out from among the plurality of columns.

3. The semiconductor memory device according to claim 2, wherein: The column selector circuit includes a fifth N-type transistor that connects a column selected from the plurality of columns to the sense amplifier circuit and disconnects unselected columns from the sense amplifier circuit.

4. The semiconductor memory device according to claim 1, wherein: The first bit line is connected to the fourth node via a fifth N-type transistor and a first data line, and the fifth N-type transistor is switched to be conductive or non-conductive based on the sense amplifier enable signal and the read signal. The second bit line is connected to the third node via a sixth N-type transistor and a second data line. The sixth N-type transistor is switched to be conductive or non-conductive based on the sense amplifier enable signal and the read signal.

5. The semiconductor memory device according to claim 1, wherein: A discharge circuit composed of a fifth N-type transistor is provided between the first bit line and the second bit line.

6. A semiconductor memory device, characterized in that: The semiconductor memory device includes a memory cell and a word line driver. The memory cell is connected to a word line, The word line driver receives a clock signal and an address signal as input, and sets the word line to a low level according to the clock signal and the address signal. The memory cell includes a first P-type transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, a third P-type transistor, and a fourth P-type transistor. The gate of the first P-type transistor is connected to the first node, the source of the first P-type transistor is connected to the first power supply, and the drain of the first P-type transistor is connected to the second node. The gate of the first N-type transistor is connected to the first node, the source of the first N-type transistor is connected to the second power supply, and the drain of the first N-type transistor is connected to the second node. The gate of the second P-type transistor is connected to the second node, the source of the second P-type transistor is connected to the first power supply, and the drain of the second P-type transistor is connected to the first node. The gate of the second N-type transistor is connected to the second node, the source of the second N-type transistor is connected to the second power supply, and the drain of the second N-type transistor is connected to the first node. The third P-type transistor is provided between the second node and the first bit line, and the gate of the third P-type transistor is connected to the word line. The fourth P-type transistor is provided between the first node and the second bit line, and the gate of the fourth P-type transistor is connected to the word line. The word line driver includes a fifth P-type transistor, A source of the fifth P-type transistor is connected to the first power source, and a gate and a drain of the fifth P-type transistor are connected to the word line.

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