Global shutter solid-state imaging device

Abstract

A solid-state imaging device (90) includes a pixel circuit (100) including a radiation sensitive section (110), a pre-amplifier transistor (118), and a voltage storage section (160). The constant current source (350) forms, with the pre-amplifier transistor (118), a source follower configured to pass an analog voltage signal having a voltage level related to the radiation intensity detected from the radiation sensitive portion (110) to the voltage storage portion (160) during a global operation period, where the constant current provided by the constant current source (350) is a capacitor charging current.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device that performs analog-to-digital conversion on an analog pixel signal output from a pixel circuit to a data signal line. In particular, the present disclosure relates to a solid-state imaging device having a voltage-domain global shutter pixel. Background Art

[0002] A solid-state imaging device has a photoelectric conversion element that generates a photocurrent proportional to the intensity of the received radiation. The pixel circuit converts the small photocurrent into an analog pixel signal and outputs the analog pixel signal to a common data signal line. In a solid-state imaging device with a global shutter (GS) pixel, each pixel circuit of the pixel array captures image information during a global operation period and buffers the image information until the pixel circuit is read out. A solid-state imaging device with a voltage domain global shutter pixel has a radiation sensitive portion and a voltage storage portion. During the global operation period, the radiation sensitive portion generates an analog voltage signal having a voltage level that continuously (steplessly) depends on the illumination intensity. The source follower transmits the analog voltage signal to the voltage storage portion, which stores the noise signal obtained in the reset phase and the data signal obtained in the data phase. A constant current source that absorbs all the source current of the source follower suppresses the feedback effect of the source follower output voltage and improves the linearity of the source follower. Summary of the Invention

[0003] The constant current source that sinks the source current of the source follower between the radiation-sensitive portion and the voltage storage portion of the GS pixel is typically based on a field-effect transistor (FET) with a constantly biased gate. Integration into the pixel circuit requires FETs with lateral dimensions where technological limitations lead to relatively large variations in lateral dimensions and transistor characteristics. Deviations between the constant current sources assigned to different pixel circuits can result in significant variations in the transfer time required from the radiation-sensitive portion to the voltage storage portion.

[0004] The present disclosure alleviates these shortcomings of the prior art. Specifically, the present disclosure provides a solid-state imaging device having a pixel circuit that uses a constant capacitor charging current to sink the source current of a source follower between a radiation-sensitive portion and a voltage storage portion. This constant capacitor charging current can be provided to the pixel circuits of a pixel array with little or no variation between pixels due to manufacturing reasons.

[0005] Therefore, a solid-state imaging device according to the present disclosure includes a pixel circuit and a constant current source. The pixel circuit includes a radiation-sensitive portion, an amplifier transistor, and a voltage storage portion. The amplifier transistor and the constant current source form a source follower configured to transmit an analog voltage signal having a voltage level related to the intensity of radiation detected from the radiation-sensitive portion to the voltage storage portion during a global operation period. The current delivered by the constant current source is a capacitor charging current.

[0006] Embodiments of the present disclosure provide a constant capacitor charging current for absorbing the source current of a source follower between a radiation-sensitive portion and a voltage storage portion. This can reduce pixel-to-pixel variation in the minimum time required to transfer a signal from the radiation-sensitive portion to the voltage storage portion. This can also reduce the global hold time required to reliably transfer image information to the voltage storage portion. This capacitive current source can reduce pixel-to-pixel variation and / or latency in GS pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] As a more complete appreciation of the present disclosure and many of its attendant advantages become better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a simplified block diagram of a solid-state imaging device according to an embodiment of the present technology that uses a constant capacitance charging current to sink a source current of a source follower between a radiation sensitive portion and a voltage storage portion of a GS pixel.

[0009] Figure 2 is a simplified circuit diagram of a GS pixel circuit according to an embodiment of the present technology, which uses a constant capacitor charging current to sink the source current of a source follower between a radiation sensitive portion and a voltage storage portion.

[0010] Figure 3 is a simplified circuit diagram of a portion of a solid-state imaging device according to an embodiment of the present technology, the solid-state imaging device including a voltage ramp circuit and a current source capacitor for supplying a constant capacitance charging current.

[0011] Figure 4 is a simplified block diagram of a solid-state imaging device according to an embodiment of the present technology, which has a voltage ramp circuit that supplies a constant capacitor charging current to a GS pixel circuit.

[0012] Figure 5 1 is a circuit diagram of a GS pixel circuit and a voltage ramp circuit for supplying a constant capacitor charging current to the GS pixel circuit according to an embodiment of the present technology.

[0013] Figure 61 is a circuit diagram of a GS pixel circuit according to an embodiment of the present technology, the GS pixel circuit having an auxiliary transistor for temporarily separating a buffer path of a voltage storage section.

[0014] Figure 7 Shows the supply to Figure 5 and Figure 6 Time diagram of the variable global bias voltage AMD of the GS pixel circuit.

[0015] Figure 8 Schematically illustrates a layout for distributing a global bias voltage AMD in a pixel array according to an embodiment.

[0016] Figure 9 Shows the supply to Figure 5 and Figure 6 Timing diagram of the variable auxiliary voltage VRG of the GS pixel circuit.

[0017] Figure 10 FIG. 1 schematically illustrates a layout for distributing an auxiliary voltage VRG in a pixel array according to an embodiment.

[0018] Figure 11 According to an embodiment, Figure 5 and Figure 6 1 is a timing diagram of the ramp signal RMP output by the voltage ramp circuit.

[0019] Figure 12 Schematically illustrates a layout for distributing the ramp signal RMP in a pixel array according to an embodiment.

[0020] Figure 13 A further time diagram of a ramp signal RMP according to an embodiment is shown, which uses the ramp signal to control the voltage in the buffer path of the voltage storage section according to the embodiment.

[0021] Figure 14A and Figure 14B A timing diagram showing control signals and internal signals of a GS pixel circuit in a global operation period according to an embodiment of the present technology is shown.

[0022] Figure 15A and Figure 15B A timing chart showing control signals and internal signals of a GS pixel circuit in a readout waiting period according to an embodiment of the present technology is shown.

[0023] Figure 16A and Figure 16B A timing chart showing control signals and internal signals of a GS pixel circuit in a row readout period according to an embodiment of the present technology is shown.

[0024] Figure 17and Figure 18 The voltages across the buffer switch in the buffer path of the GS pixel circuit are shown to discuss the effects of the embodiment.

[0025] Figure 19 is a simplified circuit diagram showing a portion of a voltage ramp circuit that generates a voltage ramp signal through DA conversion.

[0026] Figure 20 is a simplified circuit diagram showing a portion of a voltage ramp circuit that generates a voltage ramp signal through DA conversion.

[0027] Figure 21 is a simplified circuit diagram showing a configuration example of a ramp generator including a counter unit.

[0028] Figure 22 is a diagram illustrating an example of a stacked structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0029] Figure 23 is a schematic circuit diagram of a pixel circuit according to an embodiment, elements of which are formed on a first chip of a solid-state imaging device having a stacked structure.

[0030] Figures 24 to 28 is a schematic circuit diagram of a GS pixel circuit according to another embodiment of the present technology, which uses a constant capacitance charging current to perform signal transmission between a radiation sensitive portion and a voltage storage portion.

[0031] Figure 29 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0032] Figure 30 It is an auxiliary explanation Figure 29 A diagram illustrating an example of installation positions of a vehicle exterior information detection portion and an imaging portion of a vehicle control system. DETAILED DESCRIPTION

[0033] Embodiments for implementing the technology disclosed herein (hereinafter also referred to as "embodiments") will be described in detail below using the accompanying drawings. The technology disclosed herein is not limited to the described embodiments, and the various features in the embodiments are merely illustrative. The same elements or elements having the same functions are denoted by the same reference numerals. Repeated descriptions are omitted.

[0034] The electronic components that are connected can be electrically connected by direct, permanent low resistance connections (e.g., by conductive wires). The terms "electrically connected" and "signal connected" can also include connections that are suitable for permanent and / or temporary signal transmission and / or energy transmission through other electronic components provided. The electronic components can be electrically connected or signal connected via resistors, capacitors, electronic switches such as FETs (field effect transistors), or transistor circuits such as transmission gates. The load path of a transistor is the controlled path of the transistor. For example, the voltage applied to the gate of a field effect transistor controls the current flow in the load path between the source and drain electrodes by the field effect.

[0035] Although techniques for improving image quality and / or frame rate of a solid-state imaging device having certain types of voltage-domain GS pixels are described below in the context of certain types of GS pixels, the techniques may also be used for other types of GS pixels.

[0036] Figure 1 The following is a configuration example of a solid-state imaging device 90 according to an embodiment of the present technology. The solid-state imaging device 90 includes an image sensor assembly 70 and a signal processing unit 80. The image sensor assembly 70 includes a pixel array 10, a column signal processing unit 20, a vertical scanning unit 30, a readout buffer memory 40, and a sensor controller 50.

[0037] The pixel array unit 10 includes a plurality of pixel circuits 100 that are identically adapted for global shutter operation. Each pixel circuit 100 includes a radiation sensitive portion 110 and a voltage storage portion 160. The radiation sensitive portion 110 converts incident radiation into an analog voltage signal and can generally correspond to any active pixel sensor having one or two photoelectric conversion elements and three, four, or more FETs for intensity readout.

[0038] Radiation-sensitive section 110 includes a preamplifier transistor 118 for transmitting an analog voltage signal to voltage storage section 160. Preamplifier transistor 118 is configured as a source follower. The drain of preamplifier transistor 118 is electrically connected to a positive voltage. Constant current source 350 supplies a constant capacitor charging current and, during a global operation period, sinks the source current of preamplifier transistor 118, which outputs the analog voltage signal to voltage storage section 160.

[0039] The voltage storage section 160 buffers the received analog voltage signal until read out. The post-amplifier transistor 168 outputs a pixel signal delivered from the buffered analog voltage signal on one or two data signal lines 19 connecting a group of pixel circuits 100 with the column signal processing unit 20.

[0040] The photoelectric conversion elements of the pixel array 10 can be arranged in a matrix of columns and rows. A subset of pixel circuits 100 assigned to the same column of photoelectric conversion elements 101 forms a pixel column. A subset of pixel circuits 100 assigned to the same row of photoelectric conversion elements 101 forms a pixel row.

[0041] The vertical scanning unit 30 generates pixel control signals for operating and selecting groups of pixel circuits 100. The pixel control signals control pixel resetting, pixel exposure, short-term storage of illumination information within the pixel, transmission of analog voltage signals from the radiation sensitive portion 110 to the voltage storage portion 160, and output of pixel signals through the data signal line 19.

[0042] The vertical scanning unit 30 synchronously controls all pixel circuits 100 in a selected group of pixel circuits 100. The selected group of pixel circuits 100 may include some pixel circuits 100 in a pixel row, all pixel circuits 100 in a pixel row, or some or all pixel circuits 100 in more than one pixel row. In the following description, for simplicity, a "pixel row" is often referred to as an example of a "pixel circuit group." The vertical scanning unit 30 outputs control signals for operating field-effect transistors based on drive timing signals provided by the sensor controller 50.

[0043] The voltage storage unit 160 of the pixel output group sequentially routes the pixel signals to one or two data signal lines (vertical signal lines) 19. Each pixel output group may include some pixel circuits 100 in one pixel column, all pixel circuits 100 in one pixel column, or some or all pixel circuits 100 in more than one pixel column. In the following description, for simplicity, a "pixel column" is often referred to as an example of a "pixel output group."

[0044] The post-amplifier transistor 168 can be configured as a source follower together with the components of the column signal processing unit 20, wherein a load path of the post-amplifier transistor 168 is electrically connected between the positive logic supply voltage VDD and the data signal line 19. Each data signal line 19 sequentially transmits pixel signals from the pixel circuit 100 of one pixel column among the plurality of pixel columns to the column signal processing unit 20.

[0045] The column signal processing unit 20 includes a column signal processing circuit 200 for each data signal line 19 or for each pair of data signal lines 19. The column signal processing circuit 200 converts the pixel signal into a digital pixel value, may pre-process the digital pixel value, and outputs the digital pixel value or the pre-processed digital pixel value to the readout buffer memory 40. The readout buffer memory 40 temporarily stores the digital pixel value.

[0046] The sensor controller 50 generates a drive timing signal and outputs the drive timing signal to the vertical scanning unit 30. The sensor controller 50 generates a column control signal for controlling the column signal processing unit 20, and can generate a readout control signal that controls the reading out of digital pixel values ​​from the readout buffer memory 40 to the signal processing unit 80 and / or to the digital interface.

[0047] Figure 2 Components of a solid-state imaging device 90 with a voltage-domain global shutter pixel are shown.

[0048] The solid-state imaging device 90 includes a pixel circuit 100. The pixel circuit 100 includes a radiation-sensitive portion 110, a preamplifier transistor 118, and a voltage storage portion 160. A constant current source 350 and the preamplifier transistor 118 form a source follower configured to transmit an analog voltage signal having a voltage level depending on the detected radiation intensity from the radiation-sensitive portion 110 to the voltage storage portion 160 during a global operation period. The constant current delivered from the constant current source 350 is a capacitor charging current.

[0049] The radiation-sensitive portion 110 may include a single photodetector or two or more photodetectors, for example, with different sensitivities. The radiation-sensitive portion 110 may include four, five, or more transistors configured to control the reset, exposure time, and internal readout of the photodetector according to an arbitrary intensity readout scheme. The floating diffusion potential Vfd at the gate of the preamplifier transistor 118 steadily decreases as the radiation intensity received by the photodetector continues to increase.

[0050] During a global operation period, the preamplifier transistor 118 outputs an analog voltage signal at a transmission node 120 located between the source of the preamplifier transistor 118 and a constant current source 350, wherein the constant current source 350 sinks the source current of the preamplifier transistor 118 by charging a capacitor at a constant rate. The constant current source 350 includes one or more components that constitute part of the pixel circuit 100 and / or one or more components shared by some or all pixel circuits 100. The transmission node 120 forms a signal interface between the radiation sensitive portion 110 and the voltage storage portion 160.

[0051] The constant current source 350 and the preamplifier transistor 118 cooperate to form a source follower. During the global operation period, the constant current source 350 provides an active load for the preamplifier transistor 118. Outside the global operation period, the preamplifier transistor 118 can be separated from the constant current source 350.

[0052] The voltage storage unit 160 receives and buffers the analog voltage signal during the readout wait period. During the readout wait period, the voltage storage unit 160 maintains the analog voltage signal in one or more voltage storage elements. The voltage storage element may be a buffer capacitor with low leakage current. The capacitor electrodes of the buffer capacitor may include a metal structure that is separated from each other and from the semiconductor portion of the pixel circuit 100 by a dielectric layer. For example, the voltage storage element is a metal-insulator-metal capacitor (MIM capacitor).

[0053] The voltage storage unit 160 outputs an analog pixel signal reflecting the analog voltage signal to the data signal line 19 during the row readout period. The column signal processing circuit 200 receives the pixel signal through the data signal line 19 and converts the analog pixel signal into a digital pixel value.

[0054] The global operation period is applicable to all pixel circuits 100 of the pixel array at the same time. The row readout period is the same for all pixel circuits 100 in the same group of pixel circuits. Pixel rows are read out sequentially.

[0055] Each pixel circuit 100 operates as a voltage-domain global shutter pixel. The electronic global shutter provides simultaneous exposure of the radiation-sensitive portions 110 of all pixel circuits 100 during an exposure period. Each radiation-sensitive portion 110 generates an analog voltage signal having a voltage level related to the intensity of the radiation detected during the exposure period. During a portion of the global operation period following the exposure period, each radiation-sensitive portion 110 transmits the analog voltage signal to a voltage storage portion 160. The voltage storage portion 160 holds the analog voltage signal until the corresponding pixel signal is read out via a data signal line 19, which is shared by multiple pixel circuits 100 assigned to the same pixel column. The voltage storage portion 160 facilitates row-by-row readout of the pixel circuits 100 using the global shutter.

[0056] Typically, constant current sources for single-pixel circuits are based on transistors with offset gates. For a source follower to transmit the analog voltage signal from the radiation-sensitive portion 110 to the voltage storage portion 160 with a constant current in the nanoampere range, the transistor size is relatively small. However, manufacturing constraints can lead to relatively high variations in transistor channel widths. Differences in channel width can result in high deviations in the currents delivered by transistor-based constant current sources. Different constant currents in the pixel circuit 100 of an image sensor can lead to image distortion and / or long transmission periods. The constant current source 350 stimulates a constant capacitor charging current, eliminating the need for an additional transistor with an offset gate in the pixel circuit 100. Image defects caused by such transistors can be avoided. Constant current sources based on offset-gate transistors generate significant 1 / f noise, with smaller transistor areas potentially increasing the 1 / f noise. In contrast, constant current sources constructed from MIM capacitors do not generate 1 / f noise.

[0057] exist Figure 3 , the constant current source 350 includes a current source capacitor 351 and a voltage ramp circuit 352 for each pixel circuit 100. The current source capacitor 351 is electrically connected between the source of the pre-amplifier transistor 118 of the pixel circuit 100 and the output terminal of the voltage ramp circuit 352. The voltage ramp circuit 352 is configured to supply a linear voltage ramp to the current source capacitor 351 in the ramp phase of the global operation period.

[0058] The load path of the pre-stage select transistor 119 is electrically connected in series between the source of the pre-amplifier transistor 118 and the current source capacitor 351. The transmission node 120 is located between the pre-stage select transistor 119 and the current source capacitor 351. The pre-stage select transistor 119 may be an nFET. During the global operation period, an active global select signal SW turns on the pre-stage select transistor 119. During the readout wait period and the row readout period, the global select signal SW is inactive and turns off the pre-stage select transistor 119, thereby isolating the pre-amplifier transistor 118 from the transmission node 120.

[0059] Alternatively, the current source capacitor 351 may be directly connected to the source of the amplifier transistor 118 , or more intermediate elements may be electrically connected between the current source capacitor 351 and the source of the amplifier transistor 118 , where the intermediate elements may include a transistor operating as a switch.

[0060] The output of the voltage ramp circuit 352 may be directly connected to the current source capacitor 351. Alternatively, one, two, or more intermediate elements may be electrically connected between the current source capacitor 351 and the output of the voltage ramp circuit 352. The intermediate elements may include one or more transistors operating as switches and / or buffers.

[0061] For each pixel circuit 100, the load path between the source and drain of the preamplifier transistor 118, the current source capacitor 351, and the drive path of the voltage ramp circuit 352 can be electrically connected in series between a conductor having a positive potential (e.g., the global bias voltage AMD) and a conductor having a reference potential VSS. The current path through the preamplifier transistor 118 between the conductors for the global bias voltage AMD and the reference potential VSS can include additional electronic components.

[0062] The current source capacitor 351 has a capacitance C in the source path of the pre-amplifier transistor 118. During the global operation period, the voltage ramp circuit 352 applies a linear voltage ramp having a constant slope ratio Vrmp / Trmp to the first electrode (first capacitor electrode) of the current source capacitor 351. When the pre-amplifier transistor 118 maintains a constant output voltage at the second electrode (second capacitor electrode) of the current source capacitor 351, the second capacitor electrode sinks a constant charging current Ic=(Vrmp*C) / Trmp.

[0063] During the global operation period, pre-amplifier transistor 118 forces the voltage at transfer node 120 to a voltage level that is a function of the floating diffusion potential Vfd at the gate of pre-amplifier transistor 118. As long as a sufficiently steep voltage ramp is simultaneously supplied to the first capacitor electrode, current source capacitor 351 sinks the required constant current through the second capacitor electrode.

[0064] For a constant current source using a capacitor charging current, the amplitude of the constant current supplied or absorbed depends on the capacitance C of the current source capacitor and the slope ratio of the voltage ramp supplied to the current source capacitor. The same ramp signal can be supplied to multiple current source capacitors. The process of forming a capacitor with a capacitance within a relevant value range (e.g., from 35fF to 100fF) between 5fF and 500fF on a semiconductor substrate is well controllable. The capacitance fluctuation between capacitors manufactured on the same semiconductor substrate is relatively low. The source follower in the pixel circuit 100 can be formed with relatively little effort, and the deviation of its constant current is negligible. The constant current source 350 with a voltage ramp circuit 352 and a current source capacitor 351 can improve image quality.

[0065] In the voltage storage section 160, the load path of the post-amplifier transistor 168 and the load path of the post-select transistor 169 are electrically connected in series between a conductor having a positive logic supply voltage VDD and the data signal line 19. A current source circuit 210, which supplies a constant current, is electrically connected between the data signal line 19 and a reference potential VSS. An internal voltage V2 reflecting the buffered analog voltage signal is sequentially applied to the gate of the post-amplifier transistor 168. The post-amplifier transistor 168 and the current source circuit 210 form a source follower circuit that outputs an analog pixel signal to the data signal line 19, wherein the current source circuit 210 sinks a constant current.

[0066] The post-stage selection transistor 169 may be an nFET. During a row readout period, an active row selection signal SEL turns on the post-stage selection transistor 169 to connect the post-amplifier transistor 169 to the data signal line 19. Outside the row readout period, the row selection signal SEL is inactive and turns off the post-stage selection transistor 169 to disconnect the post-amplifier transistor 168 from the data signal line 19.

[0067] Figure 4 The column signal processing unit 20 is shown, which has a column signal processing circuit 200 for each data signal line 19 or for each pair of data signal lines 19, a voltage ramp generator 25, and a counter circuit 26. The pixel circuit 100 can output pixel signals for the reset phase (noise signal) and the data phase (data signal) sequentially on the same data signal line 19 or simultaneously on a pair of data signal lines 19. Each column signal processing circuit 200 includes a current source circuit 210, a comparator circuit 220, and a digital circuit 230.

[0068] The current source circuit 210 constitutes a source follower together with the post-amplifier transistor 168, which outputs the pixel signal of the selected pixel circuit 100 to the first input terminal of the comparator circuit 220 in the row readout period. The current source circuit 210 sinks a constant current.

[0069] The voltage ramp generator 25 outputs a voltage ramp signal in response to the valid ramp enable signal. The voltage ramp signal decreases from a high voltage level to a low voltage level continuously or in small steps. The voltage ramp signal is applied to the second input of the comparator circuit 220 during the row readout period. When the voltage level of the voltage ramp signal drops below the voltage level of the pixel signal applied to the first input of the comparator circuit 220, the comparator circuit 220 outputs a valid comparator output signal.

[0070] In response to the valid count enable signal, counter circuit 26 outputs the digital count value of the digital counter on the digital bus to the data input of digital circuit 230. The valid count enable signal and the valid ramp enable signal have a predetermined time relationship with each other and with the start of the row readout period. Digital circuit 230 latches the current count value applied to the data input upon the transition from the invalid comparator output signal to the valid comparator output signal. The latched count value represents the digital pixel value of the pixel signal obtained from pixel circuit 100 during the row readout period.

[0071] The column signal processing unit 20 may include one counter circuit for each digital circuit 230 or for each subset of the digital circuits 230, instead of one counter circuit 26 in which the counter value is applied to all the digital circuits 230. The column signal processing unit 20 may include one voltage ramp generator 25 for each comparator circuit 220 or for each subset of the comparator circuits 220, instead of one voltage ramp generator 25 in which the voltage ramp signal is applied to all the comparator circuits 220.

[0072] The digital circuit 230 may include an arithmetic logic unit (ALU) for preprocessing digital pixel values. For each row readout period, the ALU may calculate a corrected pixel value from the digital pixel value obtained in the reset phase (P phase) and the digital pixel value obtained from the same pixel circuit 100 in the data phase (D phase). The ALU may perform DCDS (digital correlated double sampling) and subtract the digital pixel value obtained in the reset phase from the digital pixel value obtained from the same pixel circuit 100 in the data phase to obtain the corrected pixel value. In the same global operation period, the data phase immediately follows the reset phase.

[0073] The column signal processing circuit 200 outputs the digital pixel value to the readout buffer memory 40. The readout buffer memory 40 temporarily stores the digital pixel value.

[0074] The constant current source 350 includes one current source capacitor 351 per pixel circuit 100 and a single voltage ramp circuit 352. In each pixel circuit 100, the current source capacitor 351 is electrically connected in a path connecting the source of the preamplifier transistor 118 of the pixel circuit 100 and the output terminal of the voltage ramp circuit 352.

[0075] The solid-state imaging device 90 further includes a vertical scanning unit 30 configured to output a variable global bias voltage AMD and transfer the variable global bias voltage AMD to the drain of the pre-amplifier transistor 118 .

[0076] Specifically, the drain of the preamplifier transistor 118 and the output of the vertical scanning unit 30 are electrically connected to an AMD conductor for global bias AMD. All pixel circuits 100 can be electrically connected to the same AMD conductor. The AMD conductor can include multiple column segments, wherein each column segment extends parallel to a pixel column and is connected to all pixel circuits 100 in that pixel column.

[0077] The global bias voltage AMD is simultaneously transmitted to all pixel circuits 100. The global bias voltage AMD varies between at least two (eg, three) different voltage levels to support and / or improve the function of the voltage storage portion.

[0078] The vertical scanning unit 30 outputs additional control signals for controlling the pixel circuit 100, such as a global select signal SW and a row select signal SEL for each pixel row. Furthermore, the vertical scanning unit 30 can output a control signal for controlling the voltage ramp circuit 352 to output a linear voltage ramp during a ramp phase of a global operation period, wherein the linear voltage ramp has a predetermined time relationship with the global select signal SW applied to the previous select transistor 119. The constant current source 350 having the voltage ramp circuit 352 and the current source capacitor 351 provides a switched capacitor current source that at least temporarily supplies a constant current to the transmission node 120 of the pixel circuit 100.

[0079] The vertical scanning unit 30 may be configured to change the global bias voltage AMD between a low level in a precharge phase in the global operation period and a high level outside the precharge phase.

[0080] During the global operation period, each pre-charge phase precedes the ramp phase. In the first ramp phase (reset phase, P phase), the pre-amplifier transistor 118 transmits the reset signal for correlated double sampling readout (CDS readout) to the voltage storage unit 160. In the second ramp phase (data phase, D phase), the pre-amplifier transistor 118 transmits the data signal for CDS readout to the voltage storage unit 160. During the pre-charge phase, the pre-amplifier transistor 118 is turned on and simultaneously transmits the global bias voltage AMD to the transmission nodes 120 of all pixel circuits 100, wherein at this time, the global bias voltage AMD has a low voltage level. At the end of the pre-charge phase, the transmission nodes 120 of the pixel circuits 100 are in a defined initial state with a low voltage. In the subsequent reset and data phases, the global bias voltage AMD changes to a high level. The transmission node 120 is charged to the data signal level and the reset signal level by the relatively high current provided by the pre-amplifier transistor 118 in a high-efficiency source follower configuration, rather than being discharged by the relatively low charging current of the current source capacitor. The total time required to transmit the analog voltage signal from the radiation sensitive portion 110 to the voltage storage portion 160 may be reduced.

[0081] According to another embodiment, the voltage storage unit 160 is configured to transfer a pixel signal obtained from an analog voltage signal to the data signal line 19 in the row readout period, and the vertical scanning unit 30 may be configured to drive the global bias voltage AMD at a middle level in the row readout period.

[0082] The middle level is higher than the low level of the global bias voltage AMD during the precharge phase and lower than the high level of the global bias voltage AMD during the ramp phase of the global operation period. The middle level may be equal to or approximate to a reset level obtained by subtracting the gate-source voltage of the preamplifier transistor 118 from the positive pixel supply voltage VDDH to reduce fixed pattern noise (FPN) generated by mismatching of the two buffer capacitors used to buffer the analog voltage signals of the data signal and the noise signal in the voltage storage unit 160. The positive logic supply voltage VDD and the positive pixel supply voltage VDDH may be equal or different.

[0083] The sensor controller 50 generates a drive timing signal and outputs the drive timing signal to the vertical scanning unit 30. The sensor controller 50 generates a column control signal for controlling the column signal processing unit 20. Specifically, the sensor controller 50 outputs a ramp enable signal for synchronizing the voltage ramp generator 25 and a counter enable signal for synchronizing the counter circuit 26. The sensor controller 50 can generate a readout control signal that controls the reading out of digital pixel values ​​from the readout buffer memory 40 to the signal processing unit 80 and / or via the digital interface.

[0084] Figure 5 An example of a voltage domain GS pixel is shown having a radiation sensitive portion 110 based on a design with six transistors in combination with one photodetector (photoelectric conversion element) 101. Each of the transistors is or comprises an nFET.

[0085] The photoelectric conversion element 101 photoelectrically converts incident electromagnetic radiation into electric charge. The amount of charge generated in the photoelectric conversion element 101 corresponds to the intensity of the incident electromagnetic radiation. The photoelectric conversion element 101 may include or be composed of a photodiode, which converts electromagnetic radiation incident on the detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation, and / or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein, within the intensity range of interest, the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0086] The first electrode of the floating diffusion capacitor 116 stores the charge supplied from the photoelectric conversion element 101 during the transfer period. The first electrode of the floating diffusion capacitor 116 can be a floating diffusion region. The floating diffusion voltage Vfd of the first capacitor electrode depends on the state of the radiation sensitive portion 110: in the reset phase, the floating diffusion voltage Vfd is a function of the pixel dark current representing noise. In the data phase, the floating diffusion voltage Vfd is a function of the brightness (illumination intensity) sampled by the radiation sensitive portion 110.

[0087] Preamplifier transistor 118 is configured as a source follower, with its controlled load path electrically connected between global bias voltage AMD and transmission node 120, which forms a signal interface between radiation sensitive portion 110 and voltage storage portion 160. A first electrode of floating diffusion capacitor 116 is connected to the gate of preamplifier transistor 118. The potential at the gate of preamplifier transistor 118 is equal to floating diffusion voltage Vfd. The first electrode of floating diffusion capacitor 116 serves as an input node for preamplifier transistor 118.

[0088] The load path of the transfer transistor 112 is electrically connected between the cathode of the photoelectric conversion element 101 and the first electrode of the floating diffusion capacitor 116. The transfer transistor 112 serves as a transfer element for transferring charge from the photoelectric conversion element 101 to the first electrode of the floating diffusion capacitor 116 during a transfer period. The floating diffusion capacitor 116 serves as a temporary local charge storage device. A transfer signal TRG is supplied to the gate (transfer gate) of the transfer transistor 112 via a transfer control line. The transfer signal TRG changes between an effective signal level ("effective transfer signal") and an ineffective signal level ("ineffective transfer signal"). In response to the effective transfer signal TRG, the transfer transistor 112 transfers electrons photoelectrically converted by the photoelectric conversion element 101 to the first electrode of the floating diffusion capacitor 116. In the illustrated embodiment, the effective signal level is a high level.

[0089] The load path of the PD reset transistor (photodetector reset transistor) 113 is electrically connected between the positive pixel supply voltage VDDH and the cathode of the photoelectric conversion element 101. The PD reset transistor 113 serves as a reset element for precharging the cathode of the photoelectric conversion element 101. A PD reset signal OFG is supplied to the gate of the PD reset transistor 113 via a PD reset control line. The PD reset signal OFG has an active signal level and an inactive signal level. The active PD reset signal OFG sets the potential at the cathode of the photoelectric conversion element PD to be equal to or approximately equal to the positive pixel supply potential VDDH.

[0090] The load path of FD reset transistor 114 is connected between a reset potential, which may be a positive pixel supply voltage VDDH, and the load path of intermediate transistor 115. The load path of intermediate transistor 115 is connected between the load path of FD reset transistor 114 and the gate of preamplifier transistor 118. Supplementary capacitor structure 117 is electrically connected between a network node located between FD reset transistor 114 and intermediate transistor 115. The capacitance of supplementary capacitor structure 117 includes at least the parasitic capacitance of the network node located between FD reset transistor 114 and intermediate transistor 115.

[0091] The capacitance control signal FDG applied to the gate of the middle transistor 115 controls the middle transistor 115. The reset signal RST applied to the gate of the FD reset transistor 114 controls the FD reset transistor 114.

[0092] When the effective capacitance control signal FDG turns on the middle transistor 115, the capacitance of the supplementary capacitance structure 117 is added to the capacitance of the floating diffusion capacitor 116. A relatively large amount of charge can be discharged by the detector current signal, so that even under bright lighting conditions, the total capacitance is not completely discharged during the exposure period, and the dynamic range is high. On the other hand, the sensitivity under dark lighting conditions is low.

[0093] When the deactivation capacitance control signal FDG turns off the middle transistor 115, the supplemental capacitance structure 117 is decoupled from the floating diffusion capacitor 116. Under dim lighting conditions, even a relatively small detector current signal may result in a relatively high voltage signal swing at the first electrode of the floating diffusion capacitor 116. On the other hand, under bright lighting conditions, the relatively small capacitance of the floating diffusion capacitor 116 alone may be fully discharged before the end of the exposure period, resulting in a low dynamic range.

[0094] In a pixel circuit without the intermediate transistor 115, the load path of the reset transistor 114 can directly connect the positive pixel supply voltage VDDH to the first electrode of the floating diffusion capacitor 116. The reset transistor 114 serves as a reset element that resets the floating diffusion potential Vfd at the gate of the preamplifier transistor 118. The pixel reset signal RST is supplied to the gate of the reset transistor 114 through the reset control line. The pixel reset signal RST changes between a valid signal level ("valid pixel reset signal") and an invalid signal level ("invalid pixel reset signal"). In the embodiment shown, the valid signal level is a high level. The valid pixel reset signal RST sets the floating diffusion potential Vfd to be equal to or approximately equal to the pixel reset voltage. The pixel reset voltage can be a fixed voltage, such as the positive pixel supply voltage VDDH, or can be adaptively controlled by a compensation circuit.

[0095] The load path of the pre-stage select transistor 119 is electrically connected in series between the source of the pre-amplifier transistor 118 and the transmission node 120. The transmission node 120 is located between the pre-stage select transistor 119 and the current source capacitor 351. The pre-stage select transistor 119 is an nFET. During the global operation period, an active global select signal SW turns on the pre-stage select transistor 119. At least for the majority of the readout wait period and the row readout period, the global select signal SW is inactive and turns off the pre-stage select transistor 119, thereby isolating the pre-amplifier transistor 118 from the transmission node 120.

[0096] The gates of the transfer transistor 112, the PD reset transistor 113, the FD reset transistor 114, and the intermediate transistor 115 can each be connected for a group of pixel circuits 100 (e.g., a pixel row), so that operations for each of the pixel circuits 100 in one group of pixel circuits 100 are performed simultaneously. A single global selection signal SW can control all pixel circuits 100 of the pixel array.

[0097] The voltage storage unit 160 includes a first buffer path and a second buffer path. The first buffer path includes a first buffer capacitor 161 and a first buffer switch 163 electrically connected in series. The second buffer path includes a second buffer capacitor 162 and a second buffer switch 164 electrically connected in series. The first and second buffer paths are electrically connected in parallel between the transmission node 120 and the sampling node 170, wherein the transmission node 120 is formed between the amplifier transistor 118 and the current source capacitor 351 of the pixel circuit 100.

[0098] A first electrode of first buffer capacitor 161 is directly connected to transmission node 120 between amplifier transistor 118 and current source capacitor 351. A second electrode of first buffer capacitor 161 is connected to a first load electrode of first buffer switch 163. A first electrode of second buffer capacitor 162 is connected to transmission node 120 directly or through a switch. A second electrode of second buffer capacitor 162 is connected to a first load electrode of second buffer switch 164. A second load electrode of first buffer switch 163 and a second load electrode of second buffer switch 164 are connected to sampling node 170.

[0099] The two buffer paths facilitate sequentially storing the voltage level of the noise signal on the first buffer capacitor 161 in the reset phase and storing the voltage level of the CDS-read data signal on the second buffer capacitor 162 in the data phase.

[0100] The voltage storage section 160 further includes a post-amplifier transistor 168 configured to output a pixel signal on the data signal line 19 , wherein the voltage level of the pixel signal is related to the analog voltage signal transmitted to the voltage storage section 160 .

[0101] The post-amplifier transistor 168 and the current source circuit 210 of the column signal processing circuit 200 are configured as a source follower. The sampling node 170 is connected to the gate of the post-amplifier transistor 168. The internal voltage V2 transmitted to the sampling node 170 reflects the buffered analog voltage signal and is in turn applied to the gate of the post-amplifier transistor 168. The post-amplifier transistor 168 outputs an analog pixel signal to the data signal line 19, wherein the current source circuit 210 sinks a constant current.

[0102] The load path of the post-stage selection transistor 169 and the load path of the post-stage amplifier transistor 168 are electrically connected in series between a conductor having a positive logic power supply voltage VDD and the data signal line 19 .

[0103] A row select signal SEL is supplied to the gate of the rear-stage select transistor 169 via a select control line. The row select signal SEL changes between an active signal level ("active select signal") and an inactive signal level ("inactive select signal"). In the illustrated embodiment, the rear-stage select transistor 169 is an nFET and the active signal level is a high level.

[0104] During the row readout period, the active row select signal SEL turns on the post-stage select transistor 169 to connect the post-stage amplifier transistor 169 to the data signal line 19. Outside the row readout period, the row select signal SEL is inactive and turns off the post-stage select transistor 169 to disconnect the post-stage amplifier transistor 168 from the data signal line 19. When the post-stage select transistor 169 is turned on, the post-stage amplifier transistor 169 operates in a source follower configuration.

[0105] The voltage storage section 160 further includes a post-stage reset transistor 165 configured to temporarily connect the sampling node 170 to the variable auxiliary voltage VRG.

[0106] The post-stage reset transistor 165 temporarily connects the sampling node 170 to the VRG line 391, where the variable auxiliary voltage VRG of the VRG line 391 is at least temporarily higher than the reference potential VSS. A buffered reset signal RB is supplied to the gate of the post-stage reset transistor 165 via the buffered reset line. The buffered reset signal RB varies between an active signal level ("active buffered reset signal") and an inactive signal level ("inactive buffered reset signal"). In the illustrated embodiment, the post-stage reset transistor 165 is an nFET, and the active signal level is a high level.

[0107] exist Figure 6 , the pixel circuit 100 includes an auxiliary transistor 121 configured to separate the first buffer capacitor 161 from the second buffer capacitor 162 in a readout waiting period following a global operation period.

[0108] Separating second buffer capacitor 162 from first buffer capacitor 161 during the readout wait period facilitates setting different potentials at the first electrodes of first buffer capacitor 161 and second buffer capacitor 162. By applying appropriate potentials to the separated first capacitor electrodes and sampling node 170, the potentials on both sides of first buffer switch 163 and second buffer switch 164 can be substantially equal when first buffer switch 163 and second buffer switch 164 are off. This can reduce gate-induced drain leakage through first (transistor) switch 163 and second (transistor) switch 164 during the readout wait period. This effect can be significant because the readout wait period can be relatively long.

[0109] The auxiliary transistor 121 may be electrically connected between the first electrode of the first buffer capacitor 161 and the first electrode of the second buffer capacitor 162. An auxiliary signal DIFF applied to the gate of the auxiliary transistor 121 turns off the auxiliary transistor 121 in a readout waiting period after a global operation period.

[0110] The load path of the auxiliary transistor 121 is electrically connected between the transmission node 120 and the current source capacitor 351. An auxiliary signal DIFF is supplied to the gate of the auxiliary transistor 121 via an auxiliary line. The auxiliary signal DIFF varies between an active signal level ("auxiliary signal active") and an inactive signal level ("auxiliary signal inactive"). In the illustrated embodiment, the auxiliary transistor 121 is an nFET and the active signal level is high. During at least a portion of the readout wait period, the auxiliary signal DIFF is inactive and turns off the auxiliary transistor 121, thereby separating the first buffer capacitor 161 from the second buffer capacitor 162. During at least a portion of the global operation period and the row readout period, or for the entire global operation period and / or the entire row readout period, the auxiliary signal DIFF is active and turns on the auxiliary transistor 121, thereby connecting the first buffer capacitor 161 to the second buffer capacitor 162.

[0111] The vertical scanning unit 30 may control the auxiliary signal DIFF for the auxiliary transistor 121 .

[0112] The vertical scanning unit 30 may be configured to output a variable global bias voltage AMD and transfer the variable global bias voltage AMD to the drain of the pre-amplifier transistor 118 , and drive the global bias voltage AMD at a reduced level during an initial stage of the readout wait period.

[0113] The reduced level may be lower than the low level of the global bias voltage AMD in the precharge phase of the global operation period. The pre-amplifier transistor 118 may transmit the reduced level of the global bias voltage AMD to the first electrode of the first buffer capacitor 161 toward the amplifier transistor 118. The potential at the node between the first buffer capacitor 161 and the first buffer switch 163 in the first buffer path is correspondingly reduced.

[0114] In the initial stage, the variable global bias voltage AMD can be increased during the remaining portion of the read wait period by sampling the lowered voltage level at the first electrode of the first buffer capacitor using the global selection signal SW. By applying a suitable potential to the sampling node 170 during the read wait period, the gate-induced drain leakage (GIDL) current in the first buffer switch 163 can be reduced.

[0115] The vertical scanning unit 30 may be configured to control the constant current source 350 to apply a reduced signal level to the current source capacitor 351 in the readout waiting period.

[0116] The reduced signal level delivered to the current source capacitor 351 can be lower than the voltage at the lower end of the voltage ramp delivered to the current source capacitor 351 during the global operation period. When a reduced voltage level is applied in the configuration with the auxiliary transistor 121, the potential at the node between the second buffer capacitor 162 and the second buffer switch 164 can be reduced accordingly. As long as an appropriate potential is applied to the sampling node 170 during the readout wait period, the GIDL current in the second buffer switch 164 can be reduced.

[0117] Figure 7 The timing of the variable global bias voltage AMD applied to the drain of the pre-amplifier transistor 118 is shown.

[0118] The global bias voltage AMD is simultaneously transmitted to all pixel circuits 100. In the illustrated embodiment, the global bias voltage AMD varies between four different voltage levels: a low level, a lower mid level, an upper mid level, and a high level.

[0119] During the global operation period, the global bias voltage AMD changes between a lower intermediate level in the precharge phase and a high level in the ramp phase following the precharge phase. During the precharge phase, the preamplifier transistor 118 turns on and transmits the lower intermediate level to the transmission node 120 to set the transmission node 120 to the lower intermediate level. In the subsequent reset and data phases, the global bias voltage AMD changes to a high level, and the preamplifier transistor 118, in a high-efficiency source follower configuration, efficiently charges the transmission node 120 to the data signal level and the reset signal level.

[0120] Outside the global operation period, the global bias voltage AMD has a low level in the initial stage of the read waiting period and has a higher level in the remaining part of the read waiting period and during the entire row read period. The low level in the initial stage can be latched to the transmission node 120 by controlling the front stage selection transistor 119. Combined with applying an appropriate potential to the sampling node 170, the latched low level reduces Figure 6 The GIDL current in the first buffer switch 163 is reduced.

[0121] Figure 8 shows the use, for example, of Figure 4 The AMD buffer circuit 380 receives the bias source signal AMD_IN provided by the vertical scanning circuit 30. The AMD buffer circuit 380 outputs a buffered global bias voltage AMD on an AMD conductor 381. The AMD conductor 381 includes a plurality of AMD column segments 382, ​​wherein each AMD column segment 382 extends parallel to a pixel column and is connected to all pixel circuits 100 in that pixel column.

[0122] Figure 9 The timing of the variable auxiliary voltage VRG applied to the drain of the subsequent-stage reset transistor 165 is shown.

[0123] The auxiliary voltage VRG is transmitted to all pixel circuits simultaneously. In the embodiment shown, the auxiliary voltage VRG changes between a low level and a high level.

[0124] The auxiliary voltage VRG has a low level in the initial stage of the read waiting period and has a high level in the remaining part of the read waiting period, during the entire row read period, and during the entire global operation mode. The low level in the initial stage can be latched to the sampling node 170 by controlling the rear reset transistor 165 to apply a suitable level to the transmission node 120 to reduce Figure 6 The higher level in the global operation period can help reduce the leakage of the first buffer switch 163 and the second buffer switch 164. Figure 6 The voltage stress of the first buffer capacitor 161 and the second buffer capacitor 162 is reduced.

[0125] Figure 10 shows a method for, for example, Figure 4 The auxiliary source signal VRG_IN is provided to the vertical scanning circuit 30 by the VRG buffer circuit 390. The VRG buffer circuit 390 outputs a buffered auxiliary voltage VRG on a VRG line 391. The VRG line 391 includes a plurality of VRG column segments 392, wherein each VRG column segment 392 extends parallel to a pixel column and is connected to all pixel circuits 100 in the pixel column.

[0126] Figure 11Shows the application to Figure 4 The ramp signal RMP is transmitted to all pixel circuits 100 simultaneously. In the embodiment shown, the ramp signal RMP changes between three different voltage levels (low level, middle level and high level).

[0127] During the precharge phase of the global operation period, the ramp signal is at a high level. During the ramp phases of the reset and data phases, the ramp signal linearly decreases from a high level to a low level to sink current from the other electrode of the current source capacitor. To reduce voltage stress on the current source capacitor, the high level should be approximately 0.3V higher than the reset level on the transmission node.

[0128] The low level during the readout wait period, combined with applying a suitable voltage to the sampling node 170, reduces Figure 6 The leakage in the second snubber switch 164 in FIG.

[0129] Figure 12 The solid-state imaging device is shown with a constant current source 350, which includes a switch circuit 360 electrically connected between the output terminal of a voltage ramp circuit 352, a first electrode of a current source capacitor 351, and a reference potential VSS. The switch circuit 360 applies a ramp signal RMP output by the voltage ramp circuit 352 to the current source capacitor 351 at least during a global operation period, and applies the reference potential VSS to the current source capacitor 351 during a readout wait period.

[0130] The ramp signal RMP comprises a linear voltage ramp delivered to the current source capacitor 351 during the ramp phase of the global operation period. In a configuration with the auxiliary transistor 121, the switch circuit 360 can apply a relatively low voltage level, such as the reference potential VSS, to the current source capacitor 351 during the read wait period. The potential at the node between the second buffer capacitor 162 and the second buffer switch 164 in the second buffer path can be reduced accordingly. This can reduce the GIDL current in the second buffer switch 164.

[0131] By selecting appropriate voltage levels for the global bias voltage AMD, the variable auxiliary voltage VRG, and the ramp signal RMP output by the voltage ramp circuit during the readout standby period, the drain-source voltage of the first buffer switch 163 and the drain-source voltage of the second buffer switch 164 can be set to lower values, thereby significantly reducing the leakage current between the drain and source of the first buffer switch 163 and the drain and source of the second buffer switch 164, regardless of the voltage level of the analog voltage signal buffered in the buffer capacitors 161 and 162 of the voltage storage section 160.

[0132] The illustrated embodiment shows a switch circuit 360 including a first buffer switch 361 and a second buffer switch 362. Each first buffer switch 361 is electrically connected between the output terminal of the voltage ramp circuit 352 and the plurality of current source capacitors 351. Each second buffer switch 362 is electrically connected between the plurality of current source capacitors 351 and a reference potential VSS.

[0133] The plurality of current source capacitors 351 may include current source capacitors for one or more complete pixel rows. The vertical scanning unit 30 controls the first buffer switch 361 through the first buffer switch control signal ASW1. The vertical scanning unit 30 controls the second buffer switch 362 through the second buffer switch control signal ASW2.

[0134] The constant current source 350 may include a buffer circuit 370 electrically connected between the output terminal of the voltage ramp circuit 352 and the current source capacitor 351 .

[0135] Buffer circuit 370 may include a plurality of p-channel source followers 371. Each p-channel source follower 371 is electrically connected between the output of voltage ramp circuit 352 and a subset of current source capacitors 351. Each p-channel source follower 371 may be electrically connected between the output of voltage ramp circuit 352 and switch circuit 360.

[0136] Reference again Figure 6 The vertical scanning unit 30 can be configured to control the variable auxiliary potential VRG and transfer the variable auxiliary potential VRG to the drain of the subsequent reset transistor 165, wherein the vertical scanning unit 30 maintains the variable auxiliary potential VRG at a low level during the initial stage of the readout waiting period and maintains the variable auxiliary potential at a high level at least in the global operation period.

[0137] The rear-stage reset transistor 165 passes a low voltage level to the sampling node 170 in the initial stage of the read wait period. The rear-stage reset transistor 165 can be controlled to sample the low voltage level on the sampling node 170 during the remaining portion of the read wait period, so that the auxiliary potential can be set to a higher voltage in the main stage after the initial stage of the read wait period.

[0138] As long as the potential at the transmission node 120 is properly controlled, the low voltage level at the sampling node 170 can reduce the voltage across the first and second buffer switches 163 and 164 , wherein the GIDL current in the first and second buffer switches 163 and 164 can be reduced.

[0139] The variable auxiliary potential VRG is simultaneously transmitted to all pixel circuits 100. Specifically, the drain of the post-stage reset transistor 165 is electrically connected to a VRG line 391, which transmits the variable auxiliary potential VRG to the pixel circuits 100. All pixel circuits 100 can be electrically connected to the same VRG line 391. The VRG line 391 can include a plurality of column segments, wherein each column segment extends parallel to a pixel column and is connected to all pixel circuits 100 in the pixel column.

[0140] The voltage ramp circuit 352 generates a decreasing voltage ramp for each ramp phase to sink the source current of the preamplifier transistor. The voltage ramp circuit 352 can be based on an integrator driven by a constant current source. Alternatively, the voltage ramp circuit 352 can be implemented as a digital-to-analog converter that generates a decreasing voltage ramp.

[0141] Figure 13 1 shows the timing of the ramp signal RMP within a complete cycle, which includes a global operation period, a readout waiting period, and a row readout period.

[0142] The following timing diagram shows Figure 6 The control signals and internal signals of the pixel circuit 100, wherein the variable auxiliary potential VRG, the ramp signal RMP and the global bias voltage AMD are controlled to minimize VDS leakage and GIDL, as shown in FIG. Figure 7 、 Figure 9 and Figure 13 described.

[0143] Figure 14A and Figure 14B The global operating period is shown. The transmission node 120 is precharged with the lower mid-level of the global bias voltage starting before the active pulse on the transmission signal TRG to ensure that the pre-amplifier transistor 118 is turned on regardless of the data signal level.

[0144] Figure 15A and Figure 15B The effects of the described control of the variable auxiliary potential VRG, the ramp signal RMP and the global bias voltage AMD during the readout waiting period are shown, and Figure 16A and Figure 16B The effect during the row readout period is shown.

[0145] Figure 17 A voltage VCR at a first node between the first buffer capacitor 161 and the first buffer switch 163 in the first buffer path and a voltage VCD at a second node between the second buffer capacitor 162 and the second buffer switch 164 in the second buffer path during the global operation period and the readout wait period are shown.

[0146] In order to obtain a low gate-to-drain voltage of the first buffer switch 163 , the global bias voltage AMD is pulled down from 2.8 V to 1.2 V. 1.2 V is sampled at the transmission node 120 by turning off the previous stage selection transistor 119 .

[0147] To obtain a low gate-to-drain voltage of the second buffer switch 164, the voltage of the ramp signal RMP is pulled down from 1.2 V to 0 V, wherein the voltage V3 between the second buffer path and the current source capacitor 351 is reduced by 1.2 V. Regardless of the illumination intensity, the voltage VCR at the first node is approximately 0.8 V and the voltage VCD at the second node is also approximately 0.8 V, so that the first buffer transistor 163 and the second buffer transistor 164 have a low GIDL current.

[0148] Figure 18 shows the voltage V2 on the sampling node 170 and Figure 17 The voltages VCR and VCD are shown in the reference Figure 17 As described, in the read wait period, the voltage VCR on the first node is approximately 0.8V and the voltage VCD on the second node is also approximately 0.8V.

[0149] By pulling the variable auxiliary potential VRG to approximately 0.8 V and sampling the auxiliary potential VRG on the sampling node 170 by turning off the subsequent reset transistor 165, the voltage V2 during the readout wait period is set to approximately 0.8 V. Regardless of the data signal level, the drain-source voltage is approximately 0 V for both the first buffer transistor 163 and the second buffer transistor 164. In both the first buffer transistor 163 and the second buffer transistor 164, drain-source leakage is reduced.

[0150] Figure 19 A solid-state imaging device includes a DAC stage 358 having a plurality of switchable current supply units 35-1, ..., 35-n connected in parallel, and an output resistor 353. Each current supply unit 35-1, ..., 35-n includes a unit current source 354-1, ..., 354-n and a main switching element 355-1, ..., 355-n connected in series. The output resistor 353 is connected between the parallel-connected current supply units 35-1, ..., 35-n and a first constant voltage VX1.

[0151] The current supply units 35-1, ..., 35-n connected in parallel are connected in series between the second constant voltage VX2 and the output resistor 353. The first constant voltage VX1 may be the reference potential VSS and the second constant voltage VX2 may be the positive logic power supply voltage VDD. Alternatively, the first constant voltage VX1 may be the positive logic power supply voltage VDD and the second constant voltage VX2 may be the reference potential VSS.

[0152] When the main switching element 355 - x of the switchable current supply unit 35 - x is turned on, the corresponding unit current source 354 - x generates a current flowing through the output resistor 353 between the first constant voltage VX1 and the second constant voltage VX2 .

[0153] The current supply units 35-1, ..., 35-n may include FETs with constant gate bias, may be substantially identical, and may supply the same current. The main switching elements 355-1, ..., 355-n may be FETs. Switch control signals SW1, ..., SWn control the main switching elements 355-1, ..., 355-n and turn on the selected unit. The switch control signals SW1, ..., SWn control the current supply units 35-1, ..., 35-n in such a way that the total current passing through the output resistor 353 is gradually and continuously reduced over time with a step height corresponding to the voltage drop generated by a single one of the unit current sources 354-1, ..., 354-n at the output resistor 353. For example, a counter supplying the switch control signals SW1, ..., SWn may count down.

[0154] exist Figure 20 In the DAC stage 358 shown in FIG, each switchable current cell 35-1, ..., 35-n further includes a secondary switching element 356-1, ..., 356-n connected in series between the cell current source 354-1, ..., 354-n and the reference potential VSS. The secondary switching elements 356 - 1 , . . . , 356 - n are controlled and the selected secondary switching elements are turned on so that during operation, each unit current source 354 - 1 , . . . , 354 - n supplies the same current at any time and the total current consumption remains constant.

[0155] The DAC stage 358 shown is a ground-type DAC stage, in which the first constant voltage is equal to the reference potential VSS and the second constant voltage is equal to the positive logic supply voltage VDD. Depending on the DAC stage based on the supply type, the switchable current cells 35-1, ..., 35-n can be connected to the reference potential VSS and the output resistor 353 can be connected to the positive logic supply voltage VDD.

[0156] Figure 21 A voltage ramp circuit 352 is shown including a counter 359 that controls Figure 19 or Figure 20The switchable current supply unit 35-1, ..., 35-n of any DAC stage 358 in the circuit can be a binary counter that decrements the digital count value with each rising or falling edge of the clock signal and outputs the current digital count value in parallel at data outputs D0, ..., Dn-1. The data outputs D0, ..., Dn-1 supply switch control signals SW1, ..., SWn.

[0157] Figure 22 23020 is a perspective view showing an example of a stacked structure of a solid-state imaging device having a plurality of pixels arranged in a matrix in an array. Each pixel includes a pixel circuit having at least one photoelectric conversion element.

[0158] The solid-state imaging device 23020 has a stacked structure of a first chip (upper chip) 910 and a second chip (lower chip) 920. The stacked first chip 910 and the second chip 920 can be electrically connected to each other through TC(S)Vs (through-contact (silicon) vias) formed in the first chip 910. The solid-state imaging device 23020 can be formed to have a stacked structure such that the first chip 910 and the second chip 920 are bonded together at the wafer level and cut by dicing.

[0159] In the stacked structure of upper and lower chips, the first chip 910 may be an analog chip (sensor chip) including at least one analog component for each pixel circuit, for example, photoelectric conversion elements arranged in an array.

[0160] For example, the first chip 910 may include only the photoelectric conversion elements of the pixel circuit as described above with reference to the previous figures. Alternatively, the first chip 910 may include additional elements of each pixel circuit. For example, in addition to the photoelectric conversion elements, the first chip 910 may also include some or all elements of the radiation sensitive portion. Alternatively, the first chip 910 may include each element of the pixel circuit. In addition to the elements of the pixel circuit, the first chip 910 may also include elements of the constant current source as described above.

[0161] The second chip 920 may be primarily a logic chip (digital chip) that includes components complementary to those on the first chip 910 to form a complete pixel circuit and a complete constant current source. The second chip 920 may also include analog circuits, such as circuits for quantizing analog signals transmitted from the first chip 910 through the TCV. For example, the second chip 920 may include all or at least some components of the constant current source described with reference to the preceding figures.

[0162] The second chip 920 may have one or more bonding pads BPD, and the first chip 910 may have an opening OPN for wire bonding to the second chip 920. The solid-state imaging device 23020 having a stacked structure of two chips 910 and 920 may have the following characteristic configurations:

[0163] The electrical connection between the first chip 910 and the second chip 920 is implemented, for example, through TCVs. TCVs can be arranged at the ends of the chips or between the pad area and the circuit area. TCVs for transmitting control signals and supplying power can be mainly concentrated at, for example, the four corners of the solid-state imaging device 23020, thereby reducing the signal wiring area of ​​the first chip 910.

[0164] The technology according to the present disclosure can be implemented in a light receiving device installed in any type of mobile body, such as a car, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobile device, airplane, drone, ship, or robot.

[0165] Figure 23 The TCV 915 is shown transferring the analog voltage signal driven by the preamplifier circuit 118 from the radiation sensitive portion 110 to the voltage storage portion 160. The voltage storage portion 160 is formed entirely in the second chip 920. The current source capacitor 351 is formed in the second chip 920.

[0166] Figures 24 to 28 A further pixel circuit to which the present invention may be applied is shown, wherein the current source capacitor is indicated by the reference CRMP.

[0167] Figure 29 : is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a moving body control system to which the technology according to the embodiment of the present disclosure can be applied.

[0168] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 29 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0169] Drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, drive system control unit 12010 functions as a control device to control: a drive force generating device, such as an internal combustion engine or a drive motor, for generating the vehicle's drive force; a drive force transmission mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0170] The body system control unit 12020 controls the operation of various types of equipment installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device to control the following: the keyless entry system, the smart key system, the power windows, or various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves transmitted from a mobile device that replaces the key, or signals from various switches as input. The body system control unit 12020 receives these input radio waves or signals to control the vehicle's door locks, power windows, lights, and other devices.

[0171] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the imaged image. Based on the received image, the vehicle exterior information detection unit 12030 can detect an object (such as a person, vehicle, obstacle, sign, symbol, etc. on the road) or detect the distance to the object.

[0172] According to an embodiment of the present disclosure, imaging unit 12031 may be or include a solid-state imaging device having a GS pixel circuit, which includes a radiation-sensitive portion, a voltage storage portion, and a capacitive current source serving as an active load for a preamplifier transistor that transmits an analog voltage signal from the radiation-sensitive portion to the voltage storage portion. The light received by imaging unit 12031 may be visible light or invisible light such as infrared light.

[0173] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle and may be or include a solid-state imaging device with a GS pixel circuit according to an embodiment of the present disclosure. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 may include, for example, a camera that includes a solid-state imaging device and is focused on the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the driver's fatigue level or the driver's concentration level, or may determine whether the driver is dozing off.

[0174] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact cushioning for the vehicle, following driving based on vehicle-to-vehicle distance, speed maintenance driving, vehicle collision warnings, vehicle lane departure warnings, and the like.

[0175] In addition, the microcomputer 12051 can control the driving force generating device, steering mechanism, braking device based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby performing collaborative control intended for automatic driving, etc. that is not dependent on the driver's operation.

[0176] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to change from high beam to low beam based on the position of a preceding vehicle or an oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control aimed at preventing glare by controlling the headlights.

[0177] The audio / image output unit 12052 transmits an output signal of at least one of audio and image to an output device, which can visually or audibly notify vehicle passengers or the exterior of the vehicle of information. In the example of FIG1021 , an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display, each of which may include a solid-state imaging device having a CS pixel circuit using a capacitive current source, as described with reference to the previous figures.

[0178] Figure 30 12101 , 12102 , 12103 , 12104 , and 12105 .

[0179] For example, imaging units 12101, 12102, 12103, 12104, and 12105 may be positioned at the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. Imaging unit 12101 positioned at the front nose and imaging unit 12105 positioned at the upper portion of the windshield inside the vehicle primarily capture images of the front of the vehicle 12100. Imaging units 12102 and 12103 positioned at the side mirrors primarily capture images of the sides of the vehicle 12100. Imaging unit 12104 positioned at the rear bumper or rear door primarily captures images of the rear of the vehicle 12100. Imaging unit 12105 positioned at the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0180] Incidentally, Figure 30 Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101, which is located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, located at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104, which is located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view image of vehicle 12100 can be obtained from above.

[0181] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, an imaging element having pixels for phase difference detection, or a ToF module based on the GS pixel circuit according to the present disclosure, which uses a capacitive current source for transmitting an analog voltage signal from a radiation sensitive portion to a voltage storage portion.

[0182] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to the vehicle 12100). This can then extract the closest three-dimensional object as the leading vehicle, specifically one that is located on the driving path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. Furthermore, the microcomputer 12051 can pre-set a following distance to be maintained from the leading vehicle and execute automatic braking control (including following parking control), automatic acceleration control (including following starting control), and the like. Consequently, it is possible to execute cooperative control for autonomous driving, etc., independent of the driver's operation.

[0183] For example, based on the distance information obtained from the imaging units 12101-12104, the microcomputer 12051 can classify 3D object data regarding 3D objects into 3D object data for two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other 3D objects. The microcomputer 12051 then extracts the classified 3D object data for automatic obstacle avoidance. For example, the microcomputer 12051 determines whether obstacles around the vehicle 12100 are visually recognizable by the driver of the vehicle 12100 or obstacles that are difficult for the driver to visually identify. The microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value, indicating the possibility of a collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and the drive system control unit 12010 executes forced deceleration or evasive steering. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0184] At least one of the imaging units 12101-12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether a pedestrian exists in the images captured by the imaging units 12101-12104. This pedestrian recognition is performed, for example, by a program that extracts characteristic points from the images captured by the imaging units 12101-12104, which are infrared cameras, and a program that determines whether a pedestrian exists by performing pattern matching on a series of characteristic points representing the object's outline. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101-12104 and identifies the pedestrian, the audio / visual output unit 12052 controls the display unit 12062 to display a square outline superimposed on the recognized pedestrian to emphasize the recognized pedestrian. The audio / visual output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0185] The above describes an example of a vehicle control system to which the techniques according to embodiments of the present disclosure are applicable. By employing a solid-state imaging device equipped with a GS pixel circuit and a ramp generator circuit according to the present disclosure, image recognition results can be made more reliable. For example, pedestrian recognition can be performed based on more reliable pixel information. Image sensor failures can be reliably detected and reported to superiors.

[0186] In addition, the embodiment of the present technology is not limited to the above-described embodiment, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.

[0187] A solid-state imaging device including a GS pixel circuit according to the present disclosure using a capacitive current source for transmitting an analog voltage signal from a radiation-sensitive portion to a voltage storage portion can be any device for analyzing and / or processing radiation, such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device can be any electronic device in the fields of transportation, home appliances, medicine and healthcare, security, beauty, sports, agriculture, image reproduction, and the like.

[0188] Specifically, in the field of image reproduction, solid-state imaging devices can be devices for capturing images for viewing, such as digital cameras, smartphones, or mobile phone devices with camera functions. In the field of transportation, for example, solid-state imaging devices can be integrated into in-vehicle sensors (which capture the front, rear, periphery, interior, etc. of the vehicle for safe driving, such as automatic parking and driver status recognition), surveillance cameras that monitor traveling vehicles and roads, or distance measurement sensors that measure the distance between vehicles.

[0189] In the field of home appliances, solid-state imaging devices can be integrated into any type of sensor that can be used in devices provided for home appliances (such as TV receivers, refrigerators, and air conditioners) to capture user gestures and perform device operations based on the gestures. Therefore, solid-state imaging devices can be integrated into home appliances (such as TV receivers, refrigerators, and air conditioners) and / or devices that control home appliances. In addition, in the field of medicine and healthcare, solid-state imaging devices can be integrated into any type of sensor used in medicine and healthcare, such as endoscopes or devices that perform angiography by receiving infrared light.

[0190] In the security field, solid-state imaging devices can be integrated into devices used in security, such as surveillance cameras for crime prevention or cameras for personal identification. Furthermore, in the beauty field, solid-state imaging devices can be used in devices used in beauty, such as skin meters that capture skin or microscopes that capture probes. In the sports field, solid-state imaging devices can be integrated into devices used in sports, such as action cameras or wearable cameras for sports. Furthermore, in the agricultural field, solid-state imaging devices can be used in devices used in agriculture, such as cameras for monitoring the conditions of fields and crops.

[0191] This technology can also be configured as follows:

[0192] [1] A solid-state imaging device (90) comprises: a pixel circuit (100) including a radiation sensitive portion (110), a preamplifier transistor (118) and a voltage storage portion (160); and a constant current source (350), the constant current source (350) and the preamplifier transistor (118) forming a source follower, the source follower being configured to transmit an analog voltage signal having a voltage level related to the detected radiation intensity from the radiation sensitive portion (110) to the voltage storage portion (160) during a global operation period, wherein the constant current delivered by the constant current source (350) is a capacitor charging current.

[0193] [2] A solid-state imaging device according to [1], wherein the constant current source (350) includes a current source capacitor (351) and a voltage ramp circuit (352) for each pixel circuit (100), wherein the current source capacitor (351) is electrically connected between the source of the pre-amplifier transistor (118) of the pixel circuit (100) and the output of the voltage ramp circuit (352), and wherein the voltage ramp circuit (352) is configured to supply a linear voltage ramp to the current source capacitor (351) in a ramp phase of a global operation period.

[0194] [3] The solid-state imaging device according to any one of [1] and [2] further includes: a vertical scanning unit (30) configured to output a variable global bias voltage AMD and transfer the variable global bias voltage AMD to the drain of the pre-amplifier transistor (118).

[0195] [4] The solid-state imaging device according to [3], wherein the vertical scanning unit (30) is configured to change the global bias voltage AMD between a low level in a precharge phase and a high level outside the precharge phase during a global operation period.

[0196] [5] A solid-state imaging device according to any one of [3] and [4], wherein the voltage storage section (160) is configured to transfer a pixel signal obtained from an analog voltage signal to a data signal line (19) in a row readout period, and wherein the vertical scanning unit (30) is configured to drive the global bias voltage AMD at a medium level in the row readout period.

[0197] [6] A solid-state imaging device according to any one of [1] to [5], wherein the voltage storage section (160) includes a first buffer path and a second buffer path, the first buffer path including a first buffer capacitor (161) and a first buffer switch (163) electrically connected in series, the second buffer path including a second buffer capacitor (162) and a second buffer switch (164) electrically connected in series, the first buffer path and the second buffer path being electrically connected in parallel between a transmission node (120) and a sampling node (170), and wherein the transmission node (120) is formed between a pre-amplifier transistor (118) and a current source capacitor (351) of a pixel circuit (100).

[0198] [7] The solid-state imaging device according to [6] further includes: an auxiliary transistor (121) configured to separate the first buffer capacitor (161) and the second buffer capacitor (162) in a readout waiting period after the global operation period.

[0199] [8] The solid-state imaging device according to any one of [6] and [7] further includes: an auxiliary transistor (121) electrically connected between the first electrode of the first buffer capacitor (161) and the first electrode of the second buffer capacitor (162), wherein the auxiliary transistor (121) is configured so that an auxiliary signal DIFF applied to the gate of the auxiliary transistor (121) turns off the auxiliary transistor (121) in a readout waiting period after the global operation period.

[0200] [9] The solid-state imaging device according to any one of [7] and [8] further includes: a vertical scanning unit (30) configured to output a variable global bias voltage AMD and transfer the variable global bias voltage AMD to the drain of the pre-amplifier transistor (118), wherein the vertical scanning unit (30) is configured to drive the global bias voltage AMD at a reduced level during an initial stage of the readout waiting period.

[0201]

[10] The solid-state imaging device according to any one of [7] to [9] further includes: a vertical scanning unit (30) configured to control the constant current source (350) to apply a reduced signal level to the current source capacitor (351) in a readout waiting period.

[0202]

[11] A solid-state imaging device according to

[10] , wherein the constant current source (350) includes a switching circuit (360) electrically connected between the output of the voltage ramp circuit (352), the first electrode of the current source capacitor (351) and the reference potential VSS, wherein the switching circuit (360) applies the ramp signal RMP output by the voltage ramp circuit (352) to the current source capacitor (351) at least in the global operation period, and applies the reference potential VSS to the current source capacitor (351) in the readout waiting period.

[0203]

[12] A solid-state imaging device according to

[11] , wherein the switch circuit (360) includes a first buffer switch (361) and a second buffer switch (362), each first buffer switch (361) being electrically connected between the output of the voltage ramp circuit (352) and the plurality of current source capacitors (351), and each second buffer switch (362) being electrically connected between the plurality of current source capacitors (351) and a reference potential VSS.

[0204]

[13] A solid-state imaging device according to any one of

[11] and

[12] , wherein the constant current source (350) includes a buffer circuit (370) electrically connected between the output of the voltage ramp circuit (352) and the current source capacitor (351).

[0205]

[14] A solid-state imaging device according to any one of [6] to

[13] , wherein the voltage storage unit (160) includes a post-amplifier transistor (168) configured to output a pixel signal on a data signal line (19), wherein a voltage level of the pixel signal is related to an analog voltage signal transmitted to the voltage storage unit (160).

[0206]

[15] A solid-state imaging device according to any one of [6] to

[14] , wherein the voltage storage section (160) includes a post-stage reset transistor (165) configured to temporarily connect the sampling node (170) to the variable auxiliary potential VRG.

[0207]

[16] The solid-state imaging device according to

[15] further includes: a vertical scanning unit (30) configured to control the variable auxiliary potential VRG and transfer the variable auxiliary potential VRG to the drain of the subsequent reset transistor (165), wherein the vertical scanning unit (30) is configured to maintain the variable auxiliary potential VRG at a low level during the initial stage of the readout waiting period and maintain the variable auxiliary potential at a high level at least in the global operation period.

[0208]

[17] A solid-state imaging device according to any one of [2] to

[16] , wherein the voltage ramp circuit (352) includes a plurality of switchable current supply units (35-1, ..., 35-n) connected in parallel and an output resistor (353), wherein each current supply unit (35-1, ..., 35-n) includes a unit current source (354-1, ..., 354-n) and a main switching element (355-1, ..., 355-n) connected in series, and wherein the output resistor (353) is connected between the current supply units (35-1, ..., 35-n) connected in parallel and a constant voltage.

Claims

1. A solid-state imaging device comprising: a pixel circuit comprising a radiation sensitive portion, a preamplifier transistor, and a voltage storage portion; as well as A constant current source, which forms a source follower with the pre-amplifier transistor, and the source follower is configured to transmit an analog voltage signal having a voltage level related to the detected radiation intensity from the radiation sensitive part to the voltage storage part within a global operation period, wherein the constant current delivered by the constant current source is a capacitor charging current.

2. The solid-state imaging device according to claim 1, in, The constant current source includes a current source capacitor and a voltage ramp circuit for each pixel circuit, wherein the current source capacitor is electrically connected between the source of the pre-amplifier transistor of the pixel circuit and the output end of the voltage ramp circuit, and wherein the voltage ramp circuit is configured to supply a linear voltage ramp to the current source capacitor during the ramp phase of the global operation period.

3. The solid-state imaging device according to claim 1 , further comprising: The vertical scanning unit is configured to output a variable global bias voltage and transmit the variable global bias voltage to the drain of the pre-amplifier transistor.

4. The solid-state imaging device according to claim 3, in, The vertical scanning unit is configured to change the global bias voltage between a low level in a precharge phase and a high level outside the precharge phase in the global operation period.

5. The solid-state imaging device according to claim 3, wherein The voltage storage section is configured to transfer a pixel signal obtained from the analog voltage signal to a data signal line in a row readout period, and wherein the vertical scanning unit is configured to drive the global bias voltage at a middle level in the row readout period.

6. The solid-state imaging device according to claim 1, in, The voltage storage unit includes a first buffer path and a second buffer path, the first buffer path includes a first buffer capacitor and a first buffer switch electrically connected in series, the second buffer path includes a second buffer capacitor and a second buffer switch electrically connected in series, the first buffer path and the second buffer path are electrically connected in parallel between a transmission node and a sampling node, and wherein the transmission node is formed between the pre-amplifier transistor and the current source capacitor of the pixel circuit.

7. The solid-state imaging device according to claim 6, further comprising: An auxiliary transistor is configured to separate the first buffer capacitor from the second buffer capacitor in a readout waiting period after the global operation period.

8. The solid-state imaging device according to claim 6, further comprising: an auxiliary transistor electrically connected between the first electrode of the first buffer capacitor and the first electrode of the second buffer capacitor, wherein the auxiliary transistor is configured such that an auxiliary signal applied to a gate of the auxiliary transistor turns off the auxiliary transistor in a readout waiting period after the global operation period.

9. The solid-state imaging device according to claim 7, further comprising: A vertical scanning unit is configured to output a variable global bias voltage and transfer the variable global bias voltage to the drain of the pre-amplifier transistor, wherein the vertical scanning unit is configured to drive the global bias voltage at a reduced level during an initial stage of the readout waiting period.

10. The solid-state imaging device according to claim 7, further comprising: The vertical scanning unit is configured to control the constant current source to apply a reduced signal level to the current source capacitor in the readout waiting period.

11. The solid-state imaging device according to claim 10, in, The constant current source includes a switching circuit electrically connected between the output end of the voltage ramp circuit, the first electrode of the current source capacitor and a reference potential, wherein the switching circuit applies the ramp signal output by the voltage ramp circuit to the current source capacitor at least in the global operation period, and applies the reference potential to the current source capacitor in the readout waiting period.

12. The solid-state imaging device according to claim 11, in, The switch circuit includes a first buffer switch and a second buffer switch. Each first buffer switch is electrically connected between an output terminal of the voltage ramp circuit and a plurality of current source capacitors. Each second buffer switch is electrically connected between the plurality of current source capacitors and a reference potential.

13. The solid-state imaging device according to claim 11, in, The constant current source includes a buffer circuit electrically connected between an output terminal of the voltage ramp circuit and the current source capacitor.

14. The solid-state imaging device according to claim 6, in, The voltage storage section includes a post-amplifier transistor configured to output a pixel signal on a data signal line, wherein a voltage level of the pixel signal is related to the analog voltage signal transmitted to the voltage storage section.

15. The solid-state imaging device according to claim 6, in, The voltage storage section includes a rear-stage reset transistor configured to temporarily connect the sampling node to a variable auxiliary potential.

16. The solid-state imaging device according to claim 15, further comprising: A vertical scanning unit is configured to control the variable auxiliary potential and transfer the variable auxiliary potential to the drain of the subsequent reset transistor, wherein the vertical scanning unit is configured to maintain the variable auxiliary potential at a low level during the initial stage of the readout waiting period and to maintain the variable auxiliary potential at a high level at least in the global operation period.

17. The solid-state imaging device according to claim 2, in, The voltage ramp circuit includes a plurality of switchable current supply units connected in parallel and an output resistor, wherein each current supply unit includes a unit current source and a main switching element connected in series, and wherein the output resistor is connected between the parallel-connected current supply units and a constant voltage.

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