Optoelectronic device with electrical interconnect layer

Abstract

The present disclosure discloses an optoelectronic device (5) comprising: a photoemitter assembly (15) comprising a plurality of photoemitters (20a, 20b, 20c); a controller assembly (16) including a plurality of driver circuits (70) for providing current to the plurality of photoemitters; and at least one electrical interconnect layer (500) configured between the photoemitter assembly and the controller assembly, the electrical interconnect layer configured to provide an electrical connection between one or more of the driver circuits and each of the plurality of photoemitters; wherein the at least one electrical interconnect layer comprises at least one conductor layer (511) and at least one insulator layer (540) extending across at least a portion of the conductor layer.

Description

Technical Field

[0001] The present invention relates to a photovoltaic device and a method for manufacturing the photovoltaic device. In particular, the present invention relates to an improved photovoltaic device having an electrical interconnect layer and a method for manufacturing such a device. Background Art

[0002] One type of known optoelectronic device is a light emitting diode (LED). An LED typically has an n-doped semiconductor material, a p-doped semiconductor material, and a light emitting or active region located between the n-doped and p-doped semiconductor materials. When a current is supplied across the light emitting region to forward bias the diode, the LED emits light. Variations of simple LEDs are known, each having a specific material architecture, where the wavelength of the emitted light depends on the specific material composition and configuration of the LED.

[0003] III-V semiconductor materials, particularly the III-nitride semiconductor family, have garnered significant attention for LED design. "III-V" semiconductors include binary, ternary, and quaternary alloys of Group III elements such as Ga, Al, and In with Group V elements such as N, P, As, and Sb. "III-nitride" materials include gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), as well as their ternary and quaternary alloys. (Al, In)GaN is a term encompassing AlGaN, InGaN, and GaN.

[0004] There is a huge demand for LEDs that emit at all visible wavelengths, especially at longer wavelengths towards green, yellow, and red, but historically, manufacturers have encountered more problems in making LEDs that emit at longer wavelengths. For example, a major challenge in growing longer wavelength LEDs, such as green, yellow, and red LEDs, on GaN-based platforms is the need to use high indium (In) content to reduce the band gap in the light-emitting or active region to a level suitable for long-wavelength emission. However, varying the In content of the material also affects the in-plane lattice constant of the semiconductor. The desired InGaN light-emitting or active region has a larger lattice parameter than the underlying GaN. This creates problems in device design, where the active semiconductor layer needs to be deposited on top of a base layer with a different lattice size. The lattice mismatch at the layer boundaries introduces strain into the lattice, which leads to the formation of defects in the material that act as non-radiative recombination centers and reduce device performance.

[0005] It is known to manufacture micro-LEDs using techniques such as normal LED epitaxy and laser lift-off, electrostatic loading, and elastomeric stamps for transfer.

[0006] LEDs have a range of applications. A known optoelectronic device using LEDs is a display screen. An LED display screen typically includes an array of pixels, wherein each pixel is divided into three sub-pixels, each of which includes an LED. Each LED in a pixel emits one of red, green, or blue wavelengths of light. The power supply to the LED display screen can be controlled by a matrix of driver circuits, so that each LED has its own driver circuit that controls the current supplied to the LED. An example driver circuit includes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device may include a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS). In some cases, both NMOS and PMOS devices are provided together and are collectively referred to as complementary metal-oxide-semiconductor field-effect transistors (CMOS). Such devices are known in the art.

[0007] Issues to be resolved

[0008] When assembling LED display screens, it is common to place the LED assembly above the CMOS driver circuit to electrically connect the LEDs to the driver circuit. Until now, this assembly method has required matching the LED pixel design with the CMOS driver circuit. For example, each LED sub-pixel must be stacked and matched to the CMOS driver circuit so that the CMOS driver circuit and the LED count are the same. The CMOS driver circuit for each LED must also typically have the same pitch as the LED. Furthermore, the voltage and current specifications are determined by the individual CMOS driver circuits. As a result, LED display designs are significantly constrained.

[0009] It would be desirable to provide an improved photovoltaic device and method for making the same. Summary of the Invention

[0010] In the present invention, an electrical interconnect layer enables electrical interconnection between one or more driver circuits of a controller assembly and each photoemitter of a photoemitter assembly. The electrical interconnect layer includes at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer. By using such an electrical interconnect layer, the size, shape, and location of the interconnect are not limited by the size, shape, and location of either the photoemitter or the driver circuit.

[0011] The present invention is defined in the independent claims to which reference should now be made. Preferred or advantageous features of the invention are set out in the accompanying sub-claims.

[0012] In a first aspect of the present invention, there is provided an optoelectronic device comprising:

[0013] a photoelectric transmitter assembly comprising a plurality of photoelectric transmitters;

[0014] a controller assembly including a plurality of driver circuits for providing current to the plurality of photoemitters;

[0015] as well as

[0016] at least one redistribution layer or electrical interconnect layer disposed between the photoemitter assembly and the controller assembly, the electrical interconnect layer configured to provide electrical connections between one or more of the driver circuits and each of the plurality of photoemitters;

[0017] The at least one electrical interconnect layer includes at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer.

[0018] The at least one electrical interconnect layer may have a connection area that is larger than the electrical contact area of ​​the optoelectronic emitter or driver circuit to which the at least one electrical interconnect layer is connected. This has the advantage of increasing the effective area for connection, thereby making interconnection easier.

[0019] The conductive layer may include a plurality of interconnect points. At least one interconnect point may have a connection area that is larger than the electrical contact area of ​​the photoemitter or driver circuit to which it is connected. This has the advantage of improving the yield of the bonding or connection between the photoemitter assembly and the controller assembly. By increasing the size of the interconnect point's connection area, the ease and yield of bonding between the photoemitter and controller assembly are improved.

[0020] The location of at least one interconnect point can be laterally offset from the location of the opto-emitter or driver circuit to which it is connected. This has the advantage of enabling greater flexibility in the design of the opto-emitter and controller assembly circuitry, as the location of the interconnect point is not tied to the location of either the opto-emitter or the driver circuit.

[0021] At least one photoemitter may be connected to a plurality of driver circuits via an electrical interconnect layer. This has the advantage of improving the current output from one or more driver circuits and may achieve a higher current density difference between the at least one photoemitter and the other photoemitters.

[0022] Example 1

[0023] In a preferred first embodiment of the present invention, an electrical interconnect layer is formed on a photoemitter assembly comprising a plurality of photoemitters. When forming the electrical interconnect layer on the photoemitter assembly, the electrical interconnect layer may be deposited onto the photoemitter assembly. Thus, the electrical interconnect layer may have microstructures indicating that it has been deposited onto the photoemitter assembly.

[0024] The conductive layer may include a plurality of interconnect points for connecting to one or more driver circuits. Each interconnect point may be connected to a respective photoemitter from the plurality of photoemitters. Each interconnect point may have a connection area that is larger than the electrical contact area of ​​the photoemitter. By increasing the size of the interconnect point's connection area relative to the photoemitter's electrical contact area, the ease and yield of bonding to the photoemitters is improved.

[0025] At least one interconnection point may have a connection area that is larger than the electrical contact area of ​​the driver circuit. This has the advantage of making it easier to bond to the driver circuit.

[0026] At least one interconnect point may have a connection area that is larger than the electrical contact area of ​​the plurality of driver circuits. This allows a plurality of driver circuits to be connected to the interconnect point, which has the advantage of improving the current output from the driver circuits.

[0027] The insulator layer may be disposed between the plurality of photoelectric emitters and the plurality of interconnection points. The insulator layer may have a plurality of through holes to permit electrical interconnection between the plurality of photoelectric emitters and the plurality of interconnection points.

[0028] The electrical interconnect layer may include a first conductor layer and a second conductor layer. The second conductor layer may include a plurality of interconnect points for connecting to one or more driver circuits. The first conductor layer may be disposed between the second conductor layer and the plurality of photoemitters. Each interconnect point may be connected to a respective photoemitter in the plurality of photoemitters via the first conductor layer. This has the advantage of providing greater flexibility in the design process and manufacture of the interconnect.

[0029] At least one interconnection point may be laterally offset from its respective photoemitter.This has the advantage of enabling more flexibility in the design of the circuitry of the photoemitters so that the position of the interconnection point is not linked to the position of the photoemitters.

[0030] The first and second insulator layers may be disposed between the first and second conductor layers. The first and second insulator layers may be disposed between the second conductor layer and the plurality of photoemitters, respectively. The first and second insulator layers may have a plurality of through-holes to permit electrical interconnection between the plurality of photoemitters, the second conductor layer, and the plurality of interconnection points.

[0031] Example 2

[0032] In a preferred second embodiment of the present invention, an electrical interconnect layer is formed on a controller assembly that includes a plurality of driver circuits. When forming the electrical interconnect layer on the controller assembly, the electrical interconnect layer may be deposited onto the controller assembly. Thus, the electrical interconnect layer may have microstructures indicating that it has been deposited onto the controller assembly.

[0033] The conductor layer may include a plurality of interconnect points for connecting to each of the plurality of photoemitters. Each interconnect point may be connected to one or more of the driver circuits.

[0034] At least one interconnect point may have a connection area that is larger than the electrical contact area of ​​the driver circuit. By increasing the size of the interconnect point's connection area relative to the driver circuit's electrical contact area, ease and yield of bonding to the driver circuit are improved.

[0035] At least one interconnect point may have a connection area that is larger than the electrical contact area of ​​the plurality of driver circuits. This allows a plurality of driver circuits to be connected to the interconnect point, which has the advantage of improving the current output from the driver circuits.

[0036] Example 3

[0037] In a third preferred embodiment of the present invention, a first electrical interconnection layer is formed on a photoemitter assembly including photoemitters, and a second electrical interconnection layer is formed on a controller assembly including a plurality of driver circuits.

[0038] The first electrical interconnect layer may include a first conductor layer having a plurality of first interconnect points for connecting to one or more driver circuits. Each of the first interconnect points may be connected to a respective photoemitter of the plurality of photoemitters. The second electrical interconnect layer may include a second conductor layer having a plurality of second interconnect points for connecting to each of the plurality of photoemitters. Each of the second interconnect points may be connected to one or more of the driver circuits. The connection area and location of each of the first interconnect points may be the same as the connection area and location of a corresponding one of the second interconnect points. This embodiment has the advantage of improving the ease and yield of the connection between the photoemitter and the controller assembly.

[0039] Common characteristics

[0040] The following features apply to the first, second and third embodiments discussed above.

[0041] At least one of the plurality of driver circuits may include a CMOS driver circuit. The plurality of driver circuits may be a plurality of CMOS driver circuits.

[0042] The conductor layer may comprise any suitable conductive material. The conductor layer may comprise a metal or a metal alloy. The metal or metal alloy may be or may comprise one or more of the following: titanium, platinum, chromium, aluminum, nickel, gold.

[0043] The conductor layer may include any suitable transparent conductive material, including but not limited to indium tin oxide and graphene.

[0044] The insulator layer may comprise a dielectric, preferably one or more of the following: SiO2, SiN or SiNx.

[0045] The photoelectric emitter assembly may be an LED assembly comprising a plurality of LEDs. At least one of the plurality of LEDs may comprise:

[0046] n-doped part;

[0047] p-doped part;

[0048] a light emitting or active region located between the n-doped portion and the p-doped portion; and

[0049] Porous regions of Group III nitride materials.

[0050] The LEDs described in this application are preferably formed from III-V semiconductor materials, particularly III-nitride semiconductor materials. Preferably, the plurality of LEDs are formed from GaN semiconductor materials, although other III-nitride materials may be used. As discussed above, producing LEDs emitting at longer wavelengths (such as green, yellow, and red LEDs) on GaN-based platforms can be challenging because they require the use of high indium (In) content to reduce the band gap in the light-emitting or active region to an appropriate level for long-wavelength emission. The lattice parameter of the required InGaN active region is larger than that of the underlying GaN, and the resulting strain leads to the formation of defects in the material that act as non-radiative recombination centers, thereby degrading device performance.

[0051] The present inventors have discovered that using a porous region of a Group III nitride material in a semiconductor structure results in "strain relaxation," which reduces the strain in the layers of the semiconductor structure. By providing a porous region of a Group III nitride material in an LED, the n-doped portion, the light-emitting region, and the p-doped portion can be grown above the porous region with lower strain than would be possible without the porous region. The porous region can thus facilitate the incorporation of higher indium levels in the layers of the LED grown atop the porous region, which improves emission at longer wavelengths.

[0052] The present inventors have also discovered that growing an LED structure above a porous region of a Group III nitride material results in a significant shift in emission wavelength toward longer wavelengths compared to the same LED structure grown on a non-porous substrate. While the magnitude of the red shift can vary between different LED structures, in preferred embodiments, the porous region produces a typical wavelength red shift of between 15 nm and 80 nm, or more preferably between 15 nm and 50 nm, and more preferably between 30 nm and 50 nm, or between 30 nm and 40 nm.

[0053] The present invention thus allows conventional, easily manufactured LED structures to be shifted to longer wavelength emission, thereby enabling structures previously used as shorter wavelength (e.g., violet or blue) LEDs to be made into longer wavelength LEDs by incorporating porous regions into the structure. This advantageously allows LEDs to be made without many of the technical problems experienced in prior art designs.

[0054] The layers of the LED structure may be porosified by electrochemical etching as described in International Patent Applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0055] The n-type portion, light-emitting region, and p-type portion (which may be referred to as an LED structure) are preferably grown on a semiconductor template containing a porous region. The semiconductor template may also contain multiple layers of semiconductor material configured to provide a suitable base for the overgrowth of the LED structure. However, once the n-type region, light-emitting region, and p-type region have been grown on the template, both the LED structure and the template form part of the LED.

[0056] The porous region may have a thickness of at least 1 nm, preferably at least 10 nm, particularly preferably at least 50 nm. For example, the porous region may have a thickness between 1 nm and 10,000 nm.

[0057] The porous region may have a porosity between 1% and 99% porosity or between 10% and 80% porosity or between 20% and 70% porosity or between 30% and 60% porosity.The porosity of the porous region may be measured as the volume of all pores relative to the volume of the entire porous region.

[0058] Porosity has been found to have an impact on the magnitude of the wavelength shift caused by the porous region. In general, the higher the porosity %, the greater the wavelength shift of the LED compared to the same LED structure on a non-porous template.

[0059] The porous region is preferably formed of one of GaN, InGaN, AlGaN, AlInGaN or AlN.

[0060] The LED may include a connecting layer of a Group III nitride material positioned between the n-doped portion and the porous region. Preferably, the connecting layer has a thickness of at least 100 nm, although lesser or greater thicknesses may be employed. The connecting layer may preferably be one of GaN, InGaN, AlGaN, AlInGaN, or AlN.

[0061] The LED preferably includes a non-porous interlayer of a porous region of a Group III nitride material between the porous region and the light-emitting region. Because the porous region is preferably formed by electrochemical porosification of the non-porous layer of the Group III nitride material, the non-porous layer of the Group III nitride material typically forms a non-porous interlayer that remains on top of the porous region. The non-porous interlayer advantageously provides a smooth surface for overgrowth of other layers during fabrication.

[0062] Preferably, the LED comprises a non-porous intermediate layer of a Group III nitride material positioned between the porous region and the connecting layer. This may preferably be a non-porous layer through which the porous region is electrochemically etched.

[0063] The non-porous intermediate layer may preferably be one of GaN, InGaN, AlGaN, AlInGaN or AlN.

[0064] The porous region may be a porous layer, so that the light emitting diode comprises a porous layer of group III nitride material. Preferably, the porous region may be a continuous porous layer, for example, formed by a continuous porous group III nitride material layer.

[0065] The porous region may comprise a plurality of porous layers and, optionally, a plurality of non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, wherein the top surface of the stack defines the top of the porous region and the bottom surface of the stack defines the bottom of the porous region. A light-emitting region may be formed above the porous region of the stack of porous layers comprising a Group III nitride material.

[0066] In some embodiments, the light-emitting region is positioned above a stack of multiple porous layers of a Group III nitride material. Thus, the porous region may be a stack of layers of a Group III nitride material, at least some of which are porous, rather than a single porous layer of a Group III nitride material. The stack of porous layers may preferably be a stack of alternating porous and non-porous layers.

[0067] Alternatively, the porous region may be a layer of Group III nitride material containing one or more porous regions, such as one or more porous regions in an otherwise non-porous layer of Group III nitride material. In other words, the porous region need not be a continuous layer of porous material.

[0068] In a preferred embodiment, the porous region or layer may have a lateral dimension (width or length) equivalent to that of the substrate on which the porous layer or region is grown. For example, conventional substrate wafer sizes may have various sizes, such as 1 cm 2 Or 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches in diameter. However, by patterning one or more layers and / or depositing regions of different charge carrier concentrations within the same layer, smaller porous regions that do not span the entire substrate can be formed. The lateral dimensions of the porous layer or region can thus vary from about 1 / 10 of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself.

[0069] The n-doped portion preferably comprises an n-doped Group III nitride layer.

[0070] Preferably, the n-doped portion and / or the n-doped layer comprises n-GaN or n-InGaN, or a stack of alternating layers of n-GaN / n-InGaN, or a stack of alternating layers of n-InGaN / n-InGaN containing different concentrations of indium.

[0071] The n-doped portion may comprise a single crystalline n-doped Group III-nitride portion, preferably wherein the n-doped portion comprises a single crystalline n-doped Group III-nitride layer having a planar top surface.

[0072] The porous region and the layers between the porous region and the single crystalline n-doped Group III-nitride layer may be planar layers having respective top surfaces and respective bottom surfaces parallel to the planar top surface of the single crystalline n-doped Group III-nitride layer.

[0073] The light emitting layer preferably comprises one or more InGaN quantum wells, preferably 1 to 7 quantum wells.

[0074] The light emitting layer may be a nanostructured layer of InGaN including quantum structures such as quantum dots, fragmented quantum wells, or discontinuous quantum wells.

[0075] The light emitting layer and / or the quantum well preferably has a composition InxGa1-xN, wherein 0.07≤x≤0.35, preferably 0.12≤x≤0.30 or 0.22≤x≤0.30, particularly preferably 0.22≤x≤0.27.

[0076] The LED preferably includes a Group III nitride layer on the light emitting layer; and a Group III nitride barrier layer on the Group III nitride layer.

[0077] The III-nitride layer on the light-emitting layer can be referred to as a "cap layer." This cap layer serves to 1) increase the quantum confinement Stark effect for band bending, thereby producing a red shift and achieving longer wavelength emission, and 2) protect the high In percentage in the InGaN, ensuring that sufficient In percentage is incorporated to achieve long wavelengths and providing a larger barrier.

[0078] The LED preferably includes a cap layer of a Group III nitride material between the quantum well and the p-doped region. The cap layer can be GaN, InGaN, AlGaN, or AlN.

[0079] The LED preferably includes a barrier layer of a Group III nitride material between the quantum well and the p-doped region. The barrier layer can be GaN, InGaN, AlGaN, or AlN.

[0080] The p-doped region may include a p-doped Group III nitride layer and a p-doped aluminum gallium nitride layer positioned between the p-doped Group III nitride layer and the light-emitting region. The p-doped aluminum gallium nitride layer is preferably an electron-blocking layer (EBL) positioned between the cap layer and the p-type layer. The EBL contains 5 to 25 at% aluminum and preferably has a thickness between 10 and 50 nm.

[0081] The light-emitting area and / or LED may have lateral dimensions (width and length) greater than 100 μm and less than 300 μm. In this case, the LED may be referred to as a "small LED." In preferred embodiments, the small LED may be square or circular, or square with rounded corners, and have dimensions such as 300 μm x 300 μm, 200 μm x 200 μm, or 100 μm x 100 μm.

[0082] Alternatively, the light emitting area and / or LED may have lateral dimensions (width and length) less than 100 μm. In this case, the LED may be referred to as a "micro-LED." Micro-LEDs may preferably have lateral dimensions less than 80 μm, or 70 μm, or 60 μm, or 50 μm, or 30 μm, or 25 μm, or 20 μm, or 15 μm, or 10 μm, or 5 μm, or 3 μm, or 1 μm, or 500 nm, or 200 nm, or 100 nm, or 50 nm.

[0083] In a preferred embodiment, the micro-LED may be square or round or square with rounded corners and have a size such as 75μm×75μm, 50μm×50μm, 40μm×40μm, 30μm×30μm, 25μm×25μm, 20μm×20μm or 10μm×10μm or 5μm×5μm or 2μm×2μm or 1μm×1μm or 500nm×500nm or smaller.

[0084] The LEDs can optionally be circular, square, rectangular, hexagonal, or triangular in shape. In the case of irregularly shaped pixel designs, at least one dimension should fall within the dimensions defined above in order for the LED to be classified as a small or micro LED. For example, the width or diameter of the LED is preferably less than 100 μm, for the LED to be classified as a micro LED.

[0085] At least one electrical interconnect layer may be disposed on a side of the LED structure closest to the n-doped portion. The at least one electrical interconnect layer may be configured to provide an electrical connection between one or more of the driver circuits and the n-doped portion of each of the plurality of LEDs. The electrical interconnect layer may include a common cathode for each of the plurality of LEDs. Alternatively, the at least one electrical interconnect layer may be disposed on a side of the LED structure closest to the p-doped portion. The at least one electrical interconnect layer may be configured to provide an electrical connection between one or more of the driver circuits and the p-doped portion of each of the plurality of LEDs. The electrical interconnect layer may include a common anode for each of the plurality of LEDs.

[0086] The optoelectronic emitter assembly can be a laser assembly comprising a plurality of lasers. The plurality of lasers can be a plurality of vertical cavity surface emitting lasers. One, a plurality of, or each of the lasers can include a current confinement layer to increase carrier density.

[0087] The optoelectronic device may be provided in a display. The display may be a display screen, which may include a plurality of pixels. The plurality of optoelectronic emitters may be arranged in an array, that is, the plurality of optoelectronic emitters may be arranged in a grid or regular pattern.

[0088] In embodiments where the photoemitters are LEDs, the plurality of LEDs may include: at least one LED configured to emit at a red wavelength; at least one LED configured to emit at a green wavelength; and at least one LED configured to emit at a blue wavelength. The plurality of LEDs may include a plurality of LEDs having each of these colors. A pixel of the optoelectronic device may include at least one red LED, at least one green LED, and at least one blue LED. The red LED may be larger than the green and blue LEDs.

[0089] Manufacturing method

[0090] In a second aspect of the present invention, a method of manufacturing an optoelectronic device is provided. The method of manufacturing an optoelectronic device may be a method of integrating a photoelectric emitter assembly with a controller assembly including a plurality of driver circuits.

[0091] A second aspect of the present invention provides a method for manufacturing a photovoltaic device, comprising:

[0092] providing a photoelectric transmitter assembly comprising a plurality of photoelectric transmitters;

[0093] providing a controller assembly including a plurality of driver circuits for providing current to the plurality of photoemitters;

[0094] forming at least one electrical interconnect layer on the optoelectronic emitter assembly and / or the controller assembly, the at least one electrical interconnect layer comprising at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer; and

[0095] The photoemitter assembly and the controller assembly are connected to each other via the electrical interconnect layer such that the electrical interconnect layer is disposed between the photoemitter assembly and the controller assembly and provides electrical connection between one or more of the driver circuits and each of the plurality of photoemitters.

[0096] The optoelectronic device of the first aspect of the present invention is preferably a device manufactured by the method of the second aspect of the present invention. Any features described with respect to the first aspect are therefore applicable to the second aspect of the present invention, and vice versa.

[0097] In a second aspect of the method, the or at least one electrical interconnect layer may be formed on the optoelectronic emitter assembly. The or at least one electrical interconnect layer may be formed on the controller assembly.

[0098] The step of forming the interconnect layer may include:

[0099] depositing masking material;

[0100] patterning the masking material;

[0101] removing the patterned areas of the masking material;

[0102] Depositing the conductor layer material.

[0103] The steps may be performed in the order described. The shielding material may be an insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] Specific embodiments of the present invention will now be described with reference to the drawings, in which:

[0105] Figure 1 is a schematic cross-sectional illustration of a controller assembly for an optoelectronic device having an electrical interconnect layer according to an embodiment of the present invention;

[0106] Figure 2 and Figure 3 is a schematic cross-sectional illustration of an LED assembly for an optoelectronic device having an electrical interconnect layer according to an embodiment of the present invention;

[0107] Figures 4 to 6 is a schematic cross-sectional view of an optoelectronic device according to an embodiment of the present invention;

[0108] Figure 7 is a schematic cross-sectional illustration of an LED for an optoelectronic device according to an embodiment of the present invention; and

[0109] Figure 8 FIG. 1 is a flow chart illustrating a method for manufacturing a photovoltaic device according to an embodiment of the present invention.

[0110] It should be understood that the figures in this application are schematic and that some features have been omitted for clarity. Furthermore, features in the figures may not be drawn to scale. DETAILED DESCRIPTION

[0111] Detailed description of preferred embodiments

[0112] The following embodiments and figures provide examples of how the present invention may be implemented. They should not be considered limiting examples, but rather illustrate how various features of the electrical interconnect layers and other components of an optoelectronic device may be implemented. Other optional variations will become apparent upon reading the following description in light of the figures.

[0113] As used herein, an "electrical connection" may be a conductive path through which electrical current can flow. The electrical connection may be used to provide a supply of power to an emitting component such as an LED.

[0114] Figure 1 A schematic depiction of a controller assembly 1 including a controller for controlling a plurality of LEDs (not shown) in an optoelectronic device is shown. The controller assembly 1 is configured to connect to an optoelectronic emitter assembly, such as an LED assembly including a plurality of LEDs. For clarity, the LED assembly has been removed. Figure 1 Omitted, but shown in Figure 2 and Figure 3 middle. Figure 1 The controller assembly 1 includes a substrate 60 with a plurality of driver circuits 70 disposed on or above the substrate 60. The substrate 60 may be made of any suitable material, such as silicon, and may be part of a larger wafer containing the plurality of controller assemblies. The plurality of driver circuits 70 form part of the controller. Although Figure 1 Only four driver circuits are shown, but it will be appreciated that in practice the controller may include a very large number of driver circuits, i.e. at least one driver circuit for each LED to be driven. Figure 1 In the example of , each driver circuit comprises a CMOS device, and thus the controller is a CMOS-based controller. Electrical contacts 31 are disposed on or over each of the driver circuits 70 , and portions of insulating material 40 are disposed between each of the driver circuits 70 .

[0115] The controller assembly 1 has a redistribution layer (RDL) or electrical interconnect layer 100 formed on the controller assembly 1, that is, formed above the plurality of driver circuits 70 and electrical contacts 31. By being formed on the controller assembly 1, the electrical interconnect layer 100 has a microstructure that indicates that it has been formed on (e.g., deposited on) the controller assembly 1. Any known thin film deposition method can be used for such a deposition step. Known material characterization methods can be used to determine that the electrical interconnect layer 100 is formed on the controller assembly 1. Such known methods may include, for example, electron microscopy and defect identification. The electrical interconnect layer 100 can be formed using the manufacturing methods described herein.

[0116] Electrical interconnect layer 100 is configured to provide electrical connections between one or more driver circuits 70 and each of a plurality of LEDs (not shown). Specifically, when a controller assembly is connected to an LED assembly having a plurality of LEDs, electrical interconnect layer 100 is disposed between the LED assembly and the controller assembly, and is configured to provide electrical connections between one or more driver circuits 70 and each of the plurality of LEDs. When a controller assembly is connected to an LED assembly having a plurality of LEDs, electrical interconnect layer 100 may connect at least one LED to a plurality of driver circuits 70. Electrical connections between driver circuit 70 and the LEDs are made via conductor layers 110 and 130 of electrical interconnect layer 100.

[0117] Figure 1 Four driver circuits 70 are shown electrically connected to one another and assembled for connection to an LED using electrical interconnect layer 100. However, it should be understood that any suitable number of driver circuits 70 (such as two, three, four, or more than four driver circuits 70) can be electrically connected to one another for connection to an LED using electrical interconnect layer 100. By electrically connecting multiple driver circuits 70, increased power output can be provided to the LED. For example, two driver circuits 70 can provide a higher current to the LED than a single driver circuit 70.

[0118] Figure 1 , has a controller-facing surface 101 that is electrically connected to a plurality of driver circuits 70 through electrical contacts 31. Specifically, each driver circuit 70 is connected to a corresponding electrical contact 31, which in turn is connected to the controller-facing surface 101 of the electrical interconnect layer 100. It should be understood that the controller-facing surface 101 may alternatively be configured to connect directly to one or more driver circuits 70. At least one controller-facing surface 101 may be substantially planar.

[0119] Figure 1 The electrical interconnect layer 100 includes an interconnect point 102. The interconnect point 102 is configured to electrically connect to the LED when the LED assembly and the controller assembly 1 are connected to each other via the electrical interconnect layer 100 therebetween. The interconnect point 102 can be substantially planar. The interconnect point 102 is the distal (specifically, the distal-most) surface from the driver circuit 70. It should be understood that there may be more than one interconnect point 102. It should also be understood that the interconnect point 102 may not be the distal or distal-most surface from the driver circuit 70.

[0120] Figure 1 The electrical interconnect layer 100 in the embodiment has a connection area on a surface 101 facing the controller, which connection area is larger than the electrical contact area of ​​each driver circuit 70 to which the connection area is connected. Figure 1 The connection area in the controller is also larger than the electrical contact area of ​​the multiple driver circuits 70 to which the electrical interconnect layer 100 is connected. In other words, the connection area of ​​the controller-facing surface 101 of the electrical interconnect layer is sufficient to span multiple driver circuits 70. This allows multiple driver circuits 70 to be connected to the LED. Figure 1 In the embodiment shown in FIG, four driver circuits 70 can be connected to a single LED by contacting the interconnect point 102 with the LED assembly having the LED. In this configuration, current from the four driver circuits 70 can be provided to a single LED.

[0121] exist Figure 1 In the embodiment of FIG. 1 , interconnect point 102 is laterally offset from the location of each of the driver circuits 70 to which it is connected. Specifically, the horizontal location of interconnect point 102 is different from the horizontal location of each of the driver circuits 70. This has the effect of enabling driver circuit 70 to be electrically connected to an LED that is located at a different lateral location than the driver circuit 70. In other words, it provides greater flexibility in the design of the optoelectronic device.

[0122] The electrical interconnect layer 100 includes a plurality of conductor layers, namely, a first conductor layer 110 and a second conductor layer 130. An insulator layer 140 extends across at least a portion of the first conductor layer 110, i.e., between the first conductor layer 110 and the second conductor layer 130. Vias 120 are disposed in through-holes 105 in the insulator layer 140 to provide electrical connections between the first conductor layer 110 and the second conductor layer 130. The second conductor layer 130 has been patterned by etching away portions of the second conductor layer 130 to form interconnect points 102. Although Figure 1Although not shown, the first conductor layer 110 may also be patterned to provide electrical interconnection between any suitable number and configuration of driver circuits 70. The insulator layer 140 supports the second conductor layer 130 and provides electrical isolation between the first conductor layer 110 and the second conductor layer 130, except where the vias 120 pass through the insulating layer 140. The insulating layer 140 may also be patterned to provide electrical interconnection between the first conductor layer 110 and the second conductor layer 130 at desired locations.

[0123] Conductor layers 110 and 130 may comprise at least one of the following: a metal, a metal alloy, or indium tin oxide. The metal or metal alloy may be or include one or more of the following: titanium, platinum, chromium, aluminum, nickel, or gold. Insulator layer 140 may comprise a dielectric, preferably one or more of the following: SiO2, SiN, SiNx, or a polymer such as polyimide.

[0124] Although the electrical interconnect layer can be formed on the controller assembly, e.g. Figure 1 , but the electrical interconnect layer may additionally or alternatively be formed on the LED assembly. Figure 2 A schematic depiction of an LED assembly 2 is shown having an electrical interconnect layer 200 disposed thereon. The LED assembly 2 can be combined with a controller assembly including a plurality of driver circuits to provide an optoelectronic device. Figure 2 Omit the controller assembly.

[0125] Figure 2 The LED assembly 2 includes a substrate 10, which may be part of a larger carrier wafer containing multiple LED assemblies. The substrate 10 may be made of any suitable material, for example, the substrate may be made of a transparent material such as sapphire. A plurality of LEDs 20 are arranged on or above the substrate 10. Figure 2 In some embodiments, the plurality of LEDs 20 are substantially identical in cross-sectional shape and size. The plurality of LEDs 20 may be substantially identical in 3D shape, 3D size, material composition, chemical composition, layer structure, and / or wavelength range of light emitted at a particular applied voltage. Figure 2 The LEDs 20 in the array are arranged in a regular array. The plurality of LEDs 20 are arranged so as to have a gap of the same size between the LEDs 20. The LEDs 20 are laterally connected to the insulator layer 40.

[0126] Figure 2Each LED 20 in the interconnect layer 200 has an electrical contact 30. Each electrical contact 30 has substantially the same lateral size or area as the LED 20 over which it is positioned. It should be understood that the electrical contact 30 can differ in lateral size or area from the LED 20 to which it is connected. Alternatively, the electrical interconnect layer 200 can be directly connected to each LED 20.

[0127] The electrical interconnect layer 200 includes a conductor layer 212 and an insulator layer 40. The insulator layer 40 extends down to the substrate 10 and fills the spaces between the plurality of LEDs 20 to electrically isolate the LEDs 20. The insulator layer 40 has been patterned to provide a plurality of through-holes 45 in the region of the LEDs 20, through which the conductor layer 212 extends to form vias 211 and permit electrical interconnection between the plurality of LEDs 20 and the conductor layer 212.

[0128] The conductor layer 212 has been patterned, and portions of the conductor layer 212 have been etched away to leave only sections of the conductor layer 212. Each section of the conductor layer 212 of the electrical interconnect layer 200 includes a surface 201 facing the LEDs and an interconnection point 202. Each interconnection point 202 is electrically connected to a respective LED in the plurality of LEDs 20. When the LED assembly is connected to a controller assembly (not shown), each interconnection point 202 is configured to electrically connect to one or more driver circuits, wherein the electrical interconnect layer 200 is disposed between the LED assembly and the controller assembly. Each interconnection point 202 has a connection area that is larger than the electrical contact area of ​​the LEDs 20. Thus, the conductor layer 212 includes a plurality of interconnection points 202 for connecting to one or more driver circuits 70, wherein each interconnection point 202 is connected to a respective LED in the plurality of LEDs 20 and has a connection area that is larger than the electrical contact area of ​​the LEDs 20. The benefit of each interconnect point 202 having a connection area that is larger than the electrical contact area of ​​the LED 20 to which it is connected is that the LED 20 can be more easily connected to the driver circuit 70. When a bonding process is used to connect the LEDs 20, the yield of the bonding process can be improved because the interconnect point 202 has a larger area than its respective LED. In this bonding process, the interconnect point 202 forms the interface between the LED 20 and the component to which it is connected (e.g., the driver circuit). In particular, it forms a connection or bonding surface to which the controller assembly can be connected.

[0129] exist Figure 2 In the embodiment of FIG, the interconnect points 202 are arranged in an array such that each interconnect point 202 overlies and is aligned with its respective LED in the underlying array of LEDs 20. However, the electrical interconnect layer 200 may additionally or alternatively have a configuration in which each interconnect point is not aligned with its underlying LED, that is, at least some of the interconnect points are laterally displaced from their underlying LED. This configuration is shown in FIG. Figure 3 middle.

[0130] Figure 3 A schematic depiction of an LED assembly 3 is shown having an electrical interconnect layer 300 disposed on the LED assembly 3. The LED assembly 3 can be combined with a controller assembly including a plurality of driver circuits to provide an optoelectronic device. Figure 3 The LED assembly 3 has Figure 2 The LED assembly 2 has substantially the same structure as the LED assembly 2, except that the electrical interconnection layer 300 includes two conductor layers, namely, a first conductor layer 332 and a second conductor layer 334. Figure 2 and Figure 3 , similar reference numbers have been used to refer to components common to both figures. The second conductor layer 334 of the electrical interconnect layer 302 has been patterned by etching away portions of the layer to form a plurality of interconnect points 302. By using two conductor layers in the electrical interconnect layer 300, it is possible to vary the position, size, and spacing of the interconnect points 302 relative to their corresponding LEDs 20. It should be understood that the electrical interconnect layer 300 may have more than two conductor layers. For example, the electrical interconnect layer 300 may have three, four, five, or more than five conductor layers. In fact, any suitable number of conductor layers may be used.

[0131] exist Figure 3 In the embodiment of the present invention, the electrical interconnect layer 300 includes a first insulator layer 40 disposed on or above the plurality of LEDs 20 and between the LEDs and the first conductor layer 332. The first insulator layer 40 extends down to the substrate 10 and fills the space between the plurality of LEDs 20 to electrically isolate each LED 20. The first insulator layer 40 has been patterned to provide a plurality of through-holes 45 in the region of the LEDs 20 through which the first conductor layer 332 extends to form vias 331. The first conductor layer 332 has been patterned by etching away portions of the first conductor layer 332 to form a plurality of interconnect portions 335 extending laterally in the plane of the first conductor layer 332. The interconnect portions 335 may extend on either side of their respective vias 331, for example, for Figure 3 20 is shown as an interconnection portion 335 connected to the middle LED 20. Alternatively, the interconnection portion 335 may extend on one side of its respective guide hole 331, for example, Figure 3 3. The interconnects 335 shown in FIG. 3 are connected to the leftmost and rightmost LEDs 20. Furthermore, the interconnects 335 can extend different distances on one side of their respective vias 331. Multiple interconnects 335 are electrically connected to their respective LEDs via vias 331. Portions of dielectric material 41 are disposed between the interconnects 335 to electrically isolate them from one another.

[0132] Figure 3The electrical interconnect layer 300 further includes a second insulator layer 42 disposed on or above the first conductor layer 332 and between the first conductor layer 332 and the second conductor layer 334. The second insulator layer 42 has been patterned to provide a plurality of through-holes 45 in the region of the interconnect portion 335, through which the second conductor layer 334 extends to form vias 333. As discussed above, the second conductor layer 334 has been patterned by etching away portions of the layer to form a plurality of interconnect points 302. The interconnect points 302 are electrically connected to their respective interconnect portions 335 of the first conductor layer 332 via vias 333. Thus, an electrical path is established between the interconnect point 302 and the electrical contact of each LED 20 via vias 333, the interconnect portion 335, and the vias 331.

[0133] As discussed above, the vias 333 are formed in the region of the interconnect portion 335. The vias 333 can be aligned with the underlying vias 335 and the LEDs 20, for example, for connection to a Figure 3 20. In this configuration, the interconnect point 302 is substantially aligned with its underlying LED 20. Alternatively, the via 333 may be laterally offset from its respective underlying via 335 and LED 20, such as for Figure 3 333 connected to the leftmost and rightmost LEDs 20. In this configuration, the interconnect point 302 is laterally offset from its respective underlying LED, and the interconnect portion 335 of the first conductor layer 332 provides electrical connection throughout the distance of the via offset (i.e., the distance between via 331 and its respective laterally offset via 333). The laterally offset interconnect point 302 from its respective LED 20 means that the connection of the LED 20 is not limited to the actual location of the LED 20, but rather the interconnect points 302 can be fanned out to provide more space between the interconnect points 302 than between the LEDs 20, providing greater flexibility in the design of the display.

[0134] Figure 4 Schematic diagram of an optoelectronic device 4 . The optoelectronic device 4 includes an LED assembly 11 including a plurality of LEDs 20 , and a controller assembly 13 including a plurality of driver circuits 70 for providing current to the plurality of LEDs 20 .

[0135] Figure 4 The LED assembly 11 can be described in Figure 2 and Figure 3 The orientation in the substrate is achieved by forming a material layer on top of the substrate 10. Figure 4 The controller assembly 13 can Figure 1 In order to obtain the orientation described in , that is, by forming a material layer on top of the substrate 60. Figure 4In the optoelectronic device 4, the LED assembly 11 has been flipped 180 degrees from an orientation in which the substrate 10 is at the bottom of the LED assembly 11 to an orientation in which the substrate 10 is at the top of the LED assembly 11. After the LED assembly 11 has been flipped, it is aligned with, placed on, and fixedly attached to the controller assembly 13, with the electrical interconnect layer disposed between the LED assembly 11 and the controller assembly 13. It should be understood that, alternatively, instead of flipping the LED assembly 11, the controller assembly 13 can be flipped from an orientation in which the substrate 60 is at the bottom of the controller assembly 13 to an orientation in which the substrate 60 is at the top of the controller assembly 13, so that the controller assembly 13 is superimposed on the LED assembly 11 when the assemblies are connected to form the optoelectronic device.

[0136] exist Figure 4 In the embodiment of FIG. 4 , the optoelectronic device 4 includes a first electrical interconnection layer 410 and a second electrical interconnection layer 400 .

[0137] The first electrical interconnect layer 410 is formed on the LED assembly 11 including the LED 20. The first electrical interconnect layer 410 has Figure 2 . The first electrical interconnect layer 410 includes an insulator layer 440 and a conductor layer 411. The conductor layer 411 has been patterned to etch away specific portions to leave only sections of the conductor layer 411. The sections of the conductor layer 411 provide a plurality of first interconnect points 412 for connecting to one or more driver circuits 70 of the controller assembly 13 when the LED assembly 11 and the controller assembly 13 are connected. Each of the first interconnect points 412 is electrically connected to a respective LED in the plurality of LEDs 20 via a through-hole 445 formed in the insulator layer 440. The sections of the first electrical interconnect layer 410 are substantially identical to one another in shape, size, orientation, and material composition.

[0138] A second electrical interconnect layer 400 is formed on the controller assembly 13, which includes the plurality of driver circuits 70. The second electrical interconnect layer 400 includes a conductor layer 403 that has been patterned to etch away specific portions to leave sections 405, 406, 407 of a conductor layer 411 that provide a plurality of second interconnect points 402. The second interconnect points 402 are configured to connect one or more of the driver circuits 70 of the controller assembly 13 to the LEDs of the LED assembly 11 when the LED assembly 11 and the controller assembly 13 are connected. Figure 4 Each of the second interconnect points 402 shown in FIG has a connection area that is larger than the electrical contact area of ​​the driver circuit 70. Two of the interconnect points 402 each have a connection area that is larger than the electrical contact area of ​​the plurality of driver circuits 70. The second electrical interconnect layer 400 may also include an insulator layer (not shown). In another example, the second electrical interconnect layer 400 may have a structure similar to Figure 1 The structure of the controller assembly.

[0139] Although for the sake of clarity, Figure 4 , the first and second electrical interconnect layers 400, 410 are shown separated by a gap, but it should be understood that in the assembled optoelectronic device, they will be in contact with each other and fixedly attached (i.e., bonded) to each other. By being connected, the first and second electrical interconnect layers 400, 410 together form an electrical connection between one or more of the driver circuits 70 and each of the plurality of LEDs 20. When the LED assembly 11 and the controller assembly 13 are assembled to form the optoelectronic device, the LED assembly 11 and the controller assembly 13 are aligned so that the position of each of the first interconnect points 412 is the same as the position of each corresponding one of the second interconnect points 402. This allows electrical connection to be made between the first and second electrical interconnect layers 410, 400.

[0140] Figure 4 The LED assembly 11 shown in Figure 2 and Figure 3 The LED assembly shown in FIG. 2 differs in that it has multiple LEDs 20 of different sizes. Specifically, it has a first LED 20a, a second LED 20b, and a third LED 20c, all of which have different lateral areas, that is, different areas when viewed in plan. The third LED 20c is larger than the first LED 20a, and the second LED 20b is larger than the third LED 20c. The first LED 20a may be a blue LED, that is, it may emit light in the blue wavelength range. The second LED 20b may be a red LED, that is, it may emit light in the red wavelength range. The third LED 20c may be a green LED, that is, it may emit light in the green wavelength range.

[0141] The first LED 20a is connected to four driver circuits 70 via the electrical interconnect layers 400, 410. The second LED 20b is connected to one driver circuit 70 via the electrical interconnect layers 400, 410. The third LED 20c is connected to four driver circuits 70 via the electrical interconnect layers 400, 410. This difference in the number of driver circuits to which each LED is connected is facilitated by the difference in the sizes of the different sections 405, 406, 407 of the conductor layer 403 of the second electrical interconnect layer 400. Figure 4 The first section 405 on the left side of the second electrical interconnect layer 400 in FIG. 4 connects the four driver circuits 70 to the first LED 21 . Figure 4 A second section 406 in the middle of the second electrical interconnect layer 400 connects one driver circuit 70 to the second LED 22 . Figure 4The third section 407 on the right side of the second electrical interconnect layer 400 in FIG4 connects four driver circuits 70 to the third LED 23. Connecting different numbers of driver circuits 70 to individual LEDs 20 allows the amount of current delivered to the LED to be varied, such that more current is driven to LEDs 20 connected to more than one driver circuit 70 than to LEDs 20 connected to only one driver circuit 70. This allows for tailoring of the light emission properties of the LEDs, such as intensity and wavelength.

[0142] Figure 5 Schematic diagram of an optoelectronic device 5. The optoelectronic device 5 includes an LED assembly 15 including a plurality of LEDs 20; and a controller assembly 16 including a plurality of driver circuits 70 for providing current to the plurality of LEDs 20 via an electrical interconnection layer 500. The substrate 10 and the first, second, and third LEDs 20a, 20b, and 20c are connected to the substrate 10. Figure 4 The base body 10 and the first LED 20a, the second LED 20b and the third LED 20c are identical. Figure 4 、 Figure 5 and Figure 6 In the drawings, like reference numerals have been used to refer to elements that are common to both figures.

[0143] An electrical interconnect layer 500 is formed on the LED assembly 15 including the LEDs 20. The electrical interconnect layer 500 forms electrical connections between one or more of the driver circuits 70 and each of the plurality of LEDs 20. The electrical interconnect layer 500 includes an insulator layer 540 and a conductor layer 511. The conductor layer 511 has been patterned to etch away specific portions to leave only sections 505, 506, 507 of the conductor layer 511. The sections 505, 506, 507 of the conductor layer 511 each define an interconnection point 512. Figure 5 In the embodiment of FIG, each interconnection point 512 has a connection area that is larger than the electrical contact area of ​​the driver circuit 70 to which it is connected. Figure 5 In the embodiment of FIG. 5 , the interconnection points 512 of the first segment 505 and the third segment 507 have a connection area that is larger than the electrical contact area of ​​the multiple driver circuits 70 to which they are connected. The first LED 20 a is connected to four driver circuits 70 via the first segment 505 of the conductor layer 511 of the electrical interconnect layer 500. The second LED 20 b is connected to one driver circuit 70 via the second segment 506 of the conductor layer 511 of the electrical interconnect layer 500. The third LED 20 c is connected to four driver circuits 70 via the third segment 507 of the conductor layer 511 of the electrical interconnect layer 500.

[0144] Each driver circuit 70 is connected to an electrical contact 411, which is electrically connected to the electrical interconnect layer 500. Each electrical contact 411 is laterally larger than the driver circuit 70 to which it is connected. The electrical contacts 411 can be identical in shape, size, orientation, and material composition. It should be understood that the electrical contacts 411 may comprise interconnect points of a separate electrical interconnect layer formed on the controller assembly 16. The electrical interconnect layer may further include an insulator layer. It should be understood that, alternatively, each driver circuit 70 may be directly connected to the electrical interconnect layer 50.

[0145] Figure 6 is a schematic illustration of an optoelectronic device 6 , which includes an LED assembly 15 having a plurality of LEDs 20 , and a controller assembly 13 having a plurality of driver circuits 70 for providing current to the plurality of LEDs 20 . Figure 6 LED assembly 15 with Figure 5 The LED assembly 15 is the same as that of FIG. 1 and includes a first electrical interconnect layer 500 formed on the LED assembly 15 . Figure 6 The controller assembly 13 and Figure 4 The controller assembly 13 is identical to the controller assembly 13 and includes a second electrical interconnect layer 400 formed on the controller assembly 13.

[0146] The first electrical interconnect layer 500 and the second electrical interconnect layer 400 form electrical connections between one or more of the driver circuits 70 and each of the plurality of LEDs 20. The first electrical interconnect layer 500 has a first section 505, a second section 506, and a third section 507, each of which defines an interconnection point 512. The sections 505, 506, 507 and the interconnection points 512 of the first electrical interconnect layer 500 are as described with respect to FIG. Figure 5 The second electrical interconnect layer 400 has a first section 405, a second section 406, and a third section 407, each of which defines an interconnection point 402. The sections 405, 406, 407 of the second electrical interconnect layer 400 are as described with respect to FIG. Figure 4 described.

[0147] The size and location of the interconnect points 512 of the first electrical interconnect layer 500 match the size and location of the interconnect points 402 of the second electrical interconnect layer 400. The interconnect point 402 provided by the first section 405 of the second electrical interconnect layer 400 connects four driver circuits 70 to the interconnect point 512 provided by the first section 505 of the first electrical interconnect layer 500, which is connected to the first LED 20a. The interconnect point 402 provided by the second section 406 of the second electrical interconnect layer 400 connects one driver circuit 70 to the interconnect point 512 provided by the second section 506 of the first electrical interconnect layer 500, which is connected to the second LED 20b. The interconnect point 402 provided by the third section 407 of the second electrical interconnect layer 400 connects four driver circuits 70 to the interconnect point 512 provided by the third section 507 of the first electrical interconnect layer 500, which is connected to the third LED 20c.

[0148] Although Figures 4 to 6 A single pixel having red, green, and blue LEDs is shown in FIG, but it should be understood that the LED assembly may include a greater number of LEDs 20, and the controller assembly may include a greater number of driver circuits 70. It should also be understood that in FIG. Figures 4 to 6 The electrical interconnect layers formed on the LED assembly or controller assembly may have a greater number of interconnection points when appropriate.

[0149] The LEDs described herein may be manufactured according to any suitable method. One method of manufacturing the LED assemblies described herein is shown in FIG. Figure 7 middle. Figure 7 Schematic diagram of an LED assembly having a substrate, a porous region, a connecting layer 1001, an n-doped portion 1002, a light-emitting region 1003, an n-doped cap layer 1004, a p-doped portion 1006, a transparent conductive layer 1007, a passivation layer 1008, an electrical p-contact 1009, and an electrical n-contact 1010. The porous region may be a porous region of a Group III nitride material. The LED may be configured or manufactured to have any of the features of published application WO2022 / 029434. Figure 7 In an LED of this type, the electrical interconnect layer will be disposed on the anode or p-doped portion side of the LED. However, it will be appreciated that the electrical interconnect layer may be disposed on the cathode or n-doped portion side of the LED.

[0150] Methods for making optoelectronic devices are described in Figure 8 In a first step 71, the method comprises providing an LED assembly comprising a plurality of LEDs. The provided LED assembly may be as described with respect to Figures 2 to 7 Any one of the description.

[0151] In a second step 72, the method includes providing a controller assembly including a controller having a plurality of driver circuits for providing current to a plurality of LEDs of an LED assembly. The provided controller assembly may be as described with respect to Figure 1 and Figures 4 to 6 Any one of the description.

[0152] In a third step 73, the method includes forming at least one electrical interconnect layer on the LED assembly and / or the controller assembly, the at least one electrical interconnect layer including at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer.

[0153] In a fourth step 74, the method includes connecting the LED assembly and the controller assembly to each other via one or more electrical interconnect layers, such that the one or more electrical interconnect layers are configured between the LED assembly and the controller assembly and provide electrical connections between one or more of the driver circuits and each of the plurality of LEDs.

[0154] It should be understood that it is not necessary to Figure 8 In particular, the first step 71 to the third step 73 may be performed in any suitable order.

[0155] Prior to the fourth step 74, the LED assembly or controller assembly may be flipped from its manufactured orientation to its orientation for assembly into the optoelectronic device.

[0156] The third step 73 of forming the electrical interconnect layer may include: depositing a masking material; patterning the masking material; removing the patterned areas of the masking material; and depositing a conductor layer material. The masking material may be a polymer that is completely removed from the resulting optoelectronic device, or it may be an insulator layer of the electrical interconnect layer. For example, referring to Figure 2 , the masking material may be an insulator 40 that has been selectively etched to define the area where the guide holes 211 are deposited. Figure 3 , the masking material may be the first insulator layer 40 or the second insulator layer 42, wherein areas (ie, vias 45) are selectively etched to define areas where the vias 331, 333 are deposited. In this configuration, the insulator layer extends across at least a portion of the conductor layer.

[0157] It will be appreciated that there are a range of suitable methods for fabricating the optoelectronic devices described herein.

Claims

1. A photovoltaic device comprising: a photoelectric transmitter assembly comprising a plurality of photoelectric transmitters; a controller assembly including a plurality of driver circuits for providing current to the plurality of photoemitters; as well as at least one electrical interconnect layer disposed between the photoemitter assembly and the controller assembly, the electrical interconnect layer configured to provide electrical connection between one or more of the driver circuits and each of the plurality of photoemitters; Wherein the at least one electrical interconnect layer includes at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer.

2. The optoelectronic device of claim 1, wherein the at least one electrical interconnect layer has a connection area that is larger than an electrical contact area of ​​the optoelectronic emitter or driver circuit to which the at least one electrical interconnect layer is connected.

3. The optoelectronic device of claim 1 or 2, wherein the conductor layer comprises a plurality of interconnection points.

4. The optoelectronic device of claim 3, wherein the at least one interconnect point has a connection area that is larger than an electrical contact area of ​​the optoelectronic emitter or driver circuit to which the at least one interconnect point is connected.

5. An optoelectronic device as claimed in claim 3 or 4, wherein the location of at least one interconnect point is laterally offset from the location of the optoelectronic emitter or driver circuit to which the at least one interconnect point is connected.

6. An optoelectronic device as claimed in any preceding claim, wherein at least one optoelectronic emitter is connected to a plurality of driver circuits via the electrical interconnect layer.

7. The optoelectronic device of claim 1, wherein the electrical interconnect layer is formed on the optoelectronic emitter assembly comprising the plurality of optoelectronic emitters.

8. The optoelectronic device of claim 7 , wherein the conductor layer comprises a plurality of interconnection points for connecting to one or more driver circuits, wherein each interconnection point is connected to a respective photoemitter of the plurality of photoemitters and has a connection area that is larger than an electrical contact area of ​​the photoemitter.

9. The optoelectronic device of claim 7, wherein at least one interconnection point has a connection area that is larger than an electrical contact area of ​​the driver circuit.

10. The optoelectronic device of claim 9, wherein at least one interconnection point has a connection area that is larger than an electrical contact area of ​​the plurality of driver circuits.

11. The optoelectronic device of any one of claims 7 to 10, wherein the insulator layer is disposed between the plurality of optoelectronic emitters and the plurality of interconnection points and has a plurality of through holes to permit electrical interconnection between the plurality of optoelectronic emitters and the plurality of interconnection points.

12. The optoelectronic device of claim 7 , wherein the electrical interconnect layer comprises a first conductor layer and a second conductor layer, the second conductor layer comprising a plurality of interconnection points for connecting to one or more driver circuits, the first conductor layer being disposed between the second conductor layer and the plurality of photoemitters, each interconnection point being connected to a respective photoemitter of the plurality of photoemitters via the first conductor layer.

13. The optoelectronic device of claim 12, wherein at least one interconnect point is laterally offset from its respective optoelectronic emitter.

14. The optoelectronic device of claim 12 or 13, wherein a first insulator layer and a second insulator layer are respectively disposed between the first conductor layer and the second conductor layer and between the second conductor layer and the plurality of photoelectric emitters, and the first insulator layer and the second insulator layer have a plurality of through holes to allow electrical interconnection between the plurality of photoelectric emitters, the second conductor layer and the plurality of interconnection points.

15. The optoelectronic device of claim 1, wherein the electrical interconnect layer is formed on the controller assembly including the plurality of driver circuits.

16. The optoelectronic device of claim 15, wherein the conductor layer comprises a plurality of interconnect points for connecting to each of the plurality of photoemitters, wherein each interconnect point is connected to one or more of the driver circuits.

17. The optoelectronic device of claim 16, wherein at least one interconnection point has a connection area that is larger than an electrical contact area of ​​the driver circuit.

18. The optoelectronic device of claim 16, wherein at least one interconnection point has a connection area that is larger than an electrical contact area of ​​the plurality of driver circuits.

19. The optoelectronic device of claim 1, wherein a first electrical interconnect layer is formed on the optoelectronic emitter assembly including the optoelectronic emitters, and a second electrical interconnect layer is formed on the controller assembly including the plurality of driver circuits.

20. The optoelectronic device of claim 19, wherein the first electrical interconnect layer comprises a first conductor layer having a plurality of first interconnect points for connecting to one or more driver circuits, wherein each of the first interconnect points is connected to a respective photoemitter of the plurality of photoemitters, and the second electrical interconnect layer comprises a second conductor layer having a plurality of second interconnect points for connecting to each of the plurality of photoemitters, wherein each of the second interconnect points is connected to one or more of the driver circuits, wherein the connection area and position of each of the first interconnect points are the same as the connection area and position of a corresponding one of the second interconnect points.

21. The optoelectronic device of any preceding claim, wherein at least one of the plurality of driver circuits comprises a CMOS driver circuit.

22. The optoelectronic device of any preceding claim, wherein the conductor layer comprises at least one of the following: a metal, a metal alloy, indium tin oxide, graphene.

23. The optoelectronic device of claim 22, wherein the metal or metal alloy is or comprises one or more of the following: titanium, platinum, chromium, aluminum, nickel, gold.

24. The optoelectronic device of any preceding claim, wherein the insulator layer comprises a dielectric, preferably one or more of the following: SiO2, SiN or SiNx.

25. The optoelectronic device of any preceding claim, wherein the optoelectronic emitter assembly is an LED assembly comprising a plurality of LEDs.

26. The optoelectronic device of claim 25, wherein at least one of the plurality of LEDs comprises: n-doped part; p-doped part; a light emitting region located between the n-doped portion and the p-doped portion; and Porous regions of Group III nitride materials.

27. The optoelectronic device of any one of claims 1 to 24, wherein the optoelectronic emitter assembly is a laser assembly comprising a plurality of lasers.

28. The optoelectronic device of claim 27, wherein the plurality of lasers are a plurality of vertical cavity surface emitting lasers.

29. A display comprising an optoelectronic device as claimed in any preceding claim.

30. A method of manufacturing a photovoltaic device, comprising: providing a photoelectric transmitter assembly comprising a plurality of photoelectric transmitters; providing a controller assembly including a plurality of driver circuits for providing current to the plurality of photoemitters; forming at least one electrical interconnect layer on the optoelectronic emitter assembly and / or controller assembly, the at least one electrical interconnect layer comprising at least one conductor layer and at least one insulator layer extending across at least a portion of the conductor layer; as well as The photoemitter assembly and the controller assembly are connected to each other via the electrical interconnect layer such that the electrical interconnect layer is disposed between the photoemitter assembly and the controller assembly and provides electrical connection between one or more of the driver circuits and each of the plurality of photoemitters.

31. The method of claim 30, wherein the at least one electrical interconnect layer is formed on the optoelectronic emitter assembly.

32. The method of claim 30 or 31, wherein the at least one electrical interconnect layer is formed on the controller assembly.

33. The method of any one of claims 30 to 32, wherein the step of forming the interconnect layer comprises: depositing masking material; patterning the masking material; removing the patterned areas of the masking material; Depositing the conductor layer material.

34. The method of claim 33, wherein the masking material comprises the insulating layer.

Images