Capacitive scale, capacitive displacement sensor and method for producing a capacitive scale

Abstract

The application provides a capacitive scale, a capacitive displacement sensor and a preparation method of the capacitive scale. The capacitive scale comprises at least one capacitive group. The at least one capacitive group is arranged along a preset direction. Each capacitive group comprises a plurality of capacitive units arranged continuously along the preset direction. In each capacitive group, the capacitance values of the capacitive units form a monotonic sequence in turn, and in the monotonic sequence, any two adjacent capacitive values are not equal. By arranging the capacitive groups in the capacitive scale and making the capacitance values of the capacitive units in the capacitive groups form a monotonic sequence in turn, the monotonic characteristic makes the capacitive variation gradient on the capacitive scale have directionality, which can assist the dynamic calibration of the stepping direction and avoid misoperation.

Description

Technical Field

[0001] This application relates to the field of displacement measurement, and in particular to a capacitive scale, a capacitive displacement sensor, and a method for preparing the capacitive scale. Background Technology

[0002] In the field of precision machining, precision displacement (angle) sensors are an indispensable and important component, often referred to as the ruler of intelligent manufacturing. Their accuracy directly determines the leading position of the processing and manufacturing process.

[0003] A grid-type measuring device is a precision sensor that can accurately calibrate displacement (or rotation angle) and is widely used in the precision manufacturing industry.

[0004] However, current grid capacitance scales do not have step direction calibration and error prevention. Summary of the Invention

[0005] The main technical problem addressed by this application is to provide a capacitive scale, a capacitive displacement sensor, and a method for fabricating the capacitive scale, thereby solving the problem of how to calibrate the step direction of a grid-type capacitive scale in the prior art.

[0006] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a capacitance scale, comprising:

[0007] At least one capacitor bank is arranged along a preset direction; each capacitor bank includes multiple capacitor units arranged continuously along the preset direction.

[0008] In each capacitor bank, the capacitance values ​​of each capacitor unit form a monotonic sequence, and in the monotonic sequence, no two adjacent capacitance values ​​are equal.

[0009] Each capacitor unit includes a first electrode, a dielectric layer, and a second electrode stacked sequentially; in the capacitor unit, the second electrode and the first electrode are at least partially overlapped.

[0010] The capacitance scale has multiple intervals of equal width arranged continuously along a preset direction; the capacitance units are set in the intervals and are set one-to-one with the intervals.

[0011] The area of ​​the overlapping region between the first electrode and the corresponding second electrode is defined as the overlapping area; in each capacitor group, the overlapping areas of each capacitor unit sequentially form a first arithmetic sequence, and the first arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0012] The distance between the first electrode and the corresponding second electrode is defined as the plate distance; in each capacitor group, the plate distances of each capacitor unit form a second arithmetic sequence, and the second arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0013] In each capacitor bank, the dielectric constants of the dielectric layers of each capacitor unit form a third arithmetic sequence, and the third arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0014] There is one capacitor bank; the monotonic sequence in the capacitor bank is either an increasing arithmetic sequence or a decreasing arithmetic sequence.

[0015] The capacitor bank consists of multiple capacitor banks; the multiple capacitor banks are arranged along a preset direction, and in the preset direction, the monotonic sequence in each capacitor bank is an arithmetic sequence with consistent monotonicity.

[0016] The capacitance scale also includes a capacitance unit located between any adjacent capacitance groups; the capacitance unit located between adjacent capacitance groups is defined as a reference unit; the reference unit is located in the interval; the capacitance value of the reference unit is greater than the capacitance value of any capacitance unit in each capacitance group, or the capacitance value of the reference unit is less than the capacitance value of any capacitance unit in each capacitance group.

[0017] To address the aforementioned technical problems, the second technical solution provided in this application is: a capacitive displacement sensor, comprising:

[0018] The capacitance scale is the capacitance scale described above;

[0019] The counter, relative to the capacitance scale, is used to detect changes in capacitance on the capacitance scale and output displacement data.

[0020] To address the aforementioned technical problems, the third technical solution provided in this application is: a method for preparing a capacitance scale, comprising:

[0021] At least one capacitor bank is fabricated on a substrate; the at least one capacitor bank is arranged along a predetermined direction.

[0022] The process of fabricating at least one capacitor bank on the substrate includes:

[0023] Multiple capacitor units are fabricated on a substrate; each capacitor group includes multiple capacitor units arranged continuously along a preset direction; in each capacitor group, the capacitance values ​​of each capacitor unit form a monotonic sequence, and in the monotonic sequence, any two adjacent capacitance values ​​are not equal.

[0024] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a capacitance scale, a capacitive displacement sensor, and a method for fabricating the capacitance scale. The capacitance scale includes at least one capacitor group. The at least one capacitor group is arranged along a preset direction; each capacitor group includes multiple capacitor units arranged continuously along the preset direction; wherein, in each capacitor group, the capacitance values ​​of each capacitor unit sequentially form a monotonic sequence, and in this monotonic sequence, any two adjacent capacitance values ​​are not equal. By setting capacitor groups in the capacitance scale and ensuring that the capacitance values ​​of each capacitor unit in the capacitor group sequentially form a monotonic sequence, the monotonicity gives the capacitance change gradient on the capacitance scale direction direction a directionality, which can assist in the dynamic calibration of the step direction and avoid misoperation (i.e., foolproof design). Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0026] Figure 1 This is a three-dimensional structural schematic diagram of the grid-type measuring device provided in the embodiments of this application;

[0027] Figure 2 This is a three-dimensional structural diagram of the grid-type scale provided in the embodiments of this application;

[0028] Figure 3 This is a schematic diagram of the structure of the grid-type measurement device provided in the embodiments of this application;

[0029] Figure 4 This is a schematic diagram of the structure of the first embodiment of the capacitance scale provided in this application;

[0030] Figure 5 This is a top-view structural diagram of the first embodiment of the capacitor unit in the capacitor scale provided in this application.

[0031] Figure 6 This is a top-view structural diagram of the second embodiment of the capacitor unit in the capacitor scale provided in this application.

[0032] Figure 7 This is a top-view structural diagram of the third embodiment of the capacitor unit in the capacitor scale provided in this application;

[0033] Figure 8 This is a schematic diagram of the structure of the second embodiment of the capacitance scale provided in this application;

[0034] Figure 9This is a schematic diagram of the third embodiment of the capacitance scale provided in this application;

[0035] Figure 10 This is a schematic diagram of the fourth embodiment of the capacitance scale provided in this application;

[0036] Figure 11 This is a schematic diagram of the fifth embodiment of the capacitance scale provided in this application;

[0037] Figure 12 This is a schematic diagram of the sixth embodiment of the capacitance scale provided in this application;

[0038] Figure 13 This is a structural schematic diagram of the seventh embodiment of the capacitance scale provided in this application;

[0039] Figure 14 This is a schematic diagram of the eighth embodiment of the capacitance scale provided in this application;

[0040] Figure 15 This is a structural schematic diagram of the ninth embodiment of the capacitance scale provided in this application;

[0041] Figure 16 This is a schematic diagram of the structure of an embodiment of the capacitive displacement sensor provided in this application;

[0042] Figure 17 A flowchart illustrating one embodiment of the method for preparing a capacitance scale provided in this application;

[0043] Figure 18 yes Figure 17 A flowchart illustrating an implementation method for step S10;

[0044] Figure 19 yes Figure 18 Schematic diagram of the structure corresponding to steps S11 to S14 in the middle section;

[0045] Figure 20 This is a flowchart illustrating step S15 of the embodiment provided in this application;

[0046] Figure 21 This is a schematic diagram of the structure corresponding to step S15;

[0047] Figure 22 This is a flowchart illustrating step S16 of the embodiment provided in this application;

[0048] Figure 23 This is a schematic diagram of the structure corresponding to step S16.

[0049] Explanation of icon numbers:

[0050] 1. Capacitance scale; 10. Interval; 11. Capacitor group; 111. First capacitor group; 112. Second capacitor group; 12. Capacitor unit; 121. First electrode; 1210. First lead; 1220. Second lead; 122. Second electrode; 123. Dielectric layer; 13. First conductive layer; 14. Dielectric material layer; 141. Slot; 15. Second conductive layer; 16. Insulating layer; 17. Substrate; 18. Reference unit; 2. Counter; 3. Capacitive displacement sensor; L, physical quantity; L1 / L2 / x; width; S0 / S1 / S2 / S3 / S4 / S5 / S6, capacitance value; C1 / C2 / C3 / C4 / C5 / C6 / C7 / C8 / C9, capacitance value. Detailed Implementation

[0051] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0052] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0055] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] Please see Figures 1 to 3 , Figure 1 This is a three-dimensional structural schematic diagram of the grid-type measuring device provided in the embodiments of this application. Figure 2 This is a three-dimensional structural diagram of the grid-type scale provided in the embodiments of this application. Figure 3 This is a schematic diagram of the structure of the grid-type measurement device provided in the embodiments of this application.

[0057] Generally, a grating measuring device consists of two parts: a grating scale and a counter, such as... Figure 1 As shown, the grating scale is marked with equal physical quantities L, which is a symmetrical scale. Traditional high-precision mechanical scales use equally spaced contrast substrates. Specifically, the grating scale includes alternating bright and dark substrates, with the width of the bright substrate being L2 and the width of the dark substrate being L1, where L = L1 + L2.

[0058] When the grating scale moves or rotates with the mechanical device, the number of times the equal physical quantity L repeats is N, which is captured by the counter, and the displacement X = L * N is calculated. However, the equal components L of the current equally divided scale grating are fixed values.

[0059] However, current equally spaced grid scales lack calibration and error-proofing functions for the step direction. In other words, they cannot determine whether the mechanical device is moving forward or backward because the counter's collection count N is non-directional. Figure 3 As shown. Furthermore, it lacks the ability to perform a "zeroing" calibration, meaning it cannot determine whether the mechanical device returns to "zero" after being reset.

[0060] Please see Figures 4 to 8 , Figure 4 This is a schematic diagram of the structure of the first embodiment of the capacitance scale provided in this application. Figure 5 This is a top-view structural diagram of the first embodiment of the capacitor unit in the capacitor scale provided in this application. Figure 6 This is a top-view structural diagram of the second embodiment of the capacitor unit in the capacitor scale provided in this application. Figure 7 This is a top-view structural diagram of the third embodiment of the capacitor unit in the capacitor scale provided in this application. Figure 8 This is a schematic diagram of the second embodiment of the capacitance scale provided in this application.

[0061] To address the aforementioned technical problems, this application provides a capacitance scale 1. The capacitance scale 1 includes at least one capacitor group 11. The at least one capacitor group 11 is arranged along a preset direction; each capacitor group 11 includes a plurality of capacitor units 12 arranged continuously along the preset direction; wherein, in each capacitor group 11, the capacitance values ​​of each capacitor unit 12 sequentially form a monotonic sequence, and in the monotonic sequence, any two adjacent capacitance values ​​are not equal.

[0062] By setting a capacitor group 11 in the capacitor scale 1, and making the capacitance values ​​of each capacitor unit 12 in the capacitor group 11 form a monotonic sequence, the monotonicity makes the capacitance change gradient on the capacitor scale 1 directional, which can assist in the dynamic calibration of the step direction and avoid misoperation (i.e., foolproof design).

[0063] A monotonic sequence can be either an arithmetic sequence or a non-arithmetic sequence; there are no strict restrictions here, and the choice should be made based on the actual needs.

[0064] The following explanation mainly uses a monotonic sequence as an arithmetic sequence as an example. In each capacitor group 11, the capacitance values ​​of each capacitor unit 12, arranged sequentially along a preset direction, form an arithmetic sequence.

[0065] There are no restrictions on the specific value of the common difference of the arithmetic sequence; it can be selected according to actual needs.

[0066] Each capacitor bank 11 includes at least two capacitor units 12.

[0067] In some embodiments, each capacitor unit 12 includes a first electrode 121, a dielectric layer 123, and a second electrode 122 stacked sequentially; in the capacitor unit 12, the second electrode 122 and the first electrode 121 are at least partially overlapped; the capacitance scale 1 has a plurality of intervals 10 arranged continuously along a preset direction and of equal width; the capacitor unit 12 is disposed in the intervals 10 and is disposed in a one-to-one correspondence with the intervals 10.

[0068] For example, the first electrode 121 in each capacitor cell 12 is made of the same material.

[0069] For example, the second electrodes 122 in each capacitor cell 12 are made of the same material.

[0070] One capacitor unit 12 acts as a parallel plate capacitor.

[0071] In each capacitor unit 12, the first electrode 121 and the second electrode 122 serve as the plates of a parallel plate capacitor, and the overlapping area of ​​the first electrode 121 and the second electrode 122 is the effective area of ​​the plates in the parallel plate capacitor.

[0072] The first electrode 121 is connected to a first voltage, and the second electrode 122 is connected to a second voltage. By controlling the first and second voltages, an electric field is established between the plates of the parallel plate capacitor, enabling the counter 2 to identify the capacitance value of the capacitor unit 12.

[0073] For example, in each capacitor bank 11, the voltage difference between the first electrode 121 and the second electrode 122 in the capacitor unit 12 is not 0.

[0074] In the preset direction, the width x of each interval 10 is equal, such that counter 2 (see...) Figure 16 The relative displacement between the counter 1 and the capacitor scale 1 can remain constant each time, so that the change in capacitance of the capacitor scale 1 is proportional to the relative displacement, thereby making the pulse signal or trigger interval of the counter 2 regular and reducing the complexity of signal processing (e.g., triggering a capacitor sampling once every time the width x of an interval 10 is moved).

[0075] The shape of each interval 10 can be different or the same; there are no restrictions here, and the choice can be made according to actual needs.

[0076] For example, each interval 10 has the same shape and size, and each interval 10 is a rectangle.

[0077] In other embodiments, the shapes of the intervals 10 are different, and / or the sizes of the intervals 10 are different. For example, in the direction parallel to the capacitor unit 12, the shape of the intervals 10 is rectangular, the width x of the intervals 10 is equal (i.e., the width is equal along the preset direction), and the lengths of the intervals 10 are unequal (i.e., the width is unequal along the direction perpendicular to the preset direction).

[0078] The capacitor units 12 are spaced apart to avoid electric field interference between the plates of adjacent capacitor units 12, thereby facilitating the counter 2 to collect the capacitance between each capacitor unit 12.

[0079] In some embodiments, the capacitor units 12 are not equidistantly spaced. For example, in a preset direction, the widths of the capacitor units 12 are different, and the positions of the capacitor units 12 within the corresponding interval 10 are the same (see...). Figure 4 and Figure 5 ).

[0080] For example, all capacitor cells 12 are located close to the same edge of the interval 10.

[0081] In other embodiments, capacitor unit 12 may be located in the middle of interval 10. The position of capacitor unit 12 within interval 10 is not limited here and can be selected according to actual needs.

[0082] In other embodiments, the capacitor units 12 are equidistantly spaced in a predetermined direction. For example, in the predetermined direction, the width of each capacitor unit 12 is the same, and the position of each capacitor unit 12 within the corresponding interval 10 is the same (see...). Figure 6 and Figure 7 ).

[0083] In the direction parallel to the capacitor scale 1, the shape of the capacitor unit 12 may be the same as or different from the shape of the interval 10. Also, the shape of each capacitor unit 12 in each capacitor group 11 may be the same or different. No restrictions are imposed here, and the selection is made according to actual needs.

[0084] For example, in the direction parallel to the capacitor scale 1, the shape of the capacitor cell 12 is the same as the shape of the interval 10, both being rectangular.

[0085] In some embodiments, the area of ​​the overlapping region between the first electrode 121 and the corresponding second electrode 122 is defined as the overlapping area; in each capacitor group 11, the overlapping areas of each capacitor unit 12 sequentially form a first arithmetic sequence, and the first arithmetic sequence is proportional to the corresponding monotonic sequence.

[0086] In each capacitor bank 11, the overlapping areas of each capacitor unit 12 sequentially form a first arithmetic sequence, and this first arithmetic sequence is proportional to the corresponding monotonic sequence. This can be understood as follows: in any capacitor bank 11, the overlapping areas of each capacitor unit 12 sequentially form a first arithmetic sequence, and the capacitance values ​​of each capacitor unit 12 sequentially form a first monotonic sequence. The first arithmetic sequence and the first monotonic sequence within the same capacitor bank 11 are set proportionally.

[0087] For example, the first arithmetic sequence is denoted as A = {a1, a2, ..., ak}.

[0088] The first monotonic sequence is denoted as B = {b1, b2, ..., bk}, where k is greater than 1.

[0089] The first arithmetic sequence and its corresponding first monotonic sequence have the same number of terms, which is k terms.

[0090] The first arithmetic sequence is an n-fold sequence (also called a multiple sequence) of the first monotonic sequence, i.e., A=n*B, that is, each term satisfies ai=n*bi (for all i=1,2,...,k).

[0091] In other words, the capacitance difference between each capacitor unit 12 is related to the overlapping area of ​​the capacitor units 12, and the overlapping area of ​​the capacitor units 12 determines the tolerance of the first arithmetic sequence.

[0092] The distance between the first electrode 121 and the corresponding second electrode 122 is defined as the plate distance.

[0093] In each capacitor bank 11, the distance between the plates of each capacitor unit 12 is equal, and the dielectric constant of the dielectric layer 123 of each capacitor unit 12 is equal, so as to ensure that the capacitance value of each capacitor unit 12 is determined by the overlapping area of ​​the capacitor units 12.

[0094] In some specific embodiments, such as Figure 4 As shown, in each capacitor group 11, the widths of each capacitor unit 12 along a preset direction form an arithmetic sequence. In each capacitor unit 12, the first electrode 121 and the corresponding second electrode 122 are completely overlapped, meaning the planar area of ​​the capacitor unit 12 is the same as the overlapping area. Specifically, in the direction parallel to the capacitor scale 1, each capacitor unit 12 is rectangular. The widths of the rectangles differ along the preset direction, but the lengths are the same.

[0095] In capacitor cell 12, the first electrode 121 and the second electrode 122 are completely overlapped, and a predetermined distance is maintained between them, ensuring that the capacitance value of capacitor cell 12 is determined solely by the area of ​​the electrode plates (i.e., the area of ​​the first electrode 121 or the second electrode 122). The capacitance difference is directly controlled by adjusting the width of the electrodes (i.e., the first electrode 121 or the second electrode 122) of each capacitor cell 12 arithmetically along a preset direction. This design simplifies the manufacturing process and improves the consistency of the capacitance gradient.

[0096] In other embodiments, in each capacitor bank 11, the width of each capacitor cell 12 along a predetermined direction can be a non-arithmetic sequence. Furthermore, in at least some capacitor cells 12, the first electrode 121 and the corresponding second electrode 122 are partially overlapped.

[0097] For example, the preset direction is the length direction of the capacitor scale 1.

[0098] For example, the capacitance scale 1 further includes a first conductive layer 13, a dielectric material layer 14, and a second conductive layer 15; the dielectric material layer 14 is at least partially located between the first conductive layer 13 and the second conductive layer 15; the first conductive layer 13 is used to form a first electrode 121, the second conductive layer 15 is used to form a second electrode 122; and the dielectric material layer 14 is used to form a dielectric layer 123 of the capacitor unit 12.

[0099] The first conductive layer 13 is patterned to form the first electrode 121, and the second conductive layer 15 is patterned to form the second electrode 122, so as to simplify the preparation process of the electrode plates in each capacitor unit 12.

[0100] For example, the first conductive layer 13, the dielectric material layer 14, and the second conductive layer 15 are stacked sequentially to maintain a predetermined spacing between them. This can be understood as the thickness of the dielectric material layer 14 located between the first conductive layer 13 and the second conductive layer 15 being the predetermined spacing, meaning the inter-plate spacing between each capacitor unit 12 is the same. Specifically, the first conductive layer 13 and the second conductive layer 15 are used to form the electrode plates of the capacitor unit 12, ensuring a predetermined spacing between the first electrode 121 and the second electrode 122 in each capacitor unit 12. Furthermore, this ensures that the dielectric constant of each capacitor unit 12 is the same, so that the capacitance difference between each capacitor unit 12 is mainly determined by the overlapping area of ​​each capacitor unit 12. The value of the predetermined spacing is not limited here and can be selected according to actual needs.

[0101] The materials and thicknesses of the first conductive layer 13 and the second conductive layer 15 are not limited here, and can be selected according to actual needs.

[0102] In some specific embodiments, the shapes of each capacitor unit 12 may be the same or different in the direction parallel to the capacitor scale 1.

[0103] The following example illustrates the concept of each capacitor bank 11 comprising three capacitor units 12. For instance, in the direction parallel to the capacitor scale 1, each capacitor unit 12 is rectangular in shape (see...). Figure 5 and Figure 6 For example, in the direction parallel to the capacitor scale 1, the shapes of each capacitor unit 12 are different (see...). Figure 7 ).

[0104] In some specific embodiments, the dimensions of each capacitor unit 12 may be the same or different.

[0105] For example, in the direction parallel to the capacitance scale 1, the shapes of each capacitor unit 12 are identical, but the dimensions of each capacitor unit 12 are different. The first electrode 121 and the second electrode 122 in each capacitor unit 12 are completely overlapped. The capacitance difference between each capacitor unit 12 is determined based on the difference in the overlapping area between each capacitor unit 12 (see...). Figure 4 ).

[0106] For example, in the direction parallel to the capacitance scale 1, the shapes and dimensions of each capacitor unit 12 are identical. The capacitance difference between each capacitor unit 12 is determined based on the difference in the overlapping area between them (see...). Figure 8 ).

[0107] There are no restrictions on the shape and size of each capacitor unit 12 here; they can be selected according to actual needs.

[0108] Please see Figure 4 , Figure 9 and Figure 10 , Figure 9 This is a schematic diagram of the third embodiment of the capacitance scale provided in this application. Figure 10 This is a schematic diagram of the fourth embodiment of the capacitance scale provided in this application.

[0109] In other embodiments, such as Figure 9 As shown, the distance between the first electrode 121 and the corresponding second electrode 122 is defined as the plate distance; in each capacitor group 11, the plate distances of each capacitor unit 12 form a second arithmetic sequence in sequence, and the second arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0110] The second arithmetic sequence is set in proportion to the corresponding monotonic sequence, that is, the second arithmetic sequence is a multiple sequence of the corresponding monotonic sequence in the same capacitor unit 12.

[0111] In each capacitor group 11, the overlapping area of ​​each capacitor unit 12 is equal, and the dielectric constant of the dielectric layer 123 of each capacitor unit 12 is equal, so as to ensure that the capacitance value of each capacitor unit 12 is determined by the inter-plate distance of the capacitor unit 12.

[0112] For example, the first electrode 121 of each capacitor unit 12 is formed by patterning the same conductive layer to simplify the fabrication process.

[0113] For example, the dielectric layer 123 of each capacitor unit 12 is made of the same material to ensure that the dielectric constant of the dielectric layer 123 of each capacitor unit 12 is the same.

[0114] For example, in each capacitor cell 12, the first electrode 121 and the second electrode 122 are completely overlapped. In other embodiments, the first electrode 121 and the second electrode 122 may be partially overlapped, as long as the overlap area of ​​each capacitor cell 12 is the same.

[0115] For example, each capacitor bank 11 includes three capacitor units 12. In a preset direction, the capacitance values ​​of the three capacitor units 12 arranged consecutively are represented as C1, C2, and C3, and form a first arithmetic sequence.

[0116] In some other embodiments, such as Figure 10 As shown, in each capacitor group 11, the dielectric constants of the dielectric layer 123 of each capacitor unit 12 form a third arithmetic sequence, and the third arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0117] The third arithmetic sequence is set in proportion to the corresponding monotonic sequence, that is, the third arithmetic sequence is a multiple sequence of the corresponding monotonic sequence in the same capacitor unit 12.

[0118] In each capacitor group 11, the overlapping area of ​​each capacitor unit 12 is equal, and the inter-plate distance of each capacitor unit 12 is equal, so as to ensure that the capacitance value of each capacitor unit 12 is determined by the dielectric constant of the dielectric layer 123 of the capacitor unit 12.

[0119] For example, the first electrode 121 of each capacitor unit 12 is formed by patterning the same conductive layer, and the second electrode 122 is formed by patterning the same conductive layer, so as to simplify the fabrication process.

[0120] For example, in each capacitor group 11, the dielectric layer 123 of each capacitor unit 12 is made of the same material, and the doping concentration of the dielectric layer 123 of each capacitor unit 12 is different, so as to ensure that the dielectric constant of the dielectric layer 123 of each capacitor unit 12 is the same.

[0121] In other embodiments, the dielectric layer 123 of each capacitor unit 12 in each capacitor bank 11 may be made of different materials.

[0122] In some embodiments, the capacitance scale 1 further includes a substrate 17 and an insulating layer 16; a first conductive layer 13, a dielectric material layer 14, a second conductive layer 15 and an insulating layer 16 are sequentially disposed on the substrate 17, the dielectric material layer 14 covers the first electrode 121 and fills the gap between the first electrodes 121; the insulating layer 16 covers the second conductive layer 15 and fills the gap between the second electrodes 122.

[0123] The dielectric material layer 14 covers the first electrode 121 and fills the gap between the first electrodes 121, so that in addition to forming the dielectric layer 123, the dielectric material layer 14 can also insulate the first electrodes 121 of each capacitor unit 12, which can simplify the fabrication of the capacitor unit 12.

[0124] There are no restrictions on the material and thickness of the insulation layer 16 here; they can be selected according to actual needs.

[0125] The side of the insulating layer 16 away from the substrate 17 is the working surface of the capacitance scale 1.

[0126] There is at least one capacitor group 11. The following explanation mainly takes the example that the overlapping areas of each capacitor unit 12 in each capacitor group 11 form a first arithmetic sequence, and the first arithmetic sequence is proportional to the corresponding monotonic sequence.

[0127] In some embodiments, such as Figure 4 As shown, capacitor group 11 is a single unit; the monotonic sequence in capacitor group 11 is either an increasing arithmetic sequence or a decreasing arithmetic sequence.

[0128] During the measurement process, a relative displacement occurs between the capacitance scale 1 and the counter 2. When the sequence of capacitance values received by the counter 2 includes a continuous subsequence whose monotonicity is consistent with that of the monotonic sequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the preset direction. When the sequence of capacitance values received by the counter 2 includes a continuous subsequence whose monotonicity is opposite to that of the monotonic sequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the opposite direction of the preset direction, thereby achieving direction calibration. When the sequence of capacitance values received by the counter 2 includes multiple continuous subsequences with opposite monotonicities; and / or when the sequence of capacitance values received by the counter 2 includes a constant subsequence, the measurement is abnormal, and the abnormal alarm function can be realized.

[0129] Consistent monotonicity means that the change trends of two sequences (or subsequences) are the same. For example, both of the two subsequences are increasing, or both of the two subsequences are decreasing.

[0130] Opposite monotonicity means that the change trends of two sequences (or subsequences) are opposite. For example, one of the two subsequences is increasing and the other is decreasing.

[0131] A constant subsequence refers to a continuous subsequence in which all the element values are the same.

[0132] Exemplarily, the capacitor bank 11 includes 9 capacitor units 12. In the preset direction, the capacitance values of the 9 continuously arranged capacitor units 12 are successively represented as C1, C2, C3, C4, C5, C6, C7, C8, C9, and form a monotonic sequence. In the preset direction, the overlapping areas of the 9 continuously arranged capacitor units 12 are successively represented as S1, S2, S3, S4, S5, S6, S7, S8, S9, and form a first arithmetic progression.

[0133] Specifically, when the monotonic sequence in the capacitor bank 11 is an increasing arithmetic progression, S1 < S2 < S3 < S4 < S5 < S6 < S7 < S8 < S9, and C1 < C2 < C3 < C4 < C5 < C6 < C7 < C8 < C9. During the measurement process, a relative displacement occurs between the capacitance scale 1 and the counter 2. When the sequence of capacitance values received by the counter 2 is an increasing subsequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the preset direction. When the sequence of capacitance values received by the counter 2 is a decreasing subsequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the opposite direction of the preset direction, thereby achieving direction calibration.

[0134] When the monotonic sequence in capacitor bank 11 is a decreasing arithmetic sequence, S1 > S2 > S3 > S4 > S5 > S6 > S7 > S8 > S9, C1 > C2 > C3 > C4 > C5 > C6 > C7 > C8 > C9. During the measurement process, the capacitance scale 1 and the counter 2 undergo relative displacement. When the capacitance value sequence received by the counter 2 is an increasing subsequence, it is determined that the counter 2 has shifted relative to the capacitance scale 1 in the opposite direction of the preset direction; when the capacitance value sequence received by the counter 2 is a decreasing subsequence, it is determined that the counter 2 has shifted relative to the capacitance scale 1 in the preset direction, thereby achieving direction calibration.

[0135] In response to the fact that the capacitance value sequence received by counter 2 includes both an increasing subsequence and a decreasing subsequence; and / or, when the capacitance value sequence received by counter 2 includes a constant subsequence, a measurement abnormality is detected, and an abnormality alarm function can be implemented.

[0136] Please see Figure 4 and Figure 11 , Figure 11 This is a schematic diagram of the fifth embodiment of the capacitance scale provided in this application.

[0137] In other embodiments, there are multiple capacitor groups 11; the multiple capacitor groups 11 are arranged along a preset direction, and in the preset direction, the monotonic sequence in each capacitor group 11 is an arithmetic sequence with consistent monotonicity.

[0138] In the preset direction, the monotonic sequence in each capacitor group 11 is an arithmetic sequence with consistent monotonicity, which means that in the preset direction, the monotonic sequence in each capacitor group 11 is either an increasing arithmetic sequence or the monotonic sequence in each capacitor group 11 is either a decreasing arithmetic sequence.

[0139] For example, multiple capacitor groups 11 are arranged continuously along a preset direction.

[0140] In some embodiments, such as Figure 11 As shown, all capacitor groups 11 have the same structure. Specifically, each capacitor group 11 includes the same number of capacitor units 12, and the monotonic sequence of each capacitor group 11 is the same. Each capacitor group 11 includes at least 3 capacitor units 12.

[0141] During measurement, the capacitance scale 1 and counter 2 undergo relative displacement. When the capacitance value sequence received by counter 2 includes a continuous subsequence of monotonic values, it is determined that counter 2 has shifted relative to capacitance scale 1 in a preset direction. When the capacitance value sequence received by counter 2 includes a reverse subsequence of monotonic values, it is determined that counter 2 has shifted relative to capacitance scale 1 in the opposite direction of the preset direction, thus achieving orientation calibration. When the capacitance value sequence received by counter 2 simultaneously includes both a continuous subsequence of monotonic values ​​and a reverse subsequence of monotonic values, a measurement anomaly is detected, triggering an alarm function.

[0142] A continuous subsequence is a sequence of consecutive elements selected from the original sequence in the original order. The elements in a continuous subsequence maintain their original order and do not skip any intermediate elements.

[0143] A reverse subsequence is a sequence of consecutive elements selected from the original sequence in the reverse order. For example, the reverse subsequence of a monotonic sequence is a sequence of consecutive elements selected from the monotonic sequence in the reverse order.

[0144] In this embodiment, each capacitor group 11 includes the same number of capacitor units 12, and the monotonic sequence of each capacitor group 11 is the same, which can simplify the manufacturing process and the determination procedure of the counter 2.

[0145] Please see Figure 4 , Figures 12 to 15 , Figure 12 This is a schematic diagram of the sixth embodiment of the capacitance scale provided in this application. Figure 13 This is a structural schematic diagram of the seventh embodiment of the capacitance scale provided in this application. Figure 14 This is a structural schematic diagram of the eighth embodiment of the capacitance scale provided in this application. Figure 15 This is a structural schematic diagram of the ninth embodiment of the capacitance scale provided in this application.

[0146] In other embodiments, capacitor bank 11 is divided into a first capacitor bank 111 and a second capacitor bank 112, which are arranged alternately along a predetermined direction. The monotonic sequence in the first capacitor bank 111 is different from the monotonic sequence in the second capacitor bank 112. For example, the number of capacitor cells 12 in the first capacitor bank 111 and the second capacitor bank 112 is the same, and / or, the tolerance of the monotonic sequence in the first capacitor bank 111 is different from the tolerance of the monotonic sequence in the second capacitor bank 112. Another example is that the number of capacitor cells 12 in the first capacitor bank 111 and the second capacitor bank 112 is the same, and the tolerance of the monotonic sequence in the first capacitor bank 111 is the same as the tolerance of the monotonic sequence in the second capacitor bank 112, and the values ​​in the monotonic sequence of the first capacitor bank 111 are different from the values ​​in the monotonic sequence of the second capacitor bank 112.

[0147] For example, each capacitor bank 11 includes at least two capacitor units 12.

[0148] The different monotonic sequences in capacitor bank 11 result in different methods for determining the displacement direction of counter 2.

[0149] In some embodiments, such as Figure 12 As shown, each capacitor bank 11 includes two capacitor units 12.

[0150] Define the monotonic sequence in the first capacitor bank 111 as the first sequence, and the monotonic sequence in the second capacitor bank 112 as the second sequence. The reverse of the first sequence is the first reverse sequence, and the reverse of the second sequence is the second reverse sequence. For example, as... Figure 6 As shown, the first sequence is C1, C2. The second sequence is C2, C3. The first inverse sequence is C2, C1. The second inverse sequence is C3, C2.

[0151] Specifically, during the measurement process, the capacitance scale 1 and the counter 2 undergo relative displacement. If the capacitance value sequence received by the counter 2 includes a continuous first sequence and a second sequence (e.g., C1, C2, C2, C3 or C2, C3, C1, C2), it is determined that the counter 2 has shifted relative to the capacitance scale 1 in a preset direction. If the capacitance value sequence received by the counter 2 includes a continuous first reverse sequence and a second reverse sequence (e.g., C2, C1, C3, C2 or C3, C2, C2, C1), it is determined that the counter 2 has shifted relative to the capacitance scale 1 in the opposite direction of the preset direction. If the capacitance value sequence received by the counter 2 includes both the second sequence and the first sequence, the measurement is abnormal.

[0152] In other embodiments, such as Figure 13 and Figure 14As shown, the first capacitor bank 111 includes at least two capacitor units 12, and the second capacitor bank 112 includes at least three capacitor units 12. The number of capacitor units 12 in the first capacitor bank 111 and the number of capacitor units 12 in the second capacitor bank 112 may be the same or different.

[0153] In each capacitor group 11, any continuous subsequence containing 3 capacitance values ​​is defined as the third sequence, and the reverse of the third sequence is defined as the fourth sequence.

[0154] Specifically, during the measurement process, if the capacitance scale 1 and the counter 2 are relatively displaced, and the counter 2 receives a capacitance value sequence that includes a third sequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in a preset direction; if the counter 2 receives a capacitance value sequence that includes a fourth sequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the opposite direction of the preset direction; if the counter 2 receives a capacitance value sequence that includes both the third and fourth sequences, the measurement is abnormal.

[0155] It should be understood that as the number of intervals 10 in the capacitance scale 1 increases, the overlapping area of ​​the capacitor units 12 set at the end along the preset direction may become very large, resulting in a short interval between adjacent capacitor units 12 set at the end along the preset direction, causing interference between the plates in the electric field, which is not conducive to the counter 2 collecting capacitance changes; and is not conducive to the equal width design of intervals 10 in the preset direction.

[0156] This embodiment of the application reduces the number of capacitor units 12 within a single capacitor group 11 by setting multiple capacitor groups 11, thereby reducing the constraint on the overlapping area of ​​the capacitor units 12 and facilitating the control of the spacing between the capacitor units 12, thus simplifying the manufacturing process. Furthermore, the arrangement of multiple capacitor groups 11 is applicable to capacitor scales 1 with a large number of intervals 10, thereby expanding the measurement range of the capacitor scale 1.

[0157] In some embodiments, such as Figure 15 As shown, the capacitance scale 1 also includes a capacitor unit 12 located between any adjacent capacitor groups 11; the capacitor unit 12 located between adjacent capacitor groups 11 is defined as a reference unit 18; the reference unit 18 is located in interval 10; the capacitance value of the reference unit 18 is greater than the capacitance value of any capacitor unit 12 in each capacitor group 11, or the capacitance value of the reference unit 18 is less than the capacitance value of any capacitor unit 12 in each capacitor group 11.

[0158] Reference unit 18 is located outside of capacitor group 11 and does not belong to capacitor group 11. The capacitance value of reference unit 18 is denoted as S0.

[0159] The interval 10 where the reference unit 18 is located is the zero interval, that is, the "zero point" of the capacitance scale 1.

[0160] When the capacitance value received by counter 2 is the capacitance of reference unit 18, it is determined that counter 2 returns to the "zero point" of capacitance scale 1; otherwise, it resets to zero.

[0161] There is only one reference unit 18, which ensures the uniqueness of the system's "zero point".

[0162] The capacitance value of the reference unit 18 is greater than the capacitance value of any capacitor unit 12 in each capacitor group 11, or the capacitance value of the reference unit 18 is less than the capacitance value of any capacitor unit 12 in each capacitor group 11, so as to ensure the uniqueness of the capacitance value of the reference unit 18 and guarantee the uniqueness of the system's "zero point".

[0163] For example, the voltage difference between the first electrode 121 and the second electrode 122 of the reference unit 18 is 0. At this time, the capacitance value of the reference unit 18 can be ignored, that is, the capacitance value of the reference unit 18 received by the counter 2 is 0.

[0164] In response to the capacitance value received by the reference unit 18, the counter 2 returns to the "zero point" of the capacitance scale 1. The method for determining the displacement direction of the counter 2 is described above and will not be repeated here.

[0165] The "zero point calibration" function can be achieved by setting the reference unit 18.

[0166] Please see Figure 16 , Figure 16 This is a schematic diagram of the structure of an embodiment of the capacitive displacement sensor provided in this application.

[0167] This application provides a capacitive displacement sensor 3. The capacitive displacement sensor 3 includes a capacitance scale 1 and a counter 2. The capacitance scale 1 is the capacitance scale 1 described above. The counter 2 is relative to the capacitance scale 1 and is used to detect changes in capacitance on the capacitance scale 1 and output displacement data.

[0168] Counter 2 receives the capacitance value of capacitor unit 12 on capacitor scale 1. The displacement is obtained by multiplying the number of times the capacitance value of capacitor unit 12 is received by the width x of interval 10. That is, X = x * N, where X represents the displacement and N represents the number of times the capacitance value of capacitor unit 12 is received.

[0169] The displacement direction of counter 2 is determined as described above.

[0170] Please see Figure 4 , Figure 11 , Figures 17 to 19 , Figure 17 A flowchart illustrating one embodiment of the method for preparing a capacitance scale provided in this application is shown. Figure 18 yes Figure 17A flowchart illustrating an implementation method for step S10. Figure 19 yes Figure 18 Schematic diagram of the structure corresponding to steps S11 to S14.

[0171] This application provides a method for preparing a capacitance scale, used to prepare the capacitance scale 1 described above.

[0172] Methods for preparing capacitance scales include:

[0173] S10: At least one capacitor group is prepared on a substrate; the at least one capacitor group is arranged along a preset direction; wherein, preparing at least one capacitor group on the substrate includes: preparing multiple capacitor units on the substrate; each capacitor group includes multiple capacitor units arranged continuously along the preset direction; in each capacitor group, the capacitance values ​​of each capacitor unit sequentially form a monotonic sequence, and in the monotonic sequence, any two adjacent capacitance values ​​are not equal.

[0174] In one specific embodiment, step S10 includes:

[0175] S11: Prepare a plurality of first electrodes arranged in a predetermined direction on a substrate.

[0176] Specifically, a plurality of equal-width intervals 10 are continuously arranged on the substrate 17 along a preset direction. The first electrode 121 is located within the interval 10 and is configured to correspond one-to-one with the interval 10.

[0177] In the preset direction, the width x of interval 10 is the same.

[0178] While fabricating the first electrode 121, a first lead 1210 is also fabricated. The first lead 1210 is connected to the first electrode 121 and is arranged in a one-to-one correspondence with the first electrode 121. The first electrode 121 is connected to an external power source through the first lead 1210.

[0179] S12: Prepare a dielectric material layer on the side of the first electrode away from the substrate; the dielectric material layer is used to form the dielectric layer, and the dielectric layer is set in a one-to-one correspondence with the first electrode.

[0180] Specifically, the dielectric material layer 14 covers the first electrode 121 and fills the gap between the first electrodes 121.

[0181] The surface of the dielectric material layer 14 away from the first electrode 121 is planarized so that a set distance is maintained between the first electrode 121 and the second electrode 122 through the dielectric material layer 14.

[0182] S13: A plurality of second electrodes arranged in a preset direction are prepared on the side of the dielectric material layer away from the substrate; the second electrodes are arranged in a one-to-one correspondence with the first electrodes; the first electrodes, the corresponding dielectric layers and the corresponding second electrodes constitute a capacitor unit, and the plurality of capacitor units arranged in succession constitute a capacitor group.

[0183] Specifically, the second electrode 122 is located within interval 10 and is arranged in a one-to-one correspondence with interval 10. The second electrode 122 and the corresponding first electrode 121 are arranged to overlap at least partially in a direction perpendicular to the substrate 17, such that the first electrode 121, the second electrode 122 and the dielectric layer 123 can form a parallel plate capacitor.

[0184] Simultaneously with the fabrication of the second electrode 122, a second lead 1220 is also fabricated. The second lead 1220 is connected to the second electrode 122 and is arranged in a one-to-one correspondence with the second electrode 122. The second electrode 122 is connected to an external power source through the second lead 1220.

[0185] The arrangement of capacitor unit 12 is determined based on the arrangement of capacitor group 11.

[0186] S14: An insulating layer is prepared on the side of the second electrode away from the substrate.

[0187] Specifically, the insulating layer 16 covers the second electrode 122 and fills the gap between the second electrode 122.

[0188] Please see Figure 4 , Figures 19 to 23 , Figure 20 This is a flowchart illustrating step S15 of the embodiment provided in this application. Figure 21 This is a structural diagram corresponding to step S15. Figure 22 This is a flowchart illustrating step S16 of the embodiment provided in this application. Figure 23 This is a schematic diagram of the structure corresponding to step S16.

[0189] In other implementations, such as Figure 10 , Figure 20 and Figure 21 As shown, the process between step S12 and step S13 also includes:

[0190] S15: Perform ion doping treatment on the dielectric material layer.

[0191] In each capacitor group 11, the dielectric layer 123 of each capacitor unit 12 has different ion doping and / or ion doping concentrations, so that the dielectric constants of the dielectric layer 123 of each capacitor unit 12 in each capacitor group 11 sequentially form a third arithmetic sequence, and the third arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0192] For example, in each capacitor group 11, the ion doping concentration of the dielectric layer 123 of each capacitor unit 12 is different.

[0193] In some other implementations, such as Figure 9 , Figure 20 and Figure 21 As shown, the process between step S12 and step S13 also includes:

[0194] S16: Multiple grooves with different depths are formed on the surface of the dielectric material layer, and the grooves are set one-to-one with the first electrode.

[0195] The groove 141 connects to the surface of the dielectric material layer 14 away from the first electrode 121.

[0196] In the subsequent step, namely step S13, the second electrode 122 is at least partially disposed in the slot 141, with each slot 122 corresponding to one of the slots 141, and covering the bottom wall of the corresponding slot 141, such that the distance between the bottom wall of the slot 141 and the corresponding first electrode 121 is the same as the distance between the second electrode 122 and the corresponding first electrode 121 located in the slot 141. That is, the distance between the bottom wall of the slot 141 and the corresponding first electrode 121 is the inter-plate spacing.

[0197] The second electrode 122 can be entirely located within the slot 141, or it can be partially located within the slot 141 and protrude from the surface of the dielectric material layer 14 away from the first electrode 121.

[0198] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0199] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A capacitive scale, characterized by The application relates to a capacitive scale, comprising: at least one capacitive group arranged along a preset direction; each capacitive group comprises a plurality of capacitive units arranged continuously along the preset direction; each capacitive unit comprises a first electrode, a dielectric layer and a second electrode arranged in sequence; in the capacitive unit, the second electrode is arranged at least partially overlapped with the first electrode; wherein in each capacitive group, the capacitance values of the capacitive units form a monotonic sequence in sequence, and in the monotonic sequence, any two adjacent capacitance values are not equal; wherein the area of the overlapping region between the first electrode and the corresponding second electrode is defined as an overlapping area, in each capacitive group, the overlapping areas of the capacitive units form a first arithmetic sequence in sequence, and the first arithmetic sequence is proportionally arranged with the corresponding monotonic sequence; or the distance between the first electrode and the corresponding second electrode is defined as a plate distance, in each capacitive group, the plate distances of the capacitive units form a second arithmetic sequence in sequence, and the second arithmetic sequence is proportionally arranged with the corresponding monotonic sequence; or in each capacitive group, the dielectric constant of the dielectric layer of the capacitive unit forms a third arithmetic sequence in sequence, and the third arithmetic sequence is proportionally arranged with the corresponding monotonic sequence.

2. The capacitive scale of claim 1, wherein, The capacitive scale has a plurality of intervals arranged continuously along the preset direction and with equal width; the capacitive units are arranged in the intervals and correspond to the intervals one by one.

3. Capacitive scale according to claim 1 or 2, characterized in that The capacitive group is one; the monotonic sequence in the capacitive group is an increasing arithmetic sequence or a decreasing arithmetic sequence.

4. The capacitive scale of claim 1 or 2, wherein The capacitive group is multiple; the multiple capacitive groups are arranged along the preset direction, and in the preset direction, the monotonic sequences in the capacitive groups are consistent in monotonicity.

5. The capacitive scale of claim 4, wherein, The capacitive scale further comprises a capacitive unit between any adjacent capacitive groups; the capacitive unit between the adjacent capacitive groups is defined as a reference unit; the reference unit is located in an interval. The capacitance value of the reference unit is greater than the capacitance value of any capacitive unit in each capacitive group, or the capacitance value of the reference unit is less than the capacitance value of any capacitive unit in each capacitive group.

6. A capacitive displacement sensor characterized by, The application relates to a capacitive scale, comprising: a capacitive scale, which is the capacitive scale in any one of claims 1 to 5; a counter, which is arranged opposite to the capacitive scale, is used for detecting capacitance change on the capacitive scale and outputting displacement data.

7. A method of manufacturing a capacitive scale, characterized by The application relates to a capacitive scale, comprising: preparing at least one capacitive group on a substrate; the at least one capacitive group is arranged along a preset direction; wherein the step of preparing at least one capacitive group on the substrate comprises: preparing a plurality of capacitive units on the substrate; each capacitive group comprises a plurality of capacitive units arranged continuously along the preset direction; in each capacitive group, the capacitance values of the capacitive units form a monotonic sequence in sequence, and in the monotonic sequence, any two adjacent capacitance values are not equal; each capacitive unit comprises a first electrode, a dielectric layer and a second electrode arranged in sequence; in the capacitive unit, the second electrode is arranged at least partially overlapped with the first electrode; Wherein, the area of the overlapping region between the first electrode and the corresponding second electrode is defined as an overlapping area, in each of the capacitor groups, the overlapping areas of the capacitor units successively form a first arithmetic sequence, and the first arithmetic sequence is proportionally arranged with the corresponding monotone sequence; or, The distance between the first electrode and the corresponding second electrode is defined as a plate distance, in each of the capacitor groups, the plate distances of the capacitor units successively form a second arithmetic sequence, and the second arithmetic sequence is proportionally arranged with the corresponding monotone sequence; or, In each of the capacitor groups, the dielectric constants of the dielectric layers of the capacitor units successively form a third arithmetic sequence, and the third arithmetic sequence is proportionally arranged with the corresponding monotone sequence.

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