A satellite-borne power supply chip surge protection test system and method

Abstract

The application discloses a kind of on-board power supply chip surge protection test system and method, it is related to surge protection test technical field, by surge waveform simulation monitoring module, in the test environment of well-built, the interference waveform in surge test process is accurately monitored, ensure the traceability of test source;Surge waveform quality determination and regulation module real-time acquisition and analysis waveform quality parameter, dynamically judge whether it satisfies test condition, can timely eliminate unqualified waveform, avoid invalid test, improve test efficiency;Chip test reliability grading module applies qualified surge waveform to the chip to be tested, collects and analyzes protection test process parameter, realizes the grading processing of test result;The system is designed by modularization, realizes the full-process standardization and precision of surge test, effectively guarantees the reliability and consistency of test data, provides strong support for the scientific evaluation of on-board power supply chip surge protection performance.

Description

Technical Field

[0001] This invention relates to the field of surge protection testing technology, and in particular to a surge protection testing system and method for spaceborne power chips. Background Technology

[0002] Current surge protection testing of spaceborne power chips mainly revolves around core dimensions such as surge suppression, test architecture, and environmental adaptation. In terms of protection design, a combination of NTC and MOSFET is used, along with dedicated integrated chips to achieve dynamic adjustment, which can reduce the peak surge current. In terms of the test system, a combined wave generator and high-precision acquisition equipment are used as the core, combined with electromagnetic shielding, isolation design, and an automated platform to support closed-loop adjustment of surge parameters and machine learning-assisted diagnosis. The test methods follow standards such as IEC and GJB, covering basic surge and environmental stress joint testing, and optimizing protection performance by combining load matching and failure analysis. For the spaceborne environment, the focus is on verifying radiation resistance and stability over a wide temperature range, using technologies such as aluminum nitride substrates to control junction temperature.

[0003] For example, Chinese invention patent CN107727980B discloses a test system for ultra-wideband pulse injection testing of surge protection devices. The proposed test system for ultra-wideband pulse injection testing includes a high-voltage sub-nanosecond pulse source to provide a pulse signal to the device under test (DUT). The high-voltage sub-nanosecond pulse source employs a 50-stage MARX circuit to provide a pulse signal with a rise time of 180 ps, ​​an amplitude of 3100 V, and a half-width at half-maximum (FWHM) of 300 ps to the DUT. The output of the high-voltage sub-nanosecond pulse source is connected to one end of a test fixture. The other end of the test fixture is connected to an oscilloscope via an attenuator and a coaxial cable. The high-voltage sub-nanosecond pulse source, coaxial cable, test fixture, and oscilloscope all have the same characteristic impedance of 50 Ω.

[0004] For example, Chinese invention patent with publication number CN120142794A discloses a surge testing method and a surge testing device, including: applying a surge waveform to a protection circuit; the protection circuit is used to constrain the output of the protection circuit within a safe range to protect against the surge waveform; the output of the protection circuit is detected to obtain the output waveform of the protection circuit; wherein the output waveform is used to determine the test result of the protection circuit, and the test result is used to reflect the protection result of the protection circuit against the surge waveform.

[0005] However, in the process of implementing the embodiments of this application, the above-mentioned technology has at least the following technical problems: due to the fluctuation of the characteristics of the surge generation module hardware (energy storage element, power amplifier, etc.), the change of load impedance and the environmental electromagnetic interference, the quality of the surge interference waveform is unstable; the test conditions are not strictly controlled, the chip preprocessing is not in place and the surge injection energy transfer efficiency is inconsistent, so the results cannot reflect the full-condition reliability of the spaceborne power chip. Summary of the Invention

[0006] To address the technical problems in existing technologies, such as fluctuations in the hardware characteristics of surge generation modules, unstable surge waveform quality due to load and electromagnetic interference, and inconsistent test conditions, chip preprocessing, and energy transfer efficiency, which prevent the results from reflecting the full-condition reliability of spaceborne power chips, this invention provides a surge protection testing system and method for spaceborne power chips. The technical solution is as follows:

[0007] On one hand, a surge protection testing system for spaceborne power chips is provided, comprising: a surge waveform simulation and monitoring module, used to monitor surge interference waveforms during surge testing in a pre-built test environment; a surge waveform quality judgment and adjustment module, used to acquire and analyze the quality parameters of the surge interference waveform in real time to determine whether the surge interference waveform meets the test conditions; and a chip test reliability grading module, used to apply surge interference waveforms that meet the test conditions to the spaceborne power chip under test for protection testing, collect and analyze the process parameters of the protection test, and thus grade the surge protection test results of the spaceborne power chip.

[0008] On the other hand, a surge protection test method for a spaceborne power chip is provided, including the following steps: S1. Based on the established test environment, monitor the surge interference waveform during the surge test process in the test environment; S2. Obtain the quality parameters of the surge interference waveform in real time, analyze the obtained surge interference waveform quality parameters, and thus determine whether the surge interference waveform meets the test conditions; S3. Apply the surge interference waveform that meets the test conditions to the spaceborne power chip under test for protection test, collect and analyze the process parameters of the protection test, and thus classify the surge protection test results of the spaceborne power chip.

[0009] One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0010] 1. This invention provides a surge protection testing system and method for spaceborne power chips, achieving standardization, automation, and precision throughout the entire surge protection testing process. From the simulation and monitoring of surge waveforms to quality judgment and adjustment, and then to chip protection testing and result grading, a complete closed loop is formed, effectively eliminating human error and environmental interference during the testing process, and significantly improving the reliability and consistency of test data. At the same time, the system can quickly screen out surge waveforms that meet the requirements, avoid invalid tests, significantly improve testing efficiency, and provide comprehensive and reliable technical support for the scientific evaluation of the surge protection performance of spaceborne power chips.

[0011] 2. Based on the established test environment, real-time monitoring of surge interference waveforms can accurately capture waveform changes during surge testing, ensuring the traceability of surge interference waveforms. Real-time monitoring can promptly detect waveform anomalies, providing original and accurate data for subsequent quality assessment, ensuring the effectiveness of testing from the source, and avoiding test deviations caused by waveform distortion.

[0012] 3. Real-time acquisition and analysis of surge interference waveform quality parameters enable rapid determination of whether the waveform meets test conditions; for waveforms that do not meet the conditions, timely adjustments can be made to ensure that the surge waveform applied to the chip conforms to test standards, reducing test result errors caused by waveform quality issues, improving test accuracy, avoiding invalid tests, and saving test resources.

[0013] 4. Strictly selecting surge waveforms that meet testing conditions and applying them to the chip under test (DUT) prevents interference from unqualified waveforms, ensuring consistency and standardization of test inputs and reducing result deviations caused by waveform differences. During protection testing, precise analysis and comprehensive acquisition of process parameters allow for complete recording of the chip's response data under surge impact, providing sufficient evidence for result analysis and avoiding misjudgments caused by missing key information. Furthermore, the standardized reliability grading process, employing unified evaluation standards and quantitative indicators, effectively eliminates the influence of subjective human judgment, making test results from different chips comparable and ensuring the objectivity of the grading results. Simultaneously, complete parameter recording and traceable grading logic facilitate subsequent review and verification of test results, further solidifying the reliability foundation of the test results and providing a solid guarantee for the accurate evaluation of the surge protection performance of spaceborne power chips. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This invention provides a schematic diagram of the connection of a satellite power chip surge protection test system module.

[0016] Figure 2 This invention provides a schematic flowchart of a surge protection test method for a spaceborne power chip, as shown in the embodiment of the invention.

[0017] Figure 3 This is a schematic diagram of the steps of the method for determining the quality of surge interference waveforms according to the present invention;

[0018] Figure 4 This is a schematic flowchart of the surge interference waveform fine-tuning method of the present invention;

[0019] Figure 5 This is a schematic diagram of the steps for classifying and processing surge protection test results according to the present invention.

[0020] Figure 6 This is a schematic diagram of the steps in the method for determining a change in reliability level according to the present invention;

[0021] Figure 7 This is a schematic flowchart of the method steps for re-evaluating the reliability of chip test results according to the present invention;

[0022] Figure 8 This is a schematic diagram illustrating the principle of surge protection testing and waveform analysis for the spaceborne power chip of the present invention. Figure 8 Part (a) shows the waveform after ideal surge suppression. Figure 8 Part (b) shows the surge waveform that is not suppressed or has failed to be suppressed. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or “connected,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0025] It should be noted that the terms "up", "down", "left", "right", "front", and "back" used in this invention are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0026] This invention provides a surge protection testing system and method for spaceborne power chips, such as... Figure 1 As shown in the figure, an embodiment of the present invention provides a surge protection test system for a spaceborne power chip, including: a surge waveform simulation and monitoring module, a surge waveform quality judgment and adjustment module, a chip test reliability grading module, and a test database.

[0027] The surge waveform simulation monitoring module and the surge waveform quality judgment and adjustment module are connected. The surge waveform quality judgment and adjustment module and the chip test reliability grading module are connected. The surge waveform simulation monitoring module, the surge waveform quality judgment and adjustment module, and the chip test reliability grading module are all connected to the test database. The aforementioned test database is used to store various parameters involved in a spaceborne power chip surge protection test system.

[0028] The surge waveform simulation and monitoring module is used to monitor surge interference waveforms during surge testing within the established test environment. The surge waveform quality judgment and adjustment module is used to acquire and analyze the quality parameters of the surge interference waveform in real time to determine whether the surge interference waveform meets the test conditions. The chip test reliability grading module is used to apply surge interference waveforms that meet the test conditions to the onboard power chip under test for protection testing, collect and analyze the process parameters of the protection test, and thus grade the surge protection test results of the onboard power chip.

[0029] The aforementioned established test environment refers to the standardized basic conditions built for surge protection testing of spaceborne power chips, encompassing three core elements: hardware, software, and environmental control. In terms of hardware, it is equipped with a calibrated surge generation module, high-speed monitoring equipment (such as an oscilloscope), a chip mounting platform (including a vacuum chamber), and impedance matching lines to ensure stable surge signal transmission. In terms of software, it integrates automated control programs, a data acquisition and analysis system, and a test database, storing preset thresholds and historical data to ensure accurate parameter calculation and judgment logic. In terms of environment, external interference is eliminated through electromagnetic shielding, temperature and humidity control, and grounding. This integrated platform provides a stable, controllable, and traceable operating foundation for modules such as surge waveform simulation monitoring, quality judgment and adjustment, and chip test reliability grading, ensuring the accuracy and consistency of the entire testing process.

[0030] In this embodiment, the process of determining whether the surge interference waveform meets the test conditions is as follows: analyze the obtained surge interference waveform quality parameters, obtain the surge interference waveform quality index, and compare it with the preset surge interference waveform quality threshold in the test database.

[0031] The surge interference waveform quality threshold mentioned above refers to the minimum value of the surge interference waveform quality index within the specified range.

[0032] If the surge interference waveform quality index is greater than or equal to the surge interference waveform quality threshold, the surge interference waveform is deemed to meet the test conditions. Simultaneously, the parameters of the surge interference waveform that meets the test conditions are fine-tuned to determine its stability. If the surge interference waveform quality index is less than the surge interference waveform quality threshold, the surge interference waveform is deemed not to meet the test conditions. Based on the surge interference waveform quality index and the surge interference waveform quality threshold, a surge quality deviation value is obtained. This deviation value is then matched with a trigger pulse amplitude amplification coefficient to increase the amplitude of the trigger pulse, enhancing the instantaneous excitation intensity on energy storage components in the surge generation module, such as high-voltage capacitors. This ensures rapid and sufficient release of stored energy, accelerates the conduction speed of the discharge circuit, reduces circuit delay, and makes the rise edge of the surge waveform steeper, thus reducing rise time deviation. It also avoids the problem of slow waveform oscillation due to insufficient trigger energy. Furthermore, a stable high-amplitude trigger pulse can reduce random fluctuations in the initial stage of the waveform, making the overshoot amplitude closer to the target value and reducing waveform distortion caused by inconsistent triggering. The initial oscillation is abnormal, thus improving the initial characteristics of the surge waveform from the source and laying the foundation for subsequent waveform stability. Based on the surge quality deviation value, the power amplification factor of the drive circuit is matched, thereby increasing the power of the drive circuit and enhancing the continuous energy supply capability to the surge generation module. On the one hand, higher drive power can compensate for loop losses, such as line resistance, ensuring that the peak amplitude of the surge waveform meets the design standard and avoiding amplitude reduction due to insufficient energy supply. On the other hand, stable drive power can precisely control the oscillation decay rate of the waveform—by adjusting the dynamic response of the power output, the oscillation amplitude of the waveform after overshoot decays according to a preset law, such as conforming to an exponential decay curve, reducing decay disorder caused by power fluctuations, such as sudden acceleration or deceleration. Furthermore, sufficient drive power can resist interference from external load changes, such as impedance fluctuations of the chip under test, maintaining the stability of the surge waveform throughout its duration, thereby improving the waveform's continuity characteristics and enhancing overall quality consistency. Simultaneously, historical operating data of the surge generation module is invoked to automatically recommend various parameter combinations.

[0033] The aforementioned acquisition of surge quality deviation value refers to subtracting the surge interference waveform quality index from the surge interference waveform quality threshold. The specific matching process for matching the trigger pulse amplitude amplification factor based on the surge quality deviation value is as follows: The test database stores the trigger pulse amplitude amplification factors corresponding to each surge quality deviation value interval. The obtained surge quality deviation value is input into the test database, which then matches the corresponding surge quality deviation value interval. The trigger pulse amplitude amplification factor corresponding to this interval is the required amplification factor. Multiplying the obtained trigger pulse amplitude amplification factor by the original trigger pulse amplitude yields the trigger pulse amplitude that needs to be adjusted. A trigger pulse amplitude amplification factor greater than 1 indicates that the trigger pulse amplitude needs to be increased by a certain factor.

[0034] The above-mentioned matching process for the power amplification factor of the drive circuit based on the surge quality deviation value is as follows: The test database stores the power amplification factor of the drive circuit corresponding to each surge quality deviation value interval. The obtained surge quality deviation value is input into the test database, and the test database can match the corresponding surge quality deviation value interval. The power amplification factor of the drive circuit corresponding to this interval is the required amplification factor. The obtained power amplification factor of the drive circuit is multiplied by the original power of the drive circuit, and the result is the power of the drive circuit that needs to be adjusted. The above-mentioned power amplification factor of the drive circuit is greater than 1, which indicates that the power of the drive circuit needs to be increased by a certain factor.

[0035] The aforementioned use of historical operating data from the surge generation module refers to the automatic recommendation of parameter combinations by analyzing the correlation between the current deviation value and historical non-compliance cases through machine learning algorithms, such as random forests, to shorten the parameter adjustment cycle. The automatically recommended parameter combinations refer to correction values ​​for energy storage voltage, gain correction values ​​for drive circuits, etc.

[0036] The surge interference waveform quality index is reacquired and marked as the surge quality reassessment index to determine whether to issue an early warning for the surge interference waveform.

[0037] In one specific embodiment, real-time monitoring of surge interference waveforms using a pre-built test environment enables precise capture of every change in the waveform during the test, thus ensuring the traceability of the surge interference waveform. Simultaneously, this real-time monitoring mechanism can promptly detect waveform anomalies, providing original and accurate data support for subsequent quality assessment. This ensures the effectiveness of the entire process from the source of testing and effectively avoids test deviations caused by waveform distortion.

[0038] In this embodiment, the surge interference waveform quality index is specifically analyzed as follows: the quality parameters of the surge interference waveform include the overshoot amplitude factor, the rising edge steepness factor, and the oscillation attenuation factor.

[0039] The overshoot amplitude factor described above represents the deviation relationship between the overshoot amplitude of the surge interference waveform and its corresponding reference value; the rising edge steepness factor described above represents the deviation relationship between the rising edge steepness of the surge interference waveform and its corresponding reference value; and the oscillation attenuation rate factor described above represents the deviation relationship between the oscillation attenuation rate of the surge interference waveform and its corresponding reference value.

[0040] In the test database, the influence intensity coefficients corresponding to the overshoot amplitude factor, rise edge steepness factor, and oscillation decay rate factor are set to quantify the contribution value of each factor to the surge interference waveform quality index. Finally, the surge interference waveform quality index is obtained by weighted summation of the contribution values ​​of each influence. The surge interference waveform quality index represents the quality level of the surge generated by the surge generation module. The specific evaluation method is as follows:

[0041] ;

[0042] ;

[0043] ;

[0044] ;

[0045] In the formula, SOI is the surge interference waveform quality index, OAF is the overshoot amplitude factor of the surge interference waveform, OA is the overshoot amplitude of the surge interference waveform, DOA is the preset reference overshoot amplitude in the test database, RSF is the rising edge steepness factor of the surge interference waveform, RS is the rising edge steepness of the surge interference waveform, DRS is the preset reference rising edge steepness in the test database, ODRF is the oscillation attenuation rate factor of the surge interference waveform, ODR is the oscillation attenuation rate of the surge interference waveform, DODR is the preset reference oscillation attenuation rate in the test database, gc is the action intensity coefficient corresponding to the preset overshoot amplitude factor in the test database, gh is the action intensity coefficient corresponding to the preset rising edge steepness factor in the test database, and gp is the action intensity coefficient corresponding to the preset oscillation attenuation rate factor in the test database.

[0046] It should be explained that the above-mentioned reference overshoot amplitude refers to the reference value of the overshoot amplitude within the specified range; the above-mentioned reference rising edge steepness refers to the reference value of the rising edge steepness within the specified range; and the above-mentioned reference oscillation decay rate refers to the reference value of the oscillation decay rate within the specified range.

[0047] The overshoot amplitude of the surge interference waveform refers to the additional amplitude value of the surge waveform exceeding the preset peak value after reaching the preset peak value. It is obtained by real-time acquisition of the instantaneous peak value of the waveform by the surge waveform simulation monitoring module, and the preset target peak value is subtracted from the maximum acquired instantaneous value. The rising edge steepness of the surge interference waveform refers to the speed at which the surge waveform rises from the initial value (e.g., 0) to the preset peak value. The shorter the time, the higher the steepness. It is obtained by recording the time interval of the waveform rising from the 10% peak value to the 90% peak value. The oscillation decay rate of the surge interference waveform refers to the rate at which the oscillation waveform generated by energy release or loop characteristics decays over time after the surge waveform reaches the peak value. It is obtained by calculating the peak ratio of adjacent oscillation periods after the peak value.

[0048] The steeper the rise edge, the shorter the rise time, the more rapid the energy release, and the easier it is to cause an increased overshoot amplitude; the larger the overshoot amplitude, the higher the initial surge energy, and the slower the subsequent oscillation decay, i.e., the lower the decay rate; the steeper the rise edge, the stronger the sudden energy release, the more violent the oscillation after overshoot and the slower the decay, i.e., the lower the decay rate.

[0049] The intensity coefficient corresponding to the overshoot amplitude factor mentioned above represents the degree of change in the surge interference waveform quality index when the factor changes by a unit; the intensity coefficient corresponding to the rising edge steepness factor mentioned above represents the degree of change in the surge interference waveform quality index when the factor changes by a unit; the intensity coefficient corresponding to the oscillation attenuation rate factor mentioned above represents the degree of change in the surge interference waveform quality index when the factor changes by a unit; the test database stores the mapping relationship between the overshoot amplitude factor and its corresponding intensity coefficient, the rising edge steepness factor and its corresponding intensity coefficient, and the oscillation attenuation rate factor and its corresponding intensity coefficient; for example, when the overshoot amplitude factor, rising edge steepness factor, and oscillation attenuation rate factor are input into the test database, the test database will generate the corresponding intensity coefficients for the overshoot amplitude factor, rising edge steepness factor, and oscillation attenuation rate factor based on preset mapping rules, and the numerical range of each intensity coefficient is strictly controlled between 0 and 1.

[0050] A larger overshoot amplitude factor means that the peak value of the waveform exceeds or falls below the reference standard more significantly. If the overshoot amplitude is too high, it may exceed the design impact resistance threshold of the chip under test, resulting in a distorted test scenario. If the overshoot amplitude is too low, it cannot simulate the impact intensity of a real surge, resulting in a lower surge interference waveform quality index. A larger rise edge steepness factor can lead to situations where the rise time is too long (insufficient steepness) or too short (excessive steepness). An excessively long rise time will cause the surge energy release rhythm to deviate from the real scenario, making it impossible to test the chip's response capability to rapid impacts. An excessively short rise time may cause the chip to be subjected to instantaneous stresses exceeding actual operating conditions, resulting in a lower surge interference waveform quality index. A larger oscillation decay rate factor can lead to energy release that is too fast or too slow. Too fast a release will result in insufficient surge impact time, making it impossible to test the chip's protection performance under long-term interference. Too slow a release will cause energy to remain on the chip for too long, potentially causing unnecessary cumulative damage. Both situations will lead to a decrease in the surge interference waveform quality index.

[0051] In a specific example embodiment, the surge quality threshold preset in the test database is 0.8, and the quality index ranges from 0 to 1. The closer the value is to 1, the better the waveform quality. If the surge interference waveform quality index obtained from the current analysis is 0.65, then the surge quality deviation value is equal to the surge quality threshold minus the current surge interference waveform quality index, that is, 0.8 minus 0.65, resulting in 0.15. The test database has a preset correspondence between the deviation value range and the coefficient. For example, if the deviation value is between 0.1 and 0.2, the trigger pulse amplitude amplification coefficient is 1.2. Since the current deviation value is 0.15, which falls within the 0.1 to 0.2 range, the amplification coefficient is matched to 1.2. If the original trigger pulse amplitude is 5V, the adjusted amplitude is 5V multiplied by 1.2, and the final result is 6V.

[0052] In this embodiment, the determination of whether to issue a warning for the surge interference waveform is as follows: the surge quality reassessment index is compared with the surge interference waveform quality threshold; if the surge quality reassessment index is greater than or equal to the surge interference waveform quality threshold, it is determined that no warning will be issued for the surge interference waveform, and the surge interference waveform parameters that meet the test conditions are fine-tuned to determine the stability of the surge interference waveform; if the surge quality reassessment index is less than the surge interference waveform quality threshold, it is determined that a warning will be issued for the surge interference waveform.

[0053] It should be explained that the aforementioned fine-tuning of surge interference waveform parameters that meet the test conditions refers to adjusting the surge interference waveform parameters, such as peak voltage, by a small margin without exceeding the upper or lower limit of the specified range. This achieves stability judgment of the surge interference waveform and avoids excessive fluctuations in parameters within the qualified range, which could lead to deviations in subsequent tests. The aforementioned early warning of surge interference waveforms refers to generating a real-time waveform comparison chart, marking the parameter ranges that exceed the deviation limit in red, such as overshoot peak segments, to visually display the waveform distortion location and assist in quickly locating the problem. The aforementioned small margins are usually controlled within ±1% to ±10%.

[0054] In one specific embodiment, by collecting and analyzing the quality parameters of the surge interference waveform, it is possible to quickly determine whether the waveform meets the test conditions. For waveforms that do not meet the conditions, adjustments can be made in a timely manner, thereby ensuring that the surge waveform applied to the chip conforms to the test standards, reducing test result errors caused by waveform quality issues, and improving test accuracy. At the same time, this process can also avoid invalid tests and save valuable test resources.

[0055] like Figure 3 The flowchart of the method for judging the quality of surge interference waveforms of the present invention is shown. The process begins with the established test environment. The surge generation module simulates the surge interference waveform according to preset parameters, analyzes its quality to obtain the surge interference waveform quality index. If the surge interference waveform quality index is greater than or equal to the surge interference waveform quality threshold, the surge is determined to meet the test conditions. If it is less than the surge interference waveform quality threshold, the trigger pulse amplitude is increased, the drive circuit power is enhanced, and the historical operating data of the surge generation module is called to automatically recommend parameter combinations and obtain the surge quality re-examination index. If the surge quality re-examination index is greater than or equal to the surge interference waveform quality threshold, the test conditions are determined to be met; otherwise, a surge interference waveform warning is issued.

[0056] In this embodiment, the stability of the surge interference waveform is determined by the following analysis process: the quality index of the fine-tuned surge interference waveform is obtained and marked as the surge interference waveform fine-tuning quality index. If the surge interference waveform fine-tuning quality index is greater than or equal to the surge interference waveform quality threshold, the surge interference waveform is determined to be stable. If the surge interference waveform fine-tuning quality index is less than the surge interference waveform quality threshold, the surge interference waveform is determined to be unstable, an early warning is issued to the surge generation module, and an instruction to check the linearity of the surge generation device is generated.

[0057] It should be explained that the aforementioned early warning for the surge generation module refers to sending the early warning information to the operation and maintenance platform; the aforementioned command to check the linearity of the surge generation equipment is directed to the surge generation equipment, and the command content usually includes checking the nonlinearity of the power amplifier, the temperature drift of the energy storage element, etc.

[0058] like Figure 4 The flowchart of the surge interference waveform fine-tuning method of the present invention is shown. After the test conditions are met, the surge interference waveform parameters are fine-tuned and the surge fine-tuning quality index is obtained. If the surge fine-tuning quality index is greater than or equal to the surge interference waveform quality threshold, the surge is determined to be stable, and the data is analyzed in real time to generate the chip test reliability index. Otherwise, the surge generation module is warned and an instruction to check the linearity of the equipment is generated.

[0059] In this embodiment, the surge protection test results of the spaceborne power chip are processed in a graded manner. The specific analysis process is as follows: the parameters of the protection test process are analyzed to obtain the chip test reliability index, which is then compared with the first reliability index and the second reliability index preset in the test database. It should be noted that the first reliability index is greater than the second reliability index.

[0060] The aforementioned first reliability index refers to the value used to classify reliability level 1 and level 2; the aforementioned second reliability index refers to the value used to classify reliability level 2 and level 3. If the chip test reliability index is greater than the first reliability index, the chip test result is marked as level 1 reliability, and the on-orbit stable operating time of the chip in the spaceborne environment is predicted. The aforementioned predicted on-orbit stable operating time of the chip in the spaceborne environment refers to the prediction of the on-orbit stable operating time of the chip in the spaceborne environment based on the test results of level 1 reliability, the accelerated aging test of qualified spaceborne power chips, and the parameter decay trend during the aging process, using the Weibull distribution model. The aforementioned accelerated aging test refers to repeated impacts of 1000 times under the condition of 1.2 times the rated surge energy.

[0061] If the chip test reliability index is less than or equal to the first reliability index and greater than or equal to the second reliability index, the chip test result is marked as Level 2 reliability, and the chip test process is optimized. If the chip test reliability index is less than the second reliability index, the chip test result is marked as Level 3 reliability, and the chip test process is improved. It should be noted that Level 1 reliability is superior to Level 2 reliability, and Level 2 reliability is superior to Level 3 reliability. The chip test reliability index is re-acquired and marked as the final chip test reliability value to determine whether to issue a warning regarding the reliability of the chip test result.

[0062] In one specific embodiment, qualified surge waveforms are rigorously selected before being applied to the chip to avoid interference from unqualified waveforms at the source, ensuring consistent and standardized test inputs and reducing result deviations. As shown in Table 1, the test data recording table records relevant data for a single surge impact test, covering three main categories: surge waveform parameters (input), chip response parameters (output), and environmental and system parameters. Surge waveform parameters (input) include surge peak voltage, surge rise time, surge half-peak time, and surge energy, used to characterize the input surge signal. Chip response parameters (output) record the transient voltage at the chip input port and the fluctuation amplitude of the chip output voltage, reflecting the chip's response under surge impact. Environmental and system parameters, including peak junction temperature, post-surge recovery time, leakage current change, ambient temperature, test circuit impedance, and data acquisition frequency, provide support for surge impact test analysis from environmental, system, and chip-specific perspectives. Multi-dimensional data comprehensively presents the chip and system performance during a single surge impact test. Accurate analysis of acquisition parameters and complete recording of chip response data provide sufficient evidence for analysis, avoiding omissions and misjudgments of key information. Standardized process grading, unified evaluation standards, and quantitative indicators eliminate subjective influences, ensuring comparable and objective results. Complete recording and grading logic ensure traceability, facilitating verification and consolidating the reliability of results, providing a solid guarantee for chip surge protection performance evaluation.

[0063] Table 1 Test Data Record Table

[0064]

[0065] like Figure 5 The flowchart of the surge protection test result classification processing method of the present invention is shown. If the chip test reliability index is greater than the first reliability index, it is marked as Level 1 reliability and the on-orbit stable operation time is predicted; if the chip test reliability index is between the first and second reliability indices, it is marked as Level 2 reliability and the surge injection phase deviation is reduced, while the final value of chip test reliability is obtained; if the chip test reliability index is less than the second reliability index, it is marked as Level 3 reliability and the cutoff frequency of the input filter network is increased, while the final value of chip test reliability is obtained.

[0066] In this embodiment, the process parameters of the protection test are analyzed. Specifically, the process parameters of the protection test include the impedance mutation rate factor of the surge injection point, the thermal gradient decay rate factor inside the chip after the surge, and the transient common-mode voltage factor between chip pins; and the comprehensive index of surge interference waveform quality is obtained.

[0067] The impedance mutation rate factor described above represents the ratio of the impedance mutation rate at the surge injection point to its corresponding threshold value; the thermal gradient decay rate factor described above represents the deviation relationship between the thermal gradient decay rate inside the chip after a surge and its corresponding reference value; the transient common-mode voltage factor described above represents the ratio of the transient common-mode voltage between chip pins to its corresponding threshold value; and the surge interference waveform quality comprehensive index described above refers to the surge interference waveform quality index of the surge interference waveform that finally meets the test conditions.

[0068] In the test database, the influence intensity coefficients of impedance mutation rate factor, thermal gradient decay rate factor, transient common-mode voltage factor, and surge interference waveform quality comprehensive index are set to quantify the contribution value of each factor to the chip test reliability index. Finally, the chip test reliability index is obtained by weighted summation of the contribution values ​​of each influence. The chip test reliability index refers to the reliability of the chip test results, and the specific evaluation method is as follows:

[0069] ;

[0070] ;

[0071] ;

[0072] ;

[0073] In the formula, CTRI is the chip test reliability index, SOI_Z is the surge interference waveform quality comprehensive index, ICRF is the impedance mutation rate factor at the surge injection point, ICR is the impedance mutation rate at the surge injection point, DICR is the preset defined impedance mutation rate in the test database, TGODF is the thermal gradient decay rate factor inside the chip after the surge, TGOD is the thermal gradient decay rate inside the chip after the surge, DTGOD is the preset reference thermal gradient decay rate in the test database, TCMVF is the transient common-mode voltage factor between chip pins, TCMV is the transient common-mode voltage between chip pins, DTCMV is the preset defined transient common-mode voltage in the test database, fp is the action intensity coefficient corresponding to the preset impedance mutation rate factor in the test database, fr is the action intensity coefficient corresponding to the preset thermal gradient decay rate factor in the test database, fw is the action intensity coefficient corresponding to the preset transient common-mode voltage factor in the test database, and fq is the action intensity coefficient corresponding to the preset surge interference waveform quality comprehensive index in the test database.

[0074] It should be explained that the impedance change rate defined above refers to the maximum value of the impedance change rate at the surge injection point within the specified range; the reference thermal gradient decay rate mentioned above refers to the reference value of the thermal gradient decay rate inside the chip after the surge; and the transient common-mode voltage defined above refers to the maximum value of the transient common-mode voltage between chip pins within the specified range.

[0075] The impedance change rate at the surge injection point refers to the rate of change of impedance value in a very short time when a surge signal is injected into the chip test circuit. It can be obtained by collecting the impedance values ​​before and after the injection point at the moment of surge injection and calculating the impedance change at the moment of injection divided by the time interval. The thermal gradient decay rate inside the chip after the surge refers to the rate of decay of the spatial temperature gradient inside the chip caused by the concentration of surge energy over time after the surge interference ends. After the surge ends, the temperature changes in different areas inside the chip are continuously monitored using infrared thermal imaging and other methods, and the decrease in thermal gradient per unit time is calculated. The transient common-mode voltage between chip pins refers to the instantaneous common-mode potential difference generated between each chip pin, such as the power supply pin, and the common reference ground, i.e., the test system ground, during the surge interference. It is obtained by synchronously collecting the voltage between each chip pin and the reference ground at the time of the surge using a high-speed oscilloscope and calculating the transient change of the voltage difference between the pins.

[0076] An increased impedance abrupt change rate at the surge injection point exacerbates energy transfer instability, leading to larger transient voltage fluctuations and increased transient common-mode voltage between chip pins. Simultaneously, unstable energy injection may cause uneven distribution of surge energy absorbed within the chip, increasing local heat accumulation and reducing the thermal gradient decay rate. When the transient common-mode voltage between chip pins increases, it is easily converted into additional heat through internal parasitic parameters such as resistance, exacerbating the temperature distribution differences within the chip and thus slowing down the thermal gradient decay rate.

[0077] The influence strength coefficients corresponding to the impedance mutation rate factor, as described above, represent the degree of change in the chip test reliability index when this factor changes by a unit; the influence strength coefficients corresponding to the thermal gradient decay rate factor, as described above, represent the degree of change in the chip test reliability index when this factor changes by a unit; the influence strength coefficients corresponding to the transient common-mode voltage factor, as described above, represent the degree of change in the chip test reliability index when this factor changes by a unit; and the influence strength coefficients corresponding to the surge interference waveform quality composite index, represent the degree of change in the chip test reliability index when this composite index changes by a unit. The test database stores the mapping relationship between the impedance mutation rate factor and its corresponding influence strength coefficient, and the mapping relationship between the thermal gradient decay rate factor and its corresponding influence strength coefficient. The mapping relationships between the action intensity coefficient, the transient common-mode voltage factor and its corresponding action intensity coefficient, and the surge interference waveform quality comprehensive index and its corresponding action intensity coefficient are established. For example, when the impedance mutation rate factor, thermal gradient decay rate factor, transient common-mode voltage factor, and surge interference waveform quality comprehensive index are input into the test database, the test database will generate the corresponding action intensity coefficients for the edge location error factor, the impedance mutation rate factor, the thermal gradient decay rate factor, the transient common-mode voltage factor, and the surge interference waveform quality comprehensive index based on the preset mapping rules. The numerical range of each action intensity coefficient is strictly controlled between 0 and 1.

[0078] A larger impedance mutation rate factor indicates that the actual mutation rate exceeds the acceptable range, the surge energy transfer is more unstable, and the risk of impact on the chip is higher. Therefore, the chip test reliability index decreases as the factor increases. A smaller thermal gradient decay rate factor indicates that the chip can quickly eliminate continuous thermal stress and avoid chronic damage caused by long-term temperature differences, while not exceeding the thermal shock tolerance threshold of the chip material, such as the thermal shock coefficient of silicon. Therefore, the chip test reliability index increases. A larger transient common-mode voltage factor indicates that the transient voltage between pins exceeds the safe range, which can easily cause internal circuit malfunctions or breakdowns. Therefore, the chip test reliability index decreases as the factor increases. A higher surge interference waveform quality comprehensive index indicates that the surge waveform is more in line with the test conditions, such as waveform parameters, energy transfer, and interference intensity are more controllable. The surge impact that the chip withstands can more accurately reflect its protection capability, and the reliability basis of the test results is more solid. Therefore, the chip test reliability index increases as the factor increases.

[0079] In this embodiment, the chip testing process is optimized. Specifically, the optimization process is as follows: based on the chip test reliability index and the first reliability index, a first reliability deviation value is obtained. Based on the first reliability deviation value, a surge injection phase deviation reduction amount is matched to reduce the surge injection phase deviation. Targeted matching of the phase deviation reduction amount can make the surge impact more consistent with the typical operating conditions in actual chip applications, such as surge interference under the target phase. The consistency between the test conditions and the real scenario is improved, avoiding over-testing or under-testing caused by phase deviation, and enhancing the accuracy of the results in characterizing the actual reliability of the chip.

[0080] The aforementioned acquisition of the first reliability deviation value refers to the result of subtracting the chip test reliability index from the first reliability index. The aforementioned matching of the surge injection phase deviation reduction based on the first reliability deviation value is specifically as follows: the test database stores the surge injection phase deviation reduction corresponding to each first reliability deviation value interval. The obtained first reliability deviation value is input into the test database, and the test database can match the corresponding surge injection phase deviation reduction, thereby reducing the surge injection phase deviation.

[0081] In a specific example embodiment, the test database presets a first reliability index of 0.9 and a second reliability index of 0.7. The reliability index ranges from 0 to 1, with higher values ​​indicating better reliability. Taking a chip under test as an example, its initial chip test reliability index is 0.85, which is in the second-level reliability range, and its reliability needs to be improved through optimization. Subtracting the chip test reliability index from the first reliability index, i.e., subtracting 0.85 from 0.9, yields a result of 0.05, which is the first reliability deviation value. The test database presets the correspondence between the deviation value range and the phase deviation reduction. For example, when the first reliability deviation value is between 0.03 and 0.07, the surge injection phase deviation reduction is 2°. Since the current first reliability deviation value of 0.05 belongs to this range, the matched phase deviation reduction is 2°.

[0082] The chip testing process is improved as follows: Based on the chip test reliability index and the second reliability index, a second reliability deviation value is obtained. Based on this second reliability deviation value, an amplification factor for the cutoff frequency of the input filter network is matched, thereby increasing the cutoff frequency of the chip's input filter network. On the one hand, increasing the cutoff frequency reduces excessive attenuation of high-frequency transient components in surges, making the surge signal applied to the chip closer to the interference characteristics in actual operating conditions, avoiding signal distortion caused by over-filtering, and improving the accuracy of the test in characterizing the chip's true surge resistance capability. On the other hand, by matching the adjustment factor with the second reliability deviation value, the cutoff frequency of the filter network can be precisely matched with the chip's anti-interference design target, reducing test dispersion caused by unstable filtering characteristics, avoiding misjudgments caused by "over-filtering masking defects" or "insufficient filtering introducing noise," ultimately making the test results more stable and reliable, providing a reliable basis for evaluating the chip's surge resistance performance.

[0083] The aforementioned acquisition of the second reliability deviation value refers to subtracting the chip test reliability index from the second reliability index. The specific matching process for determining the input filter network cutoff frequency amplification factor based on the second reliability deviation value is as follows: the test database stores the input filter network cutoff frequency amplification factors corresponding to each second reliability deviation value interval. The obtained second reliability deviation value is input into the test database, which then matches the corresponding second reliability deviation value interval. The input filter network cutoff frequency amplification factor corresponding to this interval is the required amplification factor. Multiplying the obtained input filter network cutoff frequency amplification factor by the original input filter network cutoff frequency yields the required input filter network cutoff frequency. An input filter network cutoff frequency amplification factor greater than 1 indicates the numerical value by which the input filter network cutoff frequency needs to be increased.

[0084] In this embodiment, the determination of whether to issue a warning regarding the reliability of the chip test results is as follows: The final value of the chip test reliability is compared with the first reliability index and the second reliability index to obtain different levels of reliability. Based on the changes in reliability at different levels, it is determined whether to issue a warning regarding the reliability of the chip test results. If the reliability changes from level two to level one or from level three to level one, it is determined that no warning will be issued regarding the reliability of the chip test results, and the on-orbit stable operation time of the chip in the spaceborne environment is predicted. If the reliability remains at level two or level three, or if the reliability changes from level two to level three, it is determined that a warning will be issued regarding the reliability of the chip test results. The aforementioned warning regarding the reliability of the chip test results refers to sending the warning information to the operation and maintenance platform.

[0085] like Figure 6The flowchart of the method for determining the change in reliability level of the present invention is shown. After obtaining the final value of chip test reliability, the method determines the change in reliability level based on the following: when the reliability level of level 2 or level 3 increases to level 1, no warning is issued and the on-orbit duration is predicted; when the reliability level is maintained at level 2, level 3, or level 2 reliability decreases to level 3, a reliability warning is issued; when the reliability level of level 3 increases to level 2, the chip test reliability improvement rate is calculated.

[0086] If the reliability is changed from Level 3 to Level 2, the chip test reliability improvement rate is obtained based on the final chip test reliability value and the chip test reliability index. A second-order amplification factor for the input filter network cutoff frequency is then matched based on this improvement rate, further increasing the chip's input filter network cutoff frequency. Simultaneously, the chip test reliability index is re-obtained and marked as the chip test reliability re-evaluation index. Obtaining the chip test reliability improvement rate refers to subtracting the chip test reliability index from the final chip test reliability value and then dividing the result by the chip test reliability index. The specific matching process for matching the second-order amplification factor for the input filter network cutoff frequency based on the chip test reliability improvement rate is as follows: The test database stores the second-order amplification factor of the input filter network cutoff frequency corresponding to the reliability improvement rate range of each chip test. The obtained chip test reliability improvement rate is input into the test database, which then matches the corresponding chip test reliability improvement rate range. The second-order amplification factor of the input filter network cutoff frequency corresponding to this range is the required second-order amplification factor. Multiplying the obtained second-order amplification factor of the input filter network cutoff frequency by the original input filter network cutoff frequency yields the required adjusted input filter network cutoff frequency. If the second-order amplification factor of the input filter network cutoff frequency is greater than 1, it indicates that the input filter network cutoff frequency needs to be further increased by a factor of 1.

[0087] The chip test reliability reassessment index is compared with the first reliability index and the second reliability index to obtain the reliability level result. If it is a level 1 reliability, it is determined that no warning will be issued for the reliability of the chip test results, and the on-orbit stable operation time of the chip in the space environment will be predicted. The above-mentioned method of obtaining different reliability levels is consistent with the previous analysis process of classifying the surge protection test results of the space-based power chip. If it is a level 2 or level 3 reliability, it is determined that a warning will be issued for the reliability of the chip test results, and the above-mentioned method of predicting the on-orbit stable operation time of the chip in the space environment is consistent with the previous method of predicting the on-orbit stable operation time of the chip in the space environment.

[0088] In one specific embodiment, the present invention provides a surge protection testing system for spaceborne power chips, achieving standardization, automation, and precision throughout the entire surge protection testing process. From the simulation and monitoring of surge waveforms to quality judgment and adjustment, and then to chip protection testing and result grading, a complete closed loop is formed, effectively eliminating human error and environmental interference during the testing process, and significantly improving the reliability and consistency of test data. At the same time, the system can quickly screen out surge waveforms that meet the requirements, avoid invalid tests, significantly improve testing efficiency, and provide comprehensive and reliable technical support for the scientific evaluation of the surge protection performance of spaceborne power chips.

[0089] like Figure 7 The flowchart of the chip test result reliability reassessment method of the present invention is shown. Based on the chip test reliability improvement rate, the cutoff frequency of the input filter network is further increased to obtain the chip test reliability reassessment index. If the reassessment is at level 1 reliability, no warning is given and the duration is predicted. If the reassessment is at level 2 or level 3 reliability, a warning is given, and the entire test process is finally completed.

[0090] Reference Figure 2 As shown, the second aspect of the present invention provides a surge protection test method for a spaceborne power chip, comprising: S1. Based on a completed test environment, monitoring the surge interference waveform during the surge test process in the test environment; S2. Real-time acquisition of the quality parameters of the surge interference waveform, analysis of the acquired surge interference waveform quality parameters, thereby determining whether the surge interference waveform meets the test conditions; S3. Applying the surge interference waveform that meets the test conditions to the spaceborne power chip under test for protection test, collecting and analyzing the process parameters of the protection test, thereby classifying the surge protection test results of the spaceborne power chip.

[0091] Reference Figure 8 The schematic diagram of the surge protection test and waveform analysis principle of the spaceborne power chip of this invention is shown. The left figure is the logic diagram of the surge protection test circuit, whose core components include surge waveform, protection circuit, and protected device. The surge waveform simulates transient high voltage or high current interference that may occur in the spaceborne environment, such as cosmic rays, equipment start-up and shutdown impacts, etc. The protection circuit is the core of the surge protection of the spaceborne power chip, and its function is to divert or suppress surge energy. The protected device is the power module in the actual spaceborne scenario, such as the spaceborne computer, sensors, etc., and its reliability under surge impact needs to be verified. Its working logic is: after the surge waveform is input, the protection circuit first absorbs the dangerous energy, and the remaining energy will reach the protected device, thereby verifying the protection effect of the protection circuit on the protected device. The core is to test the surge energy interception capability of the protection circuit. The right figure shows a comparison of surge waveform characteristics. Figure 8Part (a) shows the waveform after ideal surge suppression. It is characterized by stable amplitude and controllable duration, indicating that the protection circuit is working effectively, limiting the surge energy to a safe range, and the protected equipment can operate stably. Figure 8 Part (b) shows the surge waveform that is not suppressed or fails to be suppressed. It is characterized by abrupt amplitude changes, short duration but concentrated energy, indicating that the protection circuit has not effectively intercepted the surge energy. The protected equipment will be subjected to spike impact, which may lead to chip damage and performance degradation.

[0092] The following points need to be explained:

[0093] (1) The accompanying drawings of the embodiments of the present invention only involve the structures involved in the embodiments of the present invention. Other structures can refer to the general design.

[0094] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the invention, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0095] (3) Where there is no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other to obtain new embodiments.

[0096] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. The scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A system for testing a surge protection of a spaceborne power supply chip, characterized in that: Comprise the following modules: Surge waveform simulation monitoring module, for based on the test environment is completed, in the test environment, monitoring surge test process in the surge interference waveform; Surge waveform quality determination and adjustment module, for real-time acquisition of surge interference waveform quality parameters, analysis of the obtained surge interference waveform quality parameters, so as to determine whether the surge interference waveform meets the test conditions, the specific determination process is: analysis of the obtained surge interference waveform quality parameters, the quality index of surge interference waveform is obtained, and compared with the preset surge interference waveform quality threshold in the test database, if the quality index of surge interference waveform is greater than or equal to the quality threshold of surge interference waveform, it is judged that the surge interference waveform meets the test conditions, at the same time, the surge interference waveform parameters meeting the test conditions are fine tuned, so as to judge the stability of the surge interference waveform, if the quality index of surge interference waveform is less than the quality threshold of surge interference waveform, it is judged that the surge interference waveform does not meet the test conditions, based on the quality index of surge interference waveform and the quality threshold of surge interference waveform, the quality deviation value of surge is obtained, the trigger pulse amplitude increase coefficient is matched based on the quality deviation value of surge, so as to increase the amplitude of the trigger pulse, based on the quality deviation value of surge, the driving circuit power increase coefficient is matched, so as to increase the power of the driving circuit, at the same time, the historical operation data of the surge generation module is called, the parameter combination is automatically recommended, the quality index of surge interference waveform is reacquired, which is marked as the quality review index of surge, so as to determine whether the surge interference waveform is prewarned; The chip test reliability grading module is used for applying a surge interference waveform meeting a test condition to a satellite-borne power supply chip under test for protection test, collecting and analyzing process parameters of the protection test, thereby grading the satellite-borne power supply chip surge protection test result. The surge interference waveform quality index is analyzed in detail as follows: the quality parameters of the surge interference waveform include overshoot amplitude factor, rising edge steepness factor and oscillation damping rate factor of the surge interference waveform. The action intensity coefficients corresponding to the overshoot amplitude factor, the rising edge steepness factor and the oscillation damping rate factor are set in the test database, the influence contribution values of each factor on the surge interference waveform quality index are quantified, and finally the surge interference waveform quality index is obtained by weighting and comprehensively integrating each influence contribution value. The surge interference waveform quality index represents the quality degree of the surge generated by the surge generation module. The satellite-borne power supply chip surge protection test result is graded in detail as follows: the protection test process parameters are analyzed to obtain a chip test reliability index, which is compared with a first reliability index and a second reliability index preset in the test database. If the chip test reliability index is greater than the first reliability index, the chip test result is marked as first-level reliability, and the on-orbit stable working time of the chip in the satellite-borne environment is predicted. If the chip test reliability index is less than or equal to the first reliability index and greater than or equal to the second reliability index, the chip test result is marked as second-level reliability, and the chip test process is optimized. If the chip test reliability index is less than the second reliability index, the chip test result is marked as third-level reliability, and the chip test process is improved. The chip test reliability index is reacquired and marked as a final chip test reliability value, thereby determining whether to give a warning on the reliability of the chip test result. The process parameters of the protection test are analyzed in detail as follows: the process parameters of the protection test include impedance mutation rate factor of the surge injection point in the protection test process, thermal gradient decay rate factor inside the chip after the surge, and transient common-mode voltage factor between the chip pins. The surge interference waveform quality comprehensive index is obtained. The action intensity coefficients corresponding to the impedance mutation rate factor, the thermal gradient decay rate factor, the transient common-mode voltage factor and the surge interference waveform quality comprehensive index are set in the test database, the influence contribution values of each factor on the chip test reliability index are quantified, and finally the chip test reliability index is obtained by weighting and comprehensively integrating each influence contribution value. The chip test reliability index refers to the reliability degree of the chip test result.

2. The system for surge protection testing of a spaceborne power supply chip of claim 1, wherein: The determination of whether to give a warning on the surge interference waveform is performed in detail as follows: The surge quality review index is compared with a surge interference waveform quality threshold value. If the surge quality review index is greater than or equal to the surge interference waveform quality threshold value, it is determined not to give a warning on the surge interference waveform, and the surge interference waveform parameters meeting the test condition are fine-tuned, thereby determining the stability of the surge interference waveform. If the surge quality re-inspection index is less than the surge interference waveform quality threshold value, it is determined that the surge interference waveform is pre-warned.

3. The system for surge protection testing of a spaceborne power supply chip of claim 2, wherein: The stability of the surge interference waveform is determined, and the specific analysis process is: The fine-tuned surge interference waveform quality index is obtained and marked as the surge interference waveform fine-tuning quality index. If the surge interference waveform fine-tuning quality index is greater than or equal to the surge interference waveform quality threshold value, it is determined that the surge interference waveform has stability. If the surge interference waveform fine-tuning quality index is less than the surge interference waveform quality threshold value, it is determined that the surge interference waveform does not have stability, and the surge occurrence module is pre-warned, and an instruction for troubleshooting the linearity of the surge occurrence device is generated.

4. The system for surge protection testing of a space-borne power supply chip of claim 1, wherein: The chip test process is optimized, and the specific optimization process is: Based on the chip test reliability index and the first reliability index, a first reliability deviation value is obtained, and a surge injection phase deviation reduction amount is matched based on the first reliability deviation value, thereby reducing the phase deviation of the surge injection; The chip test process is improved, and the specific improvement process is: based on the chip test reliability index and the second reliability index, a second reliability deviation value is obtained, and an input filter network cutoff frequency increase coefficient is matched based on the second reliability deviation value, thereby increasing the input filter network cutoff frequency of the chip.

5. The system for surge protection testing of a spaceborne power supply chip of claim 1, wherein: The reliability of the chip test result is determined whether to be pre-warned, and the specific determination process is: The chip test reliability final value is compared with the first reliability index and the second reliability index to obtain different levels of reliability, and the reliability of the chip test result is determined whether to be pre-warned based on the different levels of reliability change; If the second level of reliability changes to the first level of reliability or the third level of reliability changes to the first level of reliability, it is determined that the reliability of the chip test result is not pre-warned, and the on-orbit stable working time of the chip in the spaceborne environment is predicted; If the second level of reliability is maintained or the third level of reliability is maintained or the second level of reliability changes to the third level of reliability, it is determined that the reliability of the chip test result is pre-warned; If the third level of reliability changes to the second level of reliability, the chip test reliability improvement rate is obtained based on the chip test reliability final value and the chip test reliability index, the input filter network cutoff frequency is further increased based on the input filter network cutoff frequency secondary increase coefficient matched based on the chip test reliability improvement rate, thereby further increasing the input filter network cutoff frequency of the chip, and the chip test reliability index is re-obtained and marked as the chip test reliability re-determination index; The chip test reliability re-determination index is compared with the first reliability index and the second reliability index to obtain a reliability level result; If it is the first level of reliability, it is determined that the reliability of the chip test result is not pre-warned, and the on-orbit stable working time of the chip in the spaceborne environment is predicted; If it is the second level of reliability or the third level of reliability, it is determined that the reliability of the chip test result is pre-warned.

6. A method for testing the surge protection of a spaceborne power supply chip, using a system for testing the surge protection of a spaceborne power supply chip according to any one of claims 1 to 5, characterized in that: It includes: S1. Based on the completed test environment, monitor the surge interference waveform in the test environment during the surge test process; S2. Real-time acquisition of the quality parameters of the surge interference waveform, analysis of the obtained surge interference waveform quality parameters, to determine whether the surge interference waveform meets the test conditions; S3. The surge interference waveform meeting the test condition is applied to the satellite-borne power supply chip to be tested for protection test, process parameters of the protection test are collected and analyzed, and thus the surge protection test result of the satellite-borne power supply chip is graded.

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