Online test method of semiconductor test machine, semiconductor test machine and test system

Abstract

The invention provides an online test method of a semiconductor test machine, the semiconductor test machine and a test system, self-inspection of the semiconductor test machine is triggered based on a test instruction issued to the semiconductor test machine by an EAP system, and if it is judged that at least one target self-inspection item with a self-inspection requirement exists, whether self-inspection exists or not is determined according to the idle state of corresponding hardware; and when the at least one target self-inspection item passes the self-inspection or at least one target self-inspection item with the self-inspection requirement does not exist, the semiconductor testing machine performs wafer testing based on the testing instruction. In the mode, after the semiconductor test machine receives the test instruction issued by the EAP system, self-inspection can be automatically triggered, if it is determined that at least one target self-inspection item with the self-inspection requirement exists, whether self-inspection exists or not can be automatically determined according to the idle state of corresponding hardware, manual intervention is not needed, and therefore the labor cost is reduced, and the test efficiency is improved. The flexibility and the automation degree of self-inspection are improved, the test reliability of the semiconductor test machine is ensured, and the test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an online testing method of a semiconductor testing machine, a semiconductor testing machine and a testing system. Background Art

[0002] With the development of the domestic integrated circuit industry, semiconductor testers have emerged. The performance of semiconductor testers directly impacts the quality of devices produced and production efficiency. In related technologies, wafer fab customers, operating in online mode, are required to manually perform self-tests on the tester before wafer shipment. This requires manual judgment based on experience regarding whether a self-test is necessary at this stage, and manual execution is also required during the test itself. After the self-test is completed and the results are manually determined and confirmed as passed, the test is manually closed and completed. Finally, the EAP (Equipment Automation Program) is used to schedule and schedule shipments. If a self-test is required next time, the schedule and schedule need to be stopped, impacting the fab's online mass production. Therefore, existing self-test solutions require high labor costs and lack flexibility and automation, significantly impacting online testing efficiency. A key feature of online testing is automated testing and test efficiency. Summary of the Invention

[0003] The purpose of the present invention is to provide an online testing method for a semiconductor tester, a semiconductor tester and a testing system, which automatically perform self-tests on the semiconductor tester based on the test instructions issued by EAP before each test, thereby reducing labor costs, improving the flexibility and automation of self-tests, and thereby ensuring the test reliability of the semiconductor tester and improving test efficiency.

[0004] The present invention provides an online testing method for a semiconductor tester, wherein the semiconductor tester is pre-configured with a self-test plan, the self-test plan including: at least one self-test item and self-test information corresponding to each self-test item; the method including: triggering the self-test of the semiconductor tester based on a test instruction sent to the semiconductor tester by an EAP system, determining whether there is at least one target self-test item with a self-test requirement by obtaining the self-test information of at least one self-test item in the self-test plan; if there is at least one target self-test item with a self-test requirement, determining whether to perform a self-test based on an idle state of hardware corresponding to the at least one target self-test item; and until at least one target self-test item passes the self-test or there is no at least one target self-test item with a self-test requirement, the semiconductor tester performs a wafer test based on the test instruction.

[0005] Furthermore, the self-test information includes self-test time, self-test cycle and / or self-test frequency, and determines whether there is at least one target self-test item with self-test requirements by obtaining the self-test information of at least one self-test item in the self-test plan, including: the semiconductor testing machine generates self-test logic based on the intersection of the self-test cycle and / or self-test frequency and the self-test time according to the triggering of the test instruction; and determines whether there is at least one target self-test item with self-test requirements based on the self-test logic and the time information when the test instruction is issued.

[0006] Furthermore, based on the self-test logic and the time information when the test instruction is issued, it is determined whether there is at least one target self-test item with a self-test requirement, and it also includes: when there is a self-test item in the self-test logic that is within the first specified time period and before the time when the test instruction is issued, it is determined that there is a target self-test item with a self-test requirement.

[0007] Furthermore, generating the self-check logic further includes: determining whether the self-check task of at least one target self-check item is repeated within the first specified time period; if repeated, retaining the uniqueness of the repeated self-check task.

[0008] Furthermore, if there is at least one target self-test item with a self-test requirement, whether to perform self-test is determined based on the idle state of the hardware corresponding to the at least one target self-test item, including: if there is at least one target self-test item with a self-test requirement, triggering an event to check the machine status to obtain the test status of the semiconductor testing machine, and judging the idle state of the hardware corresponding to the at least one target self-test item based on the test status.

[0009] Furthermore, if there is at least one target self-test item with a self-test requirement, whether to perform self-test is determined based on the idle state of the hardware corresponding to the at least one target self-test item, and it also includes: triggering an event to check the machine status through the machine software of the semiconductor testing machine, the machine software obtains the test status of the test machine through the communication interface with the test machine, and judges the idle state of the hardware corresponding to the at least one target self-test item based on the test status; when the hardware corresponding to the at least one target self-test item is idle, the machine software sends a self-test instruction to the hardware corresponding to the target self-test item to start the self-test function built into the hardware to obtain a first detection result.

[0010] Furthermore, the method also includes: when a problem occurs in any interaction link between the test machine and the machine software or a problem occurs in the hardware self-test, the problem is fed back to the EAP system, and the test machine does not perform wafer testing.

[0011] Furthermore, the hardware's built-in self-test capabilities include automatic tuning / calibration.

[0012] Furthermore, the method also includes: when the first test result indicates that the self-test passed, determining the first test result as the self-test result of the hardware corresponding to the target self-test item; when the first test result indicates that the self-test failed, repeating the self-test of the hardware corresponding to the target self-test item in the idle state to obtain a second test result of the hardware; and determining whether the self-test passed based on the second test result.

[0013] Furthermore, the method further includes: automatically clearing the self-inspection tasks that have not been self-inspected within each first specified time period.

[0014] A semiconductor testing machine provided by the present invention includes a testing machine and machine software, wherein the machine software includes a self-test module for setting a self-test plan; the machine software triggers the self-test module to perform self-test based on a test instruction issued by an EAP system, and performs wafer testing according to any of the above-mentioned online testing methods for semiconductor testing machines.

[0015] The present invention provides a semiconductor testing system comprising: an EAP system and a semiconductor testing machine; the EAP system is used to send a wafer running test instruction to the semiconductor testing machine; the semiconductor testing machine is used to perform wafer testing according to any of the above-mentioned online testing methods for semiconductor testing machines when receiving the test instruction.

[0016] The present invention provides an online testing method, semiconductor tester, and testing system for a semiconductor tester. Based on a test instruction issued by an EAP system to the semiconductor tester, the semiconductor tester triggers a self-test of the semiconductor tester. The method determines whether at least one target self-test item with a self-test requirement exists by obtaining self-test information of at least one self-test item in the self-test plan. If at least one target self-test item with a self-test requirement exists, the method determines whether to perform a self-test based on the idle state of the hardware corresponding to the at least one target self-test item. The method continues until at least one target self-test item passes self-test or no at least one target self-test item with a self-test requirement exists, at which point the semiconductor tester performs wafer testing based on the test instruction. In this method, upon receiving a test instruction issued by the EAP system, the semiconductor tester automatically triggers a self-test. If at least one target self-test item with a self-test requirement exists, the method automatically determines whether to perform a self-test based on the idle state of the corresponding hardware, eliminating the need for manual intervention. This reduces labor costs, improves the flexibility and automation of the self-test, ensures the test reliability of the semiconductor tester, and improves test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A flowchart of an online testing method for a semiconductor testing machine provided by an embodiment of the present invention;

[0019] Figure 2 A flowchart of another online testing method for a semiconductor testing machine provided by an embodiment of the present invention;

[0020] Figure 3 A flowchart of another online testing method for a semiconductor testing machine provided by an embodiment of the present invention;

[0021] Figure 4 A flowchart of another online testing method for a semiconductor testing machine provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] With the development of the domestic integrated circuit industry, semiconductor testers have emerged. The performance of semiconductor testers directly impacts the quality of devices produced and production efficiency. In recent years, the development of high-performance testers has placed higher demands on automated wafer testers. One implementation of related technologies provides automation solutions for semiconductor fab production tools, clarifying that automation can accelerate production speeds. However, the fundamental issue of testers and capacity utilization has not been fully addressed. Another implementation of related technologies, based on capacity issues, examines the relationship between tool capacity utilization and test fab operations. With in-depth research, the role of tester automation in production capacity is increasing. Numerous studies have focused on analyzing test system functionality through studying tester software and hardware, and subsequently determining the test program development process. Test program development often overlooks optimizing the performance of the tester's software and hardware integration process. Therefore, establishing efficient and timed self-checking tester software and hardware features while simultaneously increasing test speed is crucial for improving tester performance and promoting the development of efficient automated testers.

[0024] With the advancement of some research teams in the actual research and development of semiconductor tester software. In view of the fact that the test head of the tester is generally integrated with the tester, it is mainly used for signal acquisition. In addition, with the continuous improvement of mass production customers' demand for software, the stability and reliability of the current tester data are not enough to meet the needs of the test environment. At present, before the tester tests the wafer, it is necessary for humans to judge whether self-test is needed at this stage based on experience when executing the self-test scheme, and it is also necessary for humans to manually perform the self-test operation during the self-test. After the self-test is completed, the result is manually judged. Only after passing the result will it be manually closed and the self-test is completed. Therefore, the existing self-test scheme requires a large labor cost, and the flexibility and automation of the self-test are low. If the record is not timely, there will be missed detection, which can easily cause test failure problems of the tester. Based on this, an embodiment of the present invention provides an online testing method for a semiconductor tester, a semiconductor tester and a test system. This technology can be applied to online testing applications that require semiconductor testers.

[0025] To facilitate understanding of this embodiment, an online testing method for a semiconductor tester disclosed in an embodiment of the present invention is first introduced. The semiconductor tester is pre-configured with a self-test plan, and the self-test plan includes: at least one self-test item, and self-test information corresponding to each self-test item; the self-test information can be information such as the detection time related to the self-test of the semiconductor tester set by a legitimate login user, for example, it can include self-test time, self-test cycle and / or self-test frequency, etc.; the above-mentioned self-test items can be understood as hardware modules or functional units inside the semiconductor tester that need to be regularly inspected and calibrated; in actual implementation, the legitimate login user can pre-configure a self-test plan for the semiconductor tester according to actual needs to guide how and when the semiconductor tester performs automatic self-test tasks. The self-test plan usually needs to include: at least one self-test item, and self-test information corresponding to each self-test item; the number of the self-test items can be set according to actual needs and is not limited here, for example, it can include but is not limited to: Chassis (chassis / frame), CMU (Capacitance Measurement Unit, capacitance measurement unit), CMU Bias (CMU bias circuit), Control Bus (control bus), DC Leakage (DC leakage current), Frequency Measurement Unit (FMU), General Purpose Interface Bus (GPIB), High-Speed ​​Pulse Unit (HSPU), Pattern Generator Unit (PGU), Pin Board (pin board), Probe Card Cap (probe card cap), Radio Frequency Identification (RFID), Source Measure Unit (SMU). Test Selections (test selections), Test Status (test status), Testhead (test head), Timer. The self-test information corresponding to each self-test item can be the same or different and can be set according to actual needs. This is not limited here.

[0026] It is worth noting that hardware such as SMU has its own self-test function and automatic tuning function (calibration). Hardware self-test can be triggered by specific commands or interfaces. In this solution, the self-test process not only indicates the feasibility of the detection function, but also includes calibration of the hardware to make the hardware's accuracy and status more in line with the usage requirements. Through this self-test process, the test accuracy can be improved. If a certain hardware needs to ensure high test consistency, more self-tests can be set for the hardware (such as self-testing for incoming goods every day).

[0027] like Figure 1 As shown, the method includes:

[0028] Step S102 , triggering a self-test of the semiconductor tester based on a test instruction sent by the EAP system to the semiconductor tester, and determining whether there is at least one target self-test item with a self-test requirement by obtaining self-test information of at least one self-test item in a self-test plan;

[0029] The above-mentioned test instructions can be instructions for instructing the testing of wafers; when actually implemented in online mode, when wafers arrive and a semiconductor tester is required to test the wafers, the EAP system can send test instructions to the semiconductor tester. After receiving the test instructions, the semiconductor tester can trigger the start of self-test and obtain self-test information for each self-test item in the self-test plan. Based on the self-test information, it is determined whether there are target self-test items with self-test requirements. The number of the target self-test items may be one or more, and may be part or all of all the self-test items included in the self-test plan.

[0030] Step S104: if there is at least one target self-test item with a self-test requirement, determining whether to perform a self-test based on the idle state of the hardware corresponding to the at least one target self-test item;

[0031] The hardware corresponding to each of the above-mentioned target self-test items is usually different; the above-mentioned idle state can be used to indicate whether the hardware is idle. For example, if the semiconductor tester is not performing any test tasks, the hardware in the semiconductor tester is idle, and the hardware corresponding to each target self-test item can be self-tested; if the semiconductor tester is performing other test tasks, such as when the dual-port test EAP is delegating multiple hardware test tasks, it can be considered that the hardware in the semiconductor tester is not idle. In this case, it can be put on hold first, and then self-test can be performed according to the corresponding self-test items after all the hardware is idle; it is worth noting that if the hardware is not idle, there are two settings. There are two configuration methods. The first method is to perform the self-test when the hardware is idle; the second method is to skip the self-test, directly perform wafer testing, and perform self-test next time the goods arrive. The second method can determine whether the second method can be performed based on the priority of the self-test items, previous self-test conditions, etc. For example, if the priority is set according to the importance of the self-test items, if there is a self-test item A with high self-test importance that belongs to the target self-test item, the second method cannot be used. When the self-test importance of the target self-test item is not high, the second method can be used. It can also be determined based on the level of the self-test results of the previous self-test items whether the self-test can be skipped this time, and then the second method can be selected.

[0032] Step S106 : until at least one target self-test item passes the self-test or there is no at least one target self-test item with a self-test requirement, the semiconductor tester performs wafer testing based on the test instruction.

[0033] When each target self-test item passes the self-test, it means that the hardware corresponding to each target self-test item in the semiconductor tester meets the usage requirements. In this case, it can be considered that the semiconductor tester has passed the self-test, and the preset test process can be performed on the wafer according to the received test instructions. After the semiconductor tester completes the self-test, it can still respond to other incoming task functions issued by the EAP. If there are target self-test items that fail the self-test, it is generally believed that there may be an abnormality in the hardware of the semiconductor tester. In order to ensure the stability and reliability of the test process, in this case, it can be considered that the semiconductor tester has failed the self-test, and the preset test process is not allowed to be performed on the wafer. When there is no at least one target self-test item with a self-test requirement, it can be considered that the semiconductor tester does not need to be self-tested at present. In this case, the semiconductor tester can directly test the wafer. In actual applications, the relevant information about whether the semiconductor tester passes or fails the self-test can be fed back to the EAP and MES (Manufacturing Execution System).

[0034] In actual applications, the wafer fab needs to perform self-calibration when using semiconductor testers to test products. This embodiment fully considers the wafer fab's testing process, regular self-test, hardware performance, and prompt periodic self-test functions. The main process of this embodiment is established through on-site investigation, customer feedback, and demand discussion. Figure 2 The flowchart of another online testing method for a semiconductor tester is shown. When the EAP issues a test task (i.e., a command to test a lot, regardless of whether testing a single wafer or multiple wafers) (corresponding to the above-mentioned test command) to the semiconductor tester, the automatic timed self-test function of the semiconductor tester software will first determine whether the current machine meets the periodic self-test requirements (corresponding to the above-mentioned determination of whether there is at least one target self-test item with self-test requirements by obtaining self-test information of at least one self-test item in the self-test plan). If the periodic self-test requirements are met, the self-test process specifically triggers an event to check the machine status to obtain the test status of the current machine, thereby determining whether the hardware in the current machine related to the target self-test item is idle. If not, it is generally necessary to wait for each hardware item to become idle. After each hardware item becomes idle, the target self-test items are sequentially determined and executed. To fully meet the requirements for the usage frequency and self-test frequency of each hardware item in different situations, this embodiment can set a combination of frequency and period for the self-test items. After each hardware item passes the self-test, wafer testing can begin. If any hardware item fails the self-test, it can be considered that the semiconductor tester self-test has failed, and wafer testing can be stopped.

[0035] The above-mentioned online testing method for a semiconductor tester triggers a self-test of the semiconductor tester based on a test instruction issued by the EAP system to the semiconductor tester. The method determines whether at least one target self-test item with a self-test requirement exists by obtaining self-test information from at least one self-test item in the self-test plan. If at least one target self-test item with a self-test requirement exists, the method determines whether to perform a self-test based on the idle state of the hardware corresponding to the at least one target self-test item. The method continues until at least one target self-test item passes self-test or no at least one target self-test item with a self-test requirement exists, at which point the semiconductor tester performs wafer testing based on the test instruction. In this method, after receiving a test instruction issued by the EAP system, the semiconductor tester can automatically trigger a self-test. If at least one target self-test item with a self-test requirement exists, the method automatically determines whether to perform a self-test based on the idle state of the corresponding hardware, eliminating the need for manual intervention. This reduces labor costs, improves the flexibility and automation of self-testing, ensures the test reliability of the semiconductor tester, and improves test efficiency.

[0036] An embodiment of the present invention provides another online testing method for a semiconductor tester. This method is implemented based on the method of the above embodiment. In this method, the self-test information includes the self-test time, self-test cycle and / or self-test frequency. The self-test time can be any time point between 0:00:00 and 23:59:59; the self-test frequency can be daily, weekly, etc.; the self-test cycle can be a time period for self-test, for example, the self-test cycle is every Tuesday, etc. In actual implementation, a legitimate logged-in user can add or modify the self-test frequency, self-test cycle, self-test time, etc. according to actual needs. The method includes the following steps:

[0037] Step 1: triggering a self-test of the semiconductor tester based on a test instruction sent from the EAP system to the semiconductor tester. The semiconductor tester generates a self-test logic based on an intersection of a self-test period and / or a self-test frequency and a self-test time according to the triggering of the test instruction.

[0038] In actual implementation, the self-test period and self-test frequency set by the legally logged-in user may be repeated. For example, the self-test period is set to 9:00 am every Monday, and the self-test frequency is set to 9:00 am every day. Then, there is a problem of repeated settings on Monday. In this case, the intersection of the self-test period and the self-test frequency can be taken, and the corresponding self-test logic can be generated in combination with the self-test time. That is, on Monday, only one self-test needs to be performed at 9:00 am, and there is no need to repeat it twice. From Tuesday to Sunday, since there is no problem of repeated settings, the test instruction can be received, and after determining that the corresponding hardware is idle, the self-test can be performed on the corresponding hardware at 9:00 am every day.

[0039] Specifically, the process of generating the self-test logic may include the following steps 10 to 12:

[0040] Step 10: determining whether the self-checking task of at least one target self-checking item is repeated within a first specified time period;

[0041] Step 11: If there are duplicates, the uniqueness of the duplicate self-check tasks is preserved.

[0042] Step 12: Automatically clear the self-check tasks that have not been self-checked within each first specified time period.

[0043] The first designated time period can be set based on actual needs, for example, 0:00:00-23:59:59. In actual implementation, for each target self-test item, the self-test tasks of the target self-test item may overlap within the first designated time period. For example, if a CMU self-test is set at 9:00 every day and at 9:00 every Monday, and a delivery arrives at 9:01 on Monday, a duplicate CMU self-test occurs on Monday. In this case, the duplicate self-test tasks can be merged. Alternatively, it can be understood that only one self-test is required on Monday, and the CMU self-test task set at 9:00 every Monday is automatically cleared. In addition, if any self-test tasks have not been performed during each first designated time period, these self-test tasks can be automatically cleared. For example, if monitoring determines that any self-test tasks have not been performed on Monday at 23:59:59 on Monday, these self-test tasks will be automatically cleared to avoid affecting the self-test and online testing process on the next day.

[0044] For example, Figure 3 The flowchart of another online testing method for a semiconductor tester shows this. When EAPs arrive, if the self-test tasks for a target self-test item are repeated within a first specified time period, the repeated target self-test items can be merged and a single self-test performed. (Self-test item information can be recorded in a log, which records historical counts, and the log can be used to determine if there are repeated self-test tasks.) If there are no repeated self-test tasks, each item can be self-tested individually. After the hardware corresponding to each target self-test item passes the self-test, the corresponding log is recorded and the process continues. In other words, the semiconductor tester automatically determines whether self-tests need to be performed on all items based on the self-test item settings for the current batch.

[0045] Step 2: Based on the self-test logic and the time information of the test instruction being issued, it is determined whether there is at least one target self-test item with a self-test requirement.

[0046] This step 2 specifically includes: when there is a self-test item in the self-test logic that is within the first specified time period and before the time when the test instruction is issued, it is determined that there is a target self-test item with a self-test requirement. For example, taking the first specified time period of 0:00:00-23:59:59 as an example, the time when the test instruction is issued is 9:01 am, and there is a self-test item with a self-test time of 9:00 am in the self-test logic. Since the time point of 9:00 is within the first specified time period of 0:00:00-23:59:59 and before the time when the test instruction is issued, that is, 9:01 am, the self-test item at 9:00 am can be considered to be a target self-test item with a self-test requirement. Because the self-test time is generally matched with the order time / delivery time, and there is sometimes a time difference between the start of ordering / delivery and the issuance of the test instruction by the EAP (actual arrival of the goods).

[0047] Step 3: If there is at least one target self-test item with a self-test requirement, determining whether to perform a self-test based on the idle state of the hardware corresponding to the at least one target self-test item;

[0048] The third step may specifically include: if there is at least one target self-test item with a self-test requirement, triggering an event for checking a machine status to obtain a test status of the semiconductor tester, determining an idle state of hardware corresponding to the at least one target self-test item based on the test status, and determining whether to perform a self-test according to the idle state of the hardware corresponding to the at least one target self-test item;

[0049] The above-mentioned event of checking the machine status can be an instruction generated to indicate the status of the machine to be checked, etc.; in actual implementation, when it is determined that there is at least one target self-test item with self-test requirements, the event of checking the machine status can be automatically triggered to obtain the test status of the semiconductor testing machine, thereby determining whether the hardware involved in the target self-test item in the semiconductor testing machine is idle. If it is not idle, it is necessary to wait for the corresponding hardware to be idle. After the corresponding hardware is idle, self-test is performed on the corresponding hardware.

[0050] This step three can also be implemented by following steps 30 to 32:

[0051] Step 30 , triggering an event to check the status of the semiconductor tester through the machine software of the tester. The machine software obtains the test status of the tester through a communication interface with the tester, and determines the idle state of the hardware corresponding to at least one target self-test item based on the test status.

[0052] In step 31 , when the hardware corresponding to at least one target self-test item is idle, the machine software sends a self-test instruction to the hardware corresponding to the target self-test item to activate the self-test function built into the hardware and obtain a first test result.

[0053] The above-mentioned machine software may correspond to the test software part in the semiconductor test machine, and the above-mentioned test machine may correspond to the hardware component in the semiconductor test machine; the self-test function built into the above-mentioned hardware may include automatic tuning / calibration. In actual implementation, when it is determined that there is at least one target self-test item with a self-test requirement, the machine software in the semiconductor test machine may automatically trigger an event to check the machine status, and obtain the test status of the test machine through the communication interface with the test machine, thereby determining whether the hardware involved in the target self-test item in the semiconductor test machine is idle. If it is not idle, it is necessary to wait for the corresponding hardware to be idle. After the corresponding hardware is idle, the machine software may send a self-test instruction to the hardware corresponding to the target self-test item. After the hardware corresponding to each target self-test item receives the self-test instruction, it may start the self-test function built into the hardware to automatically tune the hardware. / calibration, and obtain a first test result, which is usually a total test result for all hardware corresponding to all target self-test items. The first test result may be a hardware self-test pass or fail. For example, when executing the self-test of the corresponding hardware in sequence according to the target self-test items, if each hardware passes the self-test, the first self-test result is that the hardware self-test passes. If, during the sequential execution process, hardware fails the self-test, and if there are other target self-test items that have not completed the self-test, the self-test of the hardware corresponding to each subsequent target self-test item will not be executed, and the first test result is directly considered to be a hardware self-test failure.

[0054] Step 32: When a problem occurs in any interaction between the test machine and the machine software or in the hardware self-test, the problem is fed back to the EAP system, and the test machine does not perform wafer testing.

[0055] In actual implementation, when any abnormality occurs in the interaction between the test machine and the machine software, or the first detection result indicates that the hardware self-test has failed, the machine software can feed back the detected problem to the EAP system. In order to ensure the stability and reliability of the test process, in this case, the preset test process is usually not allowed to be executed on the wafer.

[0056] Step 33: When the first test result indicates that the self-test has passed, the first test result is determined as the self-test result of the hardware corresponding to the target self-test item;

[0057] In actual implementation, the process of testing the hardware corresponding to each target self-test item is generally only performed once. If the above-mentioned first test result is pass, the first test result can be directly used as the self-test result of the hardware corresponding to all target self-test items, that is, it can be considered that each hardware has passed the self-test.

[0058] Step 34: When the first test result indicates that the self-test has failed, the self-test is repeated on the hardware corresponding to the target self-test item in the idle state to obtain a second test result for the hardware. It is worth noting that the self-test may be repeated only on the self-test item that has failed, or on multiple self-test items.

[0059] Step 35: Determine whether the self-test has passed based on the second test result.

[0060] If the first test result is fail, a second self-test will usually be repeated for the hardware corresponding to each target self-test item, or a second self-test will be repeated for the hardware corresponding to a target self-test item that has not passed, to prevent the hardware status from being abnormal during the first self-test. The execution process of the second self-test is the same as that of the first self-test. After the execution is completed, a second test result of the hardware corresponding to the target self-test item of the repeated self-test is obtained. The second test result may be the same as or different from the first test result. The second test result can be used as the self-test result of the hardware corresponding to each target self-test item, that is, whether the related hardware has passed the self-test is determined based on the second test result. For example, if the second test result is pass, it can be considered that the related hardware has passed the self-test, and the log can be recorded and fed back to the waring interface of the semiconductor test machine software, and then the test process for the wafer is executed. If the second test result is fail, it can be considered that the related hardware has failed the self-test. In this case, it is usually reported to the EAP system for processing, and the test process for the wafer is stopped.

[0061] like Figure 4 The flowchart of another online testing method for a semiconductor tester is shown. After determining that the current time meets the periodic self-test, it is determined whether the hardware corresponding to the target self-test item is idle. If it is not idle, it is necessary to wait for the hardware to be idle. After each hardware is idle, the hardware is self-tested for the first time. If each hardware passes the self-test, the first test result is pass, and the test begins, that is, the wafer can be tested until the test is completed. If there is hardware that fails the self-test, that is, the first self-test result is fail, the hardware is self-tested for the second time. If each hardware passes the self-test, the second test result is pass, and the test begins, that is, the wafer can be tested until the test is completed. If the second test result is fail, it can be considered that the semiconductor tester self-test has failed, and the wafer will not be tested. When the current time does not meet the periodic self-test, it can be considered that the semiconductor tester does not need to be self-tested at the moment. In this case, the semiconductor tester can directly test the wafer.

[0062] Step 4: until at least one target self-test item passes the self-test or there is no at least one target self-test item with a self-test requirement, the semiconductor tester performs wafer testing based on the test instruction.

[0063] In this embodiment, in response to the adding operation for the first self-test plan, a first self-test plan may be added for the semiconductor tester;

[0064] Specifically, a legitimate logged-in user can add a new first self-test plan to the semiconductor test machine according to actual needs, such as a timed self-test menu and function description table shown in Table 1. This embodiment allows legitimate logged-in users to add self-test plans during the idle period of the machine. All self-test plans set within the self-test validity period (such as Monday 0:00:00 to Sunday 23:59:59) will be completed within the self-test validity period. Even if the legitimate logged-in user temporarily modifies plan A to plan B while executing plan A, the self-test validity period of plan B will be executed from Monday 0:00:00 to Sunday 23:59:59 in the next cycle.

[0065] Table 1

[0066]

[0067]

[0068] This embodiment can also respond to an operation instruction for the second self-test plan and perform the operation corresponding to the operation instruction on the second self-test plan. The operation instruction can be a delete instruction, an edit instruction, etc. for the second self-test plan. As shown in Table 1, this embodiment allows a legitimate logged-in user to delete an existing self-test plan during the machine's idle time. It also allows a legitimate logged-in user to edit or modify an existing self-test plan during the machine's idle time.

[0069] The above-mentioned process of responding to the operation instruction for the second self-test plan and executing the operation corresponding to the operation instruction on the second self-test plan may specifically include: responding to a first update instruction for the self-test information in the second self-test plan, and updating the self-test information according to the first update instruction; responding to a second update instruction for at least one self-test item in the second self-test plan, and updating at least one self-test item according to the second update instruction.

[0070] As shown in Table 1, this embodiment allows legally logged-in users to add and modify self-test items; allows legally logged-in users to add and modify self-test frequencies, for example, they can be set to daily or weekly; allows legally logged-in users to add and modify self-test cycles, if set to daily, the self-test cycle is 1, if set to weekly, the self-test cycle is a day from Monday to Sunday; also allows legally logged-in users to add and modify self-test times, for example, they can set any time point between 0:00:00-23:59:59, etc.

[0071] After all self-test plans set for plan A within the self-test validity period (e.g., Monday 00:00:00 to Sunday 23:59:59) have been executed, any newly added, modified, or deleted self-test plans will be executed during the next self-test validity period (e.g., Monday 00:00 to Sunday 23:59:59). During the execution of plan A, all modifications, additions, and deletions will not directly affect the execution of the current task. For example, if a self-test is set for plan A, and while partially executing plan A, a legitimately logged-in user suddenly adds a new plan, forming plan B. After all tasks for this week are completed, plan B will be executed, and plan A will be cleared. All subsequent plans will become new plans of plan B unless the legitimately logged-in user makes further changes.

[0072] At the same time, this embodiment allows for modification, addition, and deletion of self-test items for each self-test plan. To improve security, these items cannot be edited during automated delivery. Editing is permitted when not in delivery mode, requiring administrator privileges (i.e., a legitimately logged-in user). Ordinary users can only view, not edit. A corresponding log is typically saved for each scheduled self-test result.

[0073] To facilitate understanding of the above embodiments, various examples are provided below to illustrate different situations:

[0074] Case 1: If the delivery time is set at 9:00 every Wednesday morning, and there is no delivery on Wednesday this week, but the delivery will arrive at 9:00 next Wednesday, how to conduct self-inspection?

[0075] For scenario 1: A prolonged absence of goods will not affect the self-test speed or functionality, nor will it be performed continuously. This is because it will only be performed once each time a new delivery is requested. Self-testing presupposes the arrival of goods. Since goods are arriving next Wednesday, but not this Wednesday, there is no need to perform a self-test this Wednesday. Simply wait for the first shipment scheduled for 9:00 AM next Wednesday to perform an automatic self-test. The self-test task for this Wednesday needs to be cleared. Therefore, a single self-test at 9:00 AM next Wednesday is sufficient.

[0076] Case 2: If there are repeated self-test items, for example, you set a CMU self-test at 9:00 every day and 9:00 every Monday. If goods arrive at 9:01 on the same Monday, the CMU self-test will be performed several times.

[0077] In case 2, if the CMU self-test at 9:00 AM on Monday is repeated, only one self-test is required on that day. For example, the CMU self-test task scheduled later, at 9:00 AM every Monday, can be cleared. Therefore, the CMU self-test is only performed once on Monday.

[0078] Case 3: Under what circumstances is it necessary to perform two self-tests?

[0079] Regarding situation 3: Due to the particularity of the hardware performance of the semiconductor tester, it is necessary to perform a self-test again after the first self-test fails to keep the performance of the hardware test wafer in a long-term stable state. If the product has not been shipped for a long time, for example, the hardware has been powered on for 2-3 weeks but no self-test operation has been performed, and the material suddenly arrives, one self-test may not guarantee an accurate judgment. Therefore, when the first self-test fails, a second self-test is required. If the second self-test fails, it can be confirmed that the semiconductor tester has not passed the self-test. If the second self-test passes, it can be confirmed that the semiconductor tester has passed the self-test.

[0080] Case 4: Self-test items that span multiple days are processed independently. For example, if an SMU self-test is set at 23:59 every day and 00:01 every Tuesday, and a delivery arrives at 00:01 on Tuesday, will SMU self-tests be performed at 23:59 on Monday and 00:01 on Tuesday?

[0081] For situation 4: The daily self-test validity period is usually set from 00:00:00 to 23:59:59 on the same day. After this time, the task of the day will be automatically cleared and will not be continued to the next day. Therefore, although the self-test is set at 23:59 every day, because there is no delivery on Monday, the self-test will not be performed at 23:59 on Monday. Only an SMU self-test will be performed at 00:01 on Tuesday.

[0082] The above-mentioned online testing method of the semiconductor tester is based on the demand for semiconductor testers with automatic timed self-testing. It combines the delivery process of the semiconductor tester and its own software and hardware systems to establish the software and hardware functions of the tester with efficient timed automatic self-testing.

[0083] Functionality: This solution can use existing semiconductor testers, and based on their software and hardware performance, without delaying the online mass production of FAB (usually used to refer to semiconductor wafer manufacturing plants), by adding an automatic timed self-test solution to the delivery process, in order to improve the test performance and mass production reliability of the WAT (Wafer Acceptance Test) tester (corresponding to the above-mentioned semiconductor tester). After long-term research, it was found that wafer factory customers need to manually perform self-tests on the tester for different self-test items before testing the wafer delivery. Therefore, it is necessary to integrate the above-mentioned test items into the EAP automatic delivery system through software for self-testing, so that users can set different self-test items and their combinations for timed self-testing before each delivery. At the same time, it is also possible to set different execution frequencies according to different self-test items, such as weekly or daily self-testing.

[0084] Efficiency: Within a controllable time range, self-test and calibration are automatically and regularly completed to reduce downtime failure rate.

[0085] In terms of process: This method simplifies the process, sets up automatic self-inspection of incoming goods during EAP delivery, and can judge the number of self-inspections and self-inspection behaviors within the set period to simplify the setting of additional self-inspection plans.

[0086] An embodiment of the present invention discloses a semiconductor tester, including a test machine and machine software. The machine software includes a self-test module for setting a self-test plan. The machine software triggers the self-test module to perform self-test based on a test instruction issued by an EAP system, and performs wafer testing according to the online testing method of the semiconductor tester in the above embodiment.

[0087] An embodiment of the present invention discloses a semiconductor testing system, including: an EAP system and a semiconductor testing machine; the EAP system is used to send a wafer running test instruction to the semiconductor testing machine; the semiconductor testing machine is used to perform wafer testing according to the online testing method of the semiconductor testing machine in the above embodiment when receiving the test instruction.

[0088] like Figure 4 As shown, in this embodiment, an automatic timed self-test function is added to the incoming goods process of the wafer factory WAT tester EAP and MES (Manufacturing Execution System).

[0089] In the above-mentioned semiconductor test system, when the semiconductor tester is in the process of running goods, its own software and hardware can be made to perform regular self-tests. The automatic timed self-test function of the semiconductor tester is embedded in the existing EAP's running goods process. By setting the automatic timed self-test task before running goods on the existing tester software side, it is possible to automatically perform periodic self-tests before each EAP receives goods. After the self-test is completed, the running goods process can be automatically carried out, realizing the functions of EAP running goods and semiconductor tester automatic timed self-test. This embodiment can also make full use of the software and hardware structure of the existing WAT tester, and realize the addition of user-defined timed self-test functions on the basis of maintaining the software functions of the tester. It provides large and medium-sized wafer manufacturers with a feasible solution for realizing automatic timed self-tests when using the tester EAP to run goods, and can also provide help for optimizing and improving the production capacity of wafer factories.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An online testing method for a semiconductor testing machine, characterized in that: The semiconductor tester is pre-configured with a self-test plan, wherein the self-test plan includes: at least one self-test item and self-test information corresponding to each self-test item; the method includes: triggering a self-test of the semiconductor tester based on a test instruction sent to the semiconductor tester by the EAP system, and determining whether there is at least one target self-test item with a self-test requirement by obtaining self-test information of at least one self-test item in a self-test plan; If there is at least one target self-test item with a self-test requirement, determining whether to perform a self-test according to an idle state of hardware corresponding to the at least one target self-test item; Until at least one target self-test item passes the self-test or there is no at least one target self-test item with a self-test requirement, the semiconductor testing machine performs wafer testing based on the test instruction.

2. The method according to claim 1, characterized in that The self-inspection information includes a self-inspection time, a self-inspection cycle, and / or a self-inspection frequency. The determining whether there is at least one target self-inspection item with a self-inspection requirement by obtaining the self-inspection information of at least one self-inspection item in the self-inspection plan includes: The semiconductor tester generates a self-test logic based on the intersection of the self-test period and / or the self-test frequency and the self-test time according to the triggering of the test instruction; Based on the self-test logic and the time information of issuing the test instruction, it is determined whether there is at least one target self-test item with a self-test requirement.

3. The method according to claim 2, characterized in that The determining, based on the self-test logic and the time information of issuing the test instruction, whether there is at least one target self-test item with a self-test requirement further includes: When there is a self-test item in the self-test logic that is within the first specified time period and before the time when the test instruction is issued, it is determined that there is a target self-test item with a self-test requirement.

4. The method according to claim 3, characterized in that Generating self-checking logic also includes: Determining whether the self-check task of at least one target self-check item is repeated within the first specified time period; If there are duplicates, the uniqueness of the duplicate self-check tasks is preserved.

5. The method according to claim 1, wherein If the at least one target self-test item having a self-test requirement exists, determining whether to conduct a self-test according to an idle state of hardware corresponding to the at least one target self-test item includes: If there is at least one target self-test item with self-test requirements, an event of checking the machine status is triggered to obtain the test status of the semiconductor tester, and the idle state of the hardware corresponding to the at least one target self-test item is determined based on the test status.

6. The method according to claim 5, characterized in that If the at least one target self-test item with a self-test requirement exists, determining whether to perform a self-test according to an idle state of hardware corresponding to the at least one target self-test item, further comprising: triggering an event to check the status of the semiconductor tester through the machine software of the tester, the machine software obtaining the test status of the tester through a communication interface with the tester, and determining the idle state of the hardware corresponding to the at least one target self-test item based on the test status; When the hardware corresponding to the at least one target self-test item is idle, the machine software sends a self-test instruction to the hardware corresponding to the target self-test item to start a self-test function built into the hardware and obtain a first test result.

7. The method according to claim 6, characterized in that The method further comprises: When a problem occurs in any interaction link between the test machine and the machine software or a problem occurs in the hardware self-test, the problem is fed back to the EAP system, and the test machine does not perform wafer testing.

8. The method according to claim 6, characterized in that The hardware's built-in self-test capabilities include automatic tuning / calibration.

9. The method according to claim 6, characterized in that The method further comprises: When the first detection result indicates that the self-test has passed, determining the first detection result as a self-test result of the hardware corresponding to the target self-test item; When the first test result indicates that the self-test fails, repeatedly performing the self-test on the hardware corresponding to the target self-test item in the idle state to obtain a second test result of the hardware; Determine whether the self-test passes according to the second test result.

10. The method according to claim 4, characterized in that The method further comprises: Each self-check task that has not been self-checked within the first specified time period is automatically cleared.

11. A semiconductor testing machine, characterized in that: The device comprises a test machine and machine software, wherein the machine software includes a self-test module for setting a self-test plan; The machine software triggers the self-test module to perform self-test based on the test instruction issued by the EAP system, and performs wafer testing according to the online testing method of the semiconductor testing machine according to any one of claims 1 to 10.

12. A semiconductor testing system, characterized in that: include: EAP systems and semiconductor testers; The EAP system is used to send a wafer delivery test instruction to the semiconductor test machine; The semiconductor testing machine is configured to perform wafer testing according to the online testing method for a semiconductor testing machine according to any one of claims 1 to 10 when receiving the test instruction.

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