Backside-bonded heterogeneous integrated chip and preparation method thereof

Abstract

The invention provides a back-bonded heterogeneous integrated chip and a preparation method thereof. A first silicon nitride waveguide layer of the back-bonded heterogeneous integrated chip is arranged on a silicon waveguide layer; the lithium niobate waveguide layer is arranged on the side, away from the first silicon nitride waveguide layer, of the silicon waveguide layer and is coupled with the silicon waveguide layer, a strip-shaped waveguide of the lithium niobate waveguide layer is arranged on one side of the silicon waveguide layer, and an optical signal is coupled into the lithium niobate strip-shaped waveguide from the silicon waveguide. And conversion of the strip-shaped waveguides to the ridge waveguides in the lithium niobate is realized through a forked structure so as to realize high-efficiency conversion. According to the design method, the lithium niobate waveguide can be allowed to adopt a contact type photoetching process with a larger line width, so that the etching difficulty and the equipment cost can be reduced; and meanwhile, the lithium niobate chip is integrated on the back surface of the silicon optical chip, and the lithium niobate chip can be directly coupled with the silicon waveguide layer, so that the loss of optical signals can be reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of back-bonded heterogeneous integrated chips, and in particular relates to a back-bonded heterogeneous integrated chip and a preparation method thereof. Background Art

[0002] Back-bonded heterojunction integrated chips are core components of optical communications and optoelectronic integration systems. Their performance is directly related to the transmission efficiency of high-speed signals in scenarios such as data centers and 5G networks. As transmission rates advance toward 1.6T and higher, back-bonded heterojunction integrated chips using a single material system are no longer able to simultaneously meet the combined requirements of high bandwidth, low power consumption, and integration density.

[0003] Among related technologies, back-bonded heterogeneous integrated chips primarily include silicon photonics and lithium niobate chips. Silicon photonics, leveraging mature CMOS-compatible processes, exhibit significant advantages in device integration and mass production. However, their electro-optical modulation performance is limited by carrier dispersion, making them incapable of adapting to higher transmission rate applications. Lithium niobate, with its high electro-optic coefficient and fast response, holds significant potential for high-speed modulation. However, due to difficulties in material etching and complex integration with lasers and detectors, it is difficult to independently construct a complete optoelectronic system. The current integration process for silicon photonics and lithium niobate chips is complex.

[0004] Therefore, there is an urgent need for a heterogeneous integrated chip that can combine back bonding of silicon photonic chips and lithium niobate chips. Summary of the Invention

[0005] The purpose of the present application is to provide a back-bonded heterogeneous integrated chip and a preparation method thereof, aiming to solve the problem of high processing difficulty of back-bonded heterogeneous integrated chips in traditional technologies.

[0006] A first aspect of an embodiment of the present application provides a back-side bonded heterogeneous integrated chip, the back-side bonded heterogeneous integrated chip comprising:

[0007] Silicon waveguide layer;

[0008] a first silicon nitride waveguide layer, disposed on the silicon waveguide layer and spaced apart from the silicon waveguide layer, wherein the silicon waveguide layer and the first silicon nitride waveguide layer are coupled;

[0009] a lithium niobate waveguide layer, arranged on a side of the silicon waveguide layer away from the first silicon nitride waveguide layer and spaced apart from the silicon waveguide layer, wherein the lithium niobate waveguide layer is coupled to the silicon waveguide layer;

[0010] The lithium niobate waveguide layer comprises interconnected strip waveguides and ridge waveguides. The strip waveguides are located on one side of the silicon waveguide layer, and the strip waveguide-ridge waveguide structure is achieved through a crossover structure. The waveguide structure in the vertical direction is: a first layer of silicon nitride waveguides, a second layer of silicon nitride waveguides, a silicon waveguide, and a lithium niobate waveguide.

[0011] A second aspect of the present application further provides a method for preparing a back-bonded heterogeneous integrated chip, characterized in that the preparation method comprises:

[0012] Providing a prefabricated silicon photonic chip, the prefabricated silicon photonic chip comprising the silicon waveguide layer according to any one of claims 1 to 8 and a first silicon nitride waveguide layer;

[0013] Providing a prefabricated lithium niobate chip, wherein the prefabricated lithium niobate chip includes a lithium niobate layer;

[0014] The prefabricated lithium niobate chip is bonded to the prefabricated silicon photonic chip, and the lithium niobate layer is disposed adjacent to the silicon waveguide layer.

[0015] In some embodiments of the present application, the preparation method satisfies at least one of the following conditions:

[0016] Providing a prefabricated silicon photonic chip includes:

[0017] A silicon photonic chip middleware is provided, wherein the silicon photonic chip middleware comprises the silicon waveguide layer and the first silicon nitride waveguide layer as described above;

[0018] Depositing a first silicon dioxide layer on a side of the silicon photonic chip intermediate component where the silicon waveguide layer is provided, and performing chemical mechanical polishing on the first silicon dioxide layer;

[0019] performing surface activation on the first silicon dioxide layer;

[0020] Providing a prefabricated lithium niobate chip includes:

[0021] Providing a lithium niobate chip middleware, wherein the lithium niobate chip middleware includes a lithium niobate layer;

[0022] Depositing a second silicon dioxide layer on a side of the lithium niobate chip intermediate component where the lithium niobate layer is provided, and performing chemical mechanical polishing on the second silicon dioxide layer;

[0023] performing surface activation on the second silicon dioxide layer;

[0024] After bonding the prefabricated lithium niobate chip to the prefabricated silicon photonic chip, the method further includes:

[0025] removing the substrate layer on a side of the lithium niobate layer facing away from the prefabricated silicon photonic chip to expose the lithium niobate layer;

[0026] The lithium niobate layer is etched at least twice to obtain a first sub-waveguide layer and a second sub-waveguide layer.

[0027] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: in the above-mentioned back-bonded heterogeneous integrated chip and preparation method, the back-bonded heterogeneous integrated chip includes a silicon waveguide layer, a first silicon nitride waveguide layer and a lithium niobate waveguide layer; the first silicon nitride waveguide layer is arranged on the silicon waveguide layer and is spaced apart from the silicon waveguide layer, and the silicon waveguide layer and the first silicon nitride waveguide layer are coupled; the lithium niobate waveguide layer is arranged on a side of the silicon waveguide layer away from the first silicon nitride waveguide layer and is spaced apart from the first silicon nitride waveguide layer, and the lithium niobate waveguide layer is coupled to the silicon waveguide layer; the lithium niobate waveguide layer includes a first sub-waveguide layer and a second sub-waveguide layer connected to each other, the second sub-waveguide layer is arranged on one side of the silicon waveguide layer, and the second sub-waveguide layer is on the silicon waveguide layer. The orthographic projection of the silicon waveguide layer on the silicon waveguide layer overlaps with the orthographic projection of the silicon waveguide layer on the silicon waveguide layer, and the first sub-waveguide layer is arranged on the side of the second sub-waveguide layer away from the lithium niobate waveguide layer. The present application integrates the first silicon nitride waveguide layer, the silicon waveguide layer and the lithium niobate waveguide layer on the same chip, so that the chip can have the advantages of both silicon photonics chip and lithium niobate chip. In addition, the second sub-waveguide layer of the lithium niobate waveguide layer overlaps with the orthographic projection of the silicon waveguide layer, which can allow the lithium niobate waveguide to adopt a contact lithography process with a larger line width, avoiding the requirements of traditional high-precision lithography, and helping to reduce the difficulty of etching and equipment cost. At the same time, the lithium niobate chip is integrated on the back of the silicon photonic chip, and the lithium niobate chip can be directly coupled with the silicon waveguide layer, which is conducive to reducing the loss of optical signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic cross-sectional view of the structure of a back-bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0029] Figure 2 A schematic structural diagram of a back-bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the overall steps of a method for preparing a back-side bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the silicon chip pretreatment steps of the method for preparing a back-side bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0032] Figure 5 Schematic diagram of the lithium niobate chip pretreatment steps of the method for preparing a back-bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0033] Figure 6A schematic diagram of the post-bonding processing steps of the method for preparing a back-side bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0034] Figure 7 A process flow chart of a method for preparing a back-side bonded heterogeneous integrated chip provided in an embodiment of the present application;

[0035] Figure 8 A schematic diagram showing the relationship between transmittance and alignment error provided in an embodiment of the present application;

[0036] Figure 9 Schematic diagram of the relationship between transmittance and tip width of the lithium niobate waveguide layer provided in an embodiment of the present application.

[0037] Specific element symbol explanation: 10-silicon photonic chip middleware, 20-lithium niobate chip middleware, 30-chemical mechanical polishing, 100-silicon waveguide layer, 110-first strip waveguide segment, 120-second tapered waveguide segment, 200-first silicon nitride waveguide layer, 300-lithium niobate waveguide layer, 310-second sub-waveguide layer, 311-first tapered waveguide segment, 312-second strip waveguide segment, 313-fourth tapered waveguide segment, 314-fourth strip waveguide segment, 320-first sub-waveguide layer, 321-first separated waveguide segment, 322-third tapered waveguide segment, 323-third strip waveguide segment, 400-second silicon nitride waveguide layer, 500-SOI wafer, a-first direction. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0039] It should be noted that when an element is referred to as being “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0040] It should be understood that the terms "length", "width", "up", "down", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0042] It is important to know that the performance of back-bonded heterogeneous integrated chips, as core components of optical communications and optoelectronic integrated systems, directly affects the efficiency of high-speed signal transmission in scenarios such as data centers and 5G networks. With the iterative upgrades of artificial intelligence and intelligent computing technologies, data centers have placed stringent requirements on the communication rates of chips and switches, and the transmission rate is evolving from the current 400G / 800G to 1.6T and higher. Against this background, back-bonded heterogeneous integrated chips with a single material system face significant technical bottlenecks: it is difficult to achieve a balance between high bandwidth (such as ultra-high frequency modulation corresponding to rates above 1.6T), low power consumption and integration density, prompting the industry to explore heterogeneous integration technology.

[0043] In related technologies, back-bonded heterogeneous integrated chips are mainly divided into two major systems: silicon photonic chips and lithium niobate chips. Silicon photonic chips rely on mature processes compatible with CMOS (complementary metal oxide semiconductors) and have irreplaceable advantages in device integration and large-scale mass production capabilities. The 400G / 800G optoelectronic modules based on the silicon-on-insulator (SOI) platform have entered the small-batch mass production stage, covering a variety of proven device structures such as edge couplers (ECs), grating couplers (GCs), and multi-mode interference couplers (MMIs). However, the electro-optical modulation performance of silicon photonic chips is limited by the carrier dispersion effect mechanism, and its 3dB modulation bandwidth can usually only reach 40GHz, which is difficult to meet the high-speed signal processing requirements of 1.6T and higher-speed optoelectronic modules.

[0044] Lithium niobate chips, with their high electro-optic coefficient (~32pm / V), sub-picosecond response speed, and wide optical transparency window (0.35-5.2μm), have shown significant potential in optoelectronic modules with speeds of 1.6T / 3.2T and higher. In particular, technological breakthroughs based on the thin-film lithium niobate on insulator (LNOI) platform in recent years have further promoted its application in the field of high-speed modulation. However, this platform has inherent technical challenges: First, the lithium niobate material itself does not have the ability to emit and detect light, and it is difficult to heterogeneously integrate it with optoelectronic devices such as lasers and detectors; second, lithium niobate is a difficult-to-etch material, and the processing accuracy of fine structures is affected by factors such as the etching tilt angle, making it difficult to achieve high-density lithography and etching; third, because the refractive index of lithium niobate is lower than that of silicon, the size of LNOI devices is usually larger than that of SOI devices, resulting in limited integration density.

[0045] In related technologies, back-bonded heterogeneous integrated chips consist of a substrate layer, a silicon waveguide layer, and a first silicon nitride waveguide layer. Currently, the lithium niobate chip is often integrated onto the front side of the silicon photonic chip, that is, onto the side of the first silicon nitride waveguide layer facing away from the substrate layer. This requires the first silicon nitride waveguide layer to act as an intermediate coupling layer to couple the silicon waveguide layer and the lithium niobate waveguide layer. This increases optical signal loss and reduces the chip's transmittance.

[0046] Based on this, the present application improves the related back-bonded heterogeneous integrated chip and preparation method.

[0047] See also Figure 1 and Figure 2 , Figure 1 FIG2 shows a schematic cross-sectional view of the structure of a back-bonded heterogeneous integrated chip provided by the present embodiment. The back-bonded heterogeneous integrated chip according to the present embodiment includes a silicon waveguide layer 100, a first silicon nitride waveguide layer 200, and a lithium niobate waveguide layer 300. The first silicon nitride waveguide layer 200 is disposed on the silicon waveguide layer 100 and spaced apart from the silicon waveguide layer 100. The silicon waveguide layer 100 and the first silicon nitride waveguide layer 200 are coupled. The lithium niobate waveguide layer 300 is disposed on a side of the silicon waveguide layer 100 away from the first silicon nitride waveguide layer 200. The lithium niobate waveguide layer 300 is coupled to the silicon waveguide layer 100. The lithium niobate waveguide layer 300 includes a first sub-waveguide layer 320 and a second sub-waveguide layer 310 connected to each other. The second sub-waveguide layer 310 is arranged on one side of the silicon waveguide layer 100, and the orthographic projection of the second sub-waveguide layer 310 on the silicon waveguide layer 100 overlaps with the silicon waveguide layer 100. The first sub-waveguide layer 320 is arranged on the side of the second sub-waveguide layer 310 facing away from the lithium niobate waveguide layer 300.

[0048] It should be noted that the silicon waveguide layer 100 is a waveguide structure layer based on silicon, relying on CMOS technology to achieve optical signal transmission and device integration. The lithium niobate waveguide layer 300 is a waveguide structure layer made of lithium niobate, leveraging its high electro-optical coefficient to achieve high-speed optical modulation. It is directly coupled to the silicon waveguide layer 200. The first sub-waveguide layer 320 and the second sub-waveguide layer 310 are layered structures of the lithium niobate waveguide layer 300, spatially connected to form a waveguide conversion path.

[0049] It is understood that the embodiment of the present application integrates the silicon waveguide layer 100, the first silicon nitride waveguide layer 200, and the lithium niobate waveguide layer 300 into the same chip, allowing the chip to combine the advantages of mature silicon photonic chip technology and high device integration with the high electro-optical coefficient and fast response speed of lithium niobate materials. Furthermore, the orthographic projection of the second sub-waveguide layer 310 of the lithium niobate waveguide layer 300 on the silicon waveguide layer 100 overlaps with the orthographic projection of the silicon waveguide layer 100, relaxing the etching precision requirements for the lithium niobate waveguide. Contact lithography can be used, avoiding the reliance on high-end equipment required by traditional high-precision lithography, reducing etching difficulty and equipment costs. Furthermore, this structure is tolerant to process alignment errors, adapting to process fluctuations in mass production, and improving device yield and production feasibility. Furthermore, the lithium niobate chip is integrated on the backside of the silicon photonic chip, enabling direct coupling with the silicon waveguide layer 100, which helps reduce optical signal loss.

[0050] In some embodiments, the minimum line width of the lithium niobate waveguide layer 300 is 600 nm, and the photolithography process can be completed by a contact photolithography machine.

[0051] In some embodiments of this application, please refer to Figure 2 , Figure 2 FIG. 1 is a schematic structural diagram of a back-bonded heterogeneous integrated chip provided in this embodiment. In this embodiment, the second sub-waveguide layer 310 includes a first tapered waveguide segment 311, and the silicon waveguide layer 100 includes a second tapered waveguide segment 120. The orthographic projection of the first tapered waveguide segment 311 on the silicon waveguide layer 100 overlaps with the orthographic projection of the second tapered waveguide segment 120 on the silicon waveguide layer 100.

[0052] It should be explained that the second sub-waveguide layer 310 is one of the layered structures of the lithium niobate waveguide layer 300 , is disposed on one side of the first silicon nitride waveguide layer 200 , and is connected to the first sub-waveguide layer 320 to form a waveguide transmission path.

[0053] It is understandable that in the present application, the orthographic projection of the first tapered waveguide segment 311 on the silicon waveguide layer 100 and the second tapered waveguide segment are overlapped with each other, which is beneficial to expanding the optical coupling area between the waveguides, allowing the light field to be efficiently transmitted in the overlapping area through the evanescent wave effect, thereby avoiding the reduction in coupling efficiency caused by insufficient traditional alignment accuracy.

[0054] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the silicon waveguide layer 100 further includes a first strip waveguide segment 110 connected to the second tapered waveguide segment 120 , and the second tapered waveguide segment 120 is configured to have a tapered structure in a direction away from the first strip waveguide segment 110 .

[0055] It should be explained that the tapered structure is a morphological design in which the waveguide width of the second tapered waveguide segment 120 gradually decreases in a direction away from the first strip-shaped waveguide segment 110 .

[0056] It can be understood that in the embodiment of the present application, the second tapered waveguide section 120 is configured as a tapered structure, which is conducive to faster output of the optical signal.

[0057] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the second sub-waveguide layer 310 further includes a second strip waveguide segment 312 connected to the first tapered waveguide segment 311. The second strip waveguide segment 312 extends in the same direction as the first strip waveguide segment 110, and the orthographic projection of the second strip waveguide segment 312 on the silicon waveguide layer 100 does not overlap with the first strip waveguide segment 110. The first tapered waveguide segment 311 is configured to have a tapered structure in a direction away from the second strip waveguide segment 312.

[0058] It can be understood that in the embodiment of the present application, a tapered optical mode matching region is formed at the waveguide interface through the tapered structures with opposite trends. When the optical signal enters the coupling region from the silicon waveguide, the tapered silicon waveguide compresses the light field, while the reverse tapered (equivalent to the forward expansion) lithium niobate waveguide provides expansion space for the light field. The synergistic effect of the two allows the light field to gradually squeeze from the silicon waveguide into the lithium niobate waveguide, reducing the transmission loss caused by mode mismatch.

[0059] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the width of the first tapered waveguide segment 311 at one end close to the second strip waveguide segment 312 is greater than the width of the second tapered waveguide segment 120 at one end away from the first strip waveguide segment 110 .

[0060] It can be understood that even if there is an alignment error between the silicon waveguide layer 100 and the lithium niobate waveguide layer 300, the end of the second tapered waveguide segment 120 away from the first strip waveguide segment 110 may still fall within the range of the end of the first tapered waveguide segment 311 close to the second strip waveguide segment 312, thereby ensuring good coupling performance.

[0061] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the first sub-waveguide layer includes a first split waveguide segment 321. The orthographic projection of the first split waveguide segment 321 on the silicon waveguide layer 100 overlaps with the orthographic projection of the second strip waveguide segment 312 on the silicon waveguide layer 100. The first split waveguide segment 321 and the second strip waveguide segment 312 are arranged to intersect, and a portion of the first split waveguide segment 321 extends beyond the area where the second strip waveguide segment 312 is located.

[0062] It should be explained that the first separated waveguide segment 321 is a separated waveguide structure in the first sub-waveguide layer, which overlaps and crosses with the second strip waveguide segment 312 in an orthographic projection, and part of the structure extends outside the area where the second strip waveguide segment 312 is located, for light field conversion and reflection dissipation.

[0063] As can be appreciated, the overlapping orthographic projections of the first separated waveguide segment 321 and the second strip-shaped waveguide segment 312 in this embodiment of the present application minimize structural abrupt changes. Combined with the three-dimensional cross-arrangement, this allows for effective mode conversion and minimized reflections in the overlapping region as the light field passes through. Furthermore, the cross-overlapping structure allows the first separated waveguide segment 321 to be fabricated using contact lithography (linewidth ≥ 600nm), eliminating the need for high-precision DUV lithography.

[0064] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the first sub-waveguide layer further includes a third tapered waveguide segment 322, which is connected to the first separated waveguide segment 321. The second sub-waveguide layer further includes a fourth tapered waveguide segment 313, which is connected to an end of the second strip waveguide segment 312 away from the first tapered waveguide segment 311. The orthographic projection of the third tapered waveguide segment 322 on the silicon waveguide layer 100 falls within the orthographic projection of the fourth tapered waveguide segment 313 on the silicon waveguide layer 100.

[0065] It can be understood that the third tapered waveguide segment 322 is connected to the first separated waveguide segment 321, and its orthographic projection on the silicon waveguide layer 100 completely falls within the projection range of the fourth tapered waveguide segment 313. The fourth tapered waveguide segment 313 is connected to the end of the second strip waveguide segment 312 away from the first tapered waveguide segment 311, serving as a mode matching element in the optical transmission path, and forms a projected nested relationship with the third tapered waveguide segment 322.

[0066] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the third tapered waveguide section 322 is configured to be gradually expanded in a direction away from the first separation waveguide section 321.

[0067] It should be explained that the third tapered waveguide section 322 is gradually expanded in a direction away from the first separation waveguide section 321 , and is used for light field mode conversion and coupling.

[0068] The projected nested structure allows the third tapered waveguide segment 322 to be fabricated using contact lithography (linewidth ≥ 600nm), eliminating the need for high-precision alignment. Even with an alignment error of ±800nm, the spatial redundancy of the nested region ensures effective light field coupling. Furthermore, the width gradient of the gradually expanding structure adapts to the dry etching process of lithium niobate materials, avoiding nanoscale fine processing. Simultaneously, the gradually expanding shape of the third tapered waveguide segment 322 and the fixed width of the fourth tapered waveguide segment 313 form a reverse tapered coupling region, allowing light field transmission through the nested region.

[0069] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the fourth tapered waveguide segment 313 is configured to be gradually expanded in a direction away from the second strip waveguide segment 312 .

[0070] As can be understood, the fourth tapered waveguide segment 313 gradually expands away from the second strip waveguide segment 312. Its gradual width variation allows the light field to gradually expand through a gradient change in cross-sectional dimensions as it enters the tapered waveguide from the second strip waveguide segment 312, thus avoiding mode mismatch caused by sudden changes in the light field. This structure, combined with the gradual expansion of the third tapered waveguide segment 322, forms a dual-gradient path, which helps reduce transmission losses of the light field within the lithium niobate waveguide layer 300.

[0071] In some embodiments of this application, please continue to refer to Figure 2 In this embodiment, the first sub-waveguide layer further includes a third strip waveguide segment 323, which is connected to an end of the third tapered waveguide segment 322 away from the first separated waveguide segment 321. The second sub-waveguide layer further includes a fourth strip waveguide segment 314, which is connected to an end of the fourth tapered waveguide segment 313 away from the second strip waveguide segment 312. The orthographic projection of the third strip waveguide segment 323 on the silicon waveguide layer 100 falls within the orthographic projection of the fourth strip waveguide segment 314 on the silicon waveguide layer 100, and the third strip waveguide segment 323 and the fourth strip waveguide segment 314 form a lithium niobate ridge waveguide structure.

[0072] It should be explained that the third strip waveguide segment 323 and the fourth strip waveguide segment 314 are lithium niobate ridge straight waveguide structures, connected to the end of the fourth tapered waveguide segment 313 away from the second strip waveguide segment 312, forming the light transmission end of the lithium niobate waveguide layer 300.

[0073] In some embodiments, the first strip waveguide segment 110 , the second strip waveguide segment 312 , the third strip waveguide segment 323 and the fourth strip waveguide segment 314 are all extended along the first direction a.

[0074] In some embodiments, the first tapered waveguide segment 311 , the second tapered waveguide segment 120 , the third tapered waveguide segment 322 and the fourth tapered waveguide segment 313 also extend along the first direction a.

[0075] In some embodiments of this application, please continue to refer to Figure 1 The back-bonded heterogeneous integrated chip of this embodiment further includes a second silicon nitride waveguide layer 400. The second silicon nitride waveguide layer 400 is disposed on a side of the first silicon nitride waveguide layer 200 facing away from the silicon waveguide layer 100, and an orthographic projection of the second silicon nitride waveguide layer 400 on the silicon waveguide layer 100 overlaps with an orthographic projection of the first silicon nitride waveguide layer 200 on the silicon waveguide layer 100.

[0076] Furthermore, in order to better implement the back-bonded heterogeneous integrated chip in any of the above embodiments, based on the above back-bonded heterogeneous integrated chip, please refer to Figure 3 , Figure 3 The schematic diagram of the overall steps of the preparation method provided in this embodiment is shown; the embodiment of the present application also provides a method for preparing a back-bonded heterogeneous integrated chip, the preparation method comprising:

[0077] S100: providing a prefabricated silicon photonic chip, wherein the prefabricated silicon photonic chip includes the silicon waveguide layer 100 and the first silicon nitride waveguide layer 200 as described above; specifically, the prefabricated silicon photonic chip requires the silicon waveguide layer 100 and the first silicon nitride waveguide layer 200 to be prepared on a chip substrate in advance.

[0078] S200: Providing a prefabricated lithium niobate chip, wherein the prefabricated lithium niobate chip includes a lithium niobate layer. Specifically, the prefabricated lithium niobate chip requires that the lithium niobate layer be prefabricated on a chip substrate.

[0079] S300: Bonding the prefabricated lithium niobate chip to the prefabricated silicon photonic chip, with the lithium niobate layer positioned adjacent to the silicon waveguide layer 100. Specifically, the bonding process connects the prefabricated lithium niobate chip and the prefabricated silicon photonic chip through physical and chemical interactions at the interface. This allows the lithium niobate waveguide layer 300 and the silicon waveguide layer 100 to be positioned adjacent to each other and form an optical coupling, enabling cross-material optical signal transmission.

[0080] S400: etching the lithium niobate layer to obtain the lithium niobate waveguide layer 300 as described above.

[0081] It is understandable that the independent preparation of prefabricated silicon photonic chips and prefabricated lithium niobate chips can adopt the mature mass production processes of silicon photonic production lines (such as SOI etching and PECVD deposition) to avoid process conflicts when co-processing heterogeneous materials and ensure the performance stability of each layer structure.

[0082] In some embodiments of this application, please refer to Figure 4 , Figure 4A schematic diagram of the silicon chip pretreatment steps of the preparation method provided in this embodiment is shown. Step S100 of this embodiment includes:

[0083] S110: Providing a silicon photonic chip middleware 10, the silicon photonic chip middleware 10 including the silicon waveguide layer 100 and the first silicon nitride waveguide layer 200 as described above;

[0084] S120: Depositing a first silicon dioxide layer on a side of the silicon photonic chip middleware 10 where the silicon waveguide layer 100 is provided, and performing chemical mechanical polishing 30 on the first silicon dioxide layer; specifically, the surface is planarized by the chemical mechanical polishing 30 process to construct a smooth bonding interface, thereby avoiding light scattering loss caused by surface roughness and providing a uniform physical support surface for bonding of the prefabricated lithium niobate chip.

[0085] S130: Activate the surface of the first silicon dioxide layer. Specifically, perform plasma or chemical activation treatment on the surface of the silicon dioxide layer to enhance the chemical activity of the interface, strengthen the bonding strength with the prefabricated lithium niobate chip, ensure the mechanical strength and optical transmittance of the bonding interface, and provide a reliable physical connection foundation for cross-material optical signal transmission.

[0086] It is understandable that the polishing treatment of the silicon dioxide layer improves the flatness of the bonding interface, avoids light scattering and bonding voids; surface activation enhances the interfacial bonding force and achieves low-temperature and efficient bonding.

[0087] In some embodiments of this application, please refer to Figure 5 , Figure 5 A schematic diagram of the lithium niobate chip pretreatment steps of the preparation method provided in this embodiment is shown. Step S200 of this embodiment includes:

[0088] S210: Providing a lithium niobate chip middleware 20, wherein the lithium niobate chip middleware 20 includes a lithium niobate layer;

[0089] S220: depositing a second silicon dioxide layer on the side of the lithium niobate chip middleware 20 where the lithium niobate layer is provided, and performing chemical mechanical polishing 30 on the second silicon dioxide layer; specifically, the surface is smoothed by the chemical mechanical polishing 30 process, etching residues or material defects are eliminated, and a smooth bonding interface is constructed to ensure physical fit and optical transmission quality when bonding with the silicon photonic chip middleware 10.

[0090] S230: Activate the surface of the second silicon dioxide layer. Specifically, the second silicon dioxide layer is activated (e.g., plasma treated) to increase the number of surface active groups, enhance the chemical activity of the interface, strengthen the bonding strength with the silicon photonic chip middleware 10, ensure the mechanical strength and optical transmission stability of the bonding interface, and avoid signal loss caused by poor interface bonding.

[0091] In some embodiments of this application, please refer to Figure 6 , Figure 6 A schematic diagram of the post-bonding processing steps of the preparation method provided in this embodiment is shown. Step S400 of this embodiment includes:

[0092] S410: removing the substrate layer on the side of the lithium niobate layer facing away from the prefabricated silicon photonic chip to expose the lithium niobate layer.

[0093] S410: The lithium niobate layer is etched at least twice to form a first sub-waveguide layer 320 and a second sub-waveguide layer 310. Specifically, the first etching forms the second sub-waveguide layer 310, and the second etching forms the first sub-waveguide layer 320 on the second sub-waveguide layer 310. This layered structure enables functions such as optical field coupling and mode conversion. Furthermore, during the photolithography process, the alignment error between the photolithographic structure and the orthographic overlap structure of the prefabricated silicon photonic chip is within ±300 nm, eliminating the need for high-precision photolithography alignment equipment.

[0094] In the examples of this application, please refer to Figure 7 , Figure 7 The process flow chart of the preparation method provided in this embodiment is shown. Figure 7 As shown, Si represents the silicon waveguide layer 100, SiO2 represents the dielectric layer, LN represents the lithium niobate waveguide layer 300, CMP represents chemical mechanical polishing 30, SiN represents the silicon nitride waveguide layer 100, and -OH represents surface activation. In the embodiment of the present application, an SOI wafer 500 (corresponding to the silicon photonic chip intermediate component 10) with a silicon waveguide layer 100 and a silicon nitride waveguide layer 200 is first provided, and the silicon waveguide layer 100 has a coupling structure. A silicon substrate is then bonded to the SOI wafer 500, the SOI wafer 500 is flipped over, and the original substrate layer is removed. Silicon dioxide is then deposited on the surface of the SOI wafer 500, and CMP is performed on the silicon dioxide. After polishing the silicon dioxide to the designed silicon thickness, surface activation is performed to obtain a prefabricated silicon photonic chip. At the same time, an LNOI wafer with a lithium niobate waveguide layer 300 (corresponding to a prefabricated lithium niobate chip) is also provided. Then, a layer of silicon dioxide is deposited on the LNOI wafer and polished to a designed thickness using CMP, followed by surface activation to obtain a prefabricated lithium niobate chip.

[0095] After obtaining the prefabricated silicon photonic chip and the prefabricated lithium niobate chip, the prefabricated lithium niobate chip is flipped over and bonded to the prefabricated silicon photonic chip. The substrate on the original prefabricated lithium niobate chip is thinned and removed to expose the lithium niobate waveguide layer 300. The lithium niobate waveguide layer 300 is then etched twice to form the first sub-waveguide layer 320 and the second sub-waveguide layer 310.

[0096] In some embodiments, the thickness of the silicon waveguide layer 100 is 210 nm, and the thickness of the lithium niobate waveguide layer 300 is 200 nm. The width of the second tapered waveguide segment 120 tapers from 0.5 μm to 0.15 μm, and the width of the first tapered waveguide segment 311 tapers from 0.6 μm to 1.2 μm. The coupling length between the first tapered waveguide segment 311 and the second tapered waveguide segment 120 is 58 μm, and the spacing between the first tapered waveguide segment 311 and the second tapered waveguide segment 120 is 80 nm. The coupling transmittance between the silicon waveguide layer 100 and the lithium niobate waveguide layer 300 is -0.1 dB at a wavelength of 1310 nm.

[0097] When the end edge of the first separated waveguide segment 321 deviates from the edge of the second strip waveguide segment 312 by 1.15 μm, and the length of the first separated waveguide segment 321 is 300 μm, the width of the third tapered waveguide segment 322 gradually expands from 1 μm to 1.2 μm, the width of the fourth tapered waveguide segment 313 gradually expands from 1.2 μm to 5 μm, and the lengths of the third tapered waveguide segment 322 and the fourth tapered waveguide segment 313 are 150 μm, the transmittance of the lithium niobate strip waveguide to the ridge waveguide is -0.05 dB.

[0098] See also Figure 8 , Figure 8 FIG1 shows a schematic diagram of the relationship between transmittance and alignment error provided by this embodiment; specifically, when the lithium niobate strip waveguide and the silicon nitride waveguide are perpendicular to the propagation direction, alignment error is likely to occur. Figure 8 As shown in Figure 2, when the alignment error is within ±300nm, the transmittance of the coupling structure is greater than -0.8dB. Figure 9 , Figure 9 A schematic diagram shows the relationship between transmittance and the tip width of the lithium niobate waveguide layer 300, as provided in this embodiment. It can be seen that when the tip width of the lithium niobate waveguide strip varies, the transmittance remains greater than -0.14 dB within the range of 100 nm to 1000 nm. Therefore, throughout the entire lithium niobate etched structure, the minimum feature size of the lithium niobate can be maintained above 600 nm, significantly reducing the etching precision requirements for the lithium niobate, allowing the use of relatively inexpensive contact lithography tools for photolithography.

[0099] In an embodiment, the above-mentioned back-bonded heterogeneous integrated chip can be used in data centers, 5G data backhaul, and optical communication fields.

[0100] The basic concepts have been described above. It will be apparent to those skilled in the art that the detailed disclosure above is merely illustrative and does not limit the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application and remain within the spirit and scope of the exemplary embodiments of the present application.

[0101] At the same time, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0102] Similarly, it should be noted that, in order to simplify the presentation of this application and thus facilitate understanding of one or more embodiments of the invention, the foregoing descriptions of the embodiments of this application sometimes combine multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not mean that the subject matter of this application requires more features than those recited in the claims. In fact, an embodiment may have fewer features than all of the features of a single embodiment disclosed above.

[0103] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A back-bonded heterogeneous integrated chip, characterized in that: The back-bonded heterogeneous integrated chip comprises: Silicon waveguide layer; A first silicon nitride waveguide layer is provided on the silicon waveguide layer and spaced apart from the silicon waveguide layer, and the silicon waveguide layer and the first silicon nitride waveguide layer are coupled; A lithium niobate waveguide layer is provided on a side of the silicon waveguide layer away from the first silicon nitride waveguide layer and spaced apart from the first silicon nitride waveguide layer, and the lithium niobate waveguide layer is coupled to the silicon waveguide layer; The lithium niobate waveguide layer includes a first sub-waveguide layer and a second sub-waveguide layer connected to each other, the second sub-waveguide layer is arranged on one side of the silicon waveguide layer, and the orthographic projection of the second sub-waveguide layer on the silicon waveguide layer overlaps with the silicon waveguide layer, and the first sub-waveguide layer is arranged on the side of the second sub-waveguide layer away from the lithium niobate waveguide layer.

2. The back-bonded heterogeneous integrated chip according to claim 1, characterized in that: The second sub-waveguide layer includes a first tapered waveguide segment, the silicon waveguide layer includes a second tapered waveguide segment, and an orthographic projection of the first tapered waveguide segment on the silicon waveguide layer overlaps with the second tapered waveguide segment.

3. The back-bonded heterogeneous integrated chip according to claim 2, characterized in that: The silicon waveguide layer further includes a first strip waveguide segment connected to the second tapered waveguide segment, and the second tapered waveguide segment is configured to have a tapered structure in a direction away from the first strip waveguide segment.

4. The back-bonded heterogeneous integrated chip according to claim 3, characterized in that: The second sub-waveguide layer further includes a second strip waveguide segment connected to the first tapered waveguide segment, and the second strip waveguide segment and the first strip waveguide segment extend in the same direction; The first tapered waveguide segment is configured to have a tapered structure in a direction away from the second strip waveguide segment.

5. The back-bonded heterogeneous integrated chip according to claim 4, characterized in that: The first sub-waveguide layer includes a first separated waveguide segment, an orthographic projection of the first separated waveguide segment on the silicon waveguide layer and an orthographic projection of the second strip waveguide segment on the silicon waveguide layer overlap with each other; the first separated waveguide segment and the second strip waveguide segment are arranged to intersect, and a portion of the first separated waveguide segment extends outside the area where the second strip waveguide segment is located.

6. The back-bonded heterogeneous integrated chip according to claim 5, characterized in that: The first sub-waveguide layer further includes a third tapered waveguide segment connected to the first separated waveguide segment; the second sub-waveguide layer further includes a fourth tapered waveguide segment connected to an end of the second strip waveguide segment away from the first tapered waveguide segment; an orthographic projection of the third tapered waveguide segment on the silicon waveguide layer falls within an orthographic projection of the fourth tapered waveguide segment on the silicon waveguide layer; The third tapered waveguide segment is configured to be gradually expanded along a direction away from the first separated waveguide segment; and / or the fourth tapered waveguide segment is configured to be gradually expanded along a direction away from the second strip waveguide segment.

7. The back-side bonded heterogeneous integrated chip according to claim 6, characterized in that: The first sub-waveguide layer further includes a third strip waveguide segment, the third strip waveguide segment being connected to an end of the third tapered waveguide segment away from the first separated waveguide segment; the second sub-waveguide layer further includes a fourth strip waveguide segment, the fourth strip waveguide segment being connected to an end of the fourth tapered waveguide segment away from the second strip waveguide segment; The orthographic projection of the third strip waveguide segment on the silicon waveguide layer falls within the orthographic projection of the fourth strip waveguide segment on the silicon waveguide layer, and the third strip waveguide segment and the fourth strip waveguide segment form a lithium niobate ridge waveguide structure.

8. A method for preparing a back-bonded heterogeneous integrated chip, characterized in that: The preparation method comprises: Providing a prefabricated silicon photonic chip, the prefabricated silicon photonic chip comprising the silicon waveguide layer according to any one of claims 1 to 7 and a first silicon nitride waveguide layer; Providing a prefabricated lithium niobate chip, wherein the prefabricated lithium niobate chip includes a lithium niobate layer; Bonding the prefabricated lithium niobate chip to the prefabricated silicon photonic chip, with the lithium niobate layer disposed adjacent to the silicon waveguide layer; The lithium niobate layer is etched to obtain the lithium niobate waveguide layer according to any one of claims 1 to 7.

9. The preparation method according to claim 8, characterized in that The preparation method satisfies at least one of the following conditions: Providing a prefabricated silicon photonic chip includes: A silicon photonic chip middleware is provided, wherein the silicon photonic chip middleware comprises the silicon waveguide layer according to any one of claims 1 to 8 and a first silicon nitride waveguide layer; Depositing a first silicon dioxide layer on a side of the silicon photonic chip intermediate component where the silicon waveguide layer is provided, and performing chemical mechanical polishing on the first silicon dioxide layer; performing surface activation on the first silicon dioxide layer; Providing a prefabricated lithium niobate chip includes: Providing a lithium niobate chip middleware, wherein the lithium niobate chip middleware includes a lithium niobate layer; Depositing a second silicon dioxide layer on a side of the lithium niobate chip intermediate component where the lithium niobate layer is provided, and performing chemical mechanical polishing on the second silicon dioxide layer; The second silicon dioxide layer is surface activated.

10. The preparation method according to claim 8, characterized in that The etching of the lithium niobate layer to obtain the lithium niobate waveguide layer according to any one of claims 1 to 7 comprises: removing the substrate layer on a side of the lithium niobate layer facing away from the prefabricated silicon photonic chip to expose the lithium niobate layer; The lithium niobate layer is etched at least twice to obtain a first sub-waveguide layer and a second sub-waveguide layer, thereby obtaining the lithium niobate waveguide layer according to any one of claims 1 to 7.

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