High-speed train speed pulse simulation platform

Abstract

The invention discloses a high-speed train speed pulse simulation platform, which comprises a main processor unit, an FPGA (Field Programmable Gate Array) unit and a speed pulse processing unit, and is characterized in that the main processor unit is used for receiving the advancing speed and the advancing state of a high-speed train issued by a vehicle-mounted subsystem; the FPGA unit is used for receiving the advancing speed output by the main processor unit and generating two-channel initial speed pulse signals or three-channel initial speed pulse signals according to the advancing speed; and the speed pulse processing unit carries out filtering and level conversion on the initial speed pulse signal to obtain a two-channel final speed pulse signal or a three-channel final speed pulse signal and then outputs the two-channel final speed pulse signal or the three-channel final speed pulse signal.

Description

Technical Field

[0001] The present invention belongs to the field of rail transportation technology, and in particular relates to a high-speed train speed pulse simulation platform. Background Art

[0002] With the rapid development of rail transit technology, train control systems play a vital role in ensuring driving safety and improving operational efficiency. As a crucial component of train signaling systems, the accuracy and reliability of real-time speed information for high-speed trains is directly related to safe train operation. However, speed sensors from different manufacturers have varying specifications and technical parameters, such as three-channel voltage sensors and two-channel voltage sensors, which poses a challenge in signaling system compatibility design. Furthermore, during actual train operation, speed sensors must accurately reflect train movement at various speeds, directions, and even when stopped, placing even higher demands on sensor design. Train signaling systems are safety-critical and must ensure reliable service even under the most challenging operating conditions. Therefore, identifying potential hazards and implementing appropriate protective measures are essential during the R&D phase. Given the limitations and complexity of field testing conditions, especially the difficulty of conducting tests in a real-world environment, effectively simulating a variety of possible operating scenarios becomes a key issue.

[0003] Current speed sensor simulation devices on the market often only simulate specific types or brands of products and lack full compatibility with speed sensors of various specifications and manufacturers. Furthermore, these devices often fail to fully simulate the train's speed signal output under different operating conditions, making them unable to meet the high-precision and multi-functional requirements of modern train control systems.

[0004] Therefore, there is an urgent need to develop a high-speed train speed pulse simulation platform that overcomes the above-mentioned defects. Summary of the Invention

[0005] In view of the above problems, the present invention provides a high-speed train speed pulse simulation platform, which includes:

[0006] The main processor unit is used to receive the high-speed train's travel speed and travel status from the onboard subsystem;

[0007] an FPGA unit, configured to receive the travel speed output by the main processor unit and generate a two-channel initial speed pulse signal or a three-channel initial speed pulse signal according to the travel speed;

[0008] The speed pulse processing unit filters and level-converts the initial speed pulse signal to obtain a two-channel final speed pulse signal or a three-channel final speed pulse signal and then outputs the signal.

[0009] The above-mentioned high-speed train speed pulse simulation platform, wherein the main processor unit is electrically connected to the FPGA unit through the SPI serial peripheral interface and the GPIO interface, the main processor unit transmits the travel speed to the FPGA unit through the SPI protocol, and the main processor unit also performs synchronous data exchange and reset status alarm with the FPGA unit through the GPIO interface.

[0010] The above-mentioned high-speed train speed pulse simulation platform, wherein the FPGA unit generates the initial speed pulse signal according to the travel speed trigger, and the initial speed pulse signal is a voltage-type speed pulse signal. When the initial speed pulse signals of two channels are generated, the phase difference of the initial speed pulse signals of the two channels is 90 degrees. When the initial speed pulse signals of three channels are generated, the phase difference of the initial speed pulse signals of the three channels is 120 degrees.

[0011] The above-mentioned high-speed train speed pulse simulation platform, wherein the FPGA unit generates the initial speed pulse signal according to the base frequency, the base frequency is generated by dividing the clock signal inside the FPGA unit, and the base frequency is set to n times the actual adjustment rate, where n is a positive integer.

[0012] The above-mentioned high-speed train speed pulse simulation platform, wherein, when generating the initial speed pulse signals of three channels, the initial speed pulse signal of the first channel starts synchronously with the base frequency, the initial speed pulse signal of the second channel lags 120 degrees relative to the base frequency, and the initial speed pulse signal of the third channel lags 240 degrees relative to the base frequency; when generating the initial speed pulse signals of two channels, the initial speed pulse signal of the first channel starts synchronously with the base frequency, and the initial speed pulse signal of the second channel lags 90 degrees relative to the base frequency.

[0013] The above-mentioned high-speed train speed pulse simulation platform, wherein the FPGA unit determines whether to generate the initial speed pulse signal based on the preset control strategy according to the travel state, and the FPGA unit does not respond when the travel state conforms to the preset control strategy.

[0014] The above-mentioned high-speed train speed pulse simulation platform, wherein the speed pulse processing unit includes: two speed pulse processing circuits or three speed pulse processing circuits, wherein each speed pulse processing circuit includes:

[0015] an optical coupler, one input end of which is electrically connected to the FPGA unit and receives the initial speed pulse signal of one channel output by the FPGA unit, and the optical coupler is grounded;

[0016] an internal power supply electrically connected to the other input terminal of the optocoupler via a current-limiting resistor;

[0017] a channel power supply electrically connected to the optocoupler via a first voltage-dividing resistor, an output end of the optocoupler electrically connected to one end of a second voltage-dividing resistor, and the channel power supply electrically connected to the other end of the second voltage-dividing resistor via a third voltage-dividing resistor;

[0018] Wherein, when the initial speed pulse signal is at a high level, the optocoupler is not turned on so that the output end of the optocoupler is connected to the ground, the first voltage-dividing resistor is grounded alone, and the voltage level of the output pulse signal is obtained by voltage division by the second voltage-dividing resistor and the third voltage-dividing resistor;

[0019] When the initial speed pulse signal is at a low level, the optocoupler is turned on so that the output end of the optocoupler is connected to the channel power supply, and the voltage level of the output pulse signal is obtained by dividing the voltage through the first voltage divider resistor, the second voltage divider resistor and the third voltage divider resistor.

[0020] The above-mentioned high-speed train speed pulse simulation platform, wherein the optocoupler is turned on to form an equivalent circuit in which the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and then in parallel with the third voltage-dividing resistor to obtain the voltage level of the output pulse signal.

[0021] The above-mentioned high-speed train speed pulse simulation platform, wherein the speed pulse processing circuit of each channel also includes: a filter protection circuit, one end of the filter protection circuit is electrically connected to the channel power supply, and the other end of the filter protection circuit is electrically connected to the other end of the second voltage divider resistor, and the filter protection circuit includes a low-pass filter and a transient voltage suppression diode.

[0022] The above-mentioned high-speed train speed pulse simulation platform further includes two or three speed pulse buffers, one end of each of the speed pulse buffers is electrically connected to the FPGA unit, and the other end of the speed pulse buffer is electrically connected to the speed pulse processing circuit in a one-to-one correspondence.

[0023] In summary, the present invention has the following advantages over the prior art:

[0024] The high-speed train speed pulse simulation platform of this invention not only accurately simulates the pulse waveforms of two-channel and three-channel speed sensors, but also reproduces the speed signal output characteristics of the train under various operating conditions. This innovative solution can greatly facilitate the development of train control systems, providing engineers with a more flexible and realistic testing platform, thereby improving the safety and reliability of the entire system. This type of simulation system is currently unavailable in the market and has significant application value and development prospects.

[0025] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 This is a schematic structural diagram of the high-speed train speed pulse simulation platform of the present invention;

[0028] Figure 2 for Figure 1 Schematic diagram of the speed pulse processing circuit;

[0029] Figure 3 Schematic diagram of the strategy for generating speed pulses for the FPGA unit;

[0030] Figure 4 Schematic diagram of the control strategy of the FPGA unit. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0032] The exemplary embodiments of the present invention and their description are used to explain the present invention, but are not intended to limit the present invention. In addition, elements / components with the same or similar reference numerals used in the drawings and embodiments are used to represent the same or similar parts.

[0033] The terms “first,” “second,” “S1,” “S2,” etc. used herein do not specifically refer to an order or sequence, nor are they intended to limit the present invention. They are merely used to distinguish elements or operations described with the same technical terms.

[0034] The directional terms used herein, such as up, down, left, right, front, or back, are only used to refer to the directions in the accompanying drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0035] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0036] As used herein, "and / or" includes any and all combinations of the items mentioned.

[0037] Regarding "plurality" in this document, "plurality" includes "two" and "more than two"; regarding "plurality groups" in this document, "plurality groups" includes "two groups" and "more than two groups".

[0038] As used herein, the terms "substantially" and "approximately" are used to modify any quantity or error that may vary slightly, but such variation or error does not alter the essence of the quantity. Generally speaking, the range of such variation or error modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. Those skilled in the art will appreciate that the aforementioned values ​​may be adjusted based on actual needs and are not intended to be limiting.

[0039] Certain terms used to describe the present application are discussed below, or elsewhere in this specification, to provide additional guidance to those skilled in the art regarding the description of the present application.

[0040] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of the high-speed train speed pulse simulation platform of the present invention. Figure 1As shown, a high-speed train speed pulse simulation platform 1 of the present invention includes: a main processor unit 11, an FPGA unit 12, a speed pulse processing unit 13 and a speed pulse buffer 14. The main processor unit 11 is used to receive the travel speed and travel status of the high-speed train issued by the on-board subsystem; the FPGA unit 12 is used to receive the travel speed output by the main processor unit 11 and generate a two-channel initial speed pulse signal or a three-channel initial speed pulse signal according to the travel speed; the initial speed pulse signal of each channel is transmitted to the speed pulse processing unit 13 through a speed pulse buffer 14; the speed pulse processing unit 13 filters and level-converts the initial speed pulse signal to obtain a two-channel final speed pulse signal or a three-channel final speed pulse signal and then outputs it.

[0041] In this embodiment, the present invention utilizes a domestically produced FPGA as the core control component in FPGA unit 12, achieving high-precision simulation of the speed sensor's output signal. The use of a domestically produced FPGA not only reduces the overall system cost but also ensures convenient and timely technical support, which is of great significance to the development of the domestic rail transit industry. The use of a domestically produced FPGA provides the system with sufficient logic resources and flexibility, enabling efficient processing of complex signal generation tasks and meeting the needs of diverse application scenarios.

[0042] Among them, the main processor unit 11 is electrically connected to the FPGA unit 12 through the SPI serial peripheral interface and the GPIO interface. The main processor unit 11 transmits the travel speed to the FPGA unit 12 through the SPI protocol. The main processor unit 11 also performs synchronous data exchange and reset status alarm with the FPGA unit 12 through the GPIO interface.

[0043] Specifically, if Figure 1 As shown in the figure, the onboard subsystem, shown on the far right, consists of three main components: the onboard ATP (Automatic Train Protection), the onboard ATO (Automatic Train Operation), and the onboard ATS. These subsystems communicate via 100M Ethernet, providing the speed pulse simulation platform with the train's intended speed and direction. The 100M Ethernet port ensures high-speed data transmission and real-time processing.

[0044] The speed pulse simulation platform's main processor unit 11 receives the high-speed train's travel speed from the onboard subsystem and communicates with the FPGA unit 12 via the SPI serial peripheral interface. The speed value is transmitted to the FPGA unit 12 using the SPI protocol. The main processor unit 11 also synchronizes data with the FPGA through GPIO, enabling precise control and processing of speed signals, such as reset and set status alarms. The core control unit of the FPGA unit 12 is responsible for processing and generating speed pulse signals. Upon receiving instructions from the main processor unit 11, the FPGA unit 12 triggers three or two voltage-type speed pulse signals. The speed pulse simulation platform then transmits pulses simulating real-world speed sensors to the speed acquisition platform, which includes two master control units (MPUs): Master MPU1 and Master MPU2. These two master control units are connected to the speed pulse simulation platform via a speed pulse processing circuit to receive and process the speed pulse signals. Master MPU1 and Master MPU2 exchange data with the speed pulse processing circuit via their respective interfaces, ensuring accurate signal acquisition and processing. The dual MPUs provide 2-out-of-2 redundancy for collected speed data, ensuring data reliability. The speed acquisition platform, speed pulse simulation platform, and onboard subsystem each utilize independent power modules to provide stable power to the three platforms, ensuring proper operation under various operating conditions. This series of modules and interfaces enables the speed pulse simulation platform system to accurately simulate the speed pulses of two-channel and three-channel speed sensors and reproduce the speed signal output characteristics of the train under various operating conditions, providing strong support for the design and testing of train control systems.

[0045] Please refer to Figure 2 , Figure 2 for Figure 1 The schematic diagram of the speed pulse processing circuit in FIG. Figure 2As shown, the speed pulse processing unit 12 includes: two-way speed pulse processing circuits or three-way speed pulse processing circuits, wherein each of the speed pulse processing circuits includes: an optocoupler 131, an internal power supply 132, and a channel power supply 133. An input end of the optocoupler 131 is electrically connected to the FPGA unit 12 and receives the initial speed pulse signal of a channel output by the FPGA unit 12, and the optocoupler 12 is grounded; the internal power supply 132 is electrically connected to the other input end of the optocoupler 131 through a current-limiting resistor R; the channel power supply 133 is electrically connected to the optocoupler 131 through a first voltage-dividing resistor R1, and the output end of the optocoupler 131 is electrically connected to one end of the second voltage-dividing resistor R2, and the channel power supply 133 is electrically connected to the other end of the second voltage-dividing resistor R2 through a third voltage-dividing resistor R3. ; One end of each speed pulse buffer 14 is electrically connected to the FPGA unit 12, and the other end of the speed pulse buffer 14 is electrically connected to the optocoupler 131 of the speed pulse processing circuit in a one-to-one correspondence; wherein, when the initial speed pulse signal is at a high level, the optocoupler 131 is not conducted so that the output end of the optocoupler is connected to the ground, the first voltage-dividing resistor R1 is grounded alone, and the voltage level of the output pulse signal is obtained by voltage division by the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3; when the initial speed pulse signal is at a low level, the optocoupler 131 is conducted so that the output end of the optocoupler 131 is connected to the channel power supply 133, and the voltage level of the output pulse signal is obtained by voltage division by the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3.

[0046] In this embodiment, the optocoupler 131 is turned on, and an equivalent circuit is formed by the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3, in which the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected in series and then in parallel with the third voltage-dividing resistor R3 to obtain the voltage level of the output pulse signal.

[0047] It should be noted that, in this embodiment, it is a preferred implementation to use the internal power supply 132 as DC3.3V and the channel power supply 133 as DC15V.

[0048] Furthermore, the speed pulse processing circuit of each channel also includes: a filter protection circuit 134, one end of the filter protection circuit 134 is electrically connected to the channel power supply 133, and the other end of the filter protection circuit 134 is electrically connected to the other end of the second voltage divider resistor R2, and the filter protection circuit includes a low-pass filter and a transient voltage suppression diode.

[0049] Specifically, in this embodiment, the circuit design for processing speed pulse signals is centered around an FPGA unit, responsible for generating three independent speed pulse signals. These signals first pass through a specially designed buffer and are then connected to a push-pull high-speed optocoupler, thereby achieving signal isolation, shaping, and enhanced drive capability. This design places particular emphasis on reducing noise sensitivity, ensuring signal integrity, and improving the overall performance and reliability of the system. When the FPGA outputs a high level of 3.3V, the light-emitting diode (LED) inside the optocoupler does not conduct, so the output of the optocoupler is connected to ground, forming a simple loop in which the voltage divider resistor R1 is grounded alone, having no effect on the output speed pulse signal. At this point, the voltage level of the output pulse signal is obtained by dividing the power supply through the voltage divider resistors R2 and R3. Conversely, when the FPGA outputs a low level (near 0V), the LED in the optocoupler conducts, causing the optocoupler's transistor to also conduct, connecting its output to the power supply. At this point, the equivalent circuit becomes a circuit in which the voltage divider resistors R1 and R2 are connected in series and then in parallel with the voltage divider resistor R3.

[0050] This design constructs two different current paths for voltage division through the conduction state change of the optocoupler, thereby obtaining the speed pulse signal value in the form of analog voltage.

[0051] To further enhance system stability and safety, filtering and protection measures are incorporated into the circuit. The filtering component uses a low-pass filter to eliminate high-frequency noise and ensure signal purity. Meanwhile, the protection component integrates transient voltage suppressor (TVS) diodes to prevent damage caused by voltage transients, overcurrent, and reverse voltage. These measures work together to not only improve signal quality but also enhance the system's robustness against external interference.

[0052] Please refer to Figure 3 , Figure 3 Schematic diagram of the speed pulse strategy generated by the FPGA unit. Figure 3As shown, the FPGA unit 12 generates the initial speed pulse signal based on the travel speed trigger. The initial speed pulse signal is a voltage-type speed pulse signal. When generating two channels of the initial speed pulse signal, the phase difference between the two channels is 90 degrees. When generating three channels of the initial speed pulse signal, the phase difference between the three channels is 120 degrees. The FPGA unit 12 generates the initial speed pulse signal based on a base frequency. The base frequency is generated by dividing the clock signal within the FPGA unit 12. The base frequency is set to n times the actual adjustment rate, where n is a positive integer. When generating the initial speed pulse signal of three channels, the initial speed pulse signal of the first channel starts synchronously with the fundamental frequency, the initial speed pulse signal of the second channel lags 120 degrees relative to the fundamental frequency, and the initial speed pulse signal of the third channel lags 240 degrees relative to the fundamental frequency; when generating the initial speed pulse signal of two channels, the initial speed pulse signal of the first channel starts synchronously with the fundamental frequency, and the initial speed pulse signal of the second channel lags 90 degrees relative to the fundamental frequency.

[0053] Specifically, the present invention proposes a three-channel or two-channel velocity pulse simulation strategy based on a reference frequency, aiming to achieve precise speed control through phase delay. The core of this method lies in setting the base frequency to 1000 times the actual adjustment rate. This multiple is chosen to ensure that the three-channel waveforms maintain consistent changes in the face of frequency fluctuations and minimize the phase impact of the rising and falling edges of non-periodic velocity pulses. However, for simplicity, the schematic diagram uses a 12x ratio as the demonstration scale. The base frequency is generated by dividing the 25MHz clock signal within the FPGA. When the train is running at a constant speed, the velocity pulse of the first channel starts synchronously with the base frequency, while the second channel lags 120 degrees relative to the base frequency, and the third channel lags 240 degrees. This creates a three-channel velocity pulse waveform with a phase difference of 120 degrees. In the two-channel case, the second channel lags 90 degrees relative to the base frequency. During train acceleration or deceleration, since the frequency adjustment is based on 1000 times the base frequency, the impact of sudden frequency changes on the signal is virtually eliminated, ensuring the continuity and accuracy of the base frequency calculation after acceleration. When two speed pulses are used, the phase difference is 90 degrees. When three speed pulses are used, the phase difference is 120 degrees. Each speed pulse passes through a buffer and enters the speed pulse processing circuit. The speed pulse processing circuit filters and level-converts the speed pulses sent by the FPGA, converting them into speed pulses with a high voltage of 1.4V and a low voltage of 0.7V, the same voltage values ​​as those sent by the speed sensor.

[0054] To precisely control the frequency variation of the output signal, the present invention introduces a reference frequency adjustment mechanism. This mechanism uses one period of the reference frequency as the minimum time unit and delays the minimum time unit by a corresponding number of units based on the input phase delay command. This method allows the system to adjust the frequency of the output signal with extremely high resolution (e.g., 1 Hz), thereby achieving accurate simulation of the train's operating speed. By precisely controlling the reference frequency and phase delay, the system can provide stable and accurate signal output in various operating modes, ensuring high reliability of the simulation results.

[0055] Please refer to Figure 4 , Figure 4 Figure 1 is a schematic diagram of the control strategy of the FPGA unit. Figure 4 As shown, the FPGA unit 12 determines whether to generate the initial speed pulse signal according to the travel state based on a preset control strategy. When the travel state conforms to the preset control strategy, the FPGA unit 12 does not respond.

[0056] Specifically, the preset control strategy design includes a state machine to manage the logical flow under different operating states, covering reset, wait, forward, stop, and reverse states. Each state corresponds to a different execution strategy: in the reset state, all pulses are set to a low level; the wait state provides a transition period from reset to establishing the phase difference; in the forward state, the three speed pulses are dynamically adjusted in real time according to the base frequency; the stopped state maintains the current timing unchanged so that the existing phase can be continued for calculation at the next start; and the reverse state counts back one cycle in the stopped state to ensure that the speed pulse can be restored to the initial value when restarting. This series of mechanisms works together to ensure the safety and stability of train operation. The states of the above state machines cannot be switched arbitrarily and must be judged according to certain conditions.

[0057] For example, before the FPGA unit 12 generates the initial speed pulse signal, it will make a judgment based on the current travel status of the train through a preset control strategy. For example, when the train is in a forward state, only a stop command or a reset command will trigger the FPGA unit 12 to generate the initial speed pulse signal. If a wait command or a reverse command is received, the FPGA unit 12 will not respond.

[0058] Based on the operational characteristics of real-world vehicles, this paper has designed a concise and efficient state transition process. This process accurately reflects the train's velocity pulses under various operating conditions, including acceleration, deceleration, constant speed, and parking. Specifically, the system monitors and responds to changes in actual operating parameters, dynamically adjusting its internal state to ensure the authenticity and reliability of the simulation. Furthermore, this state transition mechanism takes into account various possible operational scenarios, including abnormal conditions such as emergency braking or failures, thereby improving the system's adaptability and robustness.

[0059] In summary, the beneficial effects of the present invention are as follows:

[0060] 1. High-precision simulation of output signals of various speed sensors

[0061] The circuit design developed in this research is capable of simulating the output signals of a variety of train speed sensors, including two-channel and three-channel configurations. This system accurately simulates speed pulses in various operating modes, including acceleration, deceleration, constant speed travel, and parking, ensuring comprehensive and flexible simulation. Notably, this design achieves a resolution of 1 Hz, with the specific speed accuracy depending on the selected sensor model, providing a reliable testing platform for diverse application scenarios.

[0062] 2. Application advantages of domestic FPGA

[0063] By selecting domestically produced FPGAs as core components, this research not only significantly reduced hardware costs but also made technical support more readily available. This not only promoted the development of the domestic rail transit industry but also provided a more cost-effective option for the research and development of related technologies. The use of domestically produced FPGAs is of great significance in promoting localized technological innovation and support.

[0064] 3. Simple and efficient simulation mechanism

[0065] This design combines fundamental frequency adjustment with an efficient state transition mechanism to accurately simulate train operation. This mechanism simplifies the speed sensor signal generation process while improving simulation efficiency. Through precise control of frequency and state, this method provides a simple yet effective solution suitable for a variety of complex train operation scenarios.

[0066] 4. Widespread application in signal system research and development

[0067] This invention can simulate not only normal train operation but also abnormal operating conditions, such as emergency braking or fault conditions. This comprehensive simulation capability effectively meets the needs of signaling system research and development, helping to improve system reliability and safety. Furthermore, it provides researchers with a valuable research tool for evaluating and optimizing the design and performance of train control systems.

[0068] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed train speed pulse simulation platform, characterized in that: include: The main processor unit is used to receive the high-speed train's travel speed and travel status from the onboard subsystem; an FPGA unit, configured to receive the travel speed output by the main processor unit and generate a two-channel initial speed pulse signal or a three-channel initial speed pulse signal according to the travel speed; The speed pulse processing unit filters and level-converts the initial speed pulse signal to obtain a two-channel final speed pulse signal or a three-channel final speed pulse signal and then outputs the signal.

2. The high-speed train speed pulse simulation platform according to claim 1, characterized in that: The main processor unit is electrically connected to the FPGA unit through the SPI serial peripheral interface and the GPIO interface. The main processor unit transmits the travel speed to the FPGA unit through the SPI protocol. The main processor unit also performs synchronous data exchange and reset status alarm with the FPGA unit through the GPIO interface.

3. The high-speed train speed pulse simulation platform according to claim 1, characterized in that: The FPGA unit generates the initial speed pulse signal according to the travel speed trigger. The initial speed pulse signal is a voltage-type speed pulse signal. When the initial speed pulse signals of two channels are generated, the phase difference between the initial speed pulse signals of the two channels is 90 degrees. When the initial speed pulse signals of three channels are generated, the phase difference between the initial speed pulse signals of the three channels is 120 degrees.

4. The high-speed train speed pulse simulation platform according to claim 3, characterized in that: The FPGA unit generates the initial speed pulse signal according to the base frequency, and the base frequency is generated by dividing the clock signal inside the FPGA unit. The base frequency is set to n times the actual adjustment rate, where n is a positive integer.

5. The high-speed train speed pulse simulation platform according to claim 4, characterized in that: When generating the initial speed pulse signal of three channels, the initial speed pulse signal of the first channel starts synchronously with the fundamental frequency, the initial speed pulse signal of the second channel lags 120 degrees relative to the fundamental frequency, and the initial speed pulse signal of the third channel lags 240 degrees relative to the fundamental frequency; when generating the initial speed pulse signal of two channels, the initial speed pulse signal of the first channel starts synchronously with the fundamental frequency, and the initial speed pulse signal of the second channel lags 90 degrees relative to the fundamental frequency.

6. The high-speed train speed pulse simulation platform according to claim 3, characterized in that: The FPGA unit determines whether to generate the initial speed pulse signal according to the travel state based on a preset control strategy, and the FPGA unit does not respond when the travel state complies with the preset control strategy.

7. The high-speed train speed pulse simulation platform according to claim 4, characterized in that: The speed pulse processing unit includes: two speed pulse processing circuits or three speed pulse processing circuits, wherein each speed pulse processing circuit includes: an optical coupler, one input end of which is electrically connected to the FPGA unit and receives the initial speed pulse signal of one channel output by the FPGA unit, and the optical coupler is grounded; an internal power supply electrically connected to the other input terminal of the optocoupler via a current-limiting resistor; a channel power supply electrically connected to the optocoupler via a first voltage-dividing resistor, an output end of the optocoupler electrically connected to one end of a second voltage-dividing resistor, and the channel power supply electrically connected to the other end of the second voltage-dividing resistor via a third voltage-dividing resistor; Wherein, when the initial speed pulse signal is at a high level, the optocoupler is not turned on so that the output end of the optocoupler is connected to the ground, the first voltage-dividing resistor is grounded alone, and the voltage level of the output pulse signal is obtained by voltage division by the second voltage-dividing resistor and the third voltage-dividing resistor; When the initial speed pulse signal is at a low level, the optocoupler is turned on so that the output end of the optocoupler is connected to the channel power supply, and the voltage level of the output pulse signal is obtained by dividing the voltage through the first voltage divider resistor, the second voltage divider resistor and the third voltage divider resistor.

8. The high-speed train speed pulse simulation platform according to claim 7, characterized in that: When the optocoupler is turned on, an equivalent circuit is formed by the first voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor, in which the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series and then in parallel with the third voltage-dividing resistor to obtain the voltage level of the output pulse signal.

9. The high-speed train speed pulse simulation platform according to claim 7, characterized in that: The speed pulse processing circuit of each channel also includes: a filter protection circuit, one end of the filter protection circuit is electrically connected to the channel power supply, and the other end of the filter protection circuit is electrically connected to the other end of the second voltage divider resistor, and the filter protection circuit includes a low-pass filter and a transient voltage suppression diode.

10. The high-speed train speed pulse simulation platform according to claim 1, characterized in that: It also includes two or three speed pulse buffers, one end of each of the speed pulse buffers is electrically connected to the FPGA unit, and the other end of the speed pulse buffer is electrically connected to the speed pulse processing circuit in a one-to-one correspondence.

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