LDO circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of circuits, and discloses an LDO circuit, a chip and electronic equipment. The LDO circuit comprises a current bias circuit, a driving circuit, a reference circuit and a power circuit, the current bias circuit comprises a current unit and a control unit, the first end of the current unit is used for being connected with the first end of the reference circuit, the first end of the power circuit and the power supply end, the second end of the current unit is connected with the first end of the control unit, and the second end of the control unit is connected with the first end of the drive circuit. The third end of the control unit is connected with the second end of the power circuit; the second end of the driving circuit is connected with the second end of the reference circuit; the third end of the power circuit is connected with the output end of the LDO circuit; when the voltage difference value between the power supply voltage of the power supply end and the voltage of the output end is smaller than a first voltage threshold value, the driving circuit is in a conducting state, and the current unit outputs fixed bias current to the control unit. Therefore, the discharge speed of the battery is reduced, and the damage to the battery is reduced.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an LDO circuit, chip, and electronic device. Background Art

[0002] In integrated circuit applications, circuits with a low-dropout linear regulator (LDO) structure (hereinafter referred to as LDO circuits) are widely used in power management chips to power subsequent circuits due to their low cost, simple structure, and ease of integration. During stable operation, LDO circuits, through components such as op amps and power dissipators, ensure that when the power supply voltage VDD varies within a certain range, a stable output voltage VOUT is maintained, serving as the power supply voltage for subsequent circuits, thus ensuring the stability of these circuits. Therefore, a high-quality LDO circuit should exhibit a high power supply rejection ratio (PSRR) and strong stability.

[0003] During normal operation of an LDO circuit, if the power supply voltage VDD drops to a zero or even negative voltage difference with the output voltage VOUT, a large quiescent current will be generated in the LDO circuit. In this case, if the battery is supplying power to the LDO circuit, the large quiescent current will accelerate the battery discharge rate, causing damage to the battery. Summary of the Invention

[0004] The present application provides an LDO circuit, a chip, and an electronic device.

[0005] In a first aspect, the present application provides an LDO circuit, which includes a current bias circuit, a drive circuit, a reference circuit, and a power circuit; the current bias circuit includes a current unit and a control unit, wherein the first end of the current unit is used to connect to the first end of the reference circuit, the first end of the power circuit, and the power supply end, the second end of the current unit is connected to the first end of the control unit, the second end of the control unit is connected to the first end of the drive circuit, and the third end of the control unit is connected to the second end of the power circuit; the second end of the drive circuit is connected to the second end of the reference circuit, the third end of the drive circuit is grounded, the third end of the reference circuit is grounded, and the reference circuit is used to output a reference current; the third end of the power circuit is connected to the output end of the LDO circuit; wherein, when the voltage difference between the power supply voltage at the power supply end and the voltage at the output end of the LDO circuit is less than a first voltage threshold, the drive circuit is in an on state, and the current unit outputs a fixed bias current to the control unit.

[0006] Based on the LDO circuit provided in the embodiment of the present application, by adding a current bias circuit, during circuit operation, when the power supply voltage VDD of the LDO circuit decreases and the voltage difference between the power supply voltage VDD and the output voltage VOUT decreases to a first voltage threshold, the current unit provides a fixed bias current to the control unit, so that the current of the control unit is controlled at the fixed bias current provided by the current unit, so that the current in the LDO circuit no longer increases. This can effectively reduce the static power consumption of the LDO circuit, and is conducive to reducing the battery discharge rate and reducing damage to the battery.

[0007] In a possible implementation of the first aspect above, the LDO circuit further includes a voltage divider sampling circuit, a first switching circuit, and a second switching circuit; a first end of the first switching circuit is respectively connected to the first end of the current unit, the power supply end, the first end of the power circuit, and the first end of the second switching circuit, and a second end of the first switching circuit is connected to the first end of the reference circuit; a second end of the second switching circuit is respectively connected to the second end of the power circuit and the third end of the control unit; a first end of the voltage divider sampling circuit is respectively connected to the third end of the power circuit and the output end of the LDO circuit; a second end of the voltage divider sampling circuit is connected to the fourth end of the reference circuit, and a third end of the voltage divider sampling circuit is connected to the third end of the reference circuit.

[0008] In a possible implementation of the first aspect above, the current unit includes a first transistor, and the control unit includes a first P-type enhancement tube; the source of the first transistor is respectively connected to the first end of the first switching circuit, the first end of the second switching circuit, the first end of the power circuit, and the power supply end, and the drain of the first transistor is connected to the source of the first P-type enhancement tube; the drain of the first P-type enhancement tube is respectively connected to the gate of the first P-type enhancement tube and the first end of the drive circuit, and the gate of the first P-type enhancement tube is connected to the second end of the power circuit.

[0009] In a possible implementation of the first aspect above, the first transistor is an enhancement transistor, and a gate of the first transistor is used to receive a first bias voltage signal.

[0010] In a possible implementation of the first aspect above, the first transistor is a switching tube, the current unit also includes a second switching tube and a third switching tube, the gate of the first transistor is used to receive the first enable signal; the source of the second switching tube is respectively connected to the source of the first transistor, the first end of the first switching circuit, the first end of the second switching circuit, the first end of the power circuit, and the power supply end; the drain of the second switching tube is connected to the source of the third switching tube, and the gate of the second switching tube is used to receive the second bias voltage signal; the drain of the third switching tube is respectively connected to the drain of the first P-type enhancement tube and the first end of the drive circuit, and the gate of the third switching tube is used to receive the second enable signal.

[0011] In a possible implementation of the first aspect above, the drive circuit includes a sixth N-type enhancement tube, and the reference circuit includes an N-type power transistor and a seventh N-type enhancement tube; the drain of the sixth N-type enhancement tube is connected to the drain of the first P-type enhancement tube, the gate of the sixth N-type enhancement tube is respectively connected to the drain of the seventh N-type enhancement tube and the source of the N-type power transistor, and the source of the sixth N-type enhancement tube is grounded; the drains of the N-type power transistors are respectively connected to the second end of the first switching circuit, the gate of the N-type power transistor is short-circuited with the source of the N-type power transistor; the gate of the seventh N-type enhancement tube is connected to the second end of the voltage divider sampling circuit, and the source of the seventh N-type enhancement tube is grounded.

[0012] In a possible implementation of the first aspect above, the voltage divider sampling circuit includes a third resistor and a fourth resistor, the first switching circuit includes a fifth switching tube, and the second switching circuit includes a sixth switching tube; the first end of the third resistor is respectively connected to the third end of the power circuit and the output end of the LDO circuit, the second end of the third resistor is respectively connected to the first end of the fourth resistor and the gate of the seventh N-type enhancement tube; the second end of the fourth resistor is respectively connected to the source of the sixth N-type enhancement tube and the source of the seventh N-type enhancement tube; the drain of the fifth switching tube is connected to the drain of the N-type power transistor, the source of the fifth switching tube is respectively connected to the source of the first transistor, the source of the sixth switching tube, the first end of the power circuit, and the power supply end; the gate of the fifth switching tube is used to receive a third enable signal; the drain of the sixth switching tube is respectively connected to the second end of the power circuit and the gate of the first P-type enhancement tube; and the gate of the sixth switching tube is used to receive a fourth enable signal.

[0013] In a possible implementation of the first aspect above, the power circuit includes a first P-type power tube; the source of the first P-type power tube is respectively connected to the source of the fifth switching tube, the source of the first transistor, the source of the sixth switching tube, and the power supply end; the gate of the first P-type power tube is respectively connected to the drain of the sixth switching tube and the gate of the first P-type enhancement tube; and the drain of the first P-type power tube is respectively connected to the first end of the third resistor and the output end of the LDO circuit.

[0014] In a possible implementation of the first aspect above, the LDO circuit includes a comparator circuit and an inverter circuit; a negative input terminal of the comparator circuit is connected to a power supply terminal, a positive input terminal of the comparator circuit is connected to an output terminal of the LDO circuit, and an output terminal of the comparator circuit is connected to an input terminal of the inverter circuit.

[0015] In a possible implementation of the first aspect, the comparator circuit includes a first resistor, a second resistor, a first N-type enhancement transistor, a second N-type enhancement transistor, a third N-type enhancement transistor, a fourth N-type enhancement transistor, a fifth N-type enhancement transistor, a second P-type enhancement transistor, a third P-type enhancement transistor, a first inverter, a second inverter, and a third inverter; a first end of the first resistor is connected to a power supply terminal, and a second end of the first resistor is connected to a source of the third P-type enhancement transistor; a first end of the second resistor is connected to an output terminal of the LDO circuit, and a second end of the second resistor is connected to a source of the second P-type enhancement transistor; a drain of the second P-type enhancement transistor and a gate of the third P-type enhancement transistor are respectively connected to the gate of the second P-type enhancement transistor, and the drain of the second P-type enhancement transistor is connected to the drain of the second N-type enhancement transistor; and a drain of the third P-type enhancement transistor is respectively connected to a drain of the third N-type enhancement transistor, a drain of the fifth N-type enhancement transistor, and an input terminal of the first inverter; The source of the first N-type enhancement tube, the source of the second N-type enhancement tube, the source of the third N-type enhancement tube, and the source of the fourth N-type enhancement tube are connected to each other; the gate of the first N-type enhancement tube, the gate of the second N-type enhancement tube, the gate of the third N-type enhancement tube, and the gate of the fourth N-type enhancement tube are connected to each other; the gate of the first N-type enhancement tube is connected to the drain of the first N-type enhancement tube; the drain of the third N-type enhancement tube is connected to the input end of the first inverter; the drain of the fourth N-type enhancement tube is connected to the source of the fifth N-type enhancement tube; the drain of the fifth N-type enhancement tube is connected to the input end of the first inverter, and the gate of the fifth N-type enhancement tube is used to receive a first enable signal; the output end of the first inverter is connected to the input end of the second inverter; the output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter is connected to the input end of the inverter circuit, and the output end of the third inverter is used to output the first enable signal.

[0016] In a possible implementation of the first aspect, the inverter circuit includes a fourth inverter, an input end of the fourth inverter is connected to an output end of the third inverter, and an output end of the fourth inverter is used to output the second enable signal.

[0017] In a possible implementation of the first aspect, the comparator circuit includes an eighth N-type enhancement tube, a ninth N-type enhancement tube, a tenth N-type enhancement tube, a fifth P-type enhancement tube, a sixth P-type enhancement tube, a seventh P-type enhancement tube, an eighth P-type enhancement tube, a first inverter, a second inverter, and a third inverter; the source of the fifth P-type enhancement tube is respectively connected to the drain of the seventh P-type enhancement tube and the source of the sixth P-type enhancement tube, the drain of the fifth P-type enhancement tube is respectively connected to the drain of the ninth N-type enhancement tube and the gate of the tenth N-type enhancement tube, and the gate of the fifth P-type enhancement tube is connected to the power supply terminal; the drain of the sixth P-type enhancement tube is respectively connected to the gate of the eighth N-type enhancement tube, the drain of the eighth N-type enhancement tube, the drain of the seventh P-type enhancement tube, the drain of the eighth N ... The gates of the ninth N-type enhancement tube are connected, and the gate of the sixth P-type enhancement tube is connected to the output end of the LDO circuit; the source of the seventh P-type enhancement tube is respectively connected to the power supply end and the source of the eighth P-type enhancement tube, and the gate of the seventh P-type enhancement tube is connected to the gate of the eighth P-type enhancement tube; the drain of the eighth P-type enhancement tube and the drain of the tenth N-type enhancement tube are respectively connected to the input end of the first inverter; the source of the eighth N-type enhancement tube is respectively connected to the source of the ninth N-type enhancement tube and the source of the tenth N-type enhancement tube; the output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter is connected to the input end of the inverter circuit, and the output end of the third inverter is used to output a first enable signal.

[0018] In a second aspect, the present application provides a chip, which includes the LDO circuit mentioned in the first aspect.

[0019] In a third aspect, the present application provides an electronic device comprising the chip mentioned in the second aspect.

[0020] The beneficial effect of the present application is as follows: during the operation of the LDO circuit, when the power supply voltage VDD of the LDO circuit drops and the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to a first voltage threshold, the quiescent current in the LDO circuit is controlled to be a fixed bias current in the current bias circuit, so that the current in the LDO circuit no longer increases, thereby effectively reducing the quiescent power consumption of the LDO circuit, and facilitating the reduction of the battery discharge rate and the reduction of damage to the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 According to the prior art, a schematic diagram of the structure of an LDO circuit is shown;

[0022] Figure 2 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit is shown;

[0023] Figure 3 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit is shown;

[0024] Figure 4A According to some embodiments of the present application, a structural schematic diagram of an LDO circuit is shown;

[0025] Figure 4B According to some embodiments of the present application, a structural schematic diagram of an LDO circuit is shown;

[0026] Figure 5 According to some embodiments of the present application, a structural schematic diagram of an LDO circuit is shown;

[0027] Figure 6 According to some embodiments of the present application, a schematic structural diagram of a comparator circuit is shown;

[0028] Figure 7 According to some embodiments of the present application, a schematic structural diagram of a comparator circuit is shown. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0030] like Figure 1 FIG2 is a schematic diagram of the structure of an LDO circuit. LDO circuit 10 may include: a third resistor R1, a fourth resistor R2, a first P-type power transistor MP1, a first P-type enhancement transistor MP2, a sixth switching transistor MP3, a fifth switching transistor MP4, an N-type power transistor DN1, a seventh N-type enhancement transistor MN1, and a sixth N-type enhancement transistor MN2.

[0031] In some optional embodiments, the LDO circuit 10 has a power supply terminal that can be connected to a battery, and the battery provides a power supply voltage VDD to the LDO circuit 10. The LDO circuit 10 has an output terminal that is connected to the input terminal of a subsequent circuit, and the output terminal voltage VOUT of the LDO circuit 10 is used as the input voltage of the subsequent circuit to power the subsequent circuit.

[0032] In some optional embodiments, the source of the fifth switch tube MP4 is respectively connected to the power supply end, the source of the first P-type enhancement tube MP2, the source of the sixth switch tube MP3, and the source of the first P-type power tube MP1; the drain of the fifth switch tube MP4 is connected to the drain of the N-type consumption tube DN1; and the gate of the fifth switch tube MP4 is used to receive the third enable signal ENB.

[0033] The drain of the first P-type enhancement transistor MP2 and the gate of the first P-type enhancement transistor MP2 form a diode connection, which can improve the stability of the LDO circuit 10. The drain of the first P-type enhancement transistor MP2 is connected to the drain of the sixth N-type enhancement transistor MN2, and the gate of the first P-type enhancement transistor MP2 is connected to the gate of the first P-type power transistor MP1 and the drain of the sixth switching transistor MP3.

[0034] The gate of the sixth switch tube MP3 is configured to receive a fourth enable signal EN.

[0035] The drain of the first P-type power transistor MP1 is connected to the first end of the third resistor R1 and the output end of the LDO circuit 10 respectively.

[0036] The gate and source of the N-type power transistor DN1 are short-circuited to provide a reference current to the LDO circuit 10. The source of the N-type power transistor DN1 is connected to the drain of the seventh N-type enhancement transistor MN1 and the gate of the sixth N-type enhancement transistor MN2.

[0037] The source of the seventh N-type enhancement transistor MN1 is grounded, and the gate of the seventh N-type enhancement transistor MN1 is connected to the second end of the third resistor R1.

[0038] The source of the sixth N-type boost transistor MN2 is connected to the source of the seventh N-type boost transistor MN1.

[0039] The second end of the third resistor R1 is connected to the first end of the fourth resistor R2 , and the second end of the fourth resistor R2 is connected to the source of the seventh N-type enhancement transistor MN1 .

[0040] In some optional embodiments, the voltage at the second end of the third resistor R1 can be recorded as the feedback voltage VFB. Therefore, in the LDO circuit 10, the output voltage VOUT and the feedback voltage VFB satisfy VOUT=VFB×(R1+R2) / R2.

[0041] In some optional embodiments, when the fourth enable signal EN received by the gate of the sixth switch transistor MP3 is at a high level and the third enable signal ENB received by the gate of the fifth switch transistor MP4 is at a low level, the LDO circuit 10 is turned on. When the fourth enable signal EN received by the gate of the sixth switch transistor MP3 is at a low level and the third enable signal ENB received by the gate of the fifth switch transistor MP4 is at a high level, the LDO circuit 10 is turned off.

[0042] The working principle of the LDO circuit 10 provided in the embodiment of the present application is described below with reference to the accompanying drawings.

[0043] In some optional embodiments, the operating principle of the LDO circuit 10 may include: when the fourth enable signal EN received by the gate of the sixth switch MP3 is at a high level, and the third enable signal ENB received by the gate of the fifth switch MP4 is at a low level, the LDO circuit 10 is activated. The gate and source of the N-type power transistor DN1 are short-circuited, providing a reference current to the LDO circuit 10. This reference current can flow from the N-type power transistor DN1 to the seventh N-type power transistor MN1. At this time, the gate voltage of the seventh N-type power transistor MN1 is zero, that is, the feedback voltage VFB is zero, and the current in the seventh N-type power transistor MN1 is zero. Furthermore, the gate voltage V1 of the sixth N-type power transistor MN2 gradually increases, turning on the sixth N-type power transistor MN2, causing the gate voltage V2 of the first P-type power transistor MP1 to decrease. As a result, the first P-type power transistor MP1 is turned on, and the output voltage VOUT gradually increases to a steady-state value, and the LDO circuit 10 is in normal operation. At this time, the feedback voltage VFB is stable, and the current flowing through the seventh N-type enhancement transistor MN1 is equal to the reference current. In the LDO circuit 10, the seventh N-type enhancement transistor MN1, the N-type consumption transistor DN1, the sixth N-type enhancement transistor MN2, the first P-type power transistor MP1, the third resistor R1, and the fourth resistor R2 form a loop. The LDO circuit 10 can provide a stable output voltage VOUT to the subsequent circuit.

[0044] It can be understood that the LDO circuit 10 is a power supply circuit that is used to output a stable output voltage VOUT after the power supply voltage VDD passes through the LDO circuit 10. Furthermore, the power supply voltage VDD is constantly changing. Despite this change, the LDO circuit 10 can still ensure the stability of the output voltage VOUT. Therefore, a voltage difference exists between the output voltage VOUT and the power supply voltage VDD. For example, if the stable value of the output voltage VOUT is 2.8V and the power supply voltage VDD is 3.3V, the voltage difference is 0.5V. This voltage difference is within the set voltage difference threshold range and does not affect the LDO circuit 10's ability to provide a stable output voltage VOUT to the subsequent circuit.

[0045] In some optional embodiments, when the power supply voltage VDD of the LDO circuit 10 decreases, causing the voltage difference between the power supply voltage VDD and the output voltage VOUT to be zero or even negative, the feedback voltage VFB in the LDO circuit 10 decreases along with the power supply voltage VDD. Consequently, the gate voltage V1 of the sixth N-type enhancement transistor MN2 continues to increase until it equals the power supply voltage VDD, causing the sixth N-type enhancement transistor MN2 to be fully turned on, causing the gate voltage V2 of the first P-type power transistor MP1 to gradually decrease until it reaches zero.

[0046] In some optional embodiments, because the drain of the first P-type enhancement transistor MP2 is connected to the gate of the first P-type enhancement transistor MP2 in a diode connection, when the gate voltage V2 of the first P-type power transistor MP1 decreases until it reaches zero, the conduction level of the first P-type enhancement transistor MP2 increases. At this time, the quiescent current in the LDO circuit 10 gradually increases as the conduction level of the first P-type enhancement transistor MP2 increases. In the LDO circuit 10, the increase in quiescent current can lead to an increase in quiescent power consumption. When a battery is used to power the LDO circuit 10, the increase in quiescent power consumption further increases the rate of decrease of the power supply voltage VDD, and thus the output voltage VOUT decreases as the power supply voltage VDD decreases. This not only affects the power supply from the LDO circuit 10 to the subsequent circuit, but also accelerates the discharge of the battery, causing damage to the battery.

[0047] Therefore, in order to solve the above problems, the present application provides an LDO circuit. Figure 2 As shown, the LDO circuit 10 includes a current bias circuit 101, a driving circuit 102, a reference circuit 103 and a power circuit 107; the current bias circuit 101 includes a current unit 1011 and a control unit 1012, the first end of the current unit 1011 is used to connect to the first end of the reference circuit 103, the first end of the power circuit 107, and the power supply end, the second end of the current unit 1011 is connected to the first end of the control unit 1012, the second end of the control unit 1012 is connected to the first end of the driving circuit 102, and the third end of the control unit 1012 is connected to the first end of the driving circuit 102. The first terminal of the driving circuit 102 is connected to the second terminal of the power circuit 107; the second terminal of the driving circuit 102 is connected to the second terminal of the reference circuit 103, the third terminal of the driving circuit 102 is grounded, the third terminal of the reference circuit 103 is grounded, and the reference circuit 103 is used to output a reference current; the third terminal of the power circuit 107 is connected to the output terminal of the LDO circuit; wherein, when the voltage difference between the power supply voltage at the power supply terminal and the voltage at the output terminal of the LDO circuit is less than the first voltage threshold, the driving circuit 102 is in the on state, and the current unit 1011 outputs a fixed bias current to the control unit 1012.

[0048] It can be understood that the current unit 1011 is used to provide a fixed bias current to the LDO circuit 10. During operation of the LDO circuit 10, when the power supply voltage VDD of the LDO circuit 10 decreases and the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to a first voltage threshold, the current unit 1011 causes the current in the LDO circuit 10 to be the fixed bias current provided by the current unit 1011, so that the current in the LDO circuit 10 no longer increases. This can effectively reduce the static power consumption of the LDO circuit 10, and is conducive to reducing the battery discharge rate and reducing damage to the battery.

[0049] It is understandable that Figure 3As shown, the LDO circuit 10 further includes a voltage division sampling circuit 104 , a first switch circuit 105 and a second switch circuit.

[0050] The first end of the first switch circuit 105 is respectively connected to the first end of the current unit 1011, the power supply, the first end of the power circuit 107, and the first end of the second switch circuit. The second end of the first switch circuit 105 is respectively connected to the first end of the reference circuit 103. The second end of the second switch circuit is respectively connected to the second end of the power circuit 107 and the third end of the control unit 1012. The first end of the voltage divider sampling circuit 104 is respectively connected to the third end of the power circuit 107 and the output end of the LDO circuit 10. The second end of the voltage divider sampling circuit 104 is connected to the fourth end of the reference circuit 103, and the third end of the voltage divider sampling circuit 104 is connected to the third end of the reference circuit 103.

[0051] In some optional embodiments, the current unit 1011 may include a first transistor MP5, and the control unit 1012 may include a first P-type enhancement transistor MP2.

[0052] The source of the first transistor MP5 is connected to the first terminal of the first switch circuit 105, the first terminal of the second switch circuit, the first terminal of the power circuit 107, and the power supply terminal. The drain of the first transistor MP5 is connected to the source of the first P-type enhancement transistor MP2. The drain of the first P-type enhancement transistor MP2 is connected to the gate of the first P-type enhancement transistor MP2 and the first terminal of the drive circuit 102. The gate of the first P-type enhancement transistor MP2 is connected to the second terminal of the power circuit 107.

[0053] The structure of the LDO circuit 10 mentioned in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0054] Figure 4A Shown Figure 3 A schematic diagram of a specific structure of the LDO circuit 10 is shown in FIG. Figure 4A As shown, in some optional embodiments, the first transistor MP5 may be an enhancement transistor, and the first transistor MP5 is a P-type enhancement transistor.

[0055] In some optional embodiments, the current unit 1011 includes a first transistor MP5, and the control unit 1012 includes a first P-type enhancement transistor MP2. In some optional embodiments, the first transistor MP5 can be a P-type enhancement transistor. The source of the first transistor MP5 is the first terminal of the current unit 1011, and the drain of the first transistor MP5 is the second terminal of the current unit 1011. The source of the first P-type enhancement transistor MP2 is the first terminal of the control unit 1012, the drain of the first P-type enhancement transistor MP2 is the second terminal of the control unit 1012, and the gate of the first P-type enhancement transistor MP2 is the third terminal of the control unit 1012.

[0056] In some optional embodiments, the driving circuit 102 includes a sixth N-type enhancement transistor MN2, wherein the drain of the sixth N-type enhancement transistor MN2 is the first terminal of the driving circuit 102, the gate of the sixth N-type enhancement transistor MN2 is the second terminal of the driving circuit 102, and the source of the sixth N-type enhancement transistor MN2 is the third terminal of the driving circuit 102.

[0057] Reference circuit 103 includes an N-type power dissipation transistor DN1 and a seventh N-type enhancement transistor MN1. The drain of N-type power dissipation transistor DN1 serves as a first terminal of reference circuit 103. The source of N-type power dissipation transistor DN1 and the drain of seventh N-type enhancement transistor MN1 together constitute a second terminal of reference circuit 103. The source of seventh N-type enhancement transistor MN1 serves as a third terminal of reference circuit 103. The gate of seventh N-type enhancement transistor MN1 serves as a fourth terminal of reference circuit 103.

[0058] The voltage-dividing sampling circuit 104 includes a third resistor R1 and a fourth resistor R2. The first end of the third resistor R1 serves as the first end of the voltage-dividing sampling circuit 104. The second end of the third resistor R1 and the first end of the fourth resistor R2 together serve as the second end of the voltage-dividing sampling circuit 104. The second end of the fourth resistor R2 serves as the third end of the voltage-dividing sampling circuit 104.

[0059] The first switch circuit 105 includes a fifth switch transistor MP4 , wherein a source of the fifth switch transistor MP4 is a first terminal of the first switch circuit 105 , and a drain of the fifth switch transistor MP4 is a second terminal of the first switch circuit 105 .

[0060] The second switch circuit includes a sixth switch transistor MP3 , wherein a source of the sixth switch transistor MP3 is a first terminal of the second switch circuit, and a drain of the sixth switch transistor MP3 is a second terminal of the second switch circuit.

[0061] The power circuit 107 includes a first P-type power transistor MP1 , whose source is a first terminal, whose gate is a second terminal, and whose drain is a third terminal.

[0062] In some optional embodiments, the source of the first transistor MP5 is respectively connected to the source of the fifth switch tube MP4, the source of the sixth switch tube MP3, the source of the first P-type power tube MP1, and the power supply terminal; the drain of the first transistor MP5 is connected to the source of the first P-type enhancement tube MP2, and the gate of the first transistor MP5 is used to receive the first bias voltage signal VBP1.

[0063] The drain of the first P-type enhancement tube MP2 is connected to the gate of the first P-type enhancement tube MP2 and the drain of the sixth N-type enhancement tube MN2 respectively. The gate of the first P-type enhancement tube MP2 is connected to the gate of the first P-type power tube MP1 and the drain of the sixth switch tube MP3 respectively.

[0064] The gate of the sixth N-type enhancement transistor MN2 is connected to the source of the N-type consumption transistor DN1 and the drain of the seventh N-type enhancement transistor MN1 respectively, and the source of the sixth N-type enhancement transistor MN2 is grounded.

[0065] The drain of the N-type power transistor DN1 is connected to the drain of the fifth switch tube MP4, and the gate of the N-type power transistor DN1 is short-circuited to the source of the N-type power transistor DN1.

[0066] The drain of the seventh N-type enhancement transistor MN1 is connected to the source of the N-type consumption tube DN1, the gate of the seventh N-type enhancement transistor MN1 is connected to the second end of the third resistor R1 and the first end of the fourth resistor R2 respectively, and the source of the seventh N-type enhancement transistor MN1 is grounded.

[0067] A first end of the third resistor R1 is connected to the drain of the first P-type power transistor MP1 and the output end of the LDO circuit 10, respectively. A second end of the third resistor R1 is connected to the first end of the fourth resistor R2. A second end of the fourth resistor R2 is connected to the source of the sixth N-type enhancement transistor MN2 and the source of the seventh N-type enhancement transistor MN1, respectively.

[0068] The gate of the fifth switch transistor MP4 is configured to receive the third enable signal ENB.

[0069] The gate of the sixth switch tube MP3 is configured to receive a fourth enable signal EN.

[0070] The present application implements an LDO circuit 10 by adding a current bias circuit 101. During operation, the fifth switch MP4 in the LDO circuit 10 is turned on, and the sixth switch MP3 is turned off. When the power supply voltage VDD of the LDO circuit 10 drops, causing the voltage difference between the power supply voltage VDD and the output voltage VOUT to drop to zero or a negative value, the feedback voltage VFB decreases along with the output voltage VOUT. At this point, the gate voltage V1 of the sixth N-type enhancement transistor MN2 increases, causing the sixth N-type enhancement transistor MN2 to fully turn on. At this point, by limiting the current flowing through the first P-type enhancement transistor MP2 and the sixth N-type enhancement transistor MN2 to the fixed bias current provided by the first transistor MP5 of the current bias circuit 101, the quiescent current of the LDO circuit 10 stops increasing continuously. This effectively reduces the quiescent power consumption of the LDO circuit 10, which helps reduce the battery discharge rate and minimize damage to the battery.

[0071] Furthermore, when the power supply voltage VDD of the LDO circuit 10 no longer changes, the quiescent current of the LDO circuit 10 gradually decreases from the fixed bias current provided by the first transistor MP5 of the current bias circuit 101 to the current of the first P-type enhancement transistor MP2, without affecting the stability of the LDO circuit 10. In this way, the stability of the LDO circuit 10 can be ensured.

[0072] In some optional embodiments, when the fourth enable signal EN received by the gate of the sixth switch transistor MP3 is at a high level and the third enable signal ENB received by the gate of the fifth switch transistor MP4 is at a low level, the LDO circuit 10 starts operating. When the fourth enable signal EN received by the gate of the sixth switch transistor MP3 is at a low level and the third enable signal ENB received by the gate of the fifth switch transistor MP4 is at a high level, the LDO circuit 10 stops operating.

[0073] In some optional embodiments, the gate of the first transistor MP5 receives the first bias voltage signal VBP1 to provide a fixed bias current IBIAS to the LDO circuit 10 .

[0074] In the LDO circuit 10, when the LDO circuit 10 starts operating, the sixth switch MP3 turns off, the first transistor MP5 turns on, and the output voltage VOUT of the LDO circuit 10 gradually rises until it reaches a stable value. When VOUT reaches a stable value, VOUT = VFB × (R1 + R2) / R2, where VFB is the feedback voltage of the LDO circuit 10.

[0075] In this way, when the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to a first voltage threshold, the current flowing through the first P-type enhancement transistor MP2 is fixed to the fixed bias current provided by the first transistor MP5, so that the quiescent current of the LDO circuit 10 is equal to the fixed bias current. When the power supply voltage VDD rises to a second voltage threshold, the quiescent current of the LDO circuit 10 gradually decreases from the fixed bias current provided by the first transistor MP5 to the current flowing through the first P-type enhancement transistor MP2, without affecting the stability of the LDO circuit 10. Furthermore, by controlling the quiescent current in the LDO circuit 10 to the fixed bias current when the power supply voltage VDD changes, the quiescent power consumption of the LDO circuit 10 can be effectively reduced, which helps reduce the battery discharge rate and minimize damage to the battery. Furthermore, the stability of the LDO circuit 10 can be ensured. Furthermore, the circuit architecture of the LDO circuit 10 is simple.

[0076] Figure 4B Shown Figure 3 Another specific structure of the LDO circuit 10 is shown in FIG. Figure 4BAs shown, the current unit 1011 includes a first transistor MP5, a second switch tube MP6 and a third switch tube MP7. In this embodiment, the first transistor MP5 can be a switch tube, and the gate of the first transistor MP5 is used to receive the first enable signal EN1. The control unit 1012 includes a first P-type enhancement tube MP2.

[0077] Among them, the source of the first transistor MP5 and the source of the second switch transistor MP6 are connected to form a first end of the current unit 1011, and the drain of the first transistor MP5 is the second end of the current unit 1011; the source of the first P-type enhancement transistor MP2 is the first end of the control unit 1012, the drain of the first P-type enhancement transistor MP2 is the second end of the control unit 1012, and the gate of the first P-type enhancement transistor MP2 is the third end of the control unit 1012.

[0078] In some optional embodiments, the source of the first transistor MP5 is respectively connected to the source of the fifth switch tube MP4, the source of the second switch tube MP6, the source of the sixth switch tube MP3, the source of the first P-type power tube MP1, and the power supply terminal; the drain of the first transistor MP5 is connected to the source of the first P-type enhancement tube MP2, and the gate of the first transistor MP5 is used to receive the first enable signal EN1.

[0079] The drain of the second switch transistor MP6 is connected to the source of the third switch transistor MP7. The gate of the second switch transistor MP6 is used to receive the second bias voltage signal VBP2. The drain of the third switch transistor MP7 is connected to the drain of the first P-type enhancement transistor MP2 and the drain of the sixth N-type enhancement transistor MN2 respectively. The gate of the third switch transistor MP7 is used to receive the second enable signal ENB1. Figure 4A To avoid repetition, the structural diagram shown is not described in detail here.

[0080] In some optional embodiments, Figure 4B The LDO circuit 10 shown may further include a comparator circuit 108 and an inverter circuit 109. Figure 5 As shown in the structural diagram of the LDO circuit 10, the LDO circuit 10 includes a current bias circuit 101, a drive circuit 102, a reference circuit 103, a voltage divider sampling circuit 104, a first switch circuit 105, a second switch circuit, a comparator circuit 108 and an inverter circuit 109.

[0081] The negative input terminal of the comparator circuit 108 is connected to the power supply terminal, the positive input terminal of the comparator circuit 108 is connected to the output terminal of the LDO circuit 10, and the output terminal of the comparator circuit 108 is connected to the input terminal of the inverter circuit 109. It can be understood that other structures of the LDO circuit 10 can refer to Figure 3To avoid repetition, the structural diagram shown is not described in detail here.

[0082] In some optional embodiments, Figure 6 A schematic diagram of the circuit structure of the comparator circuit 108 is shown. Figure 6 As shown, the comparator circuit 108 may include: a first resistor R3, a second resistor R4, a first N-type enhancement transistor MN3, a second N-type enhancement transistor MN4, a third N-type enhancement transistor MN5, a fourth N-type enhancement transistor MN6, a fifth N-type enhancement transistor MN7, a second P-type enhancement transistor MP8, a third P-type enhancement transistor MP9, a first inverter SCHMIT, a second inverter INV1, and a third inverter INV2. The first inverter SCHMIT may be a Schmitt inverter. Furthermore, the inverter circuit 109 may include a fourth inverter INV0 (not shown).

[0083] exist Figure 6 In the illustrated circuit structure of the comparator circuit 108, a first end of a first resistor R3 is connected to the power supply, and a second end of the first resistor R3 is connected to the source of the third P-type enhancement transistor MP9. A first end of a second resistor R4 is connected to the output of the LDO circuit, and a second end of the second resistor R4 is connected to the source of the second P-type enhancement transistor MP8. The drain of the second P-type enhancement transistor MP8 and the gate of the third P-type enhancement transistor MP9 are respectively connected to the gate of the second P-type enhancement transistor MP8, and the drain of the second P-type enhancement transistor MP8 is connected to the drain of the second N-type enhancement transistor MN4. The drain of the third P-type enhancement transistor MP9 is respectively connected to the drain of the third N-type enhancement transistor MN5, the drain of the fifth N-type enhancement transistor MN7, and the input of the first inverter SCHMIT. The sources of the first N-type enhancement transistor MN3, the second N-type enhancement transistor MN4, the third N-type enhancement transistor MN5, and the fourth N-type enhancement transistor MN6 are interconnected. The gates of the first N-type enhancement transistor MN3, the second N-type enhancement transistor MN4, the third N-type enhancement transistor MN5, and the fourth N-type enhancement transistor MN6 are connected to each other. The gate of the first N-type enhancement transistor MN3 is connected to the drain of the first N-type enhancement transistor MN3.

[0084] The drain of the third N-type enhancement transistor MN5 is connected to the input of the first inverter SCHMIT. The drain of the fourth N-type enhancement transistor MN6 is connected to the source of the fifth N-type enhancement transistor MN7. The drain of the fifth N-type enhancement transistor MN7 is connected to the input of the first inverter SCHMIT, and the gate of the fifth N-type enhancement transistor MN7 is used to receive the first enable signal EN1. The output of the first inverter SCHMIT is connected to the input of the second inverter INV1. The output of the second inverter INV1 is connected to the input of the third inverter INV2, and the output of the third inverter INV2 is connected to the input of the inverter circuit 109. The output of the third inverter INV2 is used to output the first enable signal EN1.

[0085] The voltage at the input end of the first inverter SCHMIT may be voltage V3 , the voltage at the input end of the second inverter INV1 may be voltage V4 , and the voltage at the input end of the third inverter INV2 may be voltage V5 .

[0086] In some optional embodiments, the input end of the fourth inverter INV0 is connected to the output end of the third inverter INV2 , and the output end of the fourth inverter INV0 is used to output the second enable signal ENB1 .

[0087] In some other optional embodiments, Figure 7 FIG2 shows a schematic structural diagram of another comparator circuit 108, which includes an eighth N-type enhancement transistor MN8, a ninth N-type enhancement transistor MN9, a tenth N-type enhancement transistor MN10, a fifth P-type enhancement transistor MP11, a sixth P-type enhancement transistor MP12, a seventh P-type enhancement transistor MP13, an eighth P-type enhancement transistor MP14, a first inverter SCHMIT, a second inverter INV1, and a third inverter INV2.

[0088] Among them, the source of the fifth P-type enhancement transistor MP11 is respectively connected to the drain of the seventh P-type enhancement transistor MP13 and the source of the sixth P-type enhancement transistor MP12, the drain of the fifth P-type enhancement transistor MP11 is respectively connected to the drain of the ninth N-type enhancement transistor MN9 and the gate of the tenth N-type enhancement transistor MN10, and the gate of the fifth P-type enhancement transistor MP11 is connected to the power supply terminal; the drain of the sixth P-type enhancement transistor MP12 is respectively connected to the gate of the eighth N-type enhancement transistor MN8, the drain of the eighth N-type enhancement transistor MN8, and the gate of the ninth N-type enhancement transistor MN9, and the gate of the sixth P-type enhancement transistor MP12 is connected to the output terminal of the LDO circuit 10; the source of the seventh P-type enhancement transistor MP13 is respectively connected to the power supply terminal and the source of the eighth P-type enhancement transistor MP14. The gate of the seventh P-type enhancement transistor MP13 is connected to the gate of the eighth P-type enhancement transistor MP14; the drain of the eighth P-type enhancement transistor MP14 and the drain of the tenth N-type enhancement transistor MN10 are respectively connected to the input end of the first inverter SCHMIT; the source of the eighth N-type enhancement transistor MN8 is respectively connected to the source of the ninth N-type enhancement transistor MN9 and the source of the tenth N-type enhancement transistor MN10; the output end of the first inverter SCHMIT is connected to the input end of the second inverter INV1; the output end of the second inverter INV1 is connected to the input end of the third inverter INV2, the output end of the third inverter INV2 is connected to the input end of the inverter circuit 109, and the output end of the third inverter INV2 is used to output the first enable signal EN1.

[0089] When the LDO circuit 10 is operating, when the second enable signal ENB1 received by the gate of the third switch MP7 is at a low level and the first enable signal EN1 received by the gate of the first transistor MP5 is at a high level, the third switch MP7 is turned off and the first transistor MP5 is turned on. When the second enable signal ENB1 received by the gate of the third switch MP7 is at a high level and the first enable signal EN1 received by the gate of the first transistor MP5 is at a low level, the third switch MP7 is turned on and the first transistor MP5 is turned off. Furthermore, the gate of the second switch MP6 is configured to receive the second bias voltage signal VBP2, thereby providing a fixed bias current IBIAS to the LDO circuit 10.

[0090] When the first transistor MP5 is a switch, the present application forms an LDO circuit 10 by adding a second switch MP6, a third switch MP7, a comparator circuit 108, and an inverter circuit 109 to the LDO circuit 10. During operation of the LDO circuit 10, the fifth switch MP4 in the LDO circuit 10 is turned on, the sixth switch MP3 is turned off, the first transistor MP5 is turned on, and the third switch MP7 is turned off. At this time, the output voltage VOUT of the LDO circuit 10 gradually rises until it reaches a stable value. When the output voltage VOUT is at a stable value, VOUT = VFB × (R1 + R2) / R2, where VFB is the feedback voltage in the LDO circuit 10.

[0091] When the power supply voltage VDD of the LDO circuit 10 decreases and the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to a first voltage threshold, the first enable signal EN1 output by the third inverter INV2 to the fourth inverter INV0 is at a low level. This causes the gate of the third switch MP7 to receive the second enable signal ENB1 output by the fourth inverter INV0 to be at a high level, and the gate of the first transistor MP5 to receive the first enable signal EN1 output by the third inverter INV2 to be at a low level. As a result, the first transistor MP5 is turned off, the third switch MP7 is turned on, and the current switches from the current flowing through the first P-type enhancement transistor MP2 to the fixed bias current flowing through the second switch MP6. Because the first P-type enhancement transistor MP2 is diode-connected, when the power supply voltage VDD of the LDO circuit 10 decreases and the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to zero or a negative value, the feedback voltage VFB decreases along with the output voltage VOUT. At this time, the gate voltage V1 of the sixth N-type enhancement transistor MN2 increases, causing the sixth N-type enhancement transistor MN2 to fully conduct. Consequently, a large and constant current flows through the first P-type enhancement transistor MP2 and the sixth N-type enhancement transistor MN2, resulting in high static power consumption in the LDO circuit 10.

[0092] Therefore, in the LDO circuit 10, when the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to a first voltage threshold, the current flowing through the first P-type enhancement transistor MP2 is switched to a fixed bias current flowing through the second switch transistor MP6. This can effectively avoid an increase in quiescent current caused by a decrease in the power supply voltage VDD, effectively reduce the quiescent power consumption of the LDO circuit 10, and help reduce the battery discharge rate, thereby reducing damage to the battery.

[0093] Furthermore, when the voltage difference between the power supply voltage VDD and the output voltage VOUT rises to a second voltage threshold, the first enable signal EN1 output by the third inverter INV2 to the fourth inverter INV0 is high, causing the second enable signal ENB1 output by the fourth inverter INV0 to be low when received by the gate of the third switch MP7, and the first enable signal EN1 output by the third inverter INV2 to be high when received by the gate of the first transistor MP5. Consequently, the first transistor MP5 is turned on, the third switch MP7 is turned off, and the quiescent current of the LDO circuit 10 is switched from the fixed bias current provided by the second switch MP6 to the current flowing through the first transistor MP5, without affecting the stability of the LDO circuit 10. In this way, when the voltage difference between the power supply voltage VDD and the output voltage VOUT rises to the second voltage threshold, the quiescent current is switched back to the current flowing through the first transistor MP5, thereby ensuring the stability of the LDO circuit 10.

[0094] In some optional embodiments, when the fourth enable signal EN received by the gate of the sixth switch transistor MP3 is at a high level and the third enable signal ENB received by the gate of the fifth switch transistor MP4 is at a low level, the LDO circuit 10 starts operating. When the fourth enable signal EN received by the gate of the sixth switch transistor MP3 is at a low level and the third enable signal ENB received by the gate of the fifth switch transistor MP4 is at a high level, the LDO circuit 10 stops operating.

[0095] In this way, when the voltage difference between the power supply voltage VDD and the output voltage VOUT drops to a first voltage threshold, the current flowing through the first P-type enhancement transistor MP2 is switched to a fixed bias current provided by the second switch transistor MP6, so that the quiescent current of the LDO circuit 10 is equal to the fixed bias current. When the power supply voltage VDD rises to a second voltage threshold, the quiescent current of the LDO circuit 10 is switched from the fixed bias current provided by the second switch transistor MP6 to the current flowing through the first P-type enhancement transistor MP2, without affecting the stability of the LDO circuit 10. Furthermore, by switching the quiescent current in the LDO circuit 10 and controlling it to the fixed bias current when the power supply voltage VDD changes, the quiescent power consumption of the LDO circuit 10 can be effectively reduced, which helps to reduce the battery discharge rate and minimize damage to the battery. Furthermore, the stability of the LDO circuit 10 can be ensured.

[0096] The embodiment of the present application provides a chip, which includes the LDO circuit mentioned in the embodiment of the present application, for example, Figure 1 、 Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 5 、 Figure 6 and / or Figure 7Any circuit shown is an LDO circuit as described in the embodiment. This embodiment is a chip implementation corresponding to the aforementioned LDO circuit embodiment, and this embodiment can be implemented in conjunction with the LDO circuit implementation. The relevant technical details mentioned in the LDO circuit implementation are still valid in this embodiment and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the LDO circuit implementation.

[0097] An embodiment of the present application provides an electronic device, which may include the above-mentioned chip.

[0098] The electronic device mentioned in this application is introduced below. It is understood that the electronic device can be any electronic device including the above-mentioned LDO circuit. The scope of the present invention includes, but is not limited to: mobile phones (including foldable phones and candy-bar phones), tablet computers, desktop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), portable Android devices (PADs), personal digital assistants (PDAs), handheld devices, computing devices, vehicle-mounted devices or wearable devices with wireless communication capabilities, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical care, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and other mobile or fixed terminals, power banks and other electronic devices with data transmission synchronization requirements.

[0099] It should be noted that, in the examples and description of the present application, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0100] While the present application has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims

1. An LDO circuit, characterized in that: The LDO circuit includes a current bias circuit, a drive circuit, a reference circuit and a power circuit; The current bias circuit includes a current unit and a control unit, wherein a first end of the current unit is used to be connected to the first end of the reference circuit, the first end of the power circuit, and the power supply end, a second end of the current unit is connected to the first end of the control unit, a second end of the control unit is connected to the first end of the drive circuit, and a third end of the control unit is connected to the second end of the power circuit; The second end of the driving circuit is connected to the second end of the reference circuit, the third end of the driving circuit is grounded, the third end of the reference circuit is grounded, and the reference circuit is used to output a reference current; The third terminal of the power circuit is connected to the output terminal of the LDO circuit; When the voltage difference between the power supply voltage at the power supply end and the voltage at the output end of the LDO circuit is less than a first voltage threshold, the drive circuit is in an on state, and the current unit outputs a fixed bias current to the control unit.

2. The LDO circuit according to claim 1, wherein: The LDO circuit further includes a voltage division sampling circuit, a first switching circuit and a second switching circuit; The first end of the first switch circuit is respectively connected to the first end of the current unit, the power supply end, the first end of the power circuit, and the first end of the second switch circuit, and the second end of the first switch circuit is connected to the first end of the reference circuit; The second end of the second switch circuit is connected to the second end of the power circuit and the third end of the control unit respectively; The first end of the voltage-dividing sampling circuit is connected to the third end of the power circuit and the output end of the LDO circuit respectively; The second end of the voltage-dividing sampling circuit is connected to the fourth end of the reference circuit, and the third end of the voltage-dividing sampling circuit is connected to the third end of the reference circuit.

3. The LDO circuit according to claim 2, wherein: The current unit includes a first transistor, and the control unit includes a first P-type enhancement tube; The source of the first transistor is connected to the first end of the first switch circuit, the first end of the second switch circuit, the first end of the power circuit, and the power supply end respectively, and the drain of the first transistor is connected to the source of the first P-type enhancement transistor; The drain of the first P-type enhancement tube is connected to the gate of the first P-type enhancement tube and the first end of the driving circuit respectively, and the gate of the first P-type enhancement tube is connected to the second end of the power circuit.

4. The LDO circuit according to claim 3, wherein: The first transistor is an enhancement transistor, and a gate of the first transistor is used to receive a first bias voltage signal.

5. The LDO circuit according to claim 3, wherein: The first transistor is a switch tube, the current unit further includes a second switch tube and a third switch tube, and the gate of the first transistor is used to receive a first enable signal; The source of the second switch tube is respectively connected to the source of the first transistor, the first end of the first switch circuit, the first end of the second switch circuit, the first end of the power circuit, and the power supply end; The drain of the second switch tube is connected to the source of the third switch tube, and the gate of the second switch tube is used to receive a second bias voltage signal; The drain of the third switch tube is connected to the drain of the first P-type enhancement tube and the first end of the driving circuit respectively, and the gate of the third switch tube is used to receive a second enable signal.

6. The LDO circuit according to any one of claims 4 and 5, characterized in that The driving circuit includes a sixth N-type enhancement tube, and the reference circuit includes an N-type power dissipation tube and a seventh N-type enhancement tube; The drain of the sixth N-type enhancement tube is connected to the drain of the first P-type enhancement tube respectively, the gate of the sixth N-type enhancement tube is connected to the drain of the seventh N-type enhancement tube and the source of the N-type consumption tube respectively, and the source of the sixth N-type enhancement tube is grounded; The drain of the N-type power dissipation transistor is connected to the second end of the first switch circuit, and the gate of the N-type power dissipation transistor is short-circuited with the source of the N-type power dissipation transistor; The gate of the seventh N-type enhancement tube is connected to the second end of the voltage-dividing sampling circuit, and the source of the seventh N-type enhancement tube is grounded.

7. The LDO circuit according to claim 6, wherein: The voltage-dividing sampling circuit includes a third resistor and a fourth resistor, the first switch circuit includes a fifth switch tube, and the second switch circuit includes a sixth switch tube; The first end of the third resistor is connected to the third end of the power circuit and the output end of the LDO circuit respectively, and the second end of the third resistor is connected to the first end of the fourth resistor and the gate of the seventh N-type enhancement transistor respectively; The second end of the fourth resistor is connected to the source of the sixth N-type enhancement transistor and the source of the seventh N-type enhancement transistor respectively; The drain of the fifth switch tube is connected to the drain of the N-type power transistor, and the source of the fifth switch tube is connected to the source of the first transistor, the source of the sixth switch tube, the first end of the power circuit, and the power supply end respectively; The gate of the fifth switch tube is used to receive a third enable signal; The drain of the sixth switch tube is connected to the second end of the power circuit and the gate of the first P-type enhancement tube respectively; The gate of the sixth switch tube is used to receive a fourth enable signal.

8. The LDO circuit according to claim 7, wherein: The power circuit includes a first P-type power tube; The source of the first P-type power tube is connected to the source of the fifth switch tube, the source of the first transistor, the source of the sixth switch tube, and the power supply end respectively; The gate of the first P-type power tube is connected to the drain of the sixth switch tube and the gate of the first P-type enhancement tube respectively; The drain of the first P-type power tube is connected to the first end of the third resistor and the output end of the LDO circuit respectively.

9. The LDO circuit according to claim 5, wherein: The LDO circuit includes a comparator circuit and an inverter circuit; The negative input terminal of the comparator circuit is connected to the power supply terminal, the positive input terminal of the comparator circuit is connected to the output terminal of the LDO circuit, and the output terminal of the comparator circuit is connected to the input terminal of the inverter circuit.

10. The LDO circuit according to claim 9, wherein: The comparator circuit includes a first resistor, a second resistor, a first N-type enhancement tube, a second N-type enhancement tube, a third N-type enhancement tube, a fourth N-type enhancement tube, a fifth N-type enhancement tube, a second P-type enhancement tube, a third P-type enhancement tube, a first inverter, a second inverter and a third inverter; The first end of the first resistor is connected to the power supply end, and the second end of the first resistor is connected to the source of the third P-type enhancement tube; A first end of the second resistor R4 is connected to the output end of the LDO circuit, and a second end of the second resistor is connected to the source of the second P-type enhancement transistor; The drain of the second P-type enhancement tube and the gate of the third P-type enhancement tube are respectively connected to the gate of the second P-type enhancement tube, and the drain of the second P-type enhancement tube is connected to the drain of the second N-type enhancement tube; The drain of the third P-type enhancement tube is connected to the drain of the third N-type enhancement tube, the drain of the fifth N-type enhancement tube, and the input end of the first inverter respectively; The source of the first N-type enhancement tube, the source of the second N-type enhancement tube, the source of the third N-type enhancement tube, and the source of the fourth N-type enhancement tube are connected to each other; The gate of the first N-type enhancement tube, the gate of the second N-type enhancement tube, the gate of the third N-type enhancement tube, and the gate of the fourth N-type enhancement tube are connected to each other; The gate of the first N-type enhancement tube is connected to the drain of the first N-type enhancement tube; The drain of the third N-type enhancement transistor is connected to the input end of the first inverter; The drain of the fourth N-type enhancement transistor is connected to the source of the fifth N-type enhancement transistor; The drain of the fifth N-type enhancement transistor is connected to the input end of the first inverter, and the gate of the fifth N-type enhancement transistor is used to receive the first enable signal; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter is connected to the input end of the inverter circuit, and the output end of the third inverter is used to output the first enable signal.

11. The LDO circuit according to claim 10, wherein: The inverter circuit includes a fourth inverter; The input end of the fourth inverter is connected to the output end of the third inverter, and the output end of the fourth inverter is used to output the second enable signal.

12. The LDO circuit according to claim 9, wherein: The comparator circuit 108 includes an eighth N-type enhancement tube, a ninth N-type enhancement tube, a tenth N-type enhancement tube, a fifth P-type enhancement tube, a sixth P-type enhancement tube, a seventh P-type enhancement tube, an eighth P-type enhancement tube, a first inverter, a second inverter, and a third inverter. The source of the fifth P-type enhancement tube is connected to the drain of the seventh P-type enhancement tube and the source of the sixth P-type enhancement tube respectively, the drain of the fifth P-type enhancement tube is connected to the drain of the ninth N-type enhancement tube and the gate of the tenth N-type enhancement tube respectively, and the gate of the fifth P-type enhancement tube is connected to the power supply terminal; The drain of the sixth P-type enhancement tube is connected to the gate of the eighth N-type enhancement tube, the drain of the eighth N-type enhancement tube, and the gate of the ninth N-type enhancement tube respectively, and the gate of the sixth P-type enhancement tube is connected to the output end of the LDO circuit; The source of the seventh P-type enhancement tube is connected to the power supply end and the source of the eighth P-type enhancement tube respectively, and the gate of the seventh P-type enhancement tube is connected to the gate of the eighth P-type enhancement tube; The drain of the eighth P-type enhancement tube and the drain of the tenth N-type enhancement tube are respectively connected to the input end of the first inverter; The source of the eighth N-type enhancement tube is connected to the source of the ninth N-type enhancement tube and the source of the tenth N-type enhancement tube respectively; The output terminal of the first inverter is connected to the input terminal of the second inverter; The output end of the second inverter is connected to the input end of the third inverter, the output end of the third inverter is connected to the input end of the inverter circuit, and the output end of the third inverter is used to output the first enable signal.

13. A chip, characterized in that: The LDO circuit comprises the LDO circuit according to any one of claims 1 to 12.

14. An electronic device, characterized in that: Comprising the chip according to claim 13.

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