Clock signal adjusting method and device and integrated circuit

Abstract

The invention discloses a clock signal adjusting method and device and an integrated circuit, and the method comprises the steps: obtaining the performance state information of a processor, and determining a target load grade from all load grades according to the performance state information, thereby determining the corresponding target load grade based on the performance state information at different moments, and achieving the adjustment of a clock signal. And adjusting the first clock signal to the second clock signal corresponding to the target load level according to the target load level, namely dynamically adjusting the clock signal based on the load levels at different moments, so that the working frequency of the working unit is not always at a peak value, and meanwhile, the performance requirements of the working unit at different moments can be met. Therefore, the situation of working performance overflow can be reduced, useless power consumption of the digital circuit is reduced, and the problem of operation resource waste is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, and integrated circuit for adjusting a clock signal. Background Art

[0002] Today, most digital circuits are designed based on a global clock frequency, which coordinates the logic timing of various operating units within the digital circuit. Typically, each operating unit in a digital circuit has a corresponding operating clock, and the clock frequency of the operating clock is fixed after configuration. Therefore, the operating clock of each operating unit must be configured above the peak operating frequency of the operating unit to meet the performance requirements of the operating unit.

[0003] However, the working unit will not always maintain a full-load operation state, and the working frequency will not always be at the peak. The clock frequency of the working clock is fixed above the peak of the working frequency. There will be a situation where the clock frequency is always much higher than the actual working frequency of the working unit, resulting in a working performance overflow, thereby increasing the useless power consumption of the digital circuit and wasting operating resources. Summary of the Invention

[0004] The embodiments of the present application provide a clock signal adjustment method, device and integrated circuit, which aim to solve the problem that the existing clock signal based on a fixed configuration will have performance overflow, thereby increasing the useless power consumption of the digital circuit and wasting operating resources.

[0005] In a first aspect, an embodiment of the present application provides a method for adjusting a clock signal, comprising:

[0006] Get the performance status information of the processor;

[0007] Determining a target load level from all load levels based on the performance status information, wherein the load levels are divided based on application scenarios and target algorithm models;

[0008] According to the target load level, the first clock signal is adjusted to a second clock signal corresponding to the target load level.

[0009] In this embodiment, by obtaining the performance status information of the processor, and then determining the target load level from all load levels based on the performance status information, the corresponding target load level can be determined based on the performance status information at different times, and according to the target load level, the first clock signal is adjusted to the second clock signal corresponding to the target load level. The clock signal can be dynamically adjusted based on the load level at different times, so that the working frequency of the working unit will not always be at the peak value, while meeting the performance requirements of the working unit at different times, thereby reducing the overflow of working performance, thereby reducing the useless power consumption of the digital circuit, and reducing the problem of waste of operating resources.

[0010] In a possible implementation of the first aspect, before determining the target load level from all load levels according to the performance status information, the method further includes:

[0011] Determining a target algorithm model and determining performance characteristics of the target algorithm model in a target computing platform;

[0012] Determine the performance requirements of the application scenario;

[0013] The performance characteristics are divided into at least one load level based on the performance requirement information.

[0014] In this embodiment, the performance characteristics of the target algorithm model in the target computing platform are determined, and the performance requirement information of the application scenario is determined, and then the performance characteristics are divided into at least one load level based on the performance requirement information. Therefore, when the second clock signal is adjusted to correspond to the target load level, the target computing platform can provide corresponding performance characteristics, which can not only meet the performance requirements of the working unit, but also reduce the overflow of working performance, thereby reducing the useless power consumption of the digital circuit and reducing the problem of waste of operating resources.

[0015] In a possible implementation of the first aspect, determining the performance characteristics of the target algorithm model in the target computing platform includes:

[0016] Determine the performance range and bandwidth range of the target computing platform;

[0017] Determining the computational intensity of the target algorithm model;

[0018] According to the computational intensity, performance characteristics of the target algorithm model within the performance range and the bandwidth range are determined.

[0019] In this embodiment, by determining the performance range and bandwidth range of the target computing platform and the computing intensity of the target algorithm model, the performance characteristics of the target algorithm model within the performance range and bandwidth range can be determined based on the computing intensity, thereby improving the accuracy and reliability of the load level division. When the second clock signal corresponding to the target load level is adjusted, the performance characteristics provided by the target computing platform not only meet the performance requirements of the working unit, but also reduce the overflow of the working performance, thereby reducing the useless power consumption of the digital circuit and reducing the problem of waste of operating resources.

[0020] In a possible implementation of the first aspect, dividing the performance characteristics into at least one load level based on the performance requirement information includes:

[0021] Determining an operating frequency corresponding to the application scenario based on the performance requirement information;

[0022] The performance characteristic is divided into at least one load class according to the operating frequency.

[0023] In this embodiment, the operating frequency corresponding to the application scenario is determined based on the performance requirement information, and the performance characteristics are divided into at least one load level according to the operating frequency, thereby further improving the accuracy and reliability of the load level division, and while meeting the performance requirements of the working unit, further reducing the overflow of the working performance, reducing the useless power consumption of the digital circuit, and reducing the problem of waste of operating resources.

[0024] In a possible implementation of the first aspect, before determining the target load level from all the load levels according to the performance status information, the method further includes:

[0025] Determining whether a clock switching condition is triggered according to the performance status information;

[0026] When it is determined that the clock switching condition is triggered, the step of determining the target load level corresponding to the performance status information from all the load levels is performed.

[0027] In this embodiment, whether the clock switching condition is triggered is determined based on the performance status information, and when it is determined that the clock switching condition is triggered, the step of determining the target load level corresponding to the performance status information from all the load levels is executed, so that the clock signal can be adjusted at the correct time, thereby improving the accuracy of dynamically adjusting the clock signal.

[0028] In a possible implementation of the first aspect, the performance status information includes bandwidth status information and throughput status information, and determining whether to trigger a clock switching condition based on the performance status information includes:

[0029] When the bandwidth status information is not within the bandwidth range, or the throughput status information is not within the throughput range, determining a clock switching triggering condition;

[0030] When the bandwidth status information is within the bandwidth range and the throughput status information is within the throughput range, it is determined that a clock switching condition is not triggered.

[0031] In this embodiment, when the bandwidth status information is not within the bandwidth range or the throughput status information is not within the throughput range, it is determined that the clock switching condition is triggered, and when the bandwidth status information is within the bandwidth range and the throughput status information is within the throughput range, it is determined that the clock switching condition is not triggered, thereby further improving the accuracy of dynamically adjusting the clock signal.

[0032] In a possible implementation of the first aspect, determining the target load level corresponding to the performance status information from all the load levels includes:

[0033] Determining a load range corresponding to each load level;

[0034] determining actual load information based on the performance status information;

[0035] A target load range in which the actual load information is located is determined from all the load ranges, and a target load level corresponding to the target load range is determined.

[0036] In this embodiment, the load range corresponding to each load level is determined, and the actual load information is determined based on the performance status information, and then the target load range in which the actual load information is located is determined from all load ranges, and the target load level corresponding to the target load range is determined, that is, the target load level is determined based on the performance status information and the load range of each load level, thereby being able to provide the accuracy of adjusting the clock signal based on the target load level.

[0037] In a second aspect, an embodiment of the present application provides a clock signal adjustment device, comprising:

[0038] An acquisition module, used to obtain performance status information of the processor;

[0039] a determination module, configured to determine a target load level from all load levels according to the performance status information, wherein the load level corresponds to an application scenario;

[0040] The adjustment module is used to adjust the first clock signal to a second clock signal corresponding to the target load level according to the target load level.

[0041] In a third aspect, an embodiment of the present application provides an integrated circuit, including:

[0042] At least one logic circuit for performing at least one algorithmic function, wherein when the logic circuit executes the algorithmic function, the clock signal adjustment method provided in the first aspect is implemented.

[0043] In a fourth aspect, an embodiment of the present application provides a controller comprising the integrated circuit provided in the third aspect above.

[0044] In a fifth aspect, an embodiment of the present application provides a vehicle comprising a controller as provided in the fourth aspect above.

[0045] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a flowchart of a method for adjusting a clock signal provided in one embodiment of the present application;

[0047] Figure 2 This is a schematic diagram of the structure of an NPU architecture provided by an embodiment of the present application;

[0048] Figure 3 This is a flowchart of another method for adjusting a clock signal provided in one embodiment of the present application;

[0049] Figure 4 is a schematic diagram of a performance characteristic provided by an embodiment of the present application;

[0050] Figure 5 is a schematic diagram of a performance curve of a multi-computing platform provided in one embodiment of the present application;

[0051] Figure 6 This is a flowchart of the steps of another method for adjusting a clock signal provided in an embodiment of the present application;

[0052] Figure 7 This is a structural diagram of a clock signal adjustment device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0054] Nowadays, electronic technology is developing rapidly. The design of integrated circuits has evolved from the integration of transistors to the integration of logic gates, and then to the integration of IP, which is today's system on chip (SOC) design. Most of the current digital integrated circuits are designed based on the global clock frequency, and the clock frequency is used to coordinate the logical timing of various working units in the digital circuit.

[0055] Typically, each operating unit in a digital integrated circuit has a corresponding operating clock. For example, a SoC core typically has at least two operating clocks: clk_core, the operating clock for the IP computing unit, and clk_dma, the operating clock for the memory access unit. The operating clock configuration is usually static, meaning that the clock frequency remains fixed after configuration. However, to ensure the normal operation of each operating unit, the clock frequency of each operating unit must be configured above the peak operating frequency of the operating unit to meet the performance requirements of the operating unit during normal operation.

[0056] However, the working unit does not always maintain a full-load operation state, and the working frequency will not always be at the peak. If the working clock is fixed above the peak of the working frequency, there will be a situation where the working clock is always much larger than the actual working frequency of the working unit, resulting in performance overflow, thereby increasing the useless power consumption of the digital integrated circuit and increasing the power consumption of the clock tree, especially the Neural-Network Processing Unit (NPU), whose clock tree power consumption can reach 30% of the total power consumption, resulting in a waste of operating resources.

[0057] Among them, NPU can be a computer microprocessor used to process artificial neural network calculations, which is a type of integrated circuit. The performance of NPU is mainly constrained by two aspects: one is compute bound, and the other is memory bound.

[0058] See also Figure 1 , Figure 1 A flowchart of a method for adjusting a clock signal provided by an embodiment of the present invention is shown, which may specifically include the following steps:

[0059] Step 101: Obtain performance status information of the processor.

[0060] The processor may be an integrated circuit for processing and handling various data. Specifically, the processor may execute fixed-point or floating-point arithmetic operations, as well as commands such as address operations and conversions. The processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an NPU, a tensor processing unit (TPU), and the like.

[0061] The above performance status information may be performance parameters of the processor when it is working. The performance parameters of the processor may include parameters such as operating frequency, frequency multiplication factor, operating voltage, usage rate, load, etc.

[0062] In practical applications, the processor may obtain data to be processed from the dynamic random access memory (DRAM), process the data, and then store the processed data in the DRAM.

[0063] See also Figure 2 , Figure 2 A schematic diagram of an NPU architecture provided by an embodiment of the present invention is shown below. Figure 2 As shown, the NPU architecture may include modules such as an instruction fetch module 2 (fetch), a read module 3 (load), a compute module 4 (compute), and a storage module 5 (store). The instruction fetch module 2 may be used to load instruction fetch instructions from the dynamic random access memory 1, and then the instruction fetch module 2 may route the instruction fetch instructions to the read module 3, the compute module 4, and the storage module 5 according to the instruction opcode corresponding to the instruction fetch instruction, specifically to the first-in-first-out queue (FIFO) of the three modules, i.e. Figure 2The queue in the memory, the reading module 3 can be used to read data from the dynamic random access memory 1 and temporarily store it in the reading buffer module (input_buffer), and temporarily store the weight corresponding to the data in the weight buffer module (weight_buffer). The calculation module 4 can obtain the data in the reading buffer module, and process the obtained data and temporarily store the processed data in the writing buffer module (output_buffer). Specifically, the calculation module 4 may include an arithmetic logic unit (Arithmetic Logic Unit, ALU), a general matrix multiplication (General Matrix Multiplication, GEMM), the ALU can be used to perform operations such as addition, MAX, MIN, etc., and the GEMM can be used to perform general matrix multiplication operations. The storage module 5 can be used to write the data in the writing buffer module into the dynamic random access memory 1.

[0064] Specifically, the data stored in the DRAM may include performance status information of the processor.

[0065] When the read module reads data from the DRAM, the performance status information stored in the DRAM can be obtained.

[0066] In a specific implementation, the performance parameters of the normal operation of the processor can be obtained in real time, and the performance parameters and their corresponding timestamps can be stored in DRAM. Then, the reading module can read the performance status information stored in DRAM and process the performance status information through the calculation module.

[0067] Step 102: Determine a target load level from all load levels based on the performance status information.

[0068] Among them, the load level can be the level of platform performance in the computing platform, the computing platform can be a platform equipped with an algorithm model, and the platform performance can be represented by the upper limit of the number of floating-point operations per second of the computing platform.

[0069] In an embodiment of the present application, the above-mentioned load levels can be divided based on application scenarios and target algorithm models. The above-mentioned application scenarios can be scenarios corresponding to the tasks currently processed by the processor, such as scenarios corresponding to processing audio and video signal decoding tasks, scenarios corresponding to processing graphics processing tasks (hereinafter referred to as graphics processing scenarios), scenarios corresponding to processing network communication tasks, etc. The above-mentioned target algorithm model can be the algorithm model adopted by the processor when processing data. The target load level can specifically be the best load level applicable to the current processor among all load levels, that is, the load level with the highest comprehensive processing performance and the lowest power consumption.

[0070] After obtaining the performance status information, the current application scenario can be determined based on the currently executed task, and then based on the performance status information, it can be determined that when the processor is in the current application scenario, it can meet the performance requirements of processing data required by the current application scenario, and the load level with the lowest power consumption of the processor is the target load level.

[0071] Step 103: According to the target load level, adjust the first clock signal to a second clock signal corresponding to the target load level.

[0072] The first clock signal may be a current clock signal of the processor, and the second clock signal may be a clock signal corresponding to a target load level.

[0073] After the target load level is determined, the current first clock signal of the processor may be adjusted to a second clock signal corresponding to the target load level.

[0074] In actual applications, the clock signal can be adjusted by editing the clock configuration. Specifically, the clock signal can be directly modified through the Basic Input Output System (BIOS) settings, or the processor multiplier can be adjusted through the BIOS settings, and the clock signal can be adjusted by changing the multiplier.

[0075] In an embodiment of the present invention, by obtaining the performance status information of the processor and then determining the target load level from all load levels based on the performance status information, the corresponding target load level can be determined based on the performance status information at different times, and according to the target load level, the first clock signal is adjusted to the second clock signal corresponding to the target load level. The clock signal can be dynamically adjusted based on the load level at different times, so that the working frequency of the working unit will not always be at the peak value, while meeting the performance requirements of the working unit at different times, thereby reducing the overflow of working performance, thereby reducing the useless power consumption of the digital circuit, and reducing the problem of waste of operating resources.

[0076] See also Figure 3 , Figure 3 A flowchart of another method for adjusting a clock signal provided by an embodiment of the present invention is shown, which may specifically include the following steps:

[0077] Step 301: Obtain performance status information of the processor.

[0078] For the relevant description of step 301, please refer to step 101 and will not be repeated here.

[0079] Step 302: Determine a target algorithm model and determine the performance characteristics of the target algorithm model in a target computing platform.

[0080] Among them, the target algorithm model can be the algorithm model adopted by the processor when processing data, the target computing platform can be the computing platform equipped with the target algorithm model, and the performance characteristics can be used to describe the performance that the target algorithm model can achieve on the target computing platform, which can be specifically displayed through function graphs, tree diagrams, etc.

[0081] It needs to be understood that a digital integrated circuit can have one or more computing platforms, such as a computing platform for graphics processing, a computing platform for program running, information processing, etc. At the same time, a digital integrated circuit is also equipped with one or more algorithm models, and different algorithm models are suitable for different application scenarios.

[0082] From the above, it can be seen that there can be at least one computing platform and at least one algorithm model in a digital integrated circuit. After obtaining the performance status information, the target algorithm model used to process the performance status information can be determined from all algorithm models, and the target computing platform equipped with the target algorithm model can be determined from all computing platforms.

[0083] After determining the target algorithm model and the target computing platform, the performance characteristics of the target algorithm model in the target computing platform can be determined.

[0084] In one embodiment of the present application, determining the performance characteristics of the target algorithm model in the target computing platform in step 302 may include steps 3021 to 3023:

[0085] Step 3021: Determine the performance range and bandwidth range of the target computing platform.

[0086] Among them, the performance range can be the computing power range of the target computing platform, that is, the range of floating-point operations that the computing platform can complete per second, and the bandwidth range can be the bandwidth range of the target computing platform, that is, the range of memory swap volume that the computing platform can complete per second.

[0087] After determining the target computing platform, we can determine the target computing platform's computing power limit, that is, the upper limit of the number of floating-point operations that the target computing platform can complete per second. Based on the computing power limit, we can then determine the target computing platform's performance range. Furthermore, we can determine the target computing platform's bandwidth limit, that is, the upper limit of the amount of memory swapping that the target computing platform can complete per second. Based on the bandwidth limit, we can then determine the target computing platform's bandwidth range.

[0088] Step 3022: Determine the computational intensity of the target algorithm model.

[0089] Compute intensity can be used to describe the number of floating-point operations per unit of memory swapping during the normal operation of the target algorithm model. Generally speaking, the compute intensity of the target algorithm model is positively correlated with memory utilization: that is, the greater the compute intensity, the higher the memory utilization.

[0090] After determining the target algorithm model, the number of floating-point operations per unit of memory exchange can be determined when the target algorithm model is operating normally, and thus the computational intensity of the target algorithm model can be determined.

[0091] In practical applications, the computational intensity of the target algorithm model can be adjusted by optimizing the model parameters in the target algorithm model.

[0092] Step 3023: Determine the performance characteristics of the target algorithm model within the performance range and bandwidth range based on the computational intensity.

[0093] Among them, the performance characteristics can be displayed through the performance curve, which can be used to describe the theoretical performance that the target algorithm model can achieve on the target computing platform. The theoretical performance can be the performance that the target algorithm model can achieve under ideal conditions, that is, the number of floating-point operations per second that the target algorithm model can achieve on the target computing platform.

[0094] After the computational intensity is obtained, the theoretical performance curve of the target algorithm model within the performance range and the bandwidth range can be determined based on the roofline model.

[0095] See also Figure 4 , Figure 4 A schematic diagram of a performance characteristic may be provided for an embodiment of the present invention, such as Figure 4 As shown, the horizontal axis can be expressed as the computing intensity (I) of the target model, the vertical axis can be expressed as the theoretical performance (P) of the target model, π can be the computing power upper limit of the computing platform, β can be the bandwidth upper limit of the target computing platform, Imax can be the computing intensity upper limit of the computing platform, Imax can be the quotient of the computing power upper limit π and the bandwidth upper limit β, curve a can be expressed as the theoretical performance curve of the target algorithm model within the performance range and the bandwidth range, the inflection point O of curve a can be expressed as when the computing intensity of the target algorithm model reaches the computing intensity upper limit of the computing platform, the best performance that can be achieved is the computing power upper limit of the computing platform, and the slope of curve a before the inflection point O can be the bandwidth upper limit of the computing platform.

[0096] Before the target algorithm model reaches the inflection point O, its theoretical performance is determined by the bandwidth limit of the computing platform and the computing intensity of the target algorithm model itself, that is, Figure 4After the target algorithm model reaches the inflection point O, its theoretical performance is determined by the computing power limit of the computing platform, that is, Figure 4 The compute bound region in .

[0097] Specifically, the theoretical performance of the target algorithm model can be determined by the following formula:

[0098]

[0099] Among them, P can be expressed as the theoretical performance of the target algorithm model, β can be the bandwidth upper limit of the target computing platform, I can be the computing intensity of the target algorithm model, and π can be the computing power upper limit of the target computing platform.

[0100] In practical applications, since a digital integrated circuit can have one or more algorithm models and one or more computing platforms, the roofline model can be used to determine the theoretical performance curve of each algorithm model in different computing platforms.

[0101] Step 303: Determine the performance requirement information of the application scenario.

[0102] The performance requirement information may be performance requirement information of an application scenario, such as throughput requirement information, bandwidth requirement information, voltage requirement information, etc.

[0103] After determining the performance characteristics of the target algorithm model, the corresponding performance requirement information can be determined based on the functions, uses or tasks involved in the application scenario.

[0104] It is important to understand that different application scenarios may correspond to different functions, uses, or tasks, and based on these different functions, uses, or tasks, the performance requirements for completing the function, use, or task may be determined. The performance requirements for completing the function, use, or task may be related to the amount of data, i.e., the larger the amount of data, the higher the performance requirements. In other words, an application scenario may correspond to at least one performance requirement. For example, a graphics processing scenario may correspond to a graphics processing task, and the minimum throughput requirement, bandwidth requirement, and voltage requirement required to complete the graphics processing task may be determined, i.e., the performance requirement information corresponding to the application scenario. A graphics processing scenario may be a scenario for processing graphics. The more complex the graphics, the greater the number of graphics that need to be processed, the larger the amount of data to be processed, and the higher the performance requirements required. Based on different performance requirements, the scenario may be divided, i.e., the performance requirements for different data volume ranges may be determined.

[0105] Step 304: Classify the performance characteristics into at least one load level based on the performance requirement information.

[0106] After the performance requirement information is obtained, corresponding frequency information may be determined based on the performance requirement information, and the performance characteristics may be further divided into at least one load level based on the frequency information.

[0107] In an embodiment of the present application, step 304 may include steps 3041 and 3042:

[0108] Step 3041: Determine the operating frequency corresponding to the application scenario based on the performance requirement information.

[0109] The operating frequency may be the minimum frequency required to achieve the corresponding function, purpose or task in the application scenario.

[0110] After obtaining the performance requirement information, the minimum throughput requirement, bandwidth requirement, and voltage requirement required for the application scenario can be determined based on the performance requirement information. Then, one or more of the minimum throughput requirement, bandwidth requirement, and voltage requirement can be weighted calculated to generate the complexity corresponding to the application scenario and determine the operating frequency corresponding to the complexity.

[0111] Since there can be multiple types of application scenarios in actual operation scenarios, the complexity corresponding to each application scenario can be determined through the performance requirement information corresponding to each application scenario. The complexity corresponding to all application scenarios can be classified, and the working frequency corresponding to the complexity of each category can be determined.

[0112] Specifically, each application scenario may correspond to at least one performance requirement, and each performance requirement may correspond to a complexity, which means that each application scenario may correspond to at least one complexity.

[0113] In practical applications, the minimum operating frequency required for each category of complexity can be obtained by conducting experiments on each category of complexity, or the minimum operating frequency required for each category of complexity can be determined through simulation or theoretical calculation, and then the operating frequencies corresponding to all complexities can be determined based on the minimum operating frequencies required for all categories of complexity.

[0114] In a specific implementation, the minimum operating frequency corresponding to the complexity of each category can be sorted from low to high according to the size of the operating frequency, and the operating frequency corresponding to each complexity can be defined as any operating frequency between the minimum operating frequency corresponding to the complexity and the minimum operating frequency corresponding to the next complexity.

[0115] For example, in the same application scenario, the minimum operating frequency corresponding to complexity a is 200 MHZ, and according to the sorting, the next complexity of complexity a can be determined to be complexity b, and the minimum operating frequency corresponding to complexity b is 500 MHZ. Then, any operating frequency between 200 MHZ and 500 MHZ can be defined as the operating frequency corresponding to complexity a.

[0116] As an example, the median between the lowest operating frequency corresponding to a complexity and the operating frequency corresponding to the next complexity can be defined as the operating frequency corresponding to the complexity. For example, the operating frequency corresponding to complexity a can be the median of the operating frequencies 200MHZ to 500MHZ, which is 350MHZ.

[0117] Step 3042: Divide the performance characteristics into at least one load level according to the operating frequency.

[0118] After determining the operating frequencies corresponding to all application scenarios, the performance characteristics can be divided into load levels corresponding to the complexity of the application scenarios based on different application scenarios.

[0119] In practical applications, an application scenario may include at least one complexity, and the performance curve corresponding to the performance characteristic may be divided into at least one load level based on the operating frequency corresponding to each complexity.

[0120] For example, the complexity of application scenario A may include complexity a, complexity b and complexity c, and the operating frequency corresponding to complexity a may be 200MHZ, the operating frequency corresponding to complexity b may be 500MHZ, and the operating frequency corresponding to complexity c may be 800MHZ. Then, according to the operating frequency corresponding to each complexity, the performance curve can be divided into load levels corresponding to the complexity, that is, divided into three load levels, including the load level corresponding to complexity a, the load level corresponding to complexity b, and the load level corresponding to complexity c.

[0121] It should be understood that the above method for determining load levels is merely an example of a target computing platform, and an actual digital integrated circuit may include multiple computing platforms. Thus, for each computing platform, load levels can be divided based on the above method.

[0122] See also Figure 5 , Figure 5 A schematic diagram of a performance curve of a multi-computing platform provided by an embodiment of the present invention is shown as follows: Figure 5As shown, the horizontal axis can be expressed as the computing intensity of the target model, and the vertical axis can be expressed as the theoretical performance of the target model. 3.5TFLOP / s to 100TFLOP / s can be the upper limit of computing power for different computing platforms, and 300GB / S to 10KGB / S can be the upper limit of bandwidth for different computing platforms. The performance curves of the target algorithm model on different computing platforms can then be divided into load levels.

[0123] Step 305: Determine a target load level from all load levels based on the performance status information.

[0124] Step 306: According to the target load level, adjust the first clock signal to a second clock signal corresponding to the target load level.

[0125] For the relevant descriptions of steps 305 to 306, please refer to steps 102 to 103 and will not be repeated here.

[0126] In an embodiment of the present invention, by obtaining the performance status information of the processor and determining the target algorithm model, the performance characteristics of the target algorithm model in the target computing platform are determined, and the performance characteristics are divided into at least one load level based on the performance requirement information of the application scenario. The target load level is determined from all load levels according to the performance status information, so that the corresponding target load level can be determined based on the performance status information at different times, and the first clock signal is adjusted to the second clock signal corresponding to the target load level according to the target load level. The clock signal can be dynamically adjusted based on the load level at different times, so that the working frequency of the working unit will not always be at the peak value, while meeting the performance requirements of the working unit at different times, thereby reducing the overflow of working performance, thereby reducing the useless power consumption of the digital circuit, and reducing the problem of waste of operating resources.

[0127] See also Figure 6 , Figure 6 A flowchart of another method for adjusting a clock signal provided by an embodiment of the present invention is shown, which may specifically include the following steps:

[0128] Step 601: Obtain performance status information of the processor.

[0129] For the relevant description of step 601, please refer to step 101 and will not be repeated here.

[0130] Step 602: Determine whether a clock switching condition is triggered based on the performance status information.

[0131] The performance status information may include bandwidth status information and throughput status information. The bandwidth status information may be the bandwidth usage status at the current moment, and the throughput status information may be the throughput at the current moment. The clock switching condition may be used to determine whether to switch the clock frequency.

[0132] After the performance status information is obtained, it can be determined whether a clock switching condition is triggered based on the bandwidth status information and the throughput status information.

[0133] In an embodiment of the present application, step 602 may include steps 6021 and 6022:

[0134] Step 6021: When the bandwidth status information is within the bandwidth range and the throughput status information is within the throughput range, it is determined that the clock switching condition is not triggered.

[0135] The bandwidth range may correspond to the clock frequency at the current moment, and the throughput range may correspond to the clock frequency at the current moment.

[0136] It should be understood that the current application scenario can correspond to at least one complexity, and the complexity can correspond to an operating frequency. Then, at least one operating frequency range can be determined based on the operating frequency between each two adjacent complexities, thereby ensuring that the clock frequency at the current moment is within any operating frequency range corresponding to the current application scenario, that is, the operating frequency range corresponding to the clock frequency at the current moment.

[0137] Different complexities can correspond to different bandwidth requirements and throughput requirements, which means that different operating frequency ranges can correspond to different bandwidth requirements and throughput requirements. After determining the operating frequency range corresponding to the clock frequency at the current moment, the bandwidth requirement and throughput requirement corresponding to the operating frequency range can be determined, and the corresponding bandwidth range and throughput range can be determined based on the determined bandwidth requirement and throughput requirement.

[0138] For example, the application scenarios at the current moment may include complexity a, complexity b and complexity c, and the operating frequency corresponding to complexity a may be 200MHZ, the operating frequency corresponding to complexity b may be 500MHZ, and the operating frequency corresponding to complexity c may be 800MHZ. Based on complexity a and complexity b, the operating frequency range 1 can be determined to be 200MHZ to 500MHZ, and based on complexity b and complexity c, the operating frequency range 2 can be determined to be 500MHZ to 800MHZ. The clock frequency at the current moment may be 600MHZ, and it can be determined that the clock frequency 600MHZ at the current moment is within the operating frequency range 2. The bandwidth range and throughput range corresponding to the operating frequency range 2 can be determined.

[0139] After obtaining the performance status information, the bandwidth status information can be compared with the bandwidth range to determine whether the bandwidth corresponding to the bandwidth status information is within the bandwidth range, and the throughput status information can be compared with the throughput range to determine whether the throughput corresponding to the throughput status information is within the throughput range.

[0140] When the bandwidth corresponding to the bandwidth status information is within the bandwidth range and the throughput corresponding to the throughput status information is within the throughput range, it can be determined that the clock frequency at the current moment meets the performance requirements at the current moment, and relative to the peak value of the clock frequency, the degree of performance overflow at the current moment is low, that is, the performance overflow is reduced, and it can be determined that there is no need to switch the clock frequency, that is, the clock switching condition is not triggered.

[0141] Step 6022: When the bandwidth status information is not within the bandwidth range, or the throughput status information is not within the throughput range, determine whether a clock switching condition is triggered.

[0142] After obtaining the performance status information, the bandwidth status information can be compared with the bandwidth range to determine whether the bandwidth corresponding to the bandwidth status information is within the bandwidth range, and the throughput status information can be compared with the throughput range to determine whether the throughput corresponding to the throughput status information is within the throughput range.

[0143] When the bandwidth corresponding to the bandwidth status information is less than the bandwidth range, or the throughput corresponding to the throughput status information is less than the throughput range, it can be determined that the clock frequency at the current moment does not meet the performance requirements at the current moment, and the clock frequency at the current moment needs to be increased to meet the current performance requirements, thereby triggering the clock switching condition.

[0144] Alternatively, when the bandwidth corresponding to the bandwidth status information is greater than the bandwidth range, or the throughput corresponding to the throughput status information is greater than the throughput range, it can be determined that the clock frequency at the current moment meets the performance requirements at the current moment, but relative to all operating frequencies, the degree of performance overflow corresponding to the clock frequency at the current moment is not the lowest, that is, there is a performance overflow and it can be optimized. It can then be determined that the clock frequency needs to be switched to reduce the clock frequency at the current moment to reduce the degree of performance overflow, thereby reducing the performance overflow, that is, triggering the clock switching condition.

[0145] It should be understood that bandwidth and throughput are positively correlated. It is rare for the bandwidth corresponding to the bandwidth status information to be greater than the bandwidth range, while the throughput corresponding to the throughput status information is less than the throughput range. Alternatively, the bandwidth corresponding to the bandwidth status information is less than the bandwidth range, while the throughput corresponding to the throughput status information is greater than the throughput range. Therefore, this embodiment does not provide examples. However, for these two situations, experience or experimentation can be used to determine whether to trigger a clock switching condition. Alternatively, the target performance status information that has the greatest impact on the current application scenario can be determined from the bandwidth and throughput, and the above-described method can be used to determine whether to trigger a clock switching condition based on this target performance status information.

[0146] Step 603: When the clock switching triggering condition is determined, a step of determining a target load level corresponding to the performance status information from all load levels is executed.

[0147] When determining the clock switching triggering condition, a step of determining a target load level corresponding to the performance status information from all load levels may be performed.

[0148] When it is determined that the clock switching condition has not been triggered, it can be determined that the clock frequency at the current moment can meet the performance requirements, and the performance overflow at the current moment is low compared to the peak value of the clock frequency. Therefore, it can be determined that there is no need to switch the clock frequency, that is, continue to maintain the current clock frequency until the clock switching condition is triggered at any time in the future.

[0149] In one embodiment of the present application, the step of determining the target load level corresponding to the performance status information from all load levels in step 603 may include steps 6031 to 6033:

[0150] Step 6031: Determine the load range corresponding to each load level.

[0151] The load range may be a range of operating frequencies.

[0152] When determining the conditions for triggering clock switching, the current application scenario can be determined, and then all load levels corresponding to the previous application scenario can be determined, and the operating frequencies corresponding to all load levels can be determined, and at least one operating frequency range can be determined based on each operating frequency.

[0153] Step 6032: Determine actual load information based on the performance status information.

[0154] The actual load information may be actual performance requirements.

[0155] When determining the conditions for triggering clock switching, the performance requirements at the current moment may be evaluated based on the bandwidth status information and the throughput status information, and the operating frequency corresponding to the performance requirements at the current moment may be determined.

[0156] Step 6033: Determine the target load range where the actual load information is located from all load ranges, and determine the target load level corresponding to the target load range.

[0157] After determining the actual load information and the load range corresponding to each load level, the target load range of the operating frequency corresponding to the current performance requirement can be determined from all load ranges, and the target load level corresponding to the target load range can be determined.

[0158] In practical applications, each load level may correspond to a different operating frequency range, and the target operating frequency range corresponding to the performance requirement at the current moment, i.e., the target load range, may be determined from the operating frequency ranges corresponding to all load levels.

[0159] For example, the current application scenario may include load level 1 and load level 2, and the operating frequency range corresponding to load level 1 may be 200MHZ to 500MHZ, and the operating frequency range corresponding to load level 2 may be 500MHZ to 800MHZ, while the operating frequency corresponding to the performance requirement at the current moment may be 600MHZ. It can be determined that the operating frequency corresponding to the performance requirement at the current moment is within the operating frequency range corresponding to load level 2, that is, load level 2 is the target load level.

[0160] Step 604: According to the target load level, adjust the first clock signal to a second clock signal corresponding to the target load level.

[0161] For the relevant description of step 604, please refer to step 103 and will not be repeated here.

[0162] In an embodiment of the present invention, by obtaining the performance status information of the processor, it is determined whether the clock switching condition is triggered based on the performance status information. When it is determined that the clock switching condition is triggered, the step of determining the target load level corresponding to the performance status information from all load levels is executed, and then the target load level is determined from all load levels based on the performance status information, so that the corresponding target load level can be determined based on the performance status information at different times, and the first clock signal is adjusted to the second clock signal corresponding to the target load level based on the target load level. The clock signal can be dynamically adjusted based on the load level at different times, so that the working frequency of the working unit will not always be at the peak value, while meeting the performance requirements of the working unit at different times, thereby reducing the overflow of working performance, thereby reducing the useless power consumption of the digital circuit, and reducing the problem of waste of operating resources.

[0163] Reference Figure 7 , Figure 7 The following is a schematic diagram showing the structure of a clock signal adjustment device provided by an embodiment of the present invention, which may specifically include the following modules:

[0164] An acquisition module 701 is used to acquire performance status information of a processor;

[0165] a determination module 702 for determining a target load level from all load levels according to the performance status information, wherein the load level corresponds to an application scenario;

[0166] The adjustment module 703 is configured to adjust the first clock signal to a second clock signal corresponding to the target load level according to the target load level.

[0167] In one implementation, the determining module 702 may also be configured to:

[0168] Before determining the target load level from all the load levels according to the performance status information, determining a target algorithm model and determining performance characteristics of the target algorithm model in a target computing platform;

[0169] Determine the performance requirements of the application scenario;

[0170] The performance characteristics are divided into at least one load level based on the performance requirement information.

[0171] In one implementation, the determining module 702 may also be configured to:

[0172] Determine the performance range and bandwidth range of the target computing platform;

[0173] Determining the computational intensity of the target algorithm model;

[0174] According to the computational intensity, performance characteristics of the target algorithm model within the performance range and the bandwidth range are determined.

[0175] In one implementation, the determining module 702 may also be configured to:

[0176] Determining an operating frequency corresponding to the application scenario based on the performance requirement information;

[0177] The performance characteristic is divided into at least one load class according to the operating frequency.

[0178] In one implementation, the apparatus may further include the following modules:

[0179] a judging module, configured to judge whether a clock switching condition is triggered according to the performance status information before determining the target load level from all the load levels according to the performance status information;

[0180] An execution module is used to execute the step of determining a target load level corresponding to the performance status information from all the load levels when it is determined that the clock switching condition is triggered.

[0181] In one implementation, the performance status information includes bandwidth status information and throughput status information. The determination module may also be configured to:

[0182] When the bandwidth status information is not within the bandwidth range and / or the throughput status information is not within the throughput range, determining a clock switching triggering condition;

[0183] When the bandwidth status information is within the bandwidth range and the throughput status information is within the throughput range, it is determined that a clock switching condition is not triggered.

[0184] In one implementation, the determining module 702 may also be configured to:

[0185] Determining a load range corresponding to each load level;

[0186] determining actual load information based on the performance status information;

[0187] A target load range in which the actual load information is located is determined from all the load ranges, and a target load level corresponding to the target load range is determined.

[0188] In an embodiment of the present invention, by obtaining the performance status information of the processor and then determining the target load level from all load levels based on the performance status information, the corresponding target load level can be determined based on the performance status information at different times, and according to the target load level, the first clock signal is adjusted to the second clock signal corresponding to the target load level. The clock signal can be dynamically adjusted based on the load level at different times, so that the working frequency of the working unit will not always be at the peak value, while meeting the performance requirements of the working unit at different times, thereby reducing the overflow of working performance, thereby reducing the useless power consumption of the digital circuit, and reducing the problem of waste of operating resources.

[0189] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices are based on the same concept as the method embodiment of this application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0190] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0191] An embodiment of the present application provides an integrated circuit, characterized in that the integrated circuit includes: at least one logic circuit for performing at least one algorithmic function, and the logic circuit implements the steps of any one of the above method embodiments when executing the algorithmic function.

[0192] An embodiment of the present application further provides a controller, which includes the integrated circuit described in the above embodiment. The controller can be used to control the integrated circuit described in the above embodiment to execute algorithm functions and implement the steps in any of the above method embodiments.

[0193] The embodiment of the present application further provides a vehicle, which includes the controller described in the above embodiment. As an example, the vehicle can be a means of transportation, such as a car, a ship, an aircraft, etc.

[0194] If the units in the above-mentioned integrated circuit are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal and a software distribution medium.

[0195] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for adjusting a clock signal, characterized in that: The method comprises: Get the performance status information of the processor; Determining a target load level from all load levels based on the performance status information, wherein the load levels are divided based on application scenarios and target algorithm models; According to the target load level, the first clock signal is adjusted to a second clock signal corresponding to the target load level.

2. The clock signal adjustment method according to claim 1, wherein: Before determining the target load level from all load levels according to the performance status information, the method further includes: Determining a target algorithm model and determining performance characteristics of the target algorithm model in a target computing platform; Determine the performance requirements of the application scenario; The performance characteristics are divided into at least one load level based on the performance requirement information.

3. The clock signal adjustment method according to claim 2, wherein: Determining the performance characteristics of the target algorithm model in the target computing platform includes: Determine the performance range and bandwidth range of the target computing platform; Determining the computational intensity of the target algorithm model; According to the computational intensity, performance characteristics of the target algorithm model within the performance range and the bandwidth range are determined.

4. The clock signal adjustment method according to claim 2, wherein: The dividing the performance characteristics into at least one load level based on the performance requirement information includes: Determining an operating frequency corresponding to the application scenario based on the performance requirement information; The performance characteristic is divided into at least one load class according to the operating frequency.

5. The clock signal adjustment method according to any one of claims 1 to 4, characterized in that: Before determining the target load level from all the load levels according to the performance status information, the method further Includes, including: Determining whether a clock switching condition is triggered according to the performance status information; When it is determined that the clock switching condition is triggered, the step of determining the target load level corresponding to the performance status information from all the load levels is performed.

6. The method for adjusting a clock signal according to claim 5, wherein: The performance status information includes bandwidth status information and throughput status information, and determining whether to trigger a clock switching condition based on the performance status information includes: When the bandwidth status information is not within the bandwidth range, or the throughput status information is not within the throughput range, determining a clock switching triggering condition; When the bandwidth status information is within the bandwidth range and the throughput status information is within the throughput range, it is determined that a clock switching condition is not triggered.

7. The clock signal adjustment method according to claim 6, wherein: Determining a target load level from all load levels according to the performance status information includes: Determining a load range corresponding to each load level; determining actual load information based on the performance status information; A target load range in which the actual load information is located is determined from all the load ranges, and a target load level corresponding to the target load range is determined.

8. A clock signal adjustment device, characterized in that: include: An acquisition module, used to obtain performance status information of the processor; a determination module, configured to determine a target load level from all load levels according to the performance status information, wherein the load level corresponds to an application scenario; The adjustment module is used to adjust the first clock signal to a second clock signal corresponding to the target load level according to the target load level.

9. An integrated circuit, characterized in that: include: At least one logic circuit for performing at least one algorithmic function, wherein the logic circuit implements the method according to any one of claims 1 to 7 when executing the algorithmic function.

10. A controller, characterized in that: comprising the integrated circuit of claim 9.

11. A vehicle, characterized in that: Comprising the controller of claim 10.

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