Memory controller, configuration method and computer system

Abstract

The embodiment of the invention provides a memory controller, a configuration method and a computer system, and the memory controller comprises a plurality of sub-memory controller structures; the memory controller is used for receiving a request processing signal, wherein the request processing signal comprises a memory access request for accessing a memory module; according to the working mode of the memory module accessed by the memory access request, configuring the running state of each sub-memory controller structure, so that the sub-memory controller structure after configuration of the running state supports the access of the memory access request to the memory module when the memory module is a multiplexing memory module, the performance of the multiplexing memory module is higher than that when the memory module is a common memory module. According to the technical scheme provided by the embodiment of the invention, the performance of the memory controller can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a memory controller, a configuration method, and a computer system. Background Art

[0002] With the growing demand for higher memory bandwidth in modern servers, traditional memory technologies are becoming a performance bottleneck. Despite the continuous increase in processor core count and speed, the transfer rate of memory modules has not kept pace, making memory bandwidth the limiting factor in system performance. MRDIMMs (Multiplexed RDIMMs) significantly increase memory bandwidth through innovative multiplexing technology. The memory controller is responsible for managing and scheduling memory access requests to the memory modules (DIMMs), making memory controller performance improvements and optimizations essential for MRDIMM memory access.

[0003] Therefore, how to provide a technical solution to improve the performance of the memory controller to support the memory access requirements of MRDIMM has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a memory controller, a configuration method, and a computer system to improve the performance of the memory controller.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a memory controller, comprising: a plurality of sub-memory controller structures;

[0007] The memory controller is used to:

[0008] Receive a request processing signal, wherein the request processing signal includes a memory access request for accessing a memory module; configure the operating status of each sub-memory controller structure according to the operating mode of the memory module accessed by the memory access request, so that the sub-memory controller structure after the operating status is configured supports the memory access request for accessing the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is an ordinary memory module.

[0009] In a second aspect, an embodiment of the present invention provides a configuration method, applied to the memory controller according to the first aspect, the method comprising:

[0010] receiving a request processing signal, wherein the request processing signal includes a memory access request for accessing a memory module;

[0011] According to the working mode of the memory module accessed by the memory access request, the operating status of each sub-memory controller structure in the memory controller is configured so that the sub-memory controller structure after the operating status is configured supports the memory access request to access the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is an ordinary memory module.

[0012] In a third aspect, an embodiment of the present invention provides a computer system, comprising: a memory controller as described in the first aspect.

[0013] A memory controller provided by an embodiment of the present invention includes: multiple sub-memory controller structures; the memory controller is used to: receive a request processing signal, the request processing signal including a memory access request to access a memory module; configure the operating status of each sub-memory controller structure according to the working mode of the memory module accessed by the memory access request, so that the sub-memory controller structure after the operating status is configured supports the memory access request to access the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is an ordinary memory module.

[0014] As can be seen, the technical solution provided by the embodiment of the present invention provides multiple sub-memory controller structures within the memory controller. The memory controller, through request processing signals received by the memory controller, configures the operating state of each sub-memory controller structure based on the operating mode of the memory module to be accessed by the memory access request. This allows the sub-memory controller structure, after the operating state is configured, to support memory access requests to multiplexed memory modules in addition to ordinary memory modules. This shows that the memory controller provided by the embodiment of the present invention has the function of supporting access to multiplexed memory modules, thereby expanding the application scope and functionality of the memory controller and improving the performance of the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0016] Figure 1 1 is a schematic structural diagram of a memory controller provided by an embodiment of the present invention;

[0017] Figure 2 1 is a schematic structural diagram of a sub-memory controller structure provided by an embodiment of the present invention;

[0018] Figure 3 is another structural diagram of a memory controller provided by an embodiment of the present invention;

[0019] Figure 4 This is a flow chart of a configuration method provided by an embodiment of the present invention;

[0020] Figure 5 It is a structural diagram of a computer system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0022] As CPU (central processing unit) core counts and processing speeds continue to increase, traditional DDR5 memory modules (such as RDIMMs, Registered DIMMs) are becoming performance bottlenecks in terms of bandwidth and latency. Modern data centers and artificial intelligence (AI) applications require higher memory bandwidth to support large-scale data processing and model training.

[0023] MRDIMM (Multiplexed Rank Dual In-Line Memory Module) is a new type of multiplexed memory module designed to meet the high memory bandwidth and capacity demands of modern data centers, high-performance computing (HPC), and artificial intelligence applications.

[0024] MRDIMM significantly improves memory bandwidth and data transmission efficiency through multiplexing technology.

[0025] At the same time, in order to efficiently and reliably manage access to memory modules, the memory controller is an indispensable component in the computer system. It not only manages access operations to memory modules, but also ensures the efficient operation of the entire system by optimizing performance, improving reliability, supporting multiple memory types, and reducing processor burden.

[0026] However, with the development of memory module technology, after the emergence of multiplexed memory modules such as MRDIMM, there is no suitable memory controller to manage access to the multiplexed memory modules.

[0027] Based on this, an embodiment of the present invention provides a memory controller that supports access to common memory modules while also supporting access to multiplexed memory modules, thereby improving the performance of the memory controller.

[0028] Please refer to Figure 1 , Figure 1 It is a structural diagram of a memory controller provided by an embodiment of the present invention.

[0029] like Figure 1 As shown, the memory controller 1 includes:

[0030] Multiple sub-memory controller structures 11;

[0031] The memory controller 1 is used for:

[0032] Receive a request processing signal, wherein the request processing signal includes a memory access request for accessing a memory module; and configure the operating status of each sub-memory controller structure 11 according to the operating mode of the memory module accessed by the memory access request, so that the sub-memory controller structure after the operating status is configured supports the memory access request for accessing the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is an ordinary memory module.

[0033] For example, a multiplexed memory module such as MRDIMM, a common memory module such as DDR5 memory module, etc., and the performance of MRDIMM is higher than that of DDR5 memory module.

[0034] The working mode of the memory module is related to the specific memory module used, that is, the corresponding working mode is determined based on a certain type of memory module currently in use.

[0035] It should be noted that each sub-memory controller structure 11 can independently process memory access requests to support memory access requests to ordinary memory modules. In other words, the sub-memory controller structure 11 can be a structure that supports access to ordinary memory modules, such as an ordinary memory controller that supports DDR5 memory modules. Therefore, each sub-memory controller structure 11 itself has the function of processing memory access requests for ordinary memory modules.

[0036] To understand the architecture of the sub-memory controller structure 11, please refer to Figure 2 , Figure 2 It is a structural diagram of a sub-memory controller structure provided by an embodiment of the present invention.

[0037] like Figure 2 As shown, the sub-memory controller structure 11 includes:

[0038] The front-end interface (FEI) module 111 is configured to receive memory access requests (e.g., read or write requests) from an upstream module of the memory controller 1. These memory access requests are sent to the front-end interface module 111 of the sub-memory controller structure 11 via the system data path (SDP) interface.

[0039] The request storage module 112 (i.e., the Data Command Queue (DCQ) in a common memory controller) is responsible for converting the addresses in the memory access requests into the "normal addresses" of the common memory modules. These memory access requests are then stored in the DCQ.

[0040] The arbitration (ARB) module 113 is responsible for managing memory access requests within the DCQ. It records page status via the PGT (Page Status Tracking) module and timing information via the TIM (Timing Information Management) module. Arbitration module 113 arbitrates memory access requests within the DCQ based on a specific strategy, selecting the optimal request and sending it to the BackEnd Queue (BEQ) module 114. The BEQ implements DRAM protocol encoding and control switching.

[0041] Among them, SPAZ (SelfRefresh PowerDown ZQCalibration, self-refresh, low power mode, impedance calibration) is used to manage the low power supply functions of DRAM, including self-refresh (SelfRefresh), low power mode (Powerdown), refresh (Refresh), calibration (calibration) and other functions.

[0042] The bus encoding queue module 114 encodes received memory access requests into a command data format that conforms to the protocol of a common memory module. These formatted commands are sent to the physical interface (PHY) via the memory module front-end interface (DFI), ultimately reaching the common memory module.

[0043] Figure 2 The write data buffer (WDB) module 115 shown in FIG. 1 is used when the memory access request is a write request.

[0044] If the memory access request is a write request, the corresponding write data wdata will be stored in the write data storage module 115. After sending the write request, the bus encoding queue module 114 will send the write data stored in the write data storage module 115 at an appropriate time.

[0045] If the memory access request is a read request, the bus encoding queue module 114 will also receive the read data rdata returned by the ordinary memory module at an appropriate time after sending the read request, and convert it into a data packet that complies with the SDP interface protocol and return it to the upstream module.

[0046] For example, in Figure 2 In the illustrated architecture, the DFI can operate in different clock ratio modes, such as a 1:2 or 1:4 ratio. This means the DFI interface clock frequency can be twice or four times the clock frequency of the memory controller 1. This design allows the memory controller 1 to operate in different performance and power modes.

[0047] As can be seen, the technical solution provided by the embodiment of the present invention provides multiple sub-memory controller structures 11 within the memory controller 1. The memory controller 1 receives a request processing signal and configures the operating state of each sub-memory controller structure 11 based on the operating mode of the memory module to be accessed by the memory access request. This allows the sub-memory controller structure, after the operating state is configured, to support memory access requests to multiplexed memory modules in addition to ordinary memory modules. Therefore, the memory controller 1 provided by the embodiment of the present invention has the function of supporting access to multiplexed memory modules, thereby expanding the application scope and functionality of the memory controller and improving the performance of the memory controller.

[0048] Please continue to refer to Figure 1 and Figure 2 To further improve the reliability of the memory controller 1 in supporting access to multiplexed memory modules, in one embodiment, each sub-memory controller structure 11 includes a synchronization module 110; the memory controller 1 is further configured to:

[0049] Configuring the operating state of the synchronization module 110 of each of the sub-memory controller structures 11 according to the operating mode of the memory module accessed by the memory access request;

[0050] When the memory controller 1 configures the operation states of the sub-memory controller structures 11 to be started, the operation states of the synchronization modules 110 of the sub-memory controller structures 11 are configured to be in a working state, so that when each started sub-memory control structure 11 processes a corresponding received memory access request, the memory access request processing information between the started sub-memory control structures 11 is synchronized based on each synchronization module 110 in a working state; the memory access request processing information indicates the current processing status of the memory access request;

[0051] When the memory controller 1 configures the operating state of each sub-memory controller structure 11 to start a sub-memory controller structure, the operating state of the synchronization module 110 of each sub-memory controller structure 11 is configured to be an idle state.

[0052] The memory access request processing information indicates the current processing status of the memory access request, which means the specific status and behavior of the memory access request when each sub-memory controller structure 11 processes the memory access request received at the current moment, so as to meet the use and working requirements of different memory modules.

[0053] The specific status and behavior of the memory access request may include, for example: the timing and direction of the memory access request, the type of the memory access request (read or write), the address of the memory access request, the status of data transmission, and the like.

[0054] In the memory controller 1 provided in an embodiment of the present invention, each sub-memory controller structure 11 is additionally provided with a synchronization module 110. When the operation state of the synchronization module 110 is the working state, the memory access request processing information of each sub-memory controller structure 11 configured to be started can be synchronized, thereby meeting the use requirements of the multiplexed memory module, so that the memory controller 1 can more reliably and stably support access to the multiplexed memory module.

[0055] When the memory controller 1 configures the operating status of each sub-memory controller structure 11, software configuration or hardware configuration may be used.

[0056] For example, if the operating status of each sub-memory controller structure 11 is configured using software configuration, a control signal, such as an enable signal (enable) or a disable signal (disable), can be sent through a software program. The software program can monitor the operating mode of the memory module accessed by the current memory access request in real time, and generate a control signal in real time based on the monitoring result. When it is detected that the operating mode of the memory module is: the compatibility mode of the ordinary memory module or the non-multiplexed mode (Rank Mode) of the MRDIMM, an enable signal for starting one of the sub-memory controller structures and a disable signal for shutting down the remaining sub-memory controller structures can be sent, and a disable signal for shutting down the synchronization module 110 can be sent at the same time. When it is detected that the operating mode of the memory module is: the multiplexing mode (Mux Mode) of the MRDIMM, an enable signal for starting all sub-memory controller structures can be sent, and an enable signal for starting the synchronization module can be sent at the same time.

[0057] If the operating status of each sub-memory controller structure 11 is configured using hardware configuration, the hardware configuration can be a solidified program. When the computer system is powered on, the configuration information of the current computer system is obtained, the working mode of the memory module used in the computer system is clarified, and the memory controller 1 is triggered to configure the sub-memory controller structure 11.

[0058] If the operating mode of the memory modules used in the computer system is clearly the compatibility mode of ordinary memory modules or the Rank Mode of multiplexed memory modules, the memory controller uses a fuse to fuse the control circuits of the inoperative sub-memory controller structure, maintain connectivity of the control circuits of the operational sub-memory controller structure, and fuse the control circuits of each synchronization module. If the operating mode of the memory modules used in the computer system is clearly the Mux Mode of multiplexed memory modules, connectivity of the control circuits of each sub-memory controller structure and the synchronization module is maintained.

[0059] Hardware configuration is suitable for scenarios where the memory modules and their operating modes are well-defined, providing relatively simple control. Software configuration allows for flexible changes to the structure of each sub-memory controller within the memory controller and the operating status of the synchronization module. This makes it suitable for complex operating scenarios where the computer system integrates both standard and multiplexed memory modules. Software and hardware configuration can be selected based on specific usage scenarios and requirements.

[0060] In one embodiment, the memory controller 1 determines an operating mode of the multiplexing memory module when the memory module accessed according to the memory access request is a multiplexing memory module;

[0061] If the operating mode of the multiplexed memory module is a non-multiplexed mode, configuring the operating state of one sub-memory controller structure to be enabled, configuring the operating state of the remaining sub-memory controller structures to be disabled, and configuring the operating state of the synchronization modules of the respective sub-memory controller structures to be in an idle state;

[0062] If the working mode of the multiplexing memory module is the multiplexing mode, the running state of each sub-memory controller structure is configured to be started, and the running state of the synchronization module of each sub-memory controller structure is configured to be the working state.

[0063] As mentioned above, the two modes of the multiplexed memory module (MRDIMM): multiplexed module (MuxMode) mode and non-multiplexed mode (RankMode) are intended to achieve higher bandwidth and performance by optimizing memory access methods.

[0064] Mux Mode is a key feature of MRDIMMs. By integrating a multiplexer (Mux) chip on the memory module, it allows data to be transferred simultaneously between two ranks (memory arrays). Conventional memory modules typically contain two ranks, but only one rank can be accessed at a time, leaving the other rank idle.

[0065] A rank is a group of DRAM chips in a memory module that share the same control signals (such as address and command signals) but can be accessed independently through the chip select signal (CS#).

[0066] MRDIMMs use a mux chip to merge the data channels of two ranks, allowing both ranks to transmit data simultaneously. Data is transmitted between the two ranks in a time-interleaved manner: during one clock cycle, one rank transmits data, while during the next clock cycle, the other rank transmits data. This allows the MRDIMM's data transfer rate to be increased by accessing both ranks simultaneously. For example, the first-generation DDR5 MRDIMM (Gen1) achieved a data transfer rate of 8800 MT / s, a nearly 40% increase compared to standard memory modules, such as DDR5 RDIMMs (6400 MT / s). Subsequent iterations of DDR5 MRDIMMs, such as the second-generation DDR5 MRDIMM (Gen2), can achieve data transfer rates of up to 19200 MT / s. This fully utilizes the parallel resources of the memory module and avoids the problem of idle ranks in standard memory modules.

[0067] Of course, the data transmission rate of the above-mentioned first-generation MRDIMM is only an example. With the continuous development of memory modules, the data transmission rate of memory modules can be further improved.

[0068] Rank Mode refers to a mode in which MRDIMMs significantly increase memory capacity by introducing more ranks (e.g., 4 ranks). For example, MRDIMMs can use a higher Tall Form Factor (TFF), allowing the capacity of a single memory module to reach 256GB. Of course, in other implementations, MRDIMMs can also use other technologies to achieve increased memory capacity in Rank Mode.

[0069] Conventional memory modules typically contain one or two ranks (memory arrays) within a single module to balance performance and capacity. This Rank Mode design enables the MRDIMM to access data from both ranks within a single clock cycle, thereby exponentially increasing the module's capacity. This means that while the planar area of ​​a single memory module remains unchanged, increasing the ranks in height exponentially increases the memory capacity.

[0070] It can be seen that different working modes of the multiplexed memory module have different usage characteristics and structural characteristics. Based on this, in order to support the performance of different working modes of the multiplexed memory module, the embodiment of the present invention flexibly configures the operating status of each sub-memory controller structure 11 in the memory controller 1.

[0071] Of course, after configuring the operating status of each sub-memory controller structure 11, based on the above content, the operating status of each synchronization module 110 can also be configured at the same time to meet the working requirements in the Mux Mode of the MRDIMM.

[0072] The following describes in detail the configuration of the two MRDIMM modes.

[0073] First, regarding non-multiplexed mode, although MRDIMMs in non-multiplexed mode increase memory capacity, access to each rank remains the same as for standard memory modules: each rank is accessed independently. In other words, in Rank Mode, memory controller 1 can perform independent read and write operations on each rank, rather than merging data from multiple ranks for transmission.

[0074] Therefore, the configuration at this time can be the same as that of an ordinary memory module: one of the sub-memory controller structures 11 is selected as the final working device, that is, only the operating status of one of the sub-memory controller structures 11 is configured to be started.

[0075] Since the various ranks are not merged for transmission at this time, the synchronization of memory access request processing information is not involved. Therefore, when only one of the sub-memory controller structures 11 is configured to operate in a startup state, the operating states of the various synchronization modules 110 can be configured to be idle at the same time, and the synchronization module 110 does not need to work.

[0076] In one embodiment, when the operation mode of the multiplexing memory module is a non-multiplexing mode, the memory controller is further configured to perform address encoding management on each memory array in the memory module in the non-multiplexing mode.

[0077] In MRDIMM Rank Mode, the number of ranks increases, but each rank is still accessed independently. Therefore, to ensure accurate access to each rank for memory requests, special address encoding and control signals can be introduced. For example, an improved Multiplexed Registered Clock Driver (MRCD) and address encoding extensions are added to MRDIMM to enable independent rank access.

[0078] The MRCD can generate multiple independent chip select signals (such as CS#), for example, supporting four ranks, so that the memory controller 1 can activate and access each rank separately, rather than just operating all ranks simultaneously.

[0079] Address code extension refers to adding an address code to the 13th bit (CA13) of the first unit interval (UI) of a memory access request to identify the rank. This extended address code allows the memory controller 1 to precisely specify the rank to be accessed, enabling independent access to each rank.

[0080] In order to support the implementation of the above-mentioned MRDIMM functions in Rank Mode, the memory controller 1 provided in the embodiment of the present invention adds a function of performing address encoding management on each memory array.

[0081] For example, Figure 2 Taking the sub-memory controller structure 11 shown as an example, when the memory controller 1 provided by the embodiment of the present invention adds the function of address coding management for each memory array, address coding bits can be set in the request storage module 112, the arbitration module 113 and the bus coding queue module 114. The address coding bits are used to perform address coding management on each memory array in the memory module in non-multiplexing mode.

[0082] The address coding bit may correspond to the 13th bit mentioned above.

[0083] Next, for the multiplexing mode (Mux Mode), the memory controller 1 must support the MuxMode function of MRDIMM, that is, it can realize the combined transmission of multiple ranks. Therefore, in this case, the configuration of each sub-memory controller structure 11 is to configure the operating status of all sub-memory controller structures 11 to be started.

[0084] At the same time, in this case, since multiple ranks need to be merged and transmitted, the memory controller 1 must meet the restrictions when transmitting memory access requests, and adopts the method of synchronizing the memory access request processing information between each sub-memory controller structure 11 to meet the restrictions. At this time, the operating status of each synchronization module 110 can be configured as a working state.

[0085] To facilitate the accurate output of each command in multiplexing mode, please continue to refer to Figure 1 , the memory controller 1 may further include:

[0086] The multiplexing output unit 12 is used to receive the commands obtained after the sub-memory controller structure 11 processes the memory access request; and when the working mode of the multiplexing memory module is the multiplexing mode, select and output the commands sent by each activated sub-memory controller structure.

[0087] The multiplexer output unit 12 is a multiplexer selector (DEI MUX), whose main function is to select an input signal according to a control signal (selection signal) and transmit it to the output end, so as to select and switch between multiple input signals (such as commands obtained after memory access request processing) and transmit one of the commands to the output end.

[0088] In one embodiment, when the working mode of the multiplexed memory module is the multiplexing mode, the memory access request processing information synchronized by the synchronization module 110 includes: direction synchronization information of the memory access request and timing synchronization information of the memory access request; the synchronized memory access request processing information enables the commands sent by each activated sub-memory controller structure to have the same command execution direction and meet the timing requirements specified when the command is executed.

[0089] In MRDIMMs, the physical channel is divided into multiple pseudo channels, each capable of independent read and write operations. Pseudo channels are a virtual channel technology that further divides the physical memory channel. For example, a physical channel can be divided into two independent sub-channels (pseudo channels), each capable of independent read and write operations.

[0090] However, in multiplexing mode, MRDIMMs multiplex commands sent from two pseudo channels onto the same physical channel by time-interleaving. Therefore, to correctly use multiplexed memory modules in this mode, ensure the following:

[0091] Data direction consistency: The direction (read or write) of the commands in the two pseudo channels must be the same because the MRDIMM cannot simultaneously process a read command processed and sent by one pseudo channel and a write command processed and sent by another channel in multiplexing mode.

[0092] Design limitations: This design is intended to simplify signal processing and improve data transmission efficiency, but it also limits the independence of the Pseudo Channel.

[0093] On the other hand, the MRCD and MDB (Multi-Plexed Data Buffer) in the multiplexed memory module are key interface chips that work together to achieve efficient data transmission in the multiplexed memory module. Their use has certain timing requirements, including:

[0094] Timing synchronization: The MRCD is responsible for buffering and re-driving the address, command, and clock signals from the memory controller and sending these signals to the MDB. Due to the high-speed characteristics of the MRDIMM, the timing of these signals must be strictly synchronized to ensure data integrity and accuracy.

[0095] Command sharing and timing requirements: Certain control commands, such as PDE (Precharge All Command), PDX (Precharge Specified Row Command), SRE (Self-Refresh Entry Command), SRX (Self-Refresh Exit Command), MRS (Mode Register Set Command), and MRR (Mode Register Read Command), are shared by both Pseudo Channels. These control commands are used to manage and configure the state of the multiplexed memory module, ensuring that the multiplexed memory module can correctly respond to commands issued by the memory controller after memory access requests are processed. The transmission of these control commands must meet the timing requirements of both Pseudo Channels.

[0096] Signal topology optimization: To meet these timing requirements, MRDIMMs use special signal topology designs, such as the Y topology, to reduce signal loading and extend operating frequency.

[0097] Since the memory access synchronization processing information indicates the current processing status of the memory access request, it is possible to clearly understand the current specific status and behavior of the memory access request when each sub-memory controller structure 11 processes the corresponding received memory access request, so as to adjust the direction and timing of the memory access request processed by each sub-memory controller structure 11 based on the synchronization of the memory access synchronization processing information, thereby meeting the working requirements of the MRDIMM and allowing the MRDIMM to correctly process the command formed after the memory access request is processed.

[0098] Therefore, in order to enable the memory controller to support MRDIMM access in the above-mentioned multiplexing mode, the memory controller 1 provided in an embodiment of the present invention configures each sub-memory controller structure 11 to be started, and also configures the operating state of each synchronization module 110 to be a working state, so that the synchronization module 110 can synchronize memory access request processing information between each sub-memory controller structure 11, thereby ensuring the direction synchronization of the commands sent by each sub-memory controller structure 11, and the timing synchronization of the processed commands.

[0099] In order to enable the synchronization module 110 to synchronize commands, in one embodiment, the memory controller 1 is further configured to: configure the synchronization module 110 as a master synchronization module (master) and a slave synchronization module (slave) according to the identification number of each activated sub-memory controller structure;

[0100] The slave synchronization module is configured to send memory access request processing information of the sub-memory controller structure where the synchronization module is located to the master synchronization module;

[0101] The master synchronization module is used to perform judgment and processing based on the memory access request processing information of the sub-memory controller structure where the master synchronization module is located and the received memory access request processing information, and provide management information for synchronization to the slave synchronization module.

[0102] A master-slave configuration allows for efficient information synchronization between two modules (such as the sub-memory controller architecture described in this article) through centralized management, redundant backup, read-write separation, and failover mechanisms. This not only improves the high availability and fault tolerance of the memory controller, but also optimizes computer system performance and simplifies data management and maintenance.

[0103] To understand the implementation of master-slave configuration, please refer to Figure 3 , Figure 3 This is another structural diagram of a memory controller provided by an embodiment of the present invention.

[0104] like Figure 3 As shown, memory controller 1 includes two sub-memory controller structures, with corresponding identification numbers (PS_ID) being UMCCH0PS0 and UMCCHPS1. When the multiplexed memory module operates in multiplexed mode, memory controller 1 can perform a master-slave configuration based on the identification numbers of the two sub-memory controller structures.

[0105] For example, UMCCH0PS0 is configured as the master synchronization module: master, and UMCCHPS1 is configured as the slave synchronization module: slave.

[0106] When the two enabled sub-memory controller structures process each memory access request, the slave only provides the memory access request processing information required for arbitration for the pseudo channel (i.e., UMCCHPS1) and provides this memory access request processing information to the master. The master uniformly manages the memory access request processing information related to arbitration for the two pseudo channels (i.e., UMCCHPS1 and UMCCH0PS0) and determines the timing of read / write switching and other management (management information) required for synchronous arbitration.

[0107] Finally, the commands sent by the DFIs of the two pseudo channels are sent to the PHY (Physical Layer) through the DFI Mux. The PHY then sends the DFI bus commands sent by the DFI Mux to the MRDIMM.

[0108] When the working mode of the multiplexing memory module is the multiplexing mode, in other embodiments, the memory controller 1 is further used to: configure a peer-to-peer system for the synchronization modules 110 of each started sub-memory controller structure;

[0109] Among them, the synchronization module 110 configured as a peer system is used to receive memory access request processing information of the sub-memory controller structure 11 where the synchronization module 110 is located, and receive memory access request processing information of the sub-memory controller structure 11 where the synchronization module 110 is not located; and synchronize the various sub-memory controller structures 11 according to the received memory access request processing information.

[0110] In a peer-to-peer (P2P) architecture, each node (such as the synchronization module described herein) acts as both a service provider and a service consumer. Nodes communicate directly with each other, without a centralized control node. This decentralized architecture enables each node to independently process requests and synchronize their states through direct communication. Furthermore, the peer-to-peer architecture supports bidirectional synchronization, meaning each node can both initiate synchronization requests and respond to synchronization requests from other nodes. Therefore, to facilitate the memory controller's support of MRDIMM operation in MUX Mode, a peer-to-peer architecture configuration can be used to synchronize memory request processing information between the sub-memory controller structures where the two synchronization modules are located.

[0111] In order to achieve compatibility between the function of supporting access to ordinary memory modules and the function of supporting access to multiplexed memory modules, in other embodiments, when the memory module accessed by the memory access request is an ordinary memory module, the memory controller 1 determines that the working mode of the ordinary memory module is a compatible mode; based on the compatible mode, the memory controller 1 configures the operating status of a sub-memory controller structure to be started, configures the operating status of the remaining sub-memory controller structures to be not started, and configures the operating status of the synchronization modules of each sub-memory controller structure to be an idle state.

[0112] Compatibility mode means that the memory controller 1 can now function as a normal memory controller. Since the memory controller 1 provided in this embodiment of the present invention includes sub-memory controller structures 11 that can independently handle accesses to normal memory modules, in compatibility mode for normal memory modules, it is sufficient to ensure that at least one sub-memory controller structure 11 is functioning properly. Furthermore, synchronization of memory access request processing information between the activated sub-memory controller structures is not required, so the synchronization modules 110 are all configured to be in an idle state.

[0113] An embodiment of the present invention further provides a configuration method, which is applied to the memory controller described in the aforementioned embodiment.

[0114] Please refer to Figure 4 , Figure 4 It is a flowchart of a configuration method provided by an embodiment of the present invention.

[0115] like Figure 4 As shown, the method may include the following steps:

[0116] Step S101: receiving a request processing signal, wherein the request processing signal includes a memory access request for accessing a memory module.

[0117] The request processing signal can be generated when a functional module in a computer system, such as a GPU or CPU, performs data processing and needs to access a memory module. The request processing signal includes a memory access request for the current memory module. The operating mode of the memory module being accessed can then be determined based on the memory access request.

[0118] Step S102 : configuring the operating status of each sub-memory controller structure in the memory controller according to the operating mode of the memory module accessed by the memory access request.

[0119] The sub-memory controller structure after the running state is configured supports memory access requests to the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is a common memory module.

[0120] The configuration of the operating state of the sub-memory controller structure can change the memory controller's support for access to different memory modules to expand the functions and performance of the memory controller, making it compatible with the processing of memory access requests of ordinary memory modules and multiplexed memory modules.

[0121] As can be seen, the technical solution provided by the embodiment of the present invention, since multiple sub-memory controller structures are provided in the memory controller, can configure the operating state of each sub-memory controller structure based on the operating mode of the memory module accessed by the memory access request through the request processing signal received by the memory controller. This allows the sub-memory controller structure, after the operating state is configured, to support memory access requests to multiplexed memory modules in addition to ordinary memory modules. It can be seen that the memory controller provided by the embodiment of the present invention has the function of supporting access to multiplexed memory modules, thereby expanding the application scope and functionality of the memory controller and achieving the effect of improving the performance of the memory controller.

[0122] Please continue to refer to Figure 4 , the method may further include:

[0123] Step S103: configuring the operating status of the synchronization modules of each sub-memory controller structure according to the operating mode of the memory module accessed by the memory access request.

[0124] Among them, when the operating status of each of the sub-memory controller structures is configured to be started, the operating status of each synchronization module is configured to be a working status, so that when each started sub-memory control structure processes its corresponding received memory access request, the memory access request processing information between each started sub-memory control structure is synchronized based on the working status of each synchronization module, and the memory access request processing information indicates the current processing status of the memory access request; when the operating status of each of the sub-memory controller structures is configured to start a sub-memory controller structure, the operating status of the synchronization module of each sub-memory controller structure is configured to be an idle state.

[0125] The synchronization module is configured to further ensure the reliable execution of the memory controller.

[0126] Optionally, when the memory module is the multiplexed memory module, configuring the operating state of each sub-memory controller structure in the memory controller according to the operating mode of the memory module accessed by the memory access request includes:

[0127] determining an operating mode of the multiplexed memory module;

[0128] If the working mode of the multiplexed memory module is a non-multiplexed mode, configuring the running state of one sub-memory controller structure to be enabled, and configuring the running states of the remaining sub-memory controller structures to be disabled;

[0129] If the working mode of the multiplexing memory module is the multiplexing mode, the operating status of each sub-memory controller structure is configured to be started.

[0130] Since the multiplexed memory module includes two working modes, the sub-memory controller structure and the synchronization module can be configured according to the specific working mode used, so as to better process the memory access request to the multiplexed memory module.

[0131] Optionally, when the working mode of the multiplexed memory module is the multiplexing mode, the memory access request processing information synchronized by the synchronization module includes: direction synchronization information of the memory access request and timing synchronization information of the memory access request; the synchronized memory access request processing information enables the commands sent by each activated sub-memory controller structure to have the same command execution direction and meet the timing requirements specified when the command is executed.

[0132] When the working mode of the multiplexed memory module is the multiplexed mode, each sub-memory controller structure processes the memory access request. At this time, in order to meet the restrictions on the direction and timing of the memory access request, the synchronization module is used to synchronize the memory access request processing information so that the multiplexed working mode of the multiplexed memory module can be accurately accessed.

[0133] Optionally, when the operating mode of the multiplexing memory module is the multiplexing mode, the method further includes:

[0134] The commands obtained after processing each memory access request are selected and output.

[0135] When the multiplexed memory module operates in multiplexing mode, each sub-memory controller structure processes a memory access request, and each sub-memory controller structure issues a command obtained after processing. At this point, each command issued by each sub-memory controller structure can be selectively output.

[0136] Optionally, when the operating mode of the multiplexing memory module is a non-multiplexing mode, the method further includes:

[0137] Address coding management is performed on each memory array in the non-multiplexing mode memory module.

[0138] In the non-multiplexed mode memory module, although the memory capacity is increased, that is, the number of ranks is increased, each rank is still accessed independently. Therefore, in order to facilitate accurate access to each rank, the addresses of different ranks are encoded and managed to accurately identify and access the ranks.

[0139] Optionally, when the memory module is a common memory module, the memory module accessed by the memory access request is a common memory module, and configuring the operating state of each sub-memory controller structure according to the operating mode of the memory module accessed by the memory access request includes:

[0140] Make sure the normal memory module works in compatibility mode;

[0141] Based on the compatibility mode, the operating status of one of the sub-memory controller structures is configured as enabled, and the operating status of the remaining sub-memory controller structures is configured as disabled.

[0142] Of course, at this time, the synchronization module can also be configured to an idle state, so that the functions of the configured memory controller are the same as those of an ordinary memory controller, supporting access to ordinary memory modules, such as supporting access to RDIMM (Registered DIMM, registered dual in-line memory module) / LRDIMM (Load-Reduced DIMM, low-load dual in-line memory module).

[0143] The embodiment of the present invention also provides a computer system. Figure 5 , Figure 5 It is a structural diagram of a computer system provided by an embodiment of the present invention.

[0144] like Figure 5 As shown, the computer system includes: the memory controller 1 described in any one of the above embodiments.

[0145] The memory controller 1 can compatibly process memory access requests for memory modules in different operating modes, meeting the requirements for accessing the latest MRDIMM Rank Mode and Mux Mode. It is also compatible with the requirements of current DDR5 DIMMs (such as the aforementioned RDIMM or LRDIMM). This can be achieved by configuring and upgrading the existing memory controller structure. Compared with existing memory controllers, the embodiment of the present invention meets the high bandwidth requirements corresponding to processing various memory access requests for accessing the MRDIMM Rank Mode without changing the operating frequency and latency of the memory controller 1.

[0146] Please continue to refer to Figure 5 , the computer system may further include:

[0147] The bus 2 includes a request allocation control unit 21 ; the request allocation control unit 21 is used to evenly allocate each memory access request in the bus 2 to each sub-memory controller structure 11 of the memory controller 1 .

[0148] In a computer system, memory controller 1 is a core component that manages memory access and coordinates data transfer between the processor (e.g., CPU) and memory (e.g., MRDIMMs). Bus 2, as the upstream port of memory controller 1, connects memory controller 1 to other core components in the computer system (typically the CPU or system bus). Its primary function is to transmit memory access requests from the processor to memory controller 1 and to transfer data returned by memory controller 1 back to the processor or other requesting party.

[0149] The bus is optimized, and a request distribution control unit 21 is designed to evenly distribute memory access requests received by the bus to each sub-memory controller structure. This ensures that the bandwidth of the memory modules is fully utilized, preventing idle bandwidth in some modules and thus improving system resource utilization efficiency. Furthermore, in a memory controller with multiple sub-memory controller structures 11, evenly distributing memory access requests ensures load balancing across each sub-memory controller structure 11, preventing some sub-memory controller structures 11 from being overloaded while others are idle.

[0150] As can be seen, the technical solution provided by the embodiment of the present invention provides multiple sub-memory controller structures within the memory controller 1 of the computer system. The operating state of each sub-memory controller structure is configured based on the operating mode of the memory module to be accessed by the memory access request, via a request processing signal received by the memory controller 1. This allows the configured sub-memory controller structure to support memory access requests to multiplexed memory modules in addition to ordinary memory modules. This shows that the memory controller provided by the embodiment of the present invention can support access to multiplexed memory modules, thereby expanding the application scope and functionality of the memory controller and improving the performance of the memory controller.

[0151] The above describes multiple embodiment schemes provided by the embodiments of the present invention. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present invention.

[0152] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A memory controller, characterized in that: The memory controller includes a plurality of sub-memory controller structures; The memory controller is used to: Receive a request processing signal, wherein the request processing signal includes a memory access request for accessing a memory module; configure the operating status of each sub-memory controller structure according to the operating mode of the memory module accessed by the memory access request, so that the sub-memory controller structure after the operating status is configured supports the memory access request for accessing the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is an ordinary memory module.

2. The memory controller according to claim 1, wherein: Each sub-memory controller structure includes a synchronization module; the memory controller is further configured to: Configuring the operating state of the synchronization modules of each sub-memory controller structure according to the operating mode of the memory module accessed by the memory access request; When the memory controller configures the operating states of the sub-memory controller structures to be started, the operating states of the synchronization modules of the sub-memory controller structures are configured to be in a working state, so that when the started sub-memory control structures process their corresponding received memory access requests, the memory access request processing information between the started sub-memory control structures is synchronized based on the synchronization modules in the working state; the memory access request processing information indicates the current processing status of the memory access request; When the memory controller configures the operating state of each sub-memory controller structure to start a sub-memory controller structure, the operating state of the synchronization module of each sub-memory controller structure is configured to be an idle state.

3. The memory controller according to claim 2, wherein: The memory controller determines an operating mode of the multiplexed memory module when the memory module accessed by the memory access request is a multiplexed memory module; If the operating mode of the multiplexed memory module is a non-multiplexed mode, configuring the operating state of one sub-memory controller structure to be enabled, configuring the operating state of the remaining sub-memory controller structures to be disabled, and configuring the operating state of the synchronization modules of the respective sub-memory controller structures to be in an idle state; If the working mode of the multiplexing memory module is the multiplexing mode, the running state of each sub-memory controller structure is configured to be started, and the running state of the synchronization module of each sub-memory controller structure is configured to be the working state.

4. The memory controller according to claim 3, wherein: When the operation mode of the multiplexing memory module is the non-multiplexing mode, the memory controller is further configured to perform address coding management on each memory array in the memory module in the non-multiplexing mode.

5. The memory controller according to claim 4, wherein: The sub-memory controller structure further includes: A request storage module, configured to store each memory access request received by the memory controller; an arbitration module, configured to arbitrate each memory access request stored in the request storage module; A bus encoding queue module, configured to send the memory access request arbitrated by the arbitration module to the currently used memory module; The request storage module, the arbitration module and the bus coding queue module are all provided with address coding bits, and the address coding bits are used to perform address coding management on each memory array in the memory module in the non-multiplexing mode.

6. The memory controller according to claim 5, wherein: Also includes: A multiplexer output unit, configured to receive commands obtained after the sub-memory controller structure processes the memory access request; When the working mode of the multiplexing memory module is the multiplexing mode, the commands sent by each started sub-memory controller structure are selected and output.

7. The memory controller according to claim 6, wherein: When the working mode of the multiplexed memory module is the multiplexing mode, the memory access request processing information synchronized by the synchronization module includes: direction synchronization information of the memory access request and timing synchronization information of the memory access request; the synchronized memory access request processing information enables the commands sent by each activated sub-memory controller structure to have the same command execution direction and meet the timing requirements specified when the command is executed.

8. The memory controller according to claim 7, wherein: When the working mode of the multiplexing memory module is the multiplexing mode, the memory controller is further used to: configure the synchronization module as a master synchronization module and a slave synchronization module according to the identification number of each started sub-memory controller structure; The slave synchronization module is configured to send memory access request processing information of the sub-memory controller structure where the synchronization module is located to the master synchronization module; The master synchronization module is used to perform judgment and processing based on the memory access request processing information of the sub-memory controller structure where the master synchronization module is located and the received memory access request processing information, and provide management information for synchronization to the slave synchronization module.

9. The memory controller according to claim 7, wherein: When the working mode of the multiplexing memory module is the multiplexing mode, the memory controller is further used to: configure a peer-to-peer system for each synchronization module of the started sub-memory controller structure; Among them, the synchronization module configured as a peer system is used to receive memory access request processing information of the sub-memory controller structure where the synchronization module is located, and receive memory access request processing information of the sub-memory controller structure where the synchronization module is not located; and synchronize the various sub-memory controller structures according to the received memory access request processing information.

10. The memory controller according to claim 2, wherein: When the memory module accessed by the memory access request is a normal memory module, the memory controller determines that the operating mode of the normal memory module is a compatible mode; based on the compatible mode, the memory controller configures the operating status of a sub-memory controller structure to be started, the operating status of the remaining sub-memory controller structures to be not started, and the operating status of the synchronization modules of each sub-memory controller structure to be an idle state.

11. The memory controller according to any one of claims 1 to 10, wherein: The memory controller configures the operating status of each sub-memory controller structure in a manner including: software configuration or hardware configuration.

12. A configuration method, characterized in that: Applied to the memory controller according to any one of claims 1 to 11, the method comprising: receiving a request processing signal, wherein the request processing signal includes a memory access request for accessing a memory module; According to the working mode of the memory module accessed by the memory access request, the operating status of each sub-memory controller structure in the memory controller is configured so that the sub-memory controller structure after the operating status is configured supports the memory access request to access the memory module when it is a multiplexed memory module, wherein the performance of the multiplexed memory module is higher than the performance of the memory module when it is an ordinary memory module.

13. The configuration method according to claim 12, wherein: Also includes: Configuring the operating state of the synchronization modules of each sub-memory controller structure according to the operating mode of the memory module accessed by the memory access request; When the operating states of the sub-memory controller structures are configured to be started, the operating states of the synchronization modules are configured to be in a working state, so that when the started sub-memory control structures process their corresponding received memory access requests, the memory access request processing information between the started sub-memory control structures is synchronized based on the synchronization modules in the working state; the memory access request processing information indicates the current processing status of the memory access request; When the operating state of each sub-memory controller structure is configured to start a sub-memory controller structure, the operating state of the synchronization module of each sub-memory controller structure is configured to be an idle state.

14. The configuration method according to claim 13, wherein: When the memory module is a multiplexed memory module, configuring the operating state of each sub-memory controller structure in the memory controller according to the operating mode of the memory module accessed by the memory access request includes: determining an operating mode of the multiplexed memory module; If the working mode of the multiplexed memory module is a non-multiplexed mode, configuring the running state of one sub-memory controller structure to be enabled, and configuring the running states of the remaining sub-memory controller structures to be disabled; If the working mode of the multiplexing memory module is the multiplexing mode, the operating status of each sub-memory controller structure is configured to be started.

15. The configuration method according to claim 14, wherein: When the working mode of the multiplexed memory module is the multiplexing mode, the memory access request processing information synchronized by the synchronization module includes: direction synchronization information of the memory access request and timing synchronization information of the memory access request; the synchronized memory access request processing information enables the commands sent by each activated sub-memory controller structure to have the same command execution direction and meet the timing requirements specified when the command is executed.

16. The configuration method according to claim 15, wherein: Also includes: The commands obtained after processing each memory access request are selected and output.

17. The configuration method according to claim 14, wherein: When the operating mode of the multiplexing memory module is a non-multiplexing mode, the method further includes: Address coding management is performed on each memory array in the non-multiplexing mode memory module.

18. The configuration method according to any one of claims 13 to 17, wherein: When the memory module is a common memory module, configuring the operating state of each sub-memory controller structure in the memory controller according to the operating mode of the memory module accessed by the memory access request includes: Make sure the normal memory module works in compatibility mode; Based on the compatibility mode, the operating status of one sub-memory controller structure is configured as enabled, and the operating status of the remaining sub-memory controller structures is configured as disabled.

19. A computer system, characterized in that: include: The memory controller according to any one of claims 1 to 11.

20. The computer system of claim 19, wherein: Also includes: The bus includes a request allocation control unit; the request allocation control unit is used to evenly allocate each memory access request in the bus to each sub-memory controller structure of the memory controller.

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