Controller and control method for memory

Abstract

The invention relates to a controller and a control method for a memory. The memory comprises a memory array, a mode register and an access interface for externally accessing the memory array, wherein the access interface comprises at least one data / address multiplexing line for transmitting data and addresses in a time-sharing multiplexing manner. The controller includes: a decoding section receiving an access instruction and a mode configuration value sequentially input via the data / address multiplexing line, and configured to set the mode register based on the mode configuration value; and a cache section configured to sequentially cache at least one access address input after the mode configuration value via the data / address multiplexing line, and sequentially output the at least one access address to the memory array at a specified timing. According to the scheme, the mode configuration efficiency and access efficiency of the memory can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of storage, and in particular to a controller and a control method for a memory. Background Art

[0002] Memory plays an important role in electronic devices such as computers. There are many different types of memory, including static random access memory (SRAM), dynamic random access memory (DRAM), pseudo static random access memory (PSRAM), and flash memory.

[0003] With the development of various electronic devices, the access requirements for memory are becoming increasingly complex. For example, it is often necessary to access multiple row / column addresses at a time, or the configuration of memory modes has become changeable and complex, and there are often complex and changing mode requirements in a short period of time.

[0004] Therefore, it is expected to improve the mode configuration efficiency and access efficiency of the memory. Summary of the Invention

[0005] A technical problem to be solved by the present disclosure is to provide a controller and a control method for a memory, which can improve the mode configuration efficiency and access efficiency of the memory.

[0006] According to a first aspect of the present disclosure, a controller for a memory is provided, the memory comprising a memory array, a mode register, and an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplexing line for time-sharing multiplexing of data and addresses; the controller comprising: a decoding unit, receiving access instructions and mode configuration values ​​sequentially input via the data / address multiplexing line, and configured to set the mode register based on the mode configuration value; and a cache unit, configured to sequentially cache at least one access address input subsequent to the mode configuration value via the data / address multiplexing line, and output the at least one access address sequentially to the memory array at a specified time.

[0007] Optionally, the decoding unit is configured to input the mode configuration value into the mode register, so as to update the value of the mode register to the mode configuration value.

[0008] Optionally, the decoding unit is further configured to generate a read enable signal or a write enable signal based on the access instruction, and the designated time is determined based on the read enable signal or the write enable signal.

[0009] Optionally, the access interface also includes a transmission line; the decoding unit also receives a first enable signal input via the transmission line, and is also configured to generate an address input signal based on the first enable signal, wherein the address input signal has a signal edge corresponding to the transmission period of each access address input before the invalid edge of the first enable signal; and the cache unit is configured to cache the corresponding access address respectively in response to the signal edge of the address input signal.

[0010] Optionally, the transmission line is further used to output a signal for synchronizing sampling of read data output on the data / address multiplexing line, and / or input a signal for shielding write data received on the data / address multiplexing line.

[0011] Optionally, the access interface also includes a chip select line and a clock line; the decoding unit includes an input pointer generation unit, which is configured to receive a chip enable signal input via the chip select line, a first clock input via the clock line, and the first enable signal, and based on the first enable signal, the chip enable signal and the first clock, generate an access instruction enable signal, a mode configuration enable signal and the address input signal, wherein the access instruction enable signal has a signal edge corresponding to the transmission period of the access instruction, and the mode configuration enable signal has a signal edge corresponding to the transmission period of the mode configuration value.

[0012] Optionally, the decoding unit further includes: a first register, whose data input terminal is coupled to the data / address multiplexing line, whose clock terminal receives the mode configuration enable signal, and whose data output terminal is coupled to the mode register.

[0013] Optionally, the decoding unit also includes a read-write status generation unit, wherein the read-write status generation unit includes: a second register, whose data input terminal is coupled to the data / address multiplexing line, and whose clock terminal receives the access instruction enable signal, a first pulse generator, configured to generate a pulse triggered by the failure edge of the chip enable signal, and whose output terminal is coupled to the reset terminal of the second register, and an access instruction decoding unit, which is coupled to the data output terminal of the second register and is configured to enable the read enable signal or the write enable signal in response to the value of the access instruction.

[0014] Optionally, the address input signal includes a row address input signal group and a column address input signal group, wherein each row address input signal or column address input signal respectively has a signal edge corresponding to the transmission period of the row address or column address in each access address input before the invalid edge of the first enable signal, and the input pointer generation unit includes: a first counting clock generation unit, configured to generate a first counting clock based on the first enable signal, the chip enable signal and the first clock, wherein the first counting clock has a clock signal synchronized with the first clock only between the valid edge of the chip enable signal and the invalid edge of the first enable signal, and a first counting output unit, configured to count the rising edge and / or falling edge of the first counting clock, and enable the access instruction enable signal, the mode configuration enable signal, and each row address input signal and column address input signal in sequence in response to the results of each count.

[0015] Optionally, the first counting clock generating unit includes: a second pulse generator, configured to generate a pulse triggered by the valid edge of the chip enable signal, a third pulse generator, configured to generate a pulse triggered by the invalid edge of the first enable signal, a first SR latch, whose set end receives one of the outputs of the second pulse generator and the output of the third pulse generator, and whose reset end receives the other of the two outputs, and a first AND gate, whose two input ends respectively receive one of the two outputs of the first SR latch and the first clock, and outputs the first counting clock.

[0016] Optionally, the first counting output unit includes: a first counter, whose clock end receives the first counting clock and counts the falling edges of the first counting clock; a second counter, whose clock end receives the inverted signal of the first counting clock and counts the falling edges of the inverted signal of the first counting clock; a first one-hot decoder, which receives the counting result of the first counter and outputs a first group of one-hot decoding signals; a second one-hot decoder, which receives the counting result of the second counter and outputs a second group of one-hot decoding signals; a first group of AND gates, which respectively receive the first group of one-hot decoding signals and the first counting clock and respectively output the access instruction enable signal and each row address input signal; and a second group of AND gates, which respectively receive the second group of one-hot decoding signals and the inverted signal of the first counting clock and respectively output the mode configuration enable signal and each column address input signal.

[0017] Optionally, the input pointer generation unit further includes a fourth pulse generator, which is configured to generate a pulse triggered by the invalid edge of the chip enable signal, and whose output end is coupled to the reset end of the first counter and the set end of the second counter.

[0018] Optionally, the access interface also includes a clock line; the decoding unit includes an output pointer generation unit, which is configured to receive a first clock input via the clock line, and the read enable signal or the write enable signal, and generate an address output signal based on the first clock and the read enable signal or the write enable signal, wherein the address output signal has a signal edge that respectively indicates the output time of each access address cached by the cache unit; and the cache unit is configured to output the corresponding access address in response to the signal edge of the address output signal.

[0019] Optionally, the address output signal includes a group of access address output signals, wherein each access address output signal has a signal edge indicating the output moment of each access address cached by the cache unit, and the output pointer generation unit includes: a delay unit, configured to enable a delayed arrival signal after a predetermined number of clock cycles have passed during the validity period of the read enable signal or the write enable signal, wherein the clock cycle is the same as the clock cycle of the first clock, and an output unit, configured to periodically enable each access address output signal in sequence according to the burst length after the delayed arrival signal is enabled when the write enable signal is enabled, and to enable the first access address output signal immediately after the cache unit has cached the first input access address when the read enable signal is enabled and to periodically enable each subsequent access address output signal in sequence according to the burst length after the delayed arrival signal is enabled, wherein the burst length is set by the mode register after being set based on the mode configuration value.

[0020] Optionally, the output unit includes: a burst count clock generating unit, configured to enable an address count arrival signal when the number of output access addresses is equal to the number of cached access addresses, and generate a burst count clock based on the delayed arrival signal, the address count arrival signal and the first clock, wherein the burst count clock has a clock signal synchronized with the first clock only between the valid edge of the delayed arrival signal and the valid edge of the address count arrival signal, and a burst length counting unit, configured to cyclically count the rising edge and / or falling edge of the burst count clock, wherein the number of counts in each cycle is determined by the burst length. The second counting clock generating unit is configured to generate a second counting clock based on the read enable signal, the counting result of the burst length counting unit and the burst counting clock, wherein the second counting clock has a clock signal synchronized with the burst counting clock during the period when the burst length counting unit outputs a specific counting result, and also has a pulse immediately after the cache unit has cached the first input access address during the period when the read enable signal is valid, and a second counting output unit is configured to count the rising edge or the falling edge of the second counting clock, and enable each access address output signal in sequence in response to the result of each count.

[0021] Optionally, the delay unit includes: a first logic unit, configured to generate a delay control signal based on the read enable signal, the write enable signal and the delayed arrival signal, which is valid only when the read enable signal or the write enable signal is valid and the delayed arrival signal is invalid; a first low-pass latch, whose input terminal receives the delay control signal, whose control terminal receives the first clock, and whose output is a delayed enable signal; a second AND gate, whose two input terminals receive the delay enable signal and the first clock respectively, and outputs a delayed count clock; and a third counter, whose clock terminal receives the delayed count clock, counts the rising edge or falling edge of the delayed count clock, and enables the delayed arrival signal after reaching the predetermined number.

[0022] Optionally, the burst count clock generation unit includes: a comparator, configured to compare the number of currently output access addresses with the number of cached access addresses and enable the address count arrival signal when the two are equal, a second low-pass latch, whose input end receives the delayed arrival signal, whose control end receives the first clock, and whose output is a burst enable signal, a fifth pulse generator, configured to generate a pulse triggered by the valid edge of the address count arrival signal, a sixth pulse generator, configured to generate a pulse triggered by the valid edge of the burst enable signal, a second SR latch, whose set end receives one of the output of the fifth pulse generator and the output of the sixth pulse generator, and whose reset end receives the other of the two outputs, and a third AND gate, whose two input ends respectively receive one of the two outputs of the second SR latch and the first clock, and outputs the burst count clock.

[0023] Optionally, the burst length counting unit includes a fourth counter, a clock end of which receives the burst counting clock and cyclically counts the falling edges of the burst counting clock.

[0024] Optionally, the second counting clock generating unit includes: a third one-hot decoder, which receives the counting result of the burst length counting unit and outputs a specific one-hot decoding signal corresponding to the specific counting result; a second logic unit, which is configured to generate the second counting clock based on the specific one-hot decoding signal, the burst counting clock, the read enable signal and the first signal indicating that the cache unit has cached the first input access address, and is only valid when the specific one-hot decoding signal is valid and the burst counting clock is valid or when the read enable signal is valid and the first signal is valid.

[0025] Optionally, the second counting output unit includes: a fifth counter, whose clock end receives the second counting clock and counts the falling edges of the second counting clock; a fourth one-hot decoder, which receives the counting result of the fifth counter and outputs a third group of one-hot decoding signals; and a third group of AND gates, which respectively receive the third group of one-hot decoding signals and the second counting clock and respectively output each access address output signal.

[0026] Optionally, the memory is PSRAM.

[0027] Optionally, the access interface adopts a multi-IO SPI protocol.

[0028] Optionally, the cache unit is a FIFO buffer.

[0029] According to a second aspect of the present disclosure, a method for controlling a memory is provided, wherein the memory includes a memory array, a mode register, and an access interface for externally accessing the memory array, the access interface including at least one data / address multiplexing line for time-sharing multiplexing to transmit data and addresses; the method includes: sequentially receiving an access instruction, a mode configuration value, and at least one access address via the data / address multiplexing line; setting the mode register based on the mode configuration value; and sequentially caching the at least one access address, and sequentially outputting the at least one access address to the memory array at a specified time.

[0030] Optionally, the step of setting the mode register based on the mode configuration value includes: inputting the mode configuration value into the mode register so as to update the value of the mode register to the mode configuration value.

[0031] Optionally, the method further includes: generating a read enable signal or a write enable signal based on the access instruction, and the designated time is determined based on the read enable signal or the write enable signal.

[0032] Optionally, the access interface also includes a transmission line; the method also includes: generating an address input signal based on a first enable signal input via the transmission line, wherein the address input signal has a signal edge corresponding to a transmission period of each access address input before the invalid edge of the first enable signal; and the step of sequentially caching the at least one access address includes: caching the corresponding access address respectively in response to the signal edge of the address input signal.

[0033] The above-mentioned optional features can be combined with any one of the first to second aspects of the present disclosure as needed, and / or can be combined with each other at will.

[0034] Therefore, the present disclosure proposes a new memory control method for a memory with data / address line multiplexing of an access interface, which can instantly rewrite the mode register when issuing an access instruction to change the mode configuration of the current access operation, thereby adapting to complex and changeable mode requirements and improving read and write efficiency and data bandwidth. At the same time, the solution of the present disclosure can also read and write multiple groups of addresses in the operation of one access instruction, thereby adapting to complex and changeable addressing requirements and improving read and write efficiency and data bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0036] Figure 1 A schematic diagram illustrating an exemplary composition of a memory according to some embodiments of the present disclosure is shown.

[0037] Figure 2 A timing diagram illustrating an example of the operation of an access format according to some embodiments of the present disclosure.

[0038] Figure 3 A schematic diagram illustrating an exemplary composition of a controller according to some embodiments of the present disclosure is shown.

[0039] Figure 4 Another exemplary composition diagram of a controller according to some embodiments of the present disclosure is shown.

[0040] Figure 5 FIG2 shows an exemplary timing diagram of various signals involved in a controller in a write operation according to some embodiments of the present disclosure.

[0041] Figure 6 FIG2 shows an exemplary timing diagram of various signals involved in a controller in a read operation according to some embodiments of the present disclosure.

[0042] Figure 7 Another exemplary timing diagram of various signals involved in the controller in a write operation according to some embodiments of the present disclosure is shown.

[0043] Figure 8 Another exemplary timing diagram of various signals involved in the controller in a read operation according to some embodiments of the present disclosure is shown.

[0044] Figure 9 A schematic diagram illustrating an exemplary composition of an input pointer generating unit according to some embodiments of the present disclosure is shown.

[0045] Figure 10 An exemplary circuit diagram of an input pointer generation unit according to some embodiments of the present disclosure is shown.

[0046] Figure 11 An exemplary timing diagram of various signals involved in an input pointer generation unit in a write operation according to some embodiments of the present disclosure is shown.

[0047] Figure 12 An exemplary circuit diagram of a read / write state generating unit according to some embodiments of the present disclosure is shown.

[0048] Figure 13 A schematic diagram illustrating an exemplary composition of an output pointer generation unit according to some embodiments of the present disclosure is shown.

[0049] Figure 14 An exemplary circuit diagram of an output pointer generation unit according to some embodiments of the present disclosure is shown.

[0050] Figure 15 An exemplary timing diagram of various signals involved in an output pointer generation unit in a write operation according to some embodiments of the present disclosure is shown.

[0051] Figure 16 An exemplary timing diagram of various signals involved in an output pointer generation unit in a read operation according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0052] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0053] Usually, the data (DATA) line and the command / address (Command / Address) line in the PSRAM interface are fully or at least partially multiplexed (for example, Figure 1 The A / DQ lines shown in the figure transmit both data and instructions and addresses. Therefore, conventional PSRAM can only access one row of addresses at a time. To access addresses in other rows, the chip select CS# signal must be pulled high, and then a certain amount of time (chip select time, which is the minimum time CS# must be held high) must be waited before reissuing the read / write instruction. The next data read / write can then be performed after the read / write delay time.

[0054] However, PSRAM currently faces increasingly complex requirements for accessing read and write addresses, such as the need to access multiple row and column addresses simultaneously. Conventional PSRAM requires multiple access instructions to access multiple groups of addresses, each requiring a chip select time and a corresponding access delay. Consequently, this instruction format is inefficient for complex requirements such as accessing multiple row and column addresses simultaneously, impacting access performance.

[0055] In addition, the configuration of particle modes in PSRAM has become changeable and complex. For example, there are often complex and changing mode requirements in a short period of time. Conventional PSRAM uses an independent mode register rewrite instruction to rewrite the mode register before the access operation to change the mode configuration. When using the mode register rewrite instruction, it is also necessary to wait for the chip select time and the read / write delay time. If the mode requirements for each access operation are different, it is necessary to send a mode register rewrite instruction to rewrite the mode before each access operation, and each time it is necessary to wait for the chip select time and the read / write delay time, resulting in reduced read and write efficiency, affecting device performance, and making it difficult to adapt to the complex and changing read and write mode requirements.

[0056] Therefore, the present disclosure proposes a new type of memory control method for a memory with multiplexed data / address lines of an access interface, which can instantly rewrite the mode register when issuing an access instruction to change the mode configuration of the current access operation. Therefore, compared with the prior art, the present disclosure does not need to send a mode register rewrite instruction separately to frequently rewrite the mode. The required mode can be configured instantly when each access instruction is sent, thereby adapting to complex and changeable mode requirements and improving read and write efficiency and data bandwidth. At the same time, the present disclosure also supports reading and writing multiple groups of addresses in the operation of one access instruction. Therefore, compared with the prior art, there is no need to wait for redundant chip select time and read and write delay time to complete the read and write operations of multiple groups of addresses, thereby adapting to complex and changeable addressing requirements and improving read and write efficiency and data bandwidth. In this article, unless otherwise stated, "access" refers to the reading and writing of data in the storage array in the memory, and does not include the reading and writing of other components in the memory, such as mode registers.

[0057] The following will use a PSRAM using an SPI (Serial Peripheral Interface) interface as an example to describe the technical solution of the present disclosure in detail. However, those skilled in the art will appreciate that the present disclosure is not limited thereto and can also be applied to various memories having the same or similar access interfaces (e.g., an SPI interface or an interface similar thereto that multiplexes data / address lines), such as SRAM, DRAM, or flash. In this document, "SPI interface" refers to an access interface using the SPI protocol (including various extended protocols, such as multi-IO SPI protocols, including QSPI, OSPI, and xSPI protocols).

[0058] Figure 1 FIG. 1 shows an exemplary composition diagram of a memory according to some embodiments of the present disclosure. Figure 2 The present invention provides some embodiments of the present invention. Figure 1 The following is a timing diagram showing an example of a single access operation using the memory access format.

[0059] like Figure 1 As shown, the memory 100 includes a memory array 110, an access interface 120 for externally accessing the memory array, a mode register 130, and a controller 140, wherein the access interface 120 includes at least one data / address multiplexing line A / DQ for time-division multiplexing to transmit data and addresses.

[0060] Figure 1The access interface 120 in the embodiment can use the SPI protocol to communicate with an external host. The SPI protocol in the present disclosure may include various versions thereof, such as single-port, dual-port, 4-port or 8-port SPI protocols, etc.; the "single-port, dual-port, 4-port or 8-port" here refers to the number of data / address multiplexing lines A / DQ being 1, 2, 4 or 8 (the A / DQ line can also be said to be 1 bit wide, 2 bits wide, 4 bits wide or 8 bits wide), so that the number of data / address bits that can be transmitted in parallel is 1 bit, 2 bits, 4 bits or 8 bits. The following will take 8-port SPI (A / DQ transmits 1 byte (i.e. 8 bits) in parallel each time) as an example to describe the various embodiments of the present disclosure, but those skilled in the art will understand that the technical solution of the present disclosure does not limit its number of bits, nor is it limited to the SPI protocol. The embodiments of the present disclosure are also applicable to other access interfaces 120 that multiplex data and address lines. In summary, the number of A / DQ lines is 2 N , output or input 2 in each clock cycle via the A / DQ line N bitwise OR 2 N+1 bit of data, instruction or address (wherein, if the access interface 120 adopts SDR (Single Data Rate) timing, A / DQ transmits 2 bits per clock cycle). N If the access interface 120 uses DDR (Double Data Rate) timing, then A / DQ transmits 2 bits per clock cycle. N+1 bits), where N is a non-negative integer. In addition, in some embodiments, in addition to the data / address multiplexing lines A / DQ, the access interface 120 may further include other transmission lines to separately transmit a portion of the data or address; for example, the access interface 120 may further include a separate address line to transmit the address in parallel with the data / address multiplexing lines A / DQ.

[0061] In some embodiments, as Figure 1As shown, in addition to a set of (8) data / address multiplexing lines A / DQ, the access interface 120 may also include a clock line CLK, a chip select line CS, and a transmission line DQS for implementing the 8-port SPI protocol. The DQS line can be used to output a signal for synchronizing the sampling of the read data output on the A / DQ line in the case of a read operation, and / or input a signal for shielding the write data received on the A / DQ line in the case of a write operation. When the host accesses the memory 100 (read / write operation), the host can output a clock signal CLK to the memory via the clock line to control the signal transmission timing, pull down the CS# signal on the chip select line to select the memory, and exchange instructions, addresses, and data related to the read and write operations with the memory via the A / DQ line. In addition, during a read operation, the memory can use the signal on the DQS line to ensure that the host correctly obtains the read data; and during a write operation, the host can use the signal on the DQS line to shield part of the input data so that it is not written to the corresponding address, thereby providing users with a more flexible write method. It will be understood that the access interface according to the embodiment of the present disclosure is not limited to the illustrated transmission line configuration, but may include transmission lines for other purposes not shown as needed.

[0062] Since the instructions, addresses and data in each access operation are transmitted using the same A / DQ lines, in order to facilitate the memory to distinguish the transmitted instructions, addresses and data, it is necessary to propose a specific access format for transmission and set a controller 140 that matches the access format to control the memory access operation accordingly.

[0063] The access format according to the embodiment of the present disclosure is as follows Figure 2 As illustrated in the timing diagram of , after an access operation starts, an access instruction, a mode configuration value, and at least one access address may be received in sequence via the data / address multiplexing line A / DQ, that is, Figure 2 WR, MR, and three access addresses RA0+CA0, RA1+CA1, and RA2+CA2 are sequentially transmitted in the DQ signals in . As will be described in detail later, the controller 140 will set the mode register 130 based on the received mode configuration value MR, and the cache unit 142 will sequentially cache the at least one received access address and output the at least one access address to the memory array 110 in sequence at a specified time. As such, the embodiment of the present disclosure can instantly configure the required mode in each access operation, thereby flexibly and efficiently implementing the mode configuration of the current access operation and correspondingly improving the read efficiency of the memory. The embodiment of the present disclosure can also access multiple random access addresses, thereby greatly improving the read efficiency of the memory.

[0064] Those skilled in the art will understand that Figure 2 The “WR” in FIG. 1 is merely illustrative, and represents a write instruction value in the access instruction CMD, which is used to initiate a write operation. In subsequent figures, “RD” may also be used to represent a read instruction value in the access instruction CMD, which is used to initiate a read operation.

[0065] The following combination Figure 2 The timing diagram of the access format is used to describe the example of the access format in more detail. Those skilled in the art will understand that many of the following details are only provided for the sake of completeness of the solution and are not intended to limit the technical solution of the present disclosure.

[0066] like Figure 2 As shown in the figure, the chip enable signal CS# is first pulled low (for this signal, a low level indicates valid, and a high level indicates invalid) to start an access operation. Then, the clock signal CLK is input on the clock line, and the write command WR, the mode configuration value MR, and the three access addresses RA0+CA0, RA1+CA1, and RA2+CA2 are input on the A / DQ lines in sequence, where "RA" represents the row address and "CA" represents the column address.

[0067] In each example of the present disclosure, data transmission on the A / DQ line adopts DDR timing, that is, DQ can be sent on both the rising edge and the falling edge of CLK. However, those skilled in the art will understand that the embodiments of the present disclosure are not limited to DDR timing, and SDR timing may also be adopted, that is, data is sent only once on the rising edge or falling edge of a clock cycle.

[0068] Those skilled in the art will understand that Figure 2 The number of access addresses input in is only exemplary and can be set as needed. For example, the number of access addresses to be input can be determined by the access instruction, or a fixed number can be preset, etc.

[0069] In addition, the present disclosure notes that, as mentioned above, the DQS signal on the traditional transmission line DQS is idle before transmitting read and write data, so in some embodiments, the DQS signal can be used to determine the number of access addresses to be input, thereby improving the utilization efficiency of the interface. Figure 2 As shown, the end of access address input can be determined by the first falling edge of the DQS signal after the access operation starts. Alternatively, the end of access address input can also be determined by the first rising edge or pulse of the DQS signal after the access operation starts.

[0070] Accordingly, in order to realize the control of the access address input by the above-mentioned DQS signal, Figure 1The controller 140 can be configured to generate an address input signal based on a DQS signal (hereinafter also referred to as a "first enable signal") input via a transmission line DQS, which has a signal edge corresponding to the transmission period of each access address input before the invalid edge of the first enable signal, and caches the corresponding access addresses in sequence in response to the signal edge of the address input signal.

[0071] like Figure 2 As shown, after the access address input is completed and the preset access delay has passed, the data D0 to be written to the first access address RA0+CA0 begins to be input; at this time, the burst length is set to 16 bytes, so 16 bytes of data B0-B15 are continuously input. In some embodiments, the burst length corresponding to each address can be set by a mode register or a unified burst length can be set. While transmitting each write data, a signal for shielding part of the write data can be input on the DQS line. Immediately after the data D0, the data D1 and D2 to be written to the second and third access addresses respectively are input in sequence, which also each include 16 bytes of data B0-B15. Then, the chip enable signal CS# is pulled high to end the access operation.

[0072] Those skilled in the art will understand that Figure 2 The access delay duration shown is merely exemplary and may be set as needed. For example, the access delay duration may be a fixed value preset in advance, or may be set by a mode register, or may be determined by an input instruction value, such as a different duration for a read instruction than for a write instruction.

[0073] From the above, it can be concluded that Figure 2 An exemplary access timing of the access format represented by the timing diagram can be expressed as:

[0074] CMD+MR+RA0+CA0+…+RAn+CAn+wait access delay+D0+…+Dn

[0075] Among them, "CMD" represents the access instruction, "MR" represents the mode configuration value, "RA0" to "RAn" represent the row addresses of each of the n+1 access addresses, "CA0" to "CAn" represent the column addresses of each of the n+1 access addresses, and "D0" to "Dn" represent the read or write data corresponding to each of the n+1 access addresses, where n≥0.

[0076] Those skilled in the art will understand that Figure 2 The access instruction format is not intended to limit the solutions of the present disclosure. Figure 2There may be various variations of the access instruction format, for example, waiting for a certain clock cycle between the transmission of each two adjacent groups of data in D0 to Dn as needed, or not waiting for access delay in some cases where the burst length is large enough, etc.

[0077] Can be designed Figure 1 The controller 140 in the memory 100 controls the access operation having the above access format.

[0078] Back to Figure 1 ,like Figure 1 As shown, the controller 140 includes a decoding unit 141 and a buffer unit 142, wherein the decoding unit 141 is used to decode the signals (DQS, CLK, CS# and DQ) received via the access interface 120 and generate corresponding control signals MRS and PNT for the mode register 130 and the buffer unit 142 respectively, so that the mode configuration value (such as Figure 2 The MR in the mode register 130 is set, and the control cache unit 142 sequentially caches each access address (such as Figure 2 RA0+CA0, RA1+CA1, RA2+CA2), and controls the cache unit 142 to sequentially output the cached access addresses ADR to the memory array 110 at a specified time so as to perform read and write operations on each access address in sequence.

[0079] Although Figure 1 Although not shown, it is understood that in some embodiments, a row / column decoder may be further included inside or outside the memory array 110 to receive the access address ADR and decode the row address (RA) and column address (CA) therein, thereby opening the word line WL corresponding to the row address and the bit line BL corresponding to the column address, respectively, thereby performing corresponding read / write operations on the memory cells selected by the opened WL and BL in the memory array 110. In addition, Figure 1 The control signal PNT is merely a general illustration and does not specifically refer to a single control signal. As will be described in detail later, the control signal PNT from the decoding unit 141 to the cache unit 142 may include multiple or multiple groups of signals as needed, such as one or more address input signals and one or more address output signals.

[0080] In some embodiments, the cache unit 142 may be a first-in-first-out (FIFO) buffer, which can sequentially store and output access addresses in the order in which they are input on the A / DQ lines during a single access operation, thereby maintaining the order in which the read or written data transmitted via the A / DQ lines is consistent with the order in which the addresses are received. The depth of the buffer can be set as needed (e.g., the maximum number of addresses supported in a single access operation).

[0081] In some embodiments, each access address is composed of RA+CA, which are continuously input on the A / DQ lines. RA and CA in each access address can be stored together in one storage unit in the cache section 142, or RA and CA in each access address can be stored separately in two storage units in the cache section 142. As shown in subsequent figures, in some embodiments, the cache section 142 can include two FIFO buffers, namely a row address FIFO buffer and a column address FIFO buffer, which are respectively used to sequentially buffer RA and CA in each access address. This allows for simpler and more convenient caching and output of multiple access addresses.

[0082] In some embodiments, the mode configuration value in the DQ signal input via the A / DQ line is the mode register value corresponding to the mode used in this access operation, so the above-mentioned control signal MRS is the same as the mode configuration value in the DQ signal input via the A / DQ line; that is, the decoding unit 141 inputs the received mode configuration value into the mode register 130 so as to update the value of the mode register 130 to the mode configuration value, thereby being able to simply and quickly set the mode required for this access operation.

[0083] In some embodiments, to further improve access speed, the cache unit 142 may output each cached access address at different times based on the difference between read operations and write operations. Thus, in some examples, the decoding unit 141 may be further configured to generate a read enable signal or a write enable signal based on the access instruction in the DQ signal input via the A / DQ line, and control the cache unit 142 to sequentially output each cached access address at a specified time based on the read enable signal or the write enable signal. For example, when the access instruction is a read instruction, the read enable signal may be pulled high (i.e., the signal is enabled), and the cache unit 142 is controlled to start outputting each access address sequentially after caching the first access address based on the pulled read enable signal; and when the access instruction is a write instruction, the write enable signal may be pulled high (i.e., the signal is enabled), and the cache unit 142 is controlled to start outputting each access address sequentially after waiting for a preset clock cycle based on the pulled write enable signal.

[0084] In some embodiments, to achieve Figure 2As shown, the DQS signal controls the access address input, and the decoding unit 141 can generate an address input signal based on the DQS signal as part of the control signal PNT for the cache unit 142, wherein the address input signal has a signal edge corresponding to the transmission period of each access address input before the invalid edge of the DQS signal, and the cache unit 142 is configured to cache the corresponding access addresses respectively in response to the signal edge of the address input signal.

[0085] The aforementioned signal edges include any edge where the signal level changes, such as a rising edge, a falling edge, an active edge, and a passive edge. Appropriate edges can be selected as the signal edges defined above based on actual circuit requirements. An active edge refers to the edge where a signal changes from inactive (also called "disabled") to active (also called "enabled"), and a passive edge refers to the edge where a signal changes from active to inactive. For example, if a signal is inactive at a low level and active at a high level, the active edge of the signal is the rising edge, while the passive edge is the falling edge.

[0086] An appropriate address input signal can be designed based on the circuit structure of cache unit 142. For example, it can be a single-bit signal, a multi-bit signal indicating the input order of the current access address, or a group of single-bit signals, each signal in the group indicating an input access address. Regardless of the address input signal format used, decoding unit 141 can be configured to change the address input signal during the transmission period of each access address input before the deactivation edge of the DQS signal, thereby generating a signal edge, so that cache unit 142 caches the corresponding access address according to the signal edge.

[0087] In some embodiments, the row address and column address in the access address are cached separately, so that a row address input signal and a column address input signal can be set for the row address and the column address, respectively, which generate signal edges in the transmission periods of the row address and the column address, respectively; for example, the above-mentioned address input signal can include a row address input signal group and a column address input signal group, wherein each row address input signal or column address input signal respectively has a signal edge corresponding to the transmission period of the row address or column address in each access address input before the invalid edge of the DQS signal.

[0088] Those skilled in the art will understand that Figure 1 The internal circuit of the memory 100 shown is only a simplified block diagram drawn to illustrate the basic operations involved in the memory control method proposed in the embodiment of the present disclosure, and other components / modules may be omitted and not shown.

[0089] The following describes in more detail the structure and specific implementation circuits of the controller according to the embodiments of the present disclosure, with reference to the accompanying drawings. The specific implementation circuits in each of the following embodiments are designed for DDR timing. However, with the guidance of this disclosure, those skilled in the art will readily understand how to adapt these specific circuits to SDR timing by making simple adaptive modifications.

[0090] Figure 3 A schematic diagram illustrating an exemplary composition of a controller according to some embodiments of the present disclosure is shown.

[0091] like Figure 3 As shown, the controller 300 includes a decoding section 310 and a FIFO buffer 320 serving as the aforementioned buffer section.

[0092] The decoding unit 310 includes an input pointer generation unit 311 , an output pointer generation unit 312 , a read / write status generation unit 313 , and a register REG1 .

[0093] The input pointer generation unit 311 is configured to receive the chip enable signal CS# input via the chip select line, the first clock CLK input via the clock line, and the first enable signal DQS input via the DQS transmission line, and based on the first enable signal DQS, the chip enable signal CS# and the first clock CLK, generate an access instruction enable signal CMD_LATEN, a mode configuration enable signal MRS_LATEN and an address input signal INPNT (these generated signals may also be collectively referred to as "input pointer signals"), wherein the access instruction enable signal CMD_LATEN has a signal edge corresponding to the transmission period of the access instruction CMD, the mode configuration enable signal MRS_LATEN has a signal edge corresponding to the transmission period of the mode configuration value MR, and the address input signal INPNT has a signal edge corresponding to the transmission period of each access address input before the invalid edge of the DQS signal. Therefore, according to the access command enable signal CMD_LATEN, the mode configuration enable signal MRS_LATEN and the address input signal INPNT, the access command CMD, the mode configuration value MR and each access address sequentially transmitted in the DQ signal can be correctly obtained.

[0094] In some embodiments, the input pointer generation unit 311 may also generate a pulse as a reset signal RST in response to the rising edge of the CS# signal, and provide the reset signal RST to the output pointer generation unit 312 and the read / write state generation unit 313, so that the decoding unit 310 can be operated as described above. Figure 2As shown, after the CS# signal is raised, the current access operation is terminated and the device returns to the initial state to wait for the next access operation. Those skilled in the art will appreciate that the reset signal RST may also be generated by the output pointer generation unit 312 and / or the read / write status generation unit 313 and output to other units.

[0095] In addition, if Figure 3 As shown, the data input terminal of the register REG1 receives the DQ signal, which can also be referred to as being coupled to the Figure 1 The data / address multiplexing line A / DQ shown in FIG. 1 , the clock end of the register REG1 receives the mode configuration enable signal MRS_LATEN, and the data output end of the register REG1 outputs the MRS signal, which can also be referred to as being coupled to the Figure 1 The mode register 130 is shown. Thus, in response to the signal edge of MRS_LATEN, the register REG1 updates its output MRS to the mode configuration value MR being transmitted on the A / DQ line at that time.

[0096] In addition, if Figure 3 As shown, the read / write status generation unit 313 is configured to obtain the access command CMD transmitted in the DQ signal according to the access command enable signal CMD_LATEN, and generate and output the read enable signal RD_ACCEN and the write enable signal WR_ACCEN to the output pointer generation unit 312 based on the access command CMD.

[0097] In addition, if Figure 3 As shown, the output pointer generation unit 312 is configured to receive the first clock CLK, the read enable signal RD_ACCEN and the write enable signal WR_ACCEN, and generate an address output signal OUTPNT based on these three signals, which has a signal edge indicating the output time of each access address buffered by the FIFO buffer 320.

[0098] In some embodiments, as will be described in detail later, the determination of the output time of each access address mentioned above also needs to depend on the total number of access addresses input and the cache time of the first access address. Therefore, the input pointer generation unit 311 can also be configured to generate a signal INP_CNT indicating the total number of access addresses input for this access operation and a signal A0_INPNT indicating the cached first access address, and output both of them to the output pointer generation unit 312 for it to generate the address output signal OUTPNT.

[0099] In addition, if Figure 3As shown, the FIFO buffer 320 receives the DQ signal, the address input signal INPNT and the address output signal OUTPNT, and is configured to respectively buffer the corresponding access address being transmitted at the time in the DQ signal in response to each signal edge of the address input signal INPNT, and to sequentially output the corresponding access address as the signal ADR to the DQ signal in response to each signal edge of the address output signal OUTPNT. Figure 1 The memory array 110 is shown.

[0100] In some embodiments, each access address consists of RA+CA continuously input on the A / DQ line. The RA and CA in each access address can be stored together in a storage unit in the FIFO buffer 320 and output together, or the RA and CA in each access address can be stored separately in two storage units in the FIFO buffer 320 and output successively as the signal ADR.

[0101] Figure 4 Another exemplary schematic diagram of the controller according to some embodiments of the present disclosure is shown, which can be regarded as Figure 3 A variation of the controller.

[0102] and Figure 3 Compared with the controller 300, Figure 4 The main difference of the controller 400 is that the cache part 420 adopts two FIFO buffers, namely the row address FIFO buffer 421 and the column address FIFO buffer 422, which respectively cache RA and CA in each access address in turn, and the input pointer generation unit 411 generates and outputs two groups of address input signals, namely the row address input signal group RA0_INPNT to RAn_INPNT (n=3 in this example) and the column address input signal group CA0_INPNT to CAn_INPNT, the output pointer generation unit 412 generates and outputs a group of access address output signals A0_OUTPNT to An_OUTPNT, and the row address FIFO buffer 421 and the column address FIFO buffer 422 respectively output their corresponding row address RA and column address CA in response to the group of access address output signals.

[0103] In addition, correspondingly, in some of the above embodiments, the signals INP_CNT and A0_INPNT generated by the input pointer generation unit 311 are changed to Figure 4The input pointer generation unit 411 generates a signal CA_INP_CNT indicating the total number of column addresses input for this access operation and a signal CA0_INPNT indicating the first column address of the cache. Those skilled in the art will appreciate that the above-mentioned signal CA_INP_CNT can also be changed to a signal RA_INP_CNT indicating the total number of row addresses input for this access operation. The two are equivalent and can be arbitrarily selected based on actual circuit design.

[0104] Specifically, each row address input signal RA0_INPNT to RAn_INPNT in the above-mentioned row address input signal group sequentially has a signal edge corresponding to the transmission period of the row address in each access address sequentially input before the invalid edge of the DQS signal. The number of each row address input signal can indicate the input order of the corresponding row address and the corresponding storage position in the row address FIFO buffer 421. Similarly, each column address input signal CA0_INPNT to CAn_INPNT in the column address input signal group sequentially has a signal edge corresponding to the transmission period of the column address in each access address sequentially input before the invalid edge of the DQS signal. The number of each column address input signal can indicate the input order of the corresponding column address and the corresponding storage position in the column address FIFO buffer 422. Similarly, each of the access address output signals A0_OUTPNT through An_OUTPNT in the access address output signal group sequentially has signal edges indicating the timing at which the row addresses and column addresses buffered by the row address FIFO buffer 421 and the column address FIFO buffer 422, respectively, are sequentially output. The numbers of each access address output signal can indicate the output order of the row addresses and column addresses in the corresponding access address, as well as the corresponding storage locations in the row address FIFO buffer 421 and the column address FIFO buffer 422. The row addresses and column addresses in each access address can be output simultaneously, so the access address output signals A0_OUTPNT through An_OUTPNT are shared by the row address FIFO buffer 421 and the column address FIFO buffer 422. Using multiple groups of address input / output signals as described above can effectively distinguish and locate the elements entering and exiting the FIFO buffer.

[0105] Figure 4 The rest of Figure 3 The same parts of the controller are not described here.

[0106] The following combination Figures 5 to 8 The timing diagram is used to describe Figure 4 Some examples of controller operations.

[0107] Figure 5 and Figure 61 and 2 respectively illustrate exemplary timing diagrams of various signals involved in the controller 400 in a write operation and a read operation according to some embodiments of the present disclosure when three access addresses are input. Figure 7 and Figure 8 Another exemplary timing diagram of various signals involved in the controller 400 in the write operation and the read operation according to some embodiments of the present disclosure is respectively shown when one access address is input.

[0108] like Figure 5 As shown, Figure 5 The write operation uses the Figure 2 The same access format, i.e. Figure 5 The timing of the four signals CLK, CS#, DQS and DQ transmitted through the access interface is the same as Figure 2 The same, no longer repeated here.

[0109] Figure 5 The signals CMD_LATEN, MRS_LATEN, RA0_INPNT, CA0_INPNT, RA1_INPNT, CA1_INPNT, RA2_INPNT, and CA2_INPNT generated by the input pointer generation unit 411 are shown to each have a pulse of one and a half clock cycles, which respectively start at the rising edge / falling edge of the clock CLK corresponding to the transmission period of the write command WR, the mode configuration value MR, and each row / column address RA0, CA0, RA1, CA1, RA2, and CA2 input in sequence. It will be understood by those skilled in the art that the pulse width of each of the above-generated signals is not limited to half a clock cycle, but can be set according to the actual circuit; for example, in some embodiments, subsequent circuits only use the rising edge of these signals to trigger corresponding operations. In this case, the pulse width has no effect on the operation of the subsequent circuit and can be set as needed.

[0110] In response to the rising edges of the row / column address input signals, the row address FIFO buffer 421 and the column address FIFO buffer 422 respectively and sequentially buffer the corresponding row addresses and column addresses being transmitted in the DQ signal in corresponding locations.

[0111] In addition, if Figure 5 As shown, in response to the rising edge of CMD_LATEN, the read / write status generation unit 413 obtains the write instruction WR being transmitted in the DQ signal, and enables the write enable signal WR_ACCEN in response to the write instruction WR, and resets the write enable signal WR_ACCEN until CS# is pulled high to end the access operation.

[0112] In addition, if Figure 5As shown, in response to the rising edge of MRS_LATEN, the output signal MRS is updated from the previous value to the mode configuration value MR currently being transmitted in the DQ signal, i.e., the new MRS value. This updated MRS value can be maintained and does not need to be reset even when CS# is pulled high to end the current access operation.

[0113] In addition, if Figure 5 As shown, the access address output signal A0_OUTPNT generated by the output pointer generation unit 412 is enabled for half a clock cycle after a period of time after the access address input is completed. Then, the subsequent access address output signals A1_OUTPNT and A2_OUTPNT are periodically enabled in sequence according to the burst length and each is maintained for half a clock cycle. In this example, the burst length is 16 and DDR timing is used. Therefore, there is an interval of 8 clock cycles between each two access address output signals to align with the transmission of write data in the DQ. Figure 5 The relationship between the enabling time of the first access address output signal A0_OUTPNT and the transmission start time of the first data D0 shown in FIG is only exemplary, and the relationship between the two can be set as needed in actual applications.

[0114] In response to the rising edge of each access address output signal, the row address FIFO buffer 421 and the column address FIFO buffer 422 respectively output each row address and each column address in sequence. Figure 5 The signals RA and CA are shown in FIG.

[0115] Figure 6 The read operation shown above is Figure 5 The main difference in write operations is that Figure 6 The access instruction input through the access interface is a read instruction RD instead of a write instruction WR. In response to the read instruction RD, the read enable signal RD_ACCEN instead of the write enable signal WR_ACCEN is enabled, and the enable time of the first access address output signal A0_OUTPNT is advanced to the rising edge immediately following the first column address input signal CA0_INPNT, and the enable times of subsequent access address output signals are advanced accordingly.

[0116] Figure 6 The rest of the operations are the same as Figure 5 The same or similar ones will not be repeated here.

[0117] Figure 7 The write operation shown above is Figure 5 The main difference between the write operation and the write operation is that only one access address and its corresponding set of write data D0 are input in this write operation. Figure 7It can be seen that only the input / output signals related to the first access address, namely the first row address input signal RA0_INPNT, the first column address input signal CA0_INPNT and the first access address output signal A0_OUTPNT, are enabled, while the subsequent row address input signals, column address input signals and access address output signals are inactive and remain invalid.

[0118] Similarly, Figure 8 The read operation shown above is Figure 6 The main difference between the read operation and the read operation is that only one access address is input in this read operation and only one set of corresponding read data D0 is output. Figure 8 It can be seen that only the input / output signals related to the first access address, namely the first row address input signal RA0_INPNT, the first column address input signal CA0_INPNT and the first access address output signal A0_OUTPNT, are enabled, while the subsequent row address input signals, column address input signals and access address output signals are inactive and remain invalid.

[0119] The following will be combined Figures 9 to 16 To describe in more detail Figure 4 The specific composition of the controller.

[0120] Figure 9 Shown Figure 4 A schematic diagram of the composition of an example of an input pointer generation unit in .

[0121] like Figure 9 As shown, the input pointer generating unit 900 includes a first counting clock generating unit 910 and a first counting output unit 920. In addition, optionally, the input pointer generating unit 900 may further include a pulse generator 930 for generating a reset signal RST.

[0122] The first counting clock generation unit 910 is configured to receive the first enable signal DQS, the chip enable signal CS# and the first clock CLK, and generate a first counting clock CAIN_CK based on these three signals, and the first counting clock CAIN_CK has a clock signal synchronized with the first clock only between the valid edge of the chip enable signal CS# and the invalid edge of the first enable signal DQS.

[0123] The first counting output unit 920 is configured to count the rising and / or falling edges of the first counting clock CAIN_CK, and in response to the results of each count, sequentially enable the access command enable signal CMD_LATEN, the mode configuration enable signal MRS_LATEN, and each row address input signal and column address input signal RA0_INPNT+CA0_INPNT to RAn_INPNT+CAn_INPNT (n=2 in this example). In addition, in some embodiments, the first counting output unit 920 may optionally generate a signal CA_INP_CNT or RA_INP_CNT indicating the total number of column addresses or row addresses input for this access operation and output it to the output pointer generation unit.

[0124] When DDR transmission timing is adopted on the A / DQ line, the first counting output unit 920 counts both the rising and falling edges of the first counting clock CAIN_CK. When SDR transmission timing is adopted on the A / DQ line, only the edge involving data transmission between the rising and falling edges of the first counting clock CAIN_CK is counted.

[0125] thus, Figure 9 The input pointer generation unit can simply and effectively generate various signals that respectively indicate the transmission periods of CMD, MR and each access address RA+CA that are sequentially transmitted on the A / DQ line.

[0126] Figure 10 Shown for implementation Figure 9 An exemplary circuit diagram of an input pointer generation unit, Figure 11 shows the write operation Figure 10 An exemplary timing diagram of each signal involved in the input pointer generation unit. Those skilled in the art will understand that Figure 10 The circuit details in the subsequent figures are merely exemplary. Various modifications can be easily made to them under the teachings of the present disclosure to achieve the same functions, and these modifications are all within the scope of the solutions claimed for protection by the present disclosure.

[0127] like Figure 10 As shown, the input pointer generating unit 1000 includes a first counting clock generating unit 1010 and a first counting output unit 1020 .

[0128] The first counting clock generating unit 1010 includes a pulse generator PUL2 , a pulse generator PUL3 , an SR latch SR1 , and an AND gate AND1 .

[0129] The pulse generator PUL2 receives the chip enable signal CS# and generates a pulse triggered by its valid edge, while the pulse generator PUL3 receives the first enable signal DQS and generates a pulse triggered by its invalid edge. In this example, the valid edge of CS# and the invalid edge of DQS are both falling edges. Figure 10 As shown in the figure, pulse generators PUL2 and PUL3 are both falling-edge triggered pulse generators.

[0130] SR latch SR1 has a set terminal S receiving the output of pulse generator PUL2, a reset terminal R receiving the output of pulse generator PUL3, and a non-inverting output terminal Q coupled to one input of AND gate AND1 (this input signal is labeled "CAIN_EN" in the figure). The other input of AND gate AND1 receives the first clock CLK, and the output of AND gate AND1 is the first counting clock CAIN_CK.

[0131] However, the coupling relationship of the SR latch SR1 is not limited to Figure 10 As shown. In view of the characteristics of the SR latch, the above Figure 10 The signals of the set terminal S and reset terminal R of the SR latch SR1 are swapped, and the inverting output terminal Coupled to one input terminal of the AND gate AND1, the same circuit function can be achieved.

[0132] Therefore, the coupling relationship of the SR latch SR1 can be summarized as follows: the set terminal S of the SR latch SR1 receives one of the output of the pulse generator PUL2 and the output of the pulse generator PUL3, its reset terminal R receives the other of the two outputs, and one of its two output terminals is coupled to an input terminal of the AND gate AND1.

[0133] In addition, if Figure 10 As shown, the first counting output unit 1020 includes a counter CNT1, a counter CNT2, a one-hot decoder HOT1, a one-hot decoder HOT2, a first set of AND gates AND11-AND14, and a second set of AND gates AND21-AND24. The first counting output unit 1020 may also include an inverter INV1 for inverting the first counting clock CAIN_CK.

[0134] The clock end of counter CNT1 receives the first counting clock CAIN_CK, and the clock end of counter CNT2 receives the inverted signal of the first counting clock CAIN_CK. Moreover, both counters CNT1 and CNT2 are falling-edge triggered, and thus count the falling edge of the first counting clock CAIN_CK and the falling edge of its inverted signal (i.e., the rising edge of the first counting clock CAIN_CK), respectively.

[0135] The one-hot decoder HOT1 receives the counting result RA_INPNT_CNT of the counter CNT1 and outputs a first set of one-hot decoding signals (RACNT000, RACNT001, RACNT010, RACNT100, etc.).

[0136] For example, when RA_INPNT_CNT[2:0]=3'b000, RACNT000 is enabled; when 3'b001, RACNT001 is enabled; when 3'b010, RACNT010 is enabled; when 3'b011, RACNT100 is enabled, and so on. It can be understood that the one-hot decoding signal corresponding to the counting result RA_INPNT_CNT[2:0] can be up to 8, Figure 10 The example only uses the first four, but this number is only exemplary. The embodiment of the present disclosure can select the required number of one-hot decoding signals according to the number of input pointer signals that need to be generated subsequently.

[0137] The first set of AND gates AND11-AND14 respectively receive the first set of one-hot decoded signals and the first count clock CAIN_CK, and respectively output the access command enable signal CMD_LATEN and each row address input signal (RA0_INPNT, RA1_INPNT, RA2_INPNT, etc.). That is, the first set of AND gates corresponds one-to-one to the first set of one-hot decoded signals. Each of the first set of AND gates is used to AND one of the first set of one-hot decoded signals with the first count clock CAIN_CK to obtain the input pointer signal at the corresponding position.

[0138] Similarly, the one-hot decoder HOT2 receives the counting result CA_INPNT_CNT of the counter CNT2 and outputs a second set of one-hot decoding signals ( CACNT000 , CACNT001 , CACNT010 , CACNT100 , etc.).

[0139] The second set of AND gates AND21 - AND24 respectively receive the second set of one-hot decoding signals and the inverted signal of the first counting clock CAIN_CK, and respectively output the mode configuration enable signal MRS_LATEN and each column address input signal ( CA0_INPNT, CA1_INPNT, CA2_INPNT, etc.).

[0140] In addition, optionally, the input pointer generation unit 1000 may further include a pulse generator PUL4 for generating a reset signal RST, which is configured to generate a pulse triggered by the invalid edge of the chip enable signal CS#, and its output terminal is coupled to the reset terminal of the counter CNT1 and the set terminal of the counter CNT2. Figure 10In the example, the pulse generator PUL4 is a rising edge triggered pulse generator, thus, when CS# is pulled high to end the current access operation, the reset signal RST is activated, thereby resetting the counter CNT1 and setting the counter CNT2.

[0141] refer to Figure 11 The timing diagram shows clearly Figure 10 The working process of the circuit. It can be understood that although Figure 11 The example shows the write operation process, but for Figure 10 The signal timing generated during the read operation is the same as that during the write operation.

[0142] Figure 11 The timing of the four signals CLK, CS#, DQS and DQ transmitted through the access interface is the same as Figure 5 The same, no longer repeated here.

[0143] like Figure 11 As shown, the pull-down of CS# causes the pulse generator PUL2 to generate a pulse, which sets the SR latch SR1 so that the output becomes high, that is, the signal CAIN_EN is enabled, thereby the clock signal CLK can be converted into the clock CAIN_CK through the AND gate AND1.

[0144] The falling edge of clock CAIN_CK triggers counter CNT1 to generate a count result, RA_INPNT_CNT. Clock CAIN_CK is ANDed with the one-hot decoded signal corresponding to the count result RA_INPNT_CNT, generating the corresponding input pointer signals CMD_LATEN, RA0_INPNT, RA1_INPNT, and RA2_INPNT for each count result. For example, input pointer signal RA1_INPNT is enabled only when count result signal RA_INPNT_CNT[2:0] = 3'b010.

[0145] The rising edge of the clock CAIN_CK triggers the counter CNT2 to count and obtain the counting result CA_INPNT_CNT. The inverted signal of the clock CAIN_CK is ANDed with the one-hot decoding signal corresponding to the counting result CA_INPNT_CNT, thereby sequentially obtaining the corresponding input pointer signals MRS_LATEN, CA0_INPNT, CA1_INPNT, and CA2_INPNT under each counting result.

[0146] Figure 12 Shown Figure 4 A circuit diagram of an example of a read / write state generation unit in FIG.

[0147] like Figure 12As shown, the read / write status generating unit 1200 includes a register REG2 and an access instruction decoding unit 1210 .

[0148] The data input terminal of the register REG2 is coupled to the data / address multiplexing line, that is, receives the DQ signal transmitted thereon, and its clock terminal receives the access command enable signal CMD_LATEN, so that the register REG2 can output the access command CMD in the DQ signal.

[0149] For example, the register REG2 may be composed of 8 D flip-flops.

[0150] The access command decoding unit 1210 is coupled to the data output terminal of the register REG2 and is configured to enable the read enable signal RD_ACCEN or the write enable signal WR_ACCEN in response to the value of the access command CMD. The read enable signal RD_ACCEN is enabled when CMD is a read command, and the WR_ACCEN is enabled when CMD is a write command.

[0151] For example, the access instruction decoding unit 1210 is a logic circuit unit, which can be designed according to a truth table formed by various CMD values ​​to be input and the corresponding values ​​of RD_ACCEN and WR_ACCEN to be output.

[0152] Although Figure 12 , the reset signal RST is received from outside the read / write state generation unit (e.g., input pointer generation unit). However, in some other embodiments, the read / write state generation unit can generate the reset signal RST itself. For example, the read / write state generation unit 1200 can also include a pulse generator ( Figure 12 (not shown), it is configured to generate a pulse triggered by the invalid edge of the chip enable signal CS#, and its output terminal is coupled to the reset terminal of the register REG2; that is, the output of the pulse generator is the reset signal RST. At this time, the read / write status generation unit 1200 can also output the reset signal RST to the input pointer generation unit and the output pointer generation unit as the reset signal RST of the two, thereby Figure 9 The pulse generator 930 and the corresponding Figure 10 The pulse generator PUL4 in can also be omitted.

[0153] Figure 13 Shown Figure 4 A schematic diagram of the composition of an example of an output pointer generation unit in FIG.

[0154] like Figure 13 As shown, the output pointer generation unit 1300 includes a delay unit 1310 and an output unit 1320.

[0155] The delay unit 1310 is configured to enable the delayed arrival signal LCHIT after a predetermined number of clock cycles have elapsed while the read enable signal RD_ACCEN or the write enable signal WR_ACCEN is valid, wherein the clock cycle is the same as the clock cycle of the first clock CLK.

[0156] The output unit 1320 is configured to periodically enable each access address output signal (A0_OUTPNT, A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.) in sequence according to the burst length after the delayed arrival signal LCHIT is enabled when the write enable signal WR_ACCEN is enabled, and to enable the first access address output signal A0_OUTPNT immediately after the cache unit has cached the first input access address (this moment can be indicated by, for example, the aforementioned CA0_INPNT) when the read enable signal RD_ACCEN is enabled, and to periodically enable each subsequent access address output signal (A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.) in sequence according to the burst length after the delayed arrival signal LCHIT is enabled, where the burst length is set by the mode register after the mode configuration value is set.

[0157] In some embodiments, for example Figure 13 As shown, the output unit 1320 may include a burst counting clock generating unit 1321 , a burst length counting unit 1322 , a second counting clock generating unit 1323 and a second counting output unit 1324 .

[0158] The burst count clock generation unit 1321 is configured to enable the address count arrival signal when the number of output access addresses is equal to the number of cached access addresses (which can be indicated by, for example, the aforementioned CA_INPNT_CNT signal), and to generate a burst count clock BLC_CLK based on the delayed arrival signal LCHIT, the address count arrival signal and the first clock CLK, wherein the burst count clock BLC_CLK has a clock signal synchronized with the first clock CLK only between the valid edge of the delayed arrival signal LCHIT and the valid edge of the address count arrival signal.

[0159] The burst length counting unit 1322 is configured to cyclically count the rising and / or falling edges of the burst counting clock BLC_CLK, where the number of counts per cycle is determined by the burst length. The burst counting clock BLC_CLK can be counted for rising edges, falling edges, or both, as needed. The conversion relationship between the number of counts per cycle and the burst length can be determined based on the counting method and the data transmission timing method (DDR or SDR) on the A / DQ lines.

[0160] The second counting clock generating unit 1323 is configured to generate a second counting clock ADDR_OUTPNT_CLK based on the read enable signal RD_ACCEN, the counting result BL_CNT of the burst length counting unit 1322 and the burst counting clock BLC_CLK, wherein the second counting clock ADDR_OUTPNT_CLK has a clock signal synchronized with the burst counting clock BLC_CLK during the period when the burst length counting unit 1322 outputs a specific counting result (a certain counting result value can be selected as needed), and also has a pulse immediately after the cache unit has cached the first input access address (this moment can be indicated by, for example, the aforementioned CA0_INPNT) during the period when the read enable signal RD_ACCEN is valid.

[0161] The second counting output unit 1324 is configured to count rising edges or falling edges of the second counting clock ADDR_OUTPNT_CLK and sequentially enable respective access address output signals (A0_OUTPNT, A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.) in response to the results of respective counting.

[0162] Figure 14 Shown for implementation Figure 13 An exemplary circuit diagram of an output pointer generation unit, Figure 15 shows the write operation Figure 14 An exemplary timing diagram of various signals involved in the output pointer generation unit, Figure 16 shows a read operation Figure 14 FIG. 5 is an exemplary timing diagram of various signals involved in the output pointer generation unit.

[0163] like Figure 14 As shown, the output pointer generation unit 1400 includes a delay unit 1410 , a burst count clock generation unit 1421 , a counter CNT4 as a burst length counting unit, a second count clock generation unit 1423 and a second count output unit 1424 .

[0164] The delay unit 1410 includes a first logic unit 1411 , a low-pass latch LAT1 , an AND gate AND2 , and a counter CNT3 .

[0165] The first logic unit 1411 receives the read enable signal RD_ACCEN, the write enable signal WR_ACCEN, and the delayed arrival signal LCHIT and outputs the delay control signal LC_CRT. In other words, the first logic unit 1411 is configured to generate the delay control signal LC_CRT based on the read enable signal RD_ACCEN, the write enable signal WR_ACCEN, and the delayed arrival signal LCHIT. The delay control signal LC_CRT is valid only when the read enable signal RD_ACCEN or the write enable signal WR_ACCEN is valid and the delayed arrival signal LCHIT is invalid.

[0166] Figure 14 A specific implementation of the first logic unit 1411 is given, but those skilled in the art will understand that the embodiments of the present disclosure are not limited thereto. Instead, the logic circuit structure of the first logic unit 1411 may be designed based on the relationship between the input signal and the output signal of the first logic unit 1411 described herein.

[0167] In some embodiments, as Figure 14 As shown, the first logic unit 1411 includes an OR gate OR1 and an AND gate AND4, wherein the inputs of the OR gate OR1 are the read enable signal RD_ACCEN and the write enable signal WR_ACCEN, the output of the OR gate OR1 and the inverted signal of the delayed arrival signal LCHIT serve as the inputs of the AND gate AND4, and the AND gate AND4 outputs the delay control signal LC_CRT.

[0168] The low-pass latch LAT1 receives the delay control signal LC_CRT at its input, the first clock CLK at its control terminal, and the delay enable signal LC_CLKEN at its output. A low-pass latch passes input data when the control signal is low and latches the data when the control signal is high.

[0169] Two input terminals of the AND gate AND2 receive the delay enable signal LC_CLKEN and the first clock CLK respectively, and output the delayed counting clock LC_CLK.

[0170] The clock terminal of the counter CNT3 receives the delayed counting clock LC_CLK. Figure 14 The counter CNT3 is shown to count the rising edges of the delay counting clock LC_CLK, but in other embodiments, it can also count the falling edges thereof. The counter CNT3 enables the delayed arrival signal LCHIT after counting a predetermined number of times.

[0171] In addition, if Figure 14 As shown, the burst count clock generating unit 1421 includes a comparator CMP, a low-pass latch LAT2, a pulse generator PUL5, a pulse generator PUL6, an SR latch SR2, and an AND gate AND3.

[0172] The comparator CMP is configured to compare the number of currently output access addresses with the number of cached access addresses and enable the address count arrival signal when the two are equal. Figure 14 As shown, the previous Figure 10 The counting result CA_INPNT_CNT of the counter CNT2 in the buffer indicates the number of cached access addresses, and the number of currently output access addresses can be indicated by the counting result ADDR_OUTPNT_CNT of the counter CNT5 in the second counting output unit 1424 described later. Figure 10 and Figure 11 As shown, since CA_INPNT_CNT also counts the MR input before the address is accessed, the final result of CA_INPNT_CNT is 1 more than the number of addresses actually cached, so the comparator CMP enables the address count arrival signal when ADDR_OUTPNT_CNT=CA_INPNT_CNT-1.

[0173] An input terminal of the low-pass latch LAT2 receives the delayed arrival signal LCHIT, a control terminal thereof receives the first clock CLK, and an output of the low-pass latch LAT2 receives a burst enable signal.

[0174] The pulse generator PUL5 receives the address count arrival signal and generates a pulse triggered by its valid edge, while the pulse generator PUL6 receives the burst enable signal and generates a pulse triggered by its valid edge. In this example, the valid edges of the address count arrival signal and the burst enable signal are both rising edges. Figure 14 As shown in the figure, pulse generators PUL5 and PUL6 are both rising edge triggered pulse generators.

[0175] SR latch SR2 has a set terminal S receiving the output ADDR_CNT_HIT of pulse generator PUL5, a reset terminal R receiving the output of pulse generator PUL6, and an inverting output terminal coupled to one input terminal of AND gate AND3 (this input signal is labeled "DEN" in the figure). The other input terminal of AND gate AND3 receives the first clock CLK, and the output of AND gate AND3 is the burst count clock BLC_CLK.

[0176] However, the coupling relationship of the SR latch SR2 is not limited to Figure 14 As shown. In view of the characteristics of the SR latch, the above Figure 14 The same circuit function can be achieved by exchanging the signals of the set terminal S and the reset terminal R of the SR latch SR2 and coupling the positive phase output terminal to one input terminal of the AND gate AND3.

[0177] Therefore, the coupling relationship of the SR latch SR2 can be summarized as follows: the set terminal S of the SR latch SR2 receives one of the output of the pulse generator PUL5 and the output of the pulse generator PUL6, its reset terminal R receives the other of the two outputs, and one of its two output terminals is coupled to an input terminal of the AND gate AND3.

[0178] In addition, if Figure 14 As shown, the clock terminal of counter CNT4, which serves as a burst length counter, receives the burst count clock BLC_CLK. Counter CNT4 cyclically counts the falling edges of the burst count clock BLC_CLK. "Cyclic counting" means that after reaching a preset maximum value, the count returns to the initial value and continues counting. The reset terminal of counter CNT4 can also receive the output ADDR_CNT_HIT of pulse generator PUL5 as a reset signal.

[0179] In addition, if Figure 14 As shown, the second counting clock generating unit 1423 includes a one-hot decoder HOT3 and a second logic unit 1425 .

[0180] The one-hot decoder HOT3 receives the count result BL_CNT of the counter CNT4 as a burst length counting unit and outputs a specific one-hot decoding signal corresponding to the specific count result. Figure 14 In the example, the specific counting result is 000, and the corresponding specific one-hot decoding signal is BLC000, but in other implementations, other counting result values ​​and their corresponding one-hot decoding signals can be selected as needed.

[0181] The second logic unit 1425 receives a specific one-hot decoding signal (e.g., BLC000), a burst count clock BLC_CLK, a read enable signal RD_ACCEN, and a first signal (e.g., CA0_INPNT) indicating that the cache unit has cached the first input access address, and outputs a second count clock ADDR_OUTPNT_CLK. In other words, the second logic unit 1425 is configured to generate a second count clock based on the specific one-hot decoding signal, the burst count clock, the read enable signal, and the first signal. The second count clock is valid only when the specific one-hot decoding signal is valid and the burst count clock is valid, or when the read enable signal is valid and the first signal is valid.

[0182] Figure 14 A specific implementation of the second logic unit 1425 is given, but those skilled in the art will understand that the embodiments of the present disclosure are not limited thereto. Instead, the logic circuit structure of the second logic unit 1425 can be designed based on the relationship between the input signal and the output signal of the second logic unit 1425 described herein.

[0183] In some embodiments, as Figure 14 As shown, the second logic unit 1425 includes an AND gate AND5, an AND gate AND6 and an OR gate OR2, wherein the input of the AND gate AND5 is the specific one-hot decoding signal BLC000 and the burst counting clock BLC_CLK, the input of the AND gate AND6 is the read enable signal RD_ACCEN and the first signal CA0_INPNT, the output of the AND gate AND5 and the output of the AND gate AND6 serve as the input of the OR gate OR2, and the OR gate OR2 outputs the second counting clock ADDR_OUTPNT_CLK.

[0184] In addition, if Figure 14 As shown, the second counting output unit 1424 includes a counter CNT5 , a one-hot decoder HOT4 , and a third set of AND gates AND31 -AND34 .

[0185] The clock terminal of the counter CNT5 receives the second counting clock ADDR_OUTPNT_CLK and counts the falling edges of the second counting clock ADDR_OUTPNT_CLK.

[0186] The one-hot decoder HOT4 receives the counting result ADDR_OUTPNT_CNT of the counter CNT5 and outputs a third set of one-hot decoding signals ( CNT000 , CNT001 , CNT010 , CNT100 , etc.).

[0187] The third group of AND gates AND31 - AND34 respectively receive the third group of one-hot decoding signals and the second counting clock ADDR_OUTPNT_CLK, and respectively output respective access address output signals ( A0_OUTPNT, A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.).

[0188] In addition, if Figure 14 As shown, in some embodiments, the reset terminals of the counter CNT3 and the counter CNT5 receive a reset signal RST, which may be generated by the output pointer generation unit itself or received from other external units.

[0189] refer to Figure 15 The timing diagram shows clearly Figure 12 and Figure 14 The working process of the circuit during write operation.

[0190] Figure 15 The timing of the four signals CLK, CS#, DQS and DQ transmitted through the access interface is the same as Figure 5 The same, no longer repeated here.

[0191] like Figure 15 As shown, Figure 12The read / write status generation unit obtains the WR instruction on the rising edge of the CMD_LATEN signal and enables the WR_ACCEN signal after decoding it. At this time, the delayed arrival signal LCHIT should be low, so Figure 14 The signal LC_CLKEN in the delay unit 1410 is enabled, so that the clock signal CLK can be converted into the clock LC_CLK through the AND gate AND2, and the counter CNT3 starts to perform delay counting.

[0192] After counter CNT3 counts the delay, the delay-reach signal LCHIT is pulled high, deactivating the LC_CLKEN signal and enabling the DEN signal. This allows the CLK clock signal to pass through AND gate AND3 and become the clock BLC_CLK. Counter CNT4 then begins counting the burst length and outputs the count result BL_CNT. When the burst length is 16, using DDR timing, transmitting the data corresponding to each access address requires a total of eight clock cycles. Therefore, a 3-bit falling-edge-triggered counter can be used as counter CNT4.

[0193] When the burst length count BL_CNT[7:0] is 8'h00, BLC000 is enabled, so that the signal ADDR_OUTPNT_CLK is activated and generates a pulse, thereby triggering the counting of the counter CNT5.

[0194] The clock ADDR_OUTPNT_CLK is ANDed with each one-hot decoding signal corresponding to the counting result ADDR_OUTPNT_CNT of the counter CNT5 , thereby enabling the corresponding output pointer signals A0_OUTPNT, A1_OUTPNT, and A2_OUTPNT in sequence under each counting result.

[0195] When the counting result ADDR_OUTPNT_CNT=CA_INPNT_CNT-1, the ADDR_CNT_HIT signal becomes high, thereby deactivating the signal DEN, and the counter CNT4 stops counting and is reset.

[0196] When the chip select signal CS# is pulled high, the reset signal RST is activated, thereby resetting the signals WR_ACCEN, LCHIT, and the corresponding counters. This write instruction ends.

[0197] refer to Figure 16 The timing diagram shows clearly Figure 12 and Figure 14 The working process of the circuit during the read operation.

[0198] Figure 16 The timing of the four signals CLK, CS#, DQS and DQ transmitted through the access interface is the same as Figure 6 The same, no longer repeated here.

[0199] like Figure 16 As shown, Figure 12 The read / write status generation unit obtains the RD instruction at the rising edge of the CMD_LATEN signal and enables the RD_ACCEN signal after decoding it. At this time, the delayed arrival signal LCHIT should be low, so Figure 14 The signal LC_CLKEN in the delay unit 1410 is enabled, so that the clock signal CLK can be converted into the clock LC_CLK through the AND gate AND2, and the counter CNT3 starts to perform delay counting.

[0200] At the same time, since RD_ACCEN goes high, the pulse of CA0_INPNT causes the clock signal ADDR_OUTPNT_CLK to generate a corresponding pulse, causing counter CNT5 to perform a count. In addition, since counter CNT5 counts the falling edges of ADDR_OUTPNT_CLK, the count result of counter CNT5 during the first pulse of ADDR_OUTPNT_CLK remains at the initial value 000, and its corresponding one-hot decoding signal CNT000 is enabled. Therefore, the first pulse of ADDR_OUTPNT_CLK activates the first address output signal A0_OUTPNT.

[0201] After counter CNT3 counts the delay, the delay-reach signal LCHIT is pulled high, deactivating the LC_CLKEN signal and enabling the DEN signal. This allows the CLK clock signal to pass through AND gate AND3 and become the clock BLC_CLK. Counter CNT4 then begins counting the burst length and outputs the count result BL_CNT. When the burst length is 16, using DDR timing, transmitting the data corresponding to each access address requires a total of eight clock cycles. Therefore, a 3-bit falling-edge-triggered counter can be used as counter CNT4.

[0202] When the burst length count BL_CNT[7:0] is 8'h00, BLC000 is enabled, so that the signal ADDR_OUTPNT_CLK is activated and generates a pulse again, thereby triggering the counting of the counter CNT5 again.

[0203] The clock ADDR_OUTPNT_CLK is ANDed with each one-hot decoding signal corresponding to the counting result ADDR_OUTPNT_CNT of the counter CNT5 , thereby enabling the corresponding output pointer signals A1_OUTPNT and A2_OUTPNT in sequence under each subsequent counting result.

[0204] When the counting result ADDR_OUTPNT_CNT=CA_INPNT_CNT-1, the ADDR_CNT_HIT signal becomes high, thereby deactivating the signal DEN, and the counter CNT4 stops counting and is reset.

[0205] When the chip select signal CS# is pulled high, the reset signal RST is activated, thereby resetting the signals RD_ACCEN, LCHIT, and the corresponding counters. This read instruction ends.

[0206] It can be understood that, unless obviously contradicted, various details or variations mentioned in the above embodiments / examples can be combined with other embodiments / examples.

[0207] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A controller for a memory, the memory comprising a memory array, a mode register, and an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplexing line for time-division multiplexing of data and addresses; The controller includes: a decoding unit that receives an access instruction and a mode configuration value sequentially input via the data / address multiplexing line and is configured to set the mode register based on the mode configuration value; as well as The cache unit is configured to sequentially cache at least one access address input after the mode configuration value via the data / address multiplexing line, and sequentially output the at least one access address to the memory array at a specified time.

2. The controller according to claim 1, wherein: The decoding section is configured to input the mode configuration value into the mode register so as to update the value of the mode register to the mode configuration value.

3. The controller according to claim 1, wherein: The decoding section is further configured to generate a read enable signal or a write enable signal based on the access instruction, and the specified time is determined based on the read enable signal or the write enable signal.

4. The controller according to claim 1, wherein: The access interface also includes a transmission line; The decoding section further receives a first enable signal input via the transmission line, and is further configured to generate an address input signal based on the first enable signal, wherein the address input signal has signal edges respectively corresponding to transmission periods of respective access addresses input before an invalid edge of the first enable signal; and The cache section is configured to cache corresponding access addresses in response to the signal edge of the address input signal.

5. The controller according to claim 4, wherein: The transmission line is further used to output a signal for synchronizing sampling of read data output on the data / address multiplexing line, and / or to input a signal for shielding write data received on the data / address multiplexing line.

6. The controller according to claim 4, wherein: The access interface also includes a chip select line and a clock line; The decoding unit includes an input pointer generation unit, which is configured to receive a chip enable signal input via the chip select line, a first clock input via the clock line, and the first enable signal, and generate an access instruction enable signal, a mode configuration enable signal and the address input signal based on the first enable signal, the chip enable signal and the first clock, wherein the access instruction enable signal has a signal edge corresponding to the transmission period of the access instruction, and the mode configuration enable signal has a signal edge corresponding to the transmission period of the mode configuration value.

7. The controller according to claim 6, wherein: The decoding unit also includes: The first register has a data input terminal coupled to the data / address multiplexing line, a clock terminal receiving the mode configuration enable signal, and a data output terminal coupled to the mode register.

8. The controller according to claim 6, wherein: The decoding unit further includes a read / write status generating unit, wherein the read / write status generating unit includes: a second register, whose data input terminal is coupled to the data / address multiplexing line and whose clock terminal receives the access instruction enable signal; a first pulse generator configured to generate a pulse triggered by the invalid edge of the chip enable signal, and an output terminal of the first pulse generator coupled to the reset terminal of the second register; and An access instruction decoding unit is coupled to the data output terminal of the second register and is configured to enable a read enable signal or a write enable signal in response to a value of the access instruction.

9. The controller according to claim 6, wherein: The address input signals include a row address input signal group and a column address input signal group, wherein each row address input signal or column address input signal has a signal edge corresponding to a transmission period of a row address or a column address in each access address input before the invalid edge of the first enable signal. The input pointer generating unit comprises: a first counting clock generating unit configured to generate a first counting clock based on the first enable signal, the chip enable signal, and the first clock, wherein the first counting clock has a clock signal synchronized with the first clock only between an active edge of the chip enable signal and an inactive edge of the first enable signal; and The first counting output unit is configured to count the rising edge and / or falling edge of the first counting clock, and enable the access instruction enable signal, the mode configuration enable signal, and each row address input signal and column address input signal in sequence in response to the result of each counting.

10. The controller according to claim 9, wherein: The first counting clock generating unit includes: a second pulse generator configured to generate a pulse triggered by an active edge of the chip enable signal; a third pulse generator, configured to generate a pulse triggered by the invalid edge of the first enable signal; a first SR latch having a set terminal receiving one of the output of the second pulse generator and the output of the third pulse generator, and a reset terminal receiving the other of the two outputs; and The first AND gate has two input terminals receiving one of the two outputs of the first SR latch and the first clock respectively, and outputs the first counting clock.

11. The controller according to claim 9, wherein: The first counting output unit includes: A first counter receives the first counting clock at its clock end and counts falling edges of the first counting clock. A second counter receives the inverted signal of the first counting clock at its clock end and counts the falling edges of the inverted signal of the first counting clock. a first one-hot decoder, receiving a counting result of the first counter and outputting a first set of one-hot decoding signals, A second one-hot decoder receives the counting result of the second counter and outputs a second set of one-hot decoding signals, A first set of AND gates receives the first set of one-hot decoding signals and the first counting clock, and outputs the access instruction enable signal and each row address input signal, and The second group of AND gates respectively receive the second group of one-hot decoding signals and the inverted signal of the first counting clock, and respectively output the mode configuration enable signal and each column address input signal.

12. The controller according to claim 11, wherein: The input pointer generation unit further includes a fourth pulse generator configured to generate a pulse triggered by the invalid edge of the chip enable signal, and an output terminal of the fourth pulse generator is coupled to the reset terminal of the first counter and the set terminal of the second counter.

13. The controller according to claim 3, wherein: The access interface also includes a clock line; The decoding section includes an output pointer generation unit configured to receive a first clock input via the clock line and the read enable signal or the write enable signal, and generate an address output signal based on the first clock and the read enable signal or the write enable signal, wherein the address output signal has a signal edge indicating an output timing of each access address cached by the cache section; and The cache units are configured to output corresponding access addresses in response to signal edges of the address output signals.

14. The controller according to claim 13, wherein: The address output signal includes a group of access address output signals, wherein each access address output signal has a signal edge indicating an output time of each access address cached by the cache unit. The output pointer generating unit includes: a delay unit configured to enable the delayed arrival signal after a predetermined number of clock cycles have passed during the validity period of the read enable signal or the write enable signal, wherein the clock cycle is the same as the clock cycle of the first clock; and An output unit is configured to periodically enable each access address output signal in sequence according to a burst length after the delayed arrival signal is enabled when the write enable signal is enabled, and to enable the first access address output signal immediately after the cache unit has cached the first input access address when the read enable signal is enabled and to periodically enable subsequent access address output signals in sequence according to the burst length after the delayed arrival signal is enabled, wherein the burst length is set by the mode register after being set based on the mode configuration value.

15. The controller according to claim 14, wherein: The output unit includes: a burst count clock generating unit configured to enable an address count arrival signal when the number of output access addresses is equal to the number of cached access addresses, and to generate a burst count clock based on the delayed arrival signal, the address count arrival signal, and the first clock, wherein the burst count clock has a clock signal synchronized with the first clock only between an active edge of the delayed arrival signal and an active edge of the address count arrival signal; a burst length counting unit configured to perform cyclic counting of the rising edge and / or falling edge of the burst counting clock, wherein the number of counts in each cycle is determined by the burst length; a second counting clock generating unit configured to generate a second counting clock based on the read enable signal, the counting result of the burst length counting unit, and the burst counting clock, wherein the second counting clock has a clock signal synchronized with the burst counting clock during a period when the burst length counting unit outputs a specific counting result, and further has a pulse immediately after the cache unit has cached a first input access address during a period when the read enable signal is valid, and The second counting output unit is configured to count rising edges or falling edges of the second counting clock, and sequentially enable each access address output signal in response to a result of each counting.

16. The controller according to claim 14, wherein: The delay unit comprises: a first logic unit configured to generate a delay control signal based on the read enable signal, the write enable signal, and the delayed arrival signal, the delay control signal being valid only when the read enable signal or the write enable signal is valid and the delayed arrival signal is invalid; a first low-pass latch, whose input terminal receives the delay control signal, whose control terminal receives the first clock, and whose output delays the enable signal, a second AND gate, whose two input terminals receive the delay enable signal and the first clock respectively, and outputs a delayed count clock, and A third counter receives the delay counting clock at its clock terminal, counts rising edges or falling edges of the delay counting clock, and enables the delay arrival signal after the predetermined number is reached.

17. The controller according to claim 15, wherein: The burst counting clock generating unit comprises: a comparator configured to compare the number of currently output access addresses with the number of cached access addresses and enable the address count arrival signal when the two are equal, a second low-pass latch, whose input terminal receives the delayed arrival signal, whose control terminal receives the first clock, and whose output is a burst enable signal; a fifth pulse generator, configured to generate a pulse triggered by an active edge of the address count arrival signal; a sixth pulse generator, configured to generate a pulse triggered by an active edge of the burst enable signal, a second SR latch having a set terminal receiving one of the output of the fifth pulse generator and the output of the sixth pulse generator, and a reset terminal receiving the other of the two outputs; and a third AND gate, whose two input terminals receive one of the two outputs of the second SR latch and the first clock respectively, and outputs the burst count clock; and The burst length counting unit includes a fourth counter, a clock end of which receives the burst counting clock and cyclically counts the falling edges of the burst counting clock.

18. The controller according to claim 15, wherein: The second counting clock generating unit includes: a third one-hot decoder, receiving the counting result of the burst length counting unit and outputting a specific one-hot decoding signal corresponding to the specific counting result; The second logic unit is configured to generate the second counting clock based on the specific one-hot decoding signal, the burst counting clock, the read enable signal, and the first signal indicating that the cache unit has cached the first input access address, and the second counting clock is valid only when the specific one-hot decoding signal is valid and the burst counting clock is valid or when the read enable signal is valid and the first signal is valid.

19. The controller according to claim 15, wherein: The second counting output unit includes: a fifth counter, whose clock terminal receives the second counting clock and counts the falling edges of the second counting clock, a fourth one-hot decoder, receiving the counting result of the fifth counter and outputting a third set of one-hot decoding signals, and The third group of AND gates respectively receive the third group of one-hot decoding signals and the second counting clock, and respectively output respective access address output signals.

20. The controller according to any one of claims 1 to 19, wherein: The memory is PSRAM; and / or The access interface uses a multi-IO SPI protocol; and / or The buffer section is a FIFO buffer.

21. A method for controlling a memory, the memory comprising a memory array, a mode register, and an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplexing line for time-division multiplexing of data and addresses; The method comprises: receiving an access instruction, a mode configuration value, and at least one access address in sequence via the data / address multiplexing line; setting the mode register based on the mode configuration value; as well as The at least one access address is sequentially cached and outputted to the storage array sequentially at a specified time.

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