Controller for memory and control method

Abstract

The present disclosure relates to a controller and a control method for a memory. The memory includes a storage array, a mode register, and an access interface for externally accessing the storage array, the access interface including at least one data / address multiplex line for transmitting data and addresses in time division multiplexing. The controller includes a decoding unit configured to receive an access instruction and a mode configuration value input in sequence via the data / address multiplex line, and configured to set the mode register based on the mode configuration value; and a buffer unit configured to buffer at least one access address input after the mode configuration value via the data / address multiplex line in sequence, and output the at least one access address to the storage array in sequence at a specified time. The scheme can improve the mode configuration efficiency and the access efficiency of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of storage, and in particular to a controller and control method for a memory. Background Technology

[0002] Memory typically plays a vital role in electronic devices such as computers. Currently, there are many different types of memory, including Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Pseudo Static Random Access Memory (PSRAM), and Flash memory.

[0003] With the development of various electronic devices, the demand for memory access is becoming increasingly complex. For example, it is often necessary to access multiple row / column addresses at once, or the configuration of memory modes is becoming more varied and complex, and there are often complex and ever-changing mode requirements in a short period of time.

[0004] Therefore, it is hoped that the memory's mode configuration efficiency and access efficiency can be improved. Summary of the Invention

[0005] One technical problem this disclosure aims to solve is to provide a controller and control method for a memory that can improve the mode configuration efficiency and access efficiency of the memory.

[0006] According to a first aspect of this disclosure, a controller for a memory is provided, the memory including a memory array, a mode register, and an access interface for external access to the memory array, the access interface including at least one data / address multiplexed line for time-division multiplexing of data and address transmission; the controller includes: a decoding unit that receives access instructions and mode configuration values ​​sequentially input via the data / address multiplexed line, and is configured to set the mode register based on the mode configuration value; and a buffer unit configured to sequentially buffer at least one access address input via the data / address multiplexed line after the mode configuration value, and to sequentially output the at least one access address to the memory array at a specified time.

[0007] Optionally, the decoding unit is configured to input the mode configuration value into the mode register so as to update the value of the mode register to the mode configuration value.

[0008] Optionally, the decoding unit is further configured to generate a read enable signal or a write enable signal based on the access instruction, and the specified time is determined based on the read enable signal or the write enable signal.

[0009] Optionally, the access interface further includes a transmission line; the decoding unit also receives a first enable signal input via the transmission line and is further configured to generate an address input signal based on the first enable signal, wherein the address input signal has a signal edge corresponding to the transmission period of each access address input before the failure edge of the first enable signal; and the buffer unit is configured to buffer the corresponding access address in response to the signal edge of the address input signal.

[0010] Optionally, the transmission line is also used to output a signal for synchronizing the sampling of read data output on the data / address multiplex line, and / or input a signal for shielding write data received on the data / address multiplex line.

[0011] Optionally, the access interface further includes a chip select line and a clock line; the decoding unit includes an input pointer generation unit configured to receive a chip enable signal input via the chip select line, a first clock input via the clock line, and the first enable signal, and generate an access instruction enable signal, a mode configuration enable signal, and the address input signal based on the first enable signal, the chip enable signal, and the first clock, wherein the access instruction enable signal has a signal edge corresponding to the transmission period of the access instruction, and the mode configuration enable signal has a signal edge corresponding to the transmission period of the mode configuration value.

[0012] Optionally, the decoding unit further includes: a first register, whose data input terminal is coupled to the data / address multiplexed line, whose clock terminal receives the mode configuration enable signal, and whose data output terminal is coupled to the mode register.

[0013] Optionally, the decoding unit further includes a read / write state generation unit, wherein the read / write state generation unit includes: a second register, the data input of which is coupled to the data / address multiplexed line and the clock input of which receives the access instruction enable signal; a first pulse generator, configured to generate a pulse triggered by the failure edge of the chip enable signal and the output of which is coupled to the reset input of the second register; and an access instruction decoding unit, which is coupled to the data output of the second register and configured to enable a read enable signal or a write enable signal in response to the value of the access instruction.

[0014] Optionally, the address input signal includes a row address input signal group and a column address input signal group, wherein each row address input signal or column address input signal has a signal edge corresponding to the transmission period of the row address or column address in each access address input before the failure edge of the first enable signal. The input pointer generation unit includes: a first counting clock generation unit configured to generate a first counting clock based on the first enable signal, the chip enable signal, and the first clock, wherein the first counting clock has a clock signal synchronized with the first clock only between the effective edge of the chip enable signal and the failure edge of the first enable signal; and a first counting output unit configured to count the rising edge and / or falling edge of the first counting clock, and sequentially enable the access instruction enable signal, the mode configuration enable signal, and each row address input signal and column address input signal in response to the result of each count.

[0015] Optionally, the first counting clock generation unit includes: a second pulse generator configured to generate a pulse triggered by the active edge of the chip enable signal; a third pulse generator configured to generate a pulse triggered by the inactive edge of the first enable signal; a first SR latch whose set terminal receives one of the outputs of the second pulse generator and the third pulse generator, and whose reset terminal receives the other of the two outputs; and a first AND gate whose two input terminals respectively receive one of the two outputs of the first SR latch and the first clock, and outputs the first counting clock.

[0016] Optionally, the first counting output unit includes: a first counter, whose clock input receives the first counting clock and counts the falling edge of the first counting clock; a second counter, whose clock input receives the inverted signal of the first counting clock and counts the falling edge of the inverted signal of the first counting clock; a first one-hot decoder, which receives the counting result of the first counter and outputs a first set of one-hot decoded signals; a second one-hot decoder, which receives the counting result of the second counter and outputs a second set of one-hot decoded signals; a first AND gate, which receives the first set of one-hot decoded signals and the first counting clock respectively, and outputs the access instruction enable signal and each row address input signal respectively; and a second AND gate, which receives the second set of one-hot decoded signals and the inverted signal of the first counting clock respectively, and outputs the mode configuration enable signal and each column address input signal respectively.

[0017] Optionally, the input pointer generation unit further includes a fourth pulse generator, which is configured to generate a pulse triggered by the failure edge of the chip enable signal, and its output is coupled to the reset terminal of the first counter and the set terminal of the second counter.

[0018] Optionally, the access interface further includes a clock line; the decoding unit includes an output pointer generation unit configured to receive a first clock input via the clock line, and the read enable signal or the write enable signal, and generate an address output signal based on the first clock and the read enable signal or the write enable signal, wherein the address output signal has a signal edge that respectively indicates the output time of each access address cached by the cache unit; and the cache unit is configured to output the corresponding access address in response to the signal edge of the address output signal.

[0019] Optionally, the address output signal includes a set of access address output signals, wherein each access address output signal has a signal edge indicating the output time of each access address cached by the cache unit. The output pointer generation unit includes: a delay unit configured to enable a delayed arrival signal after a predetermined number of clock cycles have elapsed during the validity period of the read enable signal or the write enable signal, wherein the clock cycle is the same as the clock cycle of the first clock; and an output unit configured to periodically enable each access address output signal sequentially according to the burst length after the delayed arrival signal is enabled when the write enable signal is enabled, and to enable the first access address output signal immediately after the cache unit has cached the first input access address when the read enable signal is enabled, and to periodically enable each subsequent access address output signal sequentially according to the burst length after the delayed arrival signal is enabled, wherein the burst length is set by the mode register based on the mode configuration value.

[0020] Optionally, the output unit includes: a burst count clock generation unit configured to enable an address count arrival signal when the number of output access addresses equals the number of cached access addresses, and to generate a burst count clock based on the delayed arrival signal, the address count arrival signal, and the first clock, wherein the burst count clock has a clock signal synchronized with the first clock only between the effective edge of the delayed arrival signal and the effective edge of the address count arrival signal; and a burst length counting unit configured to cyclically count the rising and / or falling edges of the burst count clock, wherein the number of counts in each cycle is determined by the burst length. The degree is determined, the second counting clock generation unit is configured to generate a second counting clock based on the read enable signal, the counting result of the burst length counting unit and the burst counting clock, wherein the second counting clock has a clock signal synchronized with the burst counting clock during the period when the burst length counting unit outputs a specific counting result, and has a pulse immediately after the first input access address has been cached in the buffer during the period when the read enable signal is valid, and a second counting output unit is configured to count the rising edge or falling edge of the second counting clock, and sequentially enable the output signal of each access address in response to the result of each count.

[0021] Optionally, the delay unit includes: a first logic unit configured to generate a delay control signal based on the read enable signal, the write enable signal, and the delay arrival signal, which is valid only when the read enable signal or the write enable signal is valid and the delay arrival signal is invalid; a first low-pass latch whose input receives the delay control signal, whose control terminal receives the first clock, and whose output is a delay enable signal; a second AND gate whose two inputs respectively receive the delay enable signal and the first clock, and whose output is a delay counting clock; and a third counter whose clock terminal receives the delay counting clock, counts the rising or falling edge of the delay counting clock, and enables the delay arrival signal after reaching the predetermined number.

[0022] Optionally, the burst count clock generation unit includes: a comparator configured to compare the number of currently output access addresses with the number of cached access addresses and enable the address count arrival signal when they are equal; a second low-pass latch whose input receives the delayed arrival signal, whose control terminal receives the first clock, and whose output is a burst enable signal; a fifth pulse generator configured to generate a pulse triggered by the active edge of the address count arrival signal; a sixth pulse generator configured to generate a pulse triggered by the active edge of the burst enable signal; a second SR latch whose set terminal receives one of the outputs of the fifth pulse generator and the sixth pulse generator, whose reset terminal receives the other of the two outputs; and a third AND gate whose two inputs respectively receive one of the two outputs of the second SR latch and the first clock, and whose output is the burst count clock.

[0023] Optionally, the burst length counting unit includes a fourth counter, whose clock terminal receives the burst counting clock and performs cyclic counting on the falling edge of the burst counting clock.

[0024] Optionally, the second counting clock generation unit includes: a third one-hot decoder, which receives the counting result of the burst length counting unit and outputs a specific one-hot decoder signal corresponding to the specific counting result; and a second logic unit, configured to generate the second counting clock based on the specific one-hot decoder signal, the burst counting clock, the read enable signal, and a first signal indicating that the cache has cached the first input access address, which is valid only when the specific one-hot decoder signal is valid and the burst counting clock is valid, or when the read enable signal is valid and the first signal is valid.

[0025] Optionally, the second counting output unit includes: a fifth counter, whose clock terminal receives the second counting clock and counts the falling edge of the second counting clock; a fourth one-hot decoder, which receives the counting result of the fifth counter and outputs a third set of one-hot decoded signals; and a third set of AND gates, which respectively receive the third set of one-hot decoded signals and the second counting clock, and respectively output each access address output signal.

[0026] Optionally, the memory is PSRAM.

[0027] Optionally, the access interface adopts the multi-IO SPI protocol.

[0028] Optionally, the buffer is a FIFO buffer.

[0029] According to a second aspect of this disclosure, a method for controlling a memory is provided, the memory including a memory array, a mode register, and an access interface for external access to the memory array, the access interface including at least one data / address multiplexed line for time-division multiplexing of data and address; the method includes: sequentially receiving an access instruction, a mode configuration value, and at least one access address via the data / address multiplexed line; setting the mode register based on the mode configuration value; and sequentially buffering the at least one access address, and sequentially outputting the at least one access address to the memory array at a specified time.

[0030] Optionally, the step of setting the mode register based on the mode configuration value includes: inputting the mode configuration value into the mode register so as to update the value of the mode register to the mode configuration value.

[0031] Optionally, the method further includes: generating a read enable signal or a write enable signal based on the access instruction, and the specified time is determined based on the read enable signal or the write enable signal.

[0032] Optionally, the access interface further includes a transmission line; the method further includes: generating an address input signal based on a first enable signal input via the transmission line, wherein the address input signal has a signal edge corresponding to the transmission period of each access address input before the failure edge of the first enable signal; and the step of sequentially buffering the at least one access address includes: buffering the corresponding access address in response to the signal edge of the address input signal.

[0033] The aforementioned optional features may be combined with any of the first to second aspects of this disclosure as needed, and / or combined arbitrarily with each other.

[0034] Therefore, this disclosure proposes a novel memory control method for memory that uses multiplexed data / address lines for the access interface. This method can rewrite the mode register in real time when an access instruction is issued to change the mode configuration of the current access operation, thereby adapting to complex and ever-changing mode requirements and improving read / write efficiency and data bandwidth. At the same time, the solution of this disclosure can also perform read / write operations on multiple sets of addresses in one access instruction operation, thereby adapting to complex and ever-changing addressing requirements and improving read / write efficiency and data bandwidth. Attached Figure Description

[0035] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0036] Figure 1 An exemplary compositional diagram of a memory according to some embodiments of the present disclosure is shown.

[0037] Figure 2 A timing diagram illustrating an operational example of an access format according to some embodiments of the present disclosure is shown.

[0038] Figure 3 An exemplary compositional diagram of a controller according to some embodiments of the present disclosure is shown.

[0039] Figure 4 Another exemplary component diagram of a controller according to some embodiments of the present disclosure is shown.

[0040] Figure 5 Exemplary timing diagrams of various signals involved in a write operation according to some embodiments of the present disclosure are shown.

[0041] Figure 6 Exemplary timing diagrams of various signals involved in a controller during a read operation according to some embodiments of the present disclosure are shown.

[0042] Figure 7 Another exemplary timing diagram of the signals involved in a write operation according to some embodiments of the present disclosure is shown.

[0043] Figure 8 Another exemplary timing diagram of the signals involved in the controller during a read operation according to some embodiments of the present disclosure is shown.

[0044] Figure 9 An exemplary compositional schematic diagram of an input pointer generation unit according to some embodiments of the present disclosure is shown.

[0045] Figure 10 An exemplary circuit diagram of an input pointer generation unit according to some embodiments of the present disclosure is shown.

[0046] Figure 11 An exemplary timing diagram is shown of the signals involved in the input pointer generation unit during a write operation according to some embodiments of the present disclosure.

[0047] Figure 12 An exemplary circuit diagram of a read / write status generation unit according to some embodiments of the present disclosure is shown.

[0048] Figure 13 An exemplary compositional schematic diagram of an output pointer generation unit according to some embodiments of the present disclosure is shown.

[0049] Figure 14 An exemplary circuit diagram of an output pointer generation unit according to some embodiments of the present disclosure is shown.

[0050] Figure 15 An exemplary timing diagram is shown of the signals involved in the output pointer generation unit during a write operation according to some embodiments of the present disclosure.

[0051] Figure 16 An exemplary timing diagram is shown of the signals involved in the output pointer generation unit during a read operation according to some embodiments of the present disclosure. Detailed Implementation

[0052] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0053] Typically, in a PSRAM interface, the data lines and command / address lines are fully or at least partially multiplexed (e.g., as described later). Figure 1 The A / DQ lines shown transmit both data and instructions / addresses. Therefore, a conventional PSRAM can only access one row of addresses at a time. If access to other rows is required, the chip select CS# signal must be pulled high, and the read / write instruction must be resent after a certain time (the chip select time, i.e., the minimum time CS# must be held high). Then, the read / write delay time must be waited before the next data read / write operation can proceed.

[0054] However, current PSRAM applications are increasingly demanding in terms of address access requirements, such as accessing multiple rows / columns at once. Conventional PSRAM requires multiple access instructions to perform operations on multiple sets of addresses, each requiring waiting time for chip select and corresponding access latency. Therefore, this instruction format is inefficient for complex requirements like accessing multiple rows / columns at once, impacting access performance.

[0055] Furthermore, the configuration of chip modes in PSRAM is becoming increasingly variable and complex, with frequent and complex mode requirements occurring within a short period. Conventional PSRAM uses a separate mode register rewrite instruction to modify the mode register before each access operation, thereby changing the mode configuration. However, using the mode register rewrite instruction also requires waiting for chip select time and read / write latency. If the mode requirements for each access operation are different, a mode register rewrite instruction must be sent before each access operation to modify the mode, incurring chip select time and read / write latency each time. This reduces read / write efficiency, impacts device performance, and makes it difficult to adapt to complex and variable read / write mode requirements.

[0056] Therefore, this disclosure proposes a novel memory control method for memories with multiplexed data / address lines in the access interface. This method can rewrite the mode register in real-time when an access instruction is issued, thereby changing the mode configuration of the current access operation. Compared to existing technologies, this solution eliminates the need for frequent mode rewriting by sending separate mode register rewrite instructions. Instead, the required mode is configured in real-time with each access instruction, thus adapting to complex and variable mode requirements and improving read / write efficiency and data bandwidth. Furthermore, this solution supports reading and writing multiple addresses within a single access instruction operation. Therefore, compared to existing technologies, it eliminates the need to wait for redundant chip select time and read / write latency to complete multiple address read / write operations, thereby adapting to complex and variable addressing requirements and improving read / write efficiency and data bandwidth. In this document, unless otherwise stated, "access" refers to reading and writing data in the memory array, excluding reading and writing other components in the memory, such as mode registers.

[0057] The following section will use a PSRAM employing an SPI (Serial Peripheral Interface) interface as an example to describe the technical solution of this disclosure in detail. However, those skilled in the art will understand that this disclosure is not limited to this, but can also be applied to various memories with the same or similar access interfaces (such as SPI interfaces or similar data / address line multiplexing interfaces), such as SRAM, DRAM, or flash. In this document, "SPI interface" refers to an access interface using the SPI protocol (including various extended protocols, such as multi-IO SPI protocols, including QSPI, OSPI, xSPI protocols, etc.).

[0058] Figure 1 An exemplary compositional schematic diagram of a memory according to some embodiments of the present disclosure is shown. Figure 2 The present disclosure illustrates some embodiments of the proposed method. Figure 1 A timing diagram of a single access operation example of the memory access format.

[0059] like Figure 1 As shown, the memory 100 includes a memory array 110, an access interface 120 for external access to the memory array, a mode register 130, and a controller 140, wherein the access interface 120 includes at least one data / address multiplexed line A / DQ for time-division multiplexing of data and address transmission.

[0060] Figure 1The access interface 120 can use the SPI protocol to communicate with an external host. The SPI protocol in this disclosure can include various versions, such as single-port, dual-port, 4-port, or 8-port SPI protocols; here, "single-port, dual-port, 4-port, or 8-port" refers to the number of data / address multiplexed lines (A / DQ) being 1, 2, 4, or 8 (also referred to as A / DQ lines being 1 bit wide, 2 bit wide, 4 bit wide, or 8 bit wide), thus allowing for the parallel transmission of 1, 2, 4, or 8 bits of data / address data. The following description uses an 8-port SPI (A / DQ transmitting 1 byte, or 8 bits, in parallel each time) as an example to illustrate various embodiments of this disclosure. However, those skilled in the art will understand that the technical solutions of this disclosure are not limited to the number of bits, nor are they limited to the SPI protocol. The embodiments of this disclosure are also applicable to other data and address multiplexed access interfaces 120. In general, the number of A / DQ lines is 2... N Output or input 2 via A / DQ line in each clock cycle N Bit or 2 N+1 Data, instructions, or addresses in bits (where, if access interface 120 uses SDR (Single Data Rate) timing, then A / DQ transmits 2 bits per clock cycle). N If access interface 120 uses DDR (Double Data Rate) timing, then A / DQ transmits 2 bits per clock cycle. N+1 (bits), where N is a non-negative integer. Additionally, in some embodiments, besides the data / address multiplexing lines A / DQ, the access interface 120 may also include other transmission lines to transmit a portion of data or an address separately; for example, the access interface 120 may also include separate address lines to transmit the address in parallel with the data / address multiplexing lines A / DQ.

[0061] In some implementations, such as Figure 1As shown, in addition to a set of 8 data / address multiplexed lines A / DQ, the access interface 120 may also include a clock line CLK, a chip select line CS, and a transmission line DQS for implementing the 8-port SPI protocol. The DQS line can be used to output a signal for synchronously sampling the read data output on the A / DQ lines during a read operation, and / or to input a signal for masking the write data received on the A / DQ lines during a write operation. When the host performs an access operation (read / write operation) on the memory 100, the host can output a clock signal CLK to the memory via the clock line to control the signal transmission timing, pull down the CS# signal on the chip select line to select the memory, and exchange instructions, addresses, and data related to the read / write operation with the memory via the A / DQ lines. Furthermore, during a read operation, the memory can use the signal on the DQS line to ensure that the host correctly obtains the read data; while during a write operation, the host can use the signal on the DQS line to mask some of the input data so that it is not written to the corresponding address, thus providing the user with a more flexible writing method. It is understood that the access interface according to the embodiments of this disclosure is not limited to the transmission line configuration shown in the figure, but may include transmission lines for other purposes not shown as needed.

[0062] Since the instructions, addresses, and data in each access operation are transmitted using the same A / DQ lines, a specific access format is required for transmission in order to facilitate the memory in distinguishing the transmitted instructions, addresses, and data. A controller 140 matching this access format is then set up to control the memory access operation accordingly.

[0063] The access format according to the embodiments of this disclosure is as follows: Figure 2 As illustrated in the timing diagram, after the start of an access operation, the access command, mode configuration value, and at least one access address can be received sequentially via the data / address multiplexer (A / DQ). Figure 2 The DQ signal in the memory transmits WR, MR, and three access addresses RA0+CA0, RA1+CA1, and RA2+CA2 sequentially. As will be detailed later, the controller 140 sets the mode register 130 based on the received mode configuration value MR, and the cache unit 142 sequentially caches the received at least one access address, and outputs the at least one access address to the memory array 110 sequentially at a specified time. Therefore, embodiments of this disclosure can configure the required mode in real time during each access operation, thereby flexibly and efficiently implementing the mode configuration of the current access operation and correspondingly improving the memory read efficiency. Furthermore, embodiments of this disclosure can also perform accesses to multiple random access addresses, thereby significantly improving the memory read efficiency.

[0064] Those skilled in the art will understand that Figure 2 The “WR” in the diagram is just an example; it represents a write instruction value in the access instruction CMD and is used to initiate a write operation. In subsequent diagrams, “RD” can also be used to represent a read instruction value in the access instruction CMD and is used to initiate a read operation.

[0065] The following is combined Figure 2 The timing diagram is provided to illustrate the above access format in more detail. Those skilled in the art will understand that many of the details described below are illustrative for the sake of completeness and are not intended to limit the technical solutions of this disclosure.

[0066] like Figure 2 As shown, first, the chip enable signal CS# is pulled low (for this signal, a low level indicates validity, and a high level indicates invalidity) to begin an access operation. Then, the clock signal CLK is input on the clock line, and the write instruction WR, the mode configuration value MR, and three access addresses RA0+CA0, RA1+CA1, and RA2+CA2 are sequentially input on the A / DQ lines, where "RA" represents the row address and "CA" represents the column address.

[0067] In all the examples of this disclosure, the data transmission on the A / DQ line uses DDR timing, that is, DQ can be sent on both the rising and falling edges of CLK. However, those skilled in the art will understand that the embodiments of this disclosure are not limited to DDR timing, and SDR timing can also be used, that is, data is sent only once on the rising or falling edge of one clock cycle.

[0068] Those skilled in the art will understand that Figure 2 The number of access addresses entered is merely an example and can be set as needed. For instance, the number of access addresses to be entered can be determined by the access command, or a fixed number can be preset, and so on.

[0069] Furthermore, this disclosure notes that, as previously described, the DQS signal on a conventional transmission line DQS is idle before transmitting read / write data. Therefore, in some embodiments, the DQS signal can be used to determine the number of access addresses to be input, thereby improving the utilization efficiency of the interface. For example, as... Figure 2 As shown, the end of the access address input can be determined by the first falling edge of the DQS signal after the start of the access operation. Alternatively, the end of the access address input can also be determined similarly by the first rising edge or pulse of the DQS signal after the start of the access operation.

[0070] Accordingly, in order to achieve the control of the access address input by the DQS signal mentioned above, Figure 1The controller 140 can be configured to generate an address input signal based on a DQS signal (hereinafter also referred to as a "first enable signal") input via the transmission line DQS, having signal edges corresponding to the transmission periods of each access address input before the failure edge of the first enable signal, and sequentially buffering the corresponding access addresses in response to the signal edges of the address input signal.

[0071] like Figure 2 As shown, after a preset access delay following the input of the access address, data D0 to be written to the first access address RA0+CA0 is input. At this point, the burst length is set to 16 bytes, so 16 bytes of data B0-B15 are input consecutively. In some implementations, the burst length for each address can be set via a mode register, or a uniform burst length can be set. Simultaneously with the transmission of each write data, a signal can be input on the DQS line to shield part of the write data. Immediately after data D0, data D1 and D2 to be written to the second and third access addresses are input sequentially, each also comprising 16 bytes of data B0-B15. Then, the chip enable signal CS# is pulled high, ending the access operation.

[0072] Those skilled in the art will understand that Figure 2 The access latency shown is merely an example and can be set as needed. For example, the access latency can be a pre-set fixed value, or it can be set by the mode register, or it can be determined by the input instruction value, such as the latency for a read instruction being different from the latency for a write instruction.

[0073] From the above, we can conclude that Figure 2 An exemplary access sequence representing the access format in the sequence diagram can be expressed as:

[0074] CMD+MR+RA0+CA0+…+RAn+CAn+Waiting for access delay+D0+…+Dn

[0075] Where “CMD” represents the access instruction, “MR” represents the mode configuration value, “RA0” to “RAn” represent the row addresses of the n+1 access addresses respectively, “CA0” to “CAn” represent the column addresses of the n+1 access addresses respectively, and “D0” to “Dn” represent the read or write data corresponding to the n+1 access addresses respectively, where n≥0.

[0076] Those skilled in the art will understand that Figure 2 The access instruction format is not intended to limit the scheme disclosed herein. Figure 2The access instruction format can also have various variations. For example, it can wait for a certain number of clock cycles between the transmission of each two adjacent sets of data in D0 to Dn, or it can wait for the access delay without waiting in some cases where the burst length is large enough, and so on.

[0077] Through design Figure 1 The controller 140 controls the memory 100 to perform access operations with the access format described above.

[0078] Back Figure 1 ,like Figure 1 As shown, the controller 140 includes a decoding unit 141 and a buffer unit 142. The decoding unit 141 is used to decode the signals (DQS, CLK, CS#, and DQ) received via the access interface 120 and generate corresponding control signals MRS and PNT for the mode register 130 and the buffer unit 142, respectively, so that the mode configuration value (e.g., ...) in the DQ signal input via the A / DQ line is used to... Figure 2 The MR) setting mode register 130 and the control buffer 142 sequentially buffer each access address (e.g., ...) in the DQ signal input via the A / DQ line. Figure 2 The cache unit 142 controls the cached access address ADRs to be output sequentially to the storage array 110 at a specified time so that each access address can be read and written sequentially.

[0079] Although Figure 1 Although not shown, it is understood that in some embodiments, a row / column decoder may be included inside or outside the memory array 110 to receive the access address ADR and decode its row address (RA) and column address (CA) respectively, thereby opening the word line WL corresponding to the row address and the bit line BL corresponding to the column address, thereby performing corresponding read / write operations on the memory cells selected by the opened WL and BL in the memory array 110. Additionally, Figure 1 The control signal PNT in this context is only a general illustration and does not refer to a single control signal. As will be detailed later, the control signal PNT of the decoder 141 to the buffer 142 may include multiple or multiple sets of signals as needed, such as one or more address input signals and one or more address output signals.

[0080] In some implementations, the buffer 142 can be a first-in, first-out (FIFO) buffer, whereby access addresses can be stored and output sequentially in the order they are input on the A / DQ line during a single access operation, thereby maintaining the order in which data is read or written via the A / DQ line is consistent with the order in which addresses are received. The depth of the buffer can be set as needed (e.g., the maximum number of addresses supported in a single access operation).

[0081] In some implementations, each access address consists of RA+CA consecutively input on the A / DQ line. The RA and CA of each access address can be stored together in one storage unit of the cache section 142, or the RA and CA of each access address can be stored separately in two storage units of the cache section 142. As shown in subsequent figures, in some implementations, the cache section 142 may include two FIFO buffers, namely a row address FIFO buffer and a column address FIFO buffer, used to sequentially cache the RA and CA of each access address, thereby enabling simpler and more convenient caching and output of multiple access addresses.

[0082] In some implementations, the mode configuration value in the DQ signal input via the A / DQ line is the mode register value corresponding to the mode used in this access operation. Therefore, the control signal MRS mentioned above is the same as the mode configuration value in the DQ signal input via the A / DQ line. That is, the decoding unit 141 inputs the received mode configuration value into the mode register 130 so as to update the value of the mode register 130 to the mode configuration value, thereby enabling the mode required for this access operation to be set simply and quickly.

[0083] In some implementations, to further improve access speed, the cache unit 142 can output the cached access addresses at different times based on the difference between read and write operations. Therefore, in some examples, the decoding unit 141 can also be configured to generate a read enable signal or a write enable signal based on the access instruction in the DQ signal input via the A / DQ line, and control the cache unit 142 to sequentially output the cached access addresses at specified times based on the read enable signal or the write enable signal. For example, when the access instruction is a read instruction, the read enable signal can be pulled high (i.e., the signal is enabled), and the cache unit 142 is controlled to start outputting the access addresses sequentially after caching the first access address, based on the pulled read enable signal; while when the access instruction is a write instruction, the write enable signal can be pulled high (i.e., the signal is enabled), and the cache unit 142 is controlled to wait for a preset clock cycle before starting to output the access addresses sequentially.

[0084] In some implementations, in order to achieve Figure 2The DQS signal shown controls the access address input. The decoding unit 141 can generate an address input signal based on the DQS signal as part of the control signal PNT for the buffer unit 142. The address input signal has a signal edge corresponding to the transmission period of each access address input before the failure edge of the DQS signal, and the buffer unit 142 is configured to buffer the corresponding access address in response to the signal edge of the address input signal.

[0085] The signal edges mentioned above include edges where the signal level changes at any point, such as rising edges, falling edges, active edges, and inactive edges. Appropriate edges can be selected as the signal edges defined above according to the actual circuit requirements. An active edge refers to the edge where the signal changes from inactive (also called "de-enabled") to active (also called "enabled"), and an inactive edge refers to the edge where the signal changes from active to inactive. For example, in the case where a signal is inactive at low levels and active at high levels, the active edge of this signal is a rising edge, and the inactive edge is a falling edge.

[0086] A suitable address input signal can be designed based on the circuit configuration of the buffer unit 142. For example, it can be a single-bit signal, a multi-bit signal indicating the input order of the current access address, or a group of single-bit signals, each signal in the group indicating an input access address. Regardless of the type of address input signal used, the decoding unit 141 can be configured accordingly to change the address input signal during the transmission period of each access address input before the failure edge of the DQS signal, thereby generating a signal edge, so that the buffer unit 142 buffers the corresponding access address according to the signal edge.

[0087] In some implementations, the row address and column address in the access address are cached separately, thereby allowing for separate row address input signals and column address input signals to be set for the row address and column address respectively, which generate signal edges during the transmission periods of the row address and column address; for example, the address input signals mentioned above may include a group of row address input signals and a group of column address input signals, wherein each row address input signal or column address input signal has a signal edge corresponding to the transmission period of the row address or column address in each access address input before the failure edge of the DQS signal.

[0088] Those skilled in the art will understand that Figure 1 The internal circuitry of the memory 100 shown is a simplified block diagram drawn only to illustrate the basic operations involved in the control method of the memory proposed in the embodiments of this disclosure, and other components / modules may be omitted and not shown.

[0089] The construction and specific implementation circuitry of the controller according to embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. The specific implementation circuitry in the following embodiments is designed for DDR timing; however, those skilled in the art, guided by this disclosure, will readily understand that simple adaptive modifications can be made to these specific circuits to suit SDR timing.

[0090] Figure 3 An exemplary compositional diagram of a controller according to some embodiments of the present disclosure is shown.

[0091] like Figure 3 As shown, the controller 300 includes a decoding unit 310 and a FIFO buffer 320 that serves as the aforementioned buffer unit.

[0092] The decoding unit 310 includes an input pointer generation unit 311, an output pointer generation unit 312, a read / write status generation unit 313, and a register REG1.

[0093] The input pointer generation unit 311 is configured to receive a chip enable signal CS# input via the chip select line, a first clock CLK input via the clock line, and a first enable signal DQS input via the DQS transmission line. Based on the first enable signal DQS, the chip enable signal CS#, and the first clock CLK, it generates an access instruction enable signal CMD_LATEN, a mode configuration enable signal MRS_LATEN, and an address input signal INPNT (these generated signals can also be collectively referred to as "input pointer signals"). The access instruction enable signal CMD_LATEN has a signal edge corresponding to the transmission period of the access instruction CMD, the mode configuration enable signal MRS_LATEN has a signal edge corresponding to the transmission period of the mode configuration value MR, and the address input signal INPNT has a signal edge corresponding to the transmission period of each access address input before the failure edge of the DQS signal. Therefore, based on the access instruction enable signal CMD_LATEN, the mode configuration enable signal MRS_LATEN, and the address input signal INPNT, the access instruction CMD, the mode configuration value MR, and each access address transmitted sequentially in the DQ signal can be correctly obtained.

[0094] In some embodiments, the input pointer generation unit 311 may also generate a pulse as a reset signal RST in response to the rising edge of the CS# signal, and provide the reset signal RST to the output pointer generation unit 312 and the read / write status generation unit 313, thereby enabling the decoding unit 310 as described above. Figure 2As shown, after the CS# signal is raised, the current access operation ends and the system returns to its initial state, awaiting the next access operation. Those skilled in the art will understand that this reset signal RST can also be generated by the output pointer generation unit 312 and / or the read / write status generation unit 313 and output to other units.

[0095] In addition, such as Figure 3 As shown, the data input terminal of register REG1 receives the DQ signal, which can also be described as its coupling to... Figure 1 The data / address multiplexed line A / DQ shown has the clock input of register REG1 configured with the receive mode enable signal MRS_LATEN, and the data output of register REG1 outputs the MRS signal. This can also be described as its coupling to... Figure 1 The mode register 130 is shown. Thus, in response to the signal edge of MRS_LATEN, register REG1 updates its output MRS to the mode configuration value MR that is currently being transmitted on the A / DQ line.

[0096] In addition, such as Figure 3 As shown, the read / write state generation unit 313 is configured to obtain the access instruction CMD transmitted in the DQ signal according to the access instruction enable signal CMD_LATEN, and generate and output the read enable signal RD_ACCEN and the write enable signal WR_ACCEN to the output pointer generation unit 312 based on the access instruction CMD.

[0097] In addition, such as Figure 3 As shown, the output pointer generation unit 312 is configured to receive the first clock CLK, the read enable signal RD_ACCEN and the write enable signal WR_ACCEN, and generate the address output signal OUTPNT based on these three signals, which has signal edges that respectively indicate the output time of each access address cached by the FIFO buffer 320.

[0098] In some implementations, as will be detailed later, the determination of the output time of each access address also depends on the total number of input access addresses and the buffering time of the first access address. Thus, the input pointer generation unit 311 can also be configured to generate a signal INP_CNT indicating the total number of access addresses input in this access operation and a signal A0_INPNT indicating the buffering of the first access address, and output both to the output pointer generation unit 312 for generating the address output signal OUTPNT.

[0099] In addition, such as Figure 3As shown, the FIFO buffer 320 receives the DQ signal, the address input signal INPNT, and the address output signal OUTPNT, and is configured to buffer the corresponding access address currently being transmitted in the DQ signal in response to each signal edge of the address input signal INPNT, and to sequentially output the corresponding access address as the ADR signal in response to each signal edge of the address output signal OUTPNT. Figure 1 The storage array 110 shown.

[0100] In some implementations, each access address consists of RA+CA continuously input on the A / DQ line. RA and CA in each access address can be stored together in one storage unit of the FIFO buffer 320 and output together, or RA and CA in each access address can be stored separately in two storage units of the FIFO buffer 320 and output sequentially as the signal ADR.

[0101] Figure 4 Another exemplary component diagram of a controller according to some embodiments of the present disclosure is shown, which can be regarded as Figure 3 A variant of the controller.

[0102] and Figure 3 Compared to the controller 300, Figure 4 The main difference of the controller 400 is that the cache unit 420 uses two FIFO caches, namely the row address FIFO cache 421 and the column address FIFO cache 422, which respectively cache the RA and CA in each access address. The input pointer generation unit 411 generates and outputs two sets of address input signals, namely the row address input signal set RA0_INPNT to RAn_INPNT (n=3 in this example) and the column address input signal set CA0_INPNT to CAn_INPNT. The output pointer generation unit 412 generates and outputs a set of access address output signals A0_OUTPNT to An_OUTPNT, and the row address FIFO cache 421 and the column address FIFO cache 422 respectively respond to the set of access address output signals and output their respective row address RA and column address CA.

[0103] Furthermore, correspondingly, in some of the above embodiments, the signals INP_CNT and A0_INPNT generated by the input pointer generation unit 311 are changed to Figure 4The input pointer generation unit 411 generates a signal CA_INP_CNT indicating the total number of column addresses input in this access operation and a signal CA0_INPNT indicating the cached first column address. Those skilled in the art will understand that the aforementioned signal CA_INP_CNT can also be changed to a signal RA_INP_CNT indicating the total number of row addresses input in this access operation; these two are equal and can be arbitrarily selected according to the actual circuit design.

[0104] Specifically, each row address input signal RA0_INPNT to RAn_INPNT in the aforementioned row address input signal group has a signal edge corresponding to the transmission period of the row address in each access address sequentially input before the failure edge of the DQS signal. The number of each row address input signal can indicate the input order of its corresponding row address and its corresponding storage location in the row address FIFO buffer 421. Similarly, each column address input signal CA0_INPNT to CAn_INPNT in the column address input signal group has a signal edge corresponding to the transmission period of the column address in each access address sequentially input before the failure edge of the DQS signal. The number of each column address input signal can indicate the input order of its corresponding column address and its corresponding storage location in the column address FIFO buffer 422. Similarly, each access address output signal A0_OUTPNT to An_OUTPNT in the access address output signal group has a signal edge indicating the time when the row address FIFO buffer 421 and the column address FIFO buffer 422 output the row address and column address respectively. The number of each access address output signal can indicate the output order of the row address and column address in its corresponding access address, as well as the corresponding storage location in the row address FIFO buffer 421 and the column address FIFO buffer 422. The row address and column address in each access address can be output simultaneously, so the access address output signals A0_OUTPNT to An_OUTPNT are shared by the row address FIFO buffer 421 and the column address FIFO buffer 422. By using multiple sets of address input / output signals as described above, it is possible to effectively distinguish and locate the elements entering and exiting the FIFO buffers.

[0105] Figure 4 The rest of the ones Figure 3 The parts that are the same as those in the controller will not be described again here.

[0106] The following is combined Figures 5 to 8 To describe using timing diagrams Figure 4 Here are some examples of how the controller operates.

[0107] Figure 5 and Figure 6Exemplary timing diagrams are shown for the signals involved in the controller 400 during write and read operations according to some embodiments of this disclosure when three access addresses are input. Figure 7 and Figure 8 Another exemplary timing diagram is shown for the signals involved in the controller 400 during write and read operations according to some embodiments of the present disclosure when an access address is input.

[0108] like Figure 5 As shown, Figure 5 The write operation adopted the same as Figure 2 The same access format, i.e. Figure 5 The timing of the four signals CLK, CS#, DQS, and DQ transmitted through the access interface and Figure 2 The same applies, so I won't repeat it here.

[0109] Figure 5 The signals CMD_LATEN, MRS_LATEN, RA0_INPNT, CA0_INPNT, RA1_INPNT, CA1_INPNT, RA2_INPNT, and CA2_INPNT generated by the input pointer generation unit 411 are shown to each have a pulse of one and a half clock cycles. These pulses originate from the rising / falling edge of the clock CLK corresponding to the sequentially input write instruction WR, mode configuration value MR, and the respective transmission periods of row / column addresses RA0, CA0, RA1, CA1, RA2, and CA2. Those skilled in the art will understand that the pulse width of each of the generated signals is not limited to half a clock cycle, but can be set according to the actual circuit. For example, in some embodiments, subsequent circuits only use the rising edge of these signals to trigger corresponding operations; in this case, the pulse width has no effect on the operation of subsequent circuits and can be set as needed.

[0110] In response to the rising edge of each row / column address input signal, the row address FIFO buffer 421 and the column address FIFO buffer 422 respectively buffer the corresponding row address and column address being transmitted in the DQ signal in the corresponding positions.

[0111] In addition, such as Figure 5 As shown, in response to the rising edge of CMD_LATEN, the read / write state generation unit 413 obtains the write instruction WR being transmitted in the DQ signal, and enables the write enable signal WR_ACCEN in response to the write instruction WR, and only resets the write enable signal WR_ACCEN when CS# is pulled high to end the current access operation.

[0112] In addition, such as Figure 5As shown, in response to the rising edge of MRS_LATEN, the output signal MRS is updated from its previous value to the mode configuration value MR currently being transmitted in the DQ signal, i.e., the new MRS value. This updated MRS value can be retained and does not need to be reset even when CS# is pulled high to end the current access operation.

[0113] In addition, such as Figure 5 As shown, the access address output signal A0_OUTPNT generated by the output pointer generation unit 412 is enabled after a period of time following the completion of the access address input and remains enabled for half a clock cycle. Then, according to the burst length, subsequent access address output signals A1_OUTPNT and A2_OUTPNT are periodically enabled sequentially and each remains enabled for half a clock cycle. In this example, the burst length is 16, and DDR timing is used, so there is an 8-clock-cycle interval between every two access address output signals, thus maintaining consistency with the transmission of write data in DQ. Figure 5 The relationship between the enable time of the first access address output signal A0_OUTPNT and the start time of the transmission of the first data D0 shown is merely exemplary. In practical applications, the relationship between the two can be set as needed.

[0114] In response to the rising edge of each access address output signal, the row address FIFO buffer 421 and the column address FIFO buffer 422 output each row address and each column address sequentially, as follows: Figure 5 The signals RA and CA are shown in the figure.

[0115] Figure 6 The read operation shown is the same as the one described above. Figure 5 The main difference in write operations is that... Figure 6 The access instruction input through the access interface is a read instruction RD instead of a write instruction WR. In response to the read instruction RD, the read enable signal RD_ACCEN is enabled instead of the write enable signal WR_ACCEN. The enable time of the first access address output signal A0_OUTPNT is advanced to the rising edge immediately following the first column address input signal CA0_INPNT, and the enable time of subsequent access address output signals is also advanced accordingly.

[0116] Figure 6 The remaining operations and Figure 5 Similar or identical items will not be elaborated upon here.

[0117] Figure 7 The write operation shown is the same as described above. Figure 5 The main difference in write operations is that in this write operation, only an access address and its corresponding set of write data D0 are input. Therefore, from... Figure 7It can be seen that only the input / output signals related to the first access address, namely the first row address input signal RA0_INPNT, the first column address input signal CA0_INPNT, and the first access address output signal A0_OUTPNT, are enabled, while the subsequent row address input signals, column address input signals, and access address output signals are inactive and remain in an invalid state.

[0118] Similarly, Figure 8 The read operation shown is the same as the one described above. Figure 6 The main difference in the read operation is that in this read operation, only one access address is input and only one set of corresponding read data D0 is output. Therefore, from... Figure 8 It can be seen that only the input / output signals related to the first access address, namely the first row address input signal RA0_INPNT, the first column address input signal CA0_INPNT, and the first access address output signal A0_OUTPNT, are enabled, while the subsequent row address input signals, column address input signals, and access address output signals are inactive and remain in an invalid state.

[0119] The following will combine Figures 9 to 16 To describe in more detail Figure 4 The specific composition of the controller.

[0120] Figure 9 It shows Figure 4 A schematic diagram of an example of the input pointer generation unit in the diagram.

[0121] like Figure 9 As shown, the input pointer generation unit 900 includes a first counting clock generation unit 910 and a first counting output unit 920. Optionally, the input pointer generation unit 900 may also include a pulse generator 930 for generating a reset signal RST.

[0122] The first counting clock generation unit 910 is configured to receive a first enable signal DQS, a chip enable signal CS#, and a first clock CLK, and generate a first counting clock CAIN_CK based on these three signals. The first counting clock CAIN_CK has a clock signal synchronized with the first clock only between the active edge of the chip enable signal CS# and the inactive edge of the first enable signal DQS.

[0123] The first counting output unit 920 is configured to count on the rising and / or falling edges of the first counting clock CAIN_CK, and in response to the results of each count, sequentially enable the access instruction enable signal CMD_LATEN, the mode configuration enable signal MRS_LATEN, and the respective row address input signals RA0_INPNT+CA0_INPNT to RAN_INPNT+CAn_INPNT (n=2 in this example). Additionally, in some embodiments, the first counting output unit 920 may optionally generate a signal CA_INP_CNT or RA_INP_CNT indicating the total number of column addresses or row addresses input in this access operation and output it to the output pointer generation unit.

[0124] When DDR transmission timing is used on the A / DQ line, the first counting output unit 920 counts both the rising and falling edges of the first counting clock CAIN_CK. However, when SDR transmission timing is used on the A / DQ line, only the edge involving data transmission between the rising and falling edges of the first counting clock CAIN_CK is counted.

[0125] thus, Figure 9 The input pointer generation unit can easily and effectively generate various signals that indicate the transmission periods of CMD, MR and each access address RA+CA transmitted sequentially on the A / DQ line.

[0126] Figure 10 The following diagram illustrates the implementation. Figure 9 An exemplary circuit diagram of an input pointer generation unit, Figure 11 This shows the write operation. Figure 10 An exemplary timing diagram of the signals involved in the input pointer generation unit. Those skilled in the art will understand that... Figure 10 The circuit details in the following figures are merely exemplary and can be easily modified in various ways to achieve the same function under the teachings of this disclosure, all of which are within the scope of the claims of this disclosure.

[0127] like Figure 10 As shown, the input pointer generation unit 1000 includes a first counting clock generation unit 1010 and a first counting output unit 1020.

[0128] The first counting clock generation unit 1010 includes a pulse generator PUL2, a pulse generator PUL3, an SR latch SR1, and an AND gate AND1.

[0129] Pulse generator PUL2 receives the chip enable signal CS# and is triggered by its active edge to generate a pulse, while pulse generator PUL3 receives the first enable signal DQS and is triggered by its inactivation edge to generate a pulse. Since in this example, both the active edge of CS# and the inactivation edge of DQS are falling edges, therefore... Figure 10 As shown in the diagram, pulse generators PUL2 and PUL3 are both falling-edge triggered pulse generators.

[0130] The set input S of the SR latch SR1 receives the output of the pulse generator PUL2, its reset input R receives the output of the pulse generator PUL3, and its non-inverting output Q is coupled to one input of the AND gate AND1 (this input signal is marked "CAIN_EN" in the figure). The other input of the AND gate AND1 receives the first clock CLK, and the output of the AND gate AND1 is the first counting clock CAIN_CK.

[0131] However, the coupling relationship of SR latch SR1 is not limited to... Figure 10 As shown. Given the characteristics of the SR latch, the above... Figure 10 The set terminal S and the reset terminal R of the SR latch SR1 are interchanged, and the inverted output terminal is... It can also achieve the same circuit function when coupled to one input of the AND gate AND1.

[0132] Therefore, the coupling relationship of SR latch SR1 can be summarized as follows: the set terminal S of SR latch SR1 receives one of the outputs of pulse generator PUL2 and pulse generator PUL3, its reset terminal R receives the other of these two outputs, and one of its two output terminals is coupled to one input terminal of AND gate AND1.

[0133] In addition, such as Figure 10 As shown, the first counting output unit 1020 includes counters CNT1 and CNT2, one-hot decoders HOT1 and HOT2, a first set of AND gates AND11-AND14, and a second set of AND gates AND21-AND24. The first counting output unit 1020 may also include an inverter INV1 for inverting the first counting clock CAIN_CK.

[0134] The clock input of counter CNT1 receives the first counting clock CAIN_CK, and the clock input of counter CNT2 receives the inverted signal of the first counting clock CAIN_CK. Since both counters CNT1 and CNT2 are triggered by the falling edge, they count the falling edge of the first counting clock CAIN_CK and the falling edge of its inverted signal (i.e., the rising edge of the first counting clock CAIN_CK) respectively.

[0135] The one-hot decoder HOT1 receives the counting result RA_INPNT_CNT from the counter CNT1 and outputs the first set of one-hot decoded signals (RACNT000, RACNT001, RACNT010, RACNT100, etc.).

[0136] For example, when RA_INPNT_CNT[2:0] = 3'b000, RACNT000 is enabled; when 3'b001, RACNT001 is enabled; when 3'b010, RACNT010 is enabled; when 3'b011, RACNT100 is enabled, and so on. It can be understood that the one-hot decoded signal corresponding to the counting result RA_INPNT_CNT[2:0] can have a maximum of 8 values. Figure 10 The example only uses the first 4, but this number is merely exemplary. The embodiments of this disclosure may select the required number of one-hot decoded signals based on the number of input pointer signals that need to be generated subsequently.

[0137] The first set of AND gates AND11-AND14 receive the first set of one-hot decoded signals and the first counting clock CAIN_CK, respectively, and output the access instruction enable signal CMD_LATEN and the input signals for each row address (RA0_INPNT, RA1_INPNT, RA2_INPNT, etc.). That is, the first set of AND gates corresponds one-to-one with the first set of one-hot decoded signals. Each of the first set of AND gates is used to AND one of the first set of one-hot decoded signals with the first counting clock CAIN_CK to obtain the input pointer signal at the corresponding position.

[0138] Similarly, the one-hot decoder HOT2 receives the counting result CA_INPNT_CNT from the counter CNT2 and outputs the second set of one-hot decoded signals (CACNT000, CACNT001, CACNT010, CACNT100, etc.).

[0139] The second set of AND gates AND21-AND24 receive the second set of one-hot decoded signals and the inverted signal of the first counting clock CAIN_CK, respectively, and output the mode configuration enable signal MRS_LATEN and the column address input signals (CA0_INPNT, CA1_INPNT, CA2_INPNT, etc.).

[0140] Alternatively, the input pointer generation unit 1000 may further include a pulse generator PUL4 for generating a reset signal RST, configured to generate a pulse triggered by the failure edge of the chip enable signal CS#, and its output is coupled to the reset terminal of counter CNT1 and the set terminal of counter CNT2. Figure 10In the example, the pulse generator PUL4 is a rising edge triggered pulse generator. Therefore, when CS# is pulled high to end the current access operation, the reset signal RST is activated, thereby resetting the counter CNT1 and setting the counter CNT2.

[0141] refer to Figure 11 The timing diagram clearly shows Figure 10 The circuit's operation process. This is understandable, although... Figure 11 The example illustrates the write operation process, but for... Figure 10 The timing of the signals generated during the read operation is the same as that during the write operation.

[0142] Figure 11 The timing of the four signals CLK, CS#, DQS, and DQ transmitted through the access interface and Figure 5 The same applies, so I won't repeat it here.

[0143] like Figure 11 As shown, pulling CS# low causes pulse generator PUL2 to generate a pulse, which sets SR latch SR1, thus making the output high, that is, signal CAIN_EN is enabled. Thus, the clock signal of CLK can be transformed into clock CAIN_CK through AND gate AND1.

[0144] The falling edge of the clock CAIN_CK triggers the counter CNT1 to count, obtaining the count result RA_INPNT_CNT. The clock CAIN_CK is ANDed with the one-hot decoder signal corresponding to the count result RA_INPNT_CNT, thereby obtaining the corresponding input pointer signals CMD_LATEN, RA0_INPNT, RA1_INPNT, and RA2_INPNT in sequence for each count result. For example, the input pointer signal RA1_INPNT will only be enabled when the count result signal RA_INPNT_CNT[2:0] = 3'b010.

[0145] The rising edge of clock CAIN_CK triggers counter CNT2 to count, obtaining the count result CA_INPNT_CNT. The inverted signal of clock CAIN_CK is ANDed with the one-hot decoder signal corresponding to the count result CA_INPNT_CNT, thereby obtaining the corresponding input pointer signals MRS_LATEN, CA0_INPNT, CA1_INPNT, and CA2_INPNT in sequence for each count result.

[0146] Figure 12 It shows Figure 4 A circuit diagram of an example read / write state generation unit.

[0147] like Figure 12As shown, the read / write status generation unit 1200 includes register REG2 and access instruction decoding unit 1210.

[0148] The data input of register REG2 is coupled to the data / address multiplexed line, receiving the DQ signal transmitted on it, and its clock input receives the access instruction enable signal CMD_LATEN. Therefore, register REG2 can output the access instruction CMD from the DQ signal.

[0149] For example, register REG2 can be composed of 8 D flip-flops.

[0150] The access instruction decoding unit 1210 is coupled to the data output of register REG2 and is configured to enable the read enable signal RD_ACCEN or the write enable signal WR_ACCEN in response to the value of the access instruction CMD. The read enable signal RD_ACCEN is enabled when CMD is a read instruction, and WR_ACCEN is enabled when CMD is a write instruction.

[0151] For example, the access instruction decoding unit 1210 is a logic circuit unit that can be designed based on a truth table formed by the various CMD values ​​to be input and the corresponding values ​​of RD_ACCEN and WR_ACCEN to be output.

[0152] Although Figure 12 The diagram shows the read / write state generation unit receiving a reset signal RST from outside the read / write state generation unit (e.g., an input pointer generation unit). However, in some other embodiments, the read / write state generation unit may generate the reset signal RST itself. For example, the read / write state generation unit 1200 may also include a pulse generator. Figure 12 (Not shown in the image), it is configured to generate a pulse triggered by the failure edge of the chip enable signal CS#, and its output is coupled to the reset terminal of register REG2; that is, the output of this pulse generator is the reset signal RST. At this time, the read / write status generation unit 1200 can also output this reset signal RST to the input pointer generation unit and the output pointer generation unit as the reset signal RST for these two units, thereby... Figure 9 The pulse generator 930 and its corresponding Figure 10 The pulse generator PUL4 in the code can also be omitted.

[0153] Figure 13 It shows Figure 4 A schematic diagram of an example of the output pointer generation unit in the diagram.

[0154] like Figure 13 As shown, the output pointer generation unit 1300 includes a delay unit 1310 and an output unit 1320.

[0155] The delay unit 1310 is configured to enable the delayed arrival signal LCHIT after a predetermined number of clock cycles have elapsed during the active period of the read enable signal RD_ACCEN or the write enable signal WR_ACCEN, wherein the clock cycle is the same as the clock cycle of the first clock CLK.

[0156] Output unit 1320 is configured to periodically enable each access address output signal (A0_OUTPNT, A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.) according to the burst length after the delay arrival signal LCHIT is enabled when the write enable signal WR_ACCEN is enabled. When the read enable signal RD_ACCEN is enabled, the first access address output signal A0_OUTPNT is enabled immediately after the first input access address has been cached in the cache (which can be indicated by, for example, CA0_INPNT mentioned above), and after the delay arrival signal LCHIT is enabled, the subsequent access address output signals (A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.) are periodically enabled according to the burst length after the burst length is enabled, wherein the burst length is set by the mode register based on the mode configuration value.

[0157] In some implementations, for example Figure 13 As shown, the output unit 1320 may include a burst count clock generation unit 1321, a burst length count unit 1322, a second count clock generation unit 1323, and a second count output unit 1324.

[0158] The burst count clock generation unit 1321 is configured to enable the address count arrival signal when the number of output access addresses is equal to the number of cached access addresses (which may be indicated by, for example, the aforementioned CA_INPNT_CNT signal), and to generate a burst count clock BLC_CLK based on the delayed arrival signal LCHIT, the address count arrival signal, and the first clock CLK, wherein the burst count clock BLC_CLK has a clock signal synchronized with the first clock CLK only between the effective edge of the delayed arrival signal LCHIT and the effective edge of the address count arrival signal.

[0159] Burst length counting unit 1322 is configured to cyclically count the rising and / or falling edges of the burst counting clock BLC_CLK, where the number of counts in each cycle is determined by the burst length. Counting can be performed on the rising edge, the falling edge, or both of the rising and falling edges of the burst counting clock BLC_CLK, as needed. The conversion relationship between the number of counts in each cycle and the burst length can be determined based on the counting method and the data transmission timing method (DDR or SDR) on the A / DQ line.

[0160] The second counting clock generation unit 1323 is configured to generate a second counting clock ADDR_OUTPNT_CLK based on the read enable signal RD_ACCEN, the counting result BL_CNT of the burst length counting unit 1322, and the burst counting clock BLC_CLK. The second counting clock ADDR_OUTPNT_CLK has a clock signal synchronized with the burst counting clock BLC_CLK during the period when the burst length counting unit 1322 outputs a specific counting result (a certain counting result value can be selected as needed). Furthermore, during the period when the read enable signal RD_ACCEN is valid, it has a pulse immediately following the first input access address that has been cached in the buffer (this moment can be indicated by, for example, CA0_INPNT mentioned above).

[0161] The second counting output unit 1324 is configured to count on the rising or falling edge of the second counting clock ADDR_OUTPNT_CLK, and in response to the result of each count, sequentially enable the output signals of each access address (A0_OUTPNT, A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.).

[0162] Figure 14 The following diagram illustrates the implementation. Figure 13 An exemplary circuit diagram of the output pointer generation unit. Figure 15 This shows the write operation. Figure 14 An exemplary timing diagram of the signals involved in the output pointer generation unit, Figure 16 This shows the read operation. Figure 14 An exemplary timing diagram of the signals involved in the output pointer generation unit.

[0163] like Figure 14 As shown, the output pointer generation unit 1400 includes a delay unit 1410, a burst count clock generation unit 1421, a counter CNT4 which serves as a burst length counting unit, a second count clock generation unit 1423, and a second count output unit 1424.

[0164] The delay unit 1410 includes a first logic unit 1411, a low-pass latch LAT1, an AND gate AND2, and a counter CNT3.

[0165] The first logic unit 1411 receives the read enable signal RD_ACCEN, the write enable signal WR_ACCEN, and the delay arrival signal LCHIT, and outputs the delay control signal LC_CRT. That is, it is configured to generate the delay control signal LC_CRT based on the read enable signal RD_ACCEN, the write enable signal WR_ACCEN, and the delay arrival signal LCHIT. The delay control signal LC_CRT is only valid when either the read enable signal RD_ACCEN or the write enable signal WR_ACCEN is valid and the delay arrival signal LCHIT is invalid.

[0166] Figure 14 A specific implementation of the first logic unit 1411 is given, but those skilled in the art will understand that the embodiments of this disclosure are not limited thereto, but can be designed according to the relationship between the input signals and output signals of the first logic unit 1411 described herein.

[0167] In some implementations, such as Figure 14 As shown, the first logic unit 1411 includes an OR gate OR1 and an AND gate AND4, wherein the inputs of the OR gate OR1 are the read enable signal RD_ACCEN and the write enable signal WR_ACCEN, the output of the OR gate OR1 and the inverted signal of the delayed arrival signal LCHIT are used as the inputs of the AND gate AND4, and the AND gate AND4 outputs the delay control signal LC_CRT.

[0168] The low-pass latch LAT1 receives the delay control signal LC_CRT at its input, the first clock CLK at its control terminal, and the delay enable signal LC_CLKEN at its output. A low-pass latch is one where input data passes through when the control signal is low and is latched when the control signal is high.

[0169] The two inputs of AND gate AND2 receive the delay enable signal LC_CLKEN and the first clock CLK respectively, and output the delay counting clock LC_CLK.

[0170] The clock input of counter CNT3 receives the delayed counting clock LC_CLK. Figure 14 The illustration shows counter CNT3 counting the rising edge of the delayed counting clock LC_CLK, but in other embodiments, it can also count the falling edge. Counter CNT3 enables the delayed arrival signal LCHIT after the count reaches a predetermined number.

[0171] In addition, such as Figure 14 As shown, the burst counting clock generation unit 1421 includes a comparator CMP, a low-pass latch LAT2, a pulse generator PUL5, a pulse generator PUL6, an SR latch SR2, and an AND gate AND3.

[0172] The comparator CMP is configured to compare the number of currently output access addresses with the number of cached access addresses and enable the address count arrival signal when they are equal. In some implementations, such as Figure 14 As shown, the previous method can be used. Figure 10 The count result CA_INPNT_CNT of the counter CNT2 indicates the number of cached access addresses, while the number of currently output access addresses can be indicated by the count result ADDR_OUTPNT_CNT of the counter CNT5 in the second counting output unit 1424, which will be described later. As mentioned above... Figure 10 and Figure 11 As shown, given that CA_INPNT_CNT also counts the MRs entered before the access address, the final result of CA_INPNT_CNT is 1 more than the actual number of cached addresses. Therefore, the comparator CMP enables the address count arrival signal when ADDR_OUTPNT_CNT = CA_INPNT_CNT - 1.

[0173] The input of the low-pass latch LAT2 receives the delayed arrival signal LCHIT, its control terminal receives the first clock CLK, and its output is a burst enable signal.

[0174] Pulse generator PUL5 receives the address count arrival signal and generates a pulse triggered by its active edge, while pulse generator PUL6 receives the burst enable signal and generates a pulse triggered by its active edge. Since in this example, both the address count arrival signal and the burst enable signal have rising edges, therefore... Figure 14 As shown in the diagram, pulse generators PUL5 and PUL6 are both rising edge triggered pulse generators.

[0175] The set input S of the SR latch SR2 receives the output ADDR_CNT_HIT from the pulse generator PUL5, and its reset input R receives the output of the pulse generator PUL6. Its inverted output is coupled to one input of the AND gate AND3 (marked "DEN" in the diagram). The other input of the AND gate AND3 receives the first clock CLK, and the output of the AND gate AND3 is the burst counting clock BLC_CLK.

[0176] However, the coupling relationship of SR latch SR2 is not limited to... Figure 14 As shown. Given the characteristics of the SR latch, the above... Figure 14 The signals of the set terminal S and the reset terminal R of the SR latch SR2 in the circuit are interchanged, and the positive output terminal is coupled to one input terminal of the AND gate AND3 to achieve the same circuit function.

[0177] Therefore, the coupling relationship of SR latch SR2 can be summarized as follows: the set terminal S of SR latch SR2 receives one of the outputs of pulse generator PUL5 and pulse generator PUL6, its reset terminal R receives the other of these two outputs, and one of its two output terminals is coupled to one input terminal of AND gate AND3.

[0178] In addition, such as Figure 14 As shown, the clock input of counter CNT4, which serves as the burst length counting unit, receives the burst counting clock BLC_CLK. Counter CNT4 performs cyclic counting on the falling edge of the burst counting clock BLC_CLK. "Cyclic counting" means that after reaching a preset maximum value, it returns to the initial value and continues counting. The reset input of counter CNT4 can also receive the output ADDR_CNT_HIT of pulse generator PUL5 as a reset signal.

[0179] In addition, such as Figure 14 As shown, the second counting clock generation unit 1423 includes a one-hot decoder HOT3 and a second logic unit 1425.

[0180] The one-hot decoder HOT3 receives the count result BL_CNT from the counter CNT4, which serves as a burst length counting unit, and outputs a specific one-hot decoded signal corresponding to a specific count result. Figure 14 In the example, the specific count result is 000, and the corresponding specific one-hot decoder signal is BLC000. However, in other implementations, other count result values ​​and their corresponding one-hot decoder signals can be selected as needed.

[0181] The second logic unit 1425 receives a specific one-hot decoder signal (e.g., BLC000), a burst counter clock BLC_CLK, a read enable signal RD_ACCEN, and a first signal indicating that the buffer has cached the first input access address (e.g., the aforementioned CA0_INPNT), and outputs a second counter clock ADDR_OUTPNT_CLK. That is, it is configured to generate the second counter clock based on the specific one-hot decoder signal, the burst counter clock, the read enable signal, and the first signal. The second counter clock is valid only when the specific one-hot decoder signal is valid and the burst counter clock is valid, or when the read enable signal is valid and the first signal is valid.

[0182] Figure 14 A specific implementation of the second logic unit 1425 is given, but those skilled in the art will understand that the embodiments of this disclosure are not limited thereto, but can be designed according to the relationship between the input signals and output signals of the second logic unit 1425 described herein.

[0183] In some implementations, such as Figure 14 As shown, the second logic unit 1425 includes AND gate AND5, AND gate AND6, and OR gate OR2. The inputs of AND gate AND5 are a specific one-hot decoder signal BLC000 and a burst counting clock BLC_CLK. The inputs of AND gate AND6 are a read enable signal RD_ACCEN and a first signal CA0_INPNT. The outputs of AND gate AND5 and AND gate AND6 serve as the inputs of OR gate OR2. OR gate OR2 outputs a second counting clock ADDR_OUTPNT_CLK.

[0184] In addition, such as Figure 14 As shown, the second counting output unit 1424 includes a counter CNT5, a one-hot decoder HOT4, and a third set of AND gates AND31-AND34.

[0185] The clock input of counter CNT5 receives the second counting clock ADDR_OUTPNT_CLK. Counter CNT5 counts on the falling edge of the second counting clock ADDR_OUTPNT_CLK.

[0186] The one-hot decoder HOT4 receives the counting result ADDR_OUTPNT_CNT from the counter CNT5 and outputs the third set of one-hot decoded signals (CNT000, CNT001, CNT010, CNT100, etc.).

[0187] The third set of AND gates AND31-AND34 receive the third set of one-hot decoding signals and the second counting clock ADDR_OUTPNT_CLK, respectively, and output the respective access address output signals (A0_OUTPNT, A1_OUTPNT, A2_OUTPNT, A3_OUTPNT, etc.).

[0188] In addition, such as Figure 14 As shown, in some embodiments, the reset terminals of counters CNT3 and CNT5 receive a reset signal RST, which can be generated by the output pointer generation unit itself or received from other external units.

[0189] refer to Figure 15 The timing diagram clearly shows Figure 12 and Figure 14 The circuit's operation process during write operations.

[0190] Figure 15 The timing of the four signals CLK, CS#, DQS, and DQ transmitted through the access interface and Figure 5 The same applies, so I won't repeat it here.

[0191] like Figure 15 As shown, Figure 12The read / write status generation unit acquires the WR instruction on the rising edge of the CMD_LATEN signal and enables the WR_ACCEN signal after decoding it. At this time, the delayed arrival signal LCHIT should be low. Figure 14 The signal LC_CLKEN in the delay unit 1410 is enabled, so that the clock signal of CLK can be turned into clock LC_CLK through AND gate AND2, and counter CNT3 starts to perform delay counting.

[0192] After counter CNT3 counts the required delay, the delay arrival signal LCHIT is pulled high, thus disabling the signal LC_CLKEN and enabling the signal DEN. This allows the CLK clock signal to be converted into clock BLC_CLK through AND gate AND3. Counter CNT4 then begins counting the burst length and outputs the count result BL_CNT. With a burst length of 16, transmitting the data corresponding to each access address using DDR timing requires a total of 8 clock cycles. Therefore, a 3-bit falling edge triggered counter can be used as counter CNT4.

[0193] When the burst length count BL_CNT[7:0] is 8'h00, BLC000 is enabled, thereby activating the signal ADDR_OUTPNT_CLK and generating a pulse, which triggers the counter CNT5 to count.

[0194] The clock ADDR_OUTPNT_CLK is ANDed with the count result ADDR_OUTPNT_CNT of the counter CNT5, and the corresponding one-hot decoded signals are ANDed together, thereby enabling the corresponding output pointer signals A0_OUTPNT, A1_OUTPNT, and A2_OUTPNT in sequence under each count result.

[0195] When the counting result ADDR_OUTPNT_CNT = CA_INPNT_CNT-1, the ADDR_CNT_HIT signal goes high, which causes the DEN signal to fail, and the counter CNT4 stops counting and is reset.

[0196] When the chip select signal CS# is pulled high, the reset signal RST is activated, thereby resetting the signals WR_ACCEN, LCHIT, and the corresponding counters. This write instruction is now complete.

[0197] refer to Figure 16 The timing diagram clearly shows Figure 12 and Figure 14 The circuit's operation process during read operations.

[0198] Figure 16 The timing of the four signals CLK, CS#, DQS, and DQ transmitted through the access interface and Figure 6 The same applies, so I won't repeat it here.

[0199] like Figure 16 As shown, Figure 12 The read / write status generation unit acquires the RD instruction on the rising edge of the CMD_LATEN signal and enables the RD_ACCEN signal after decoding it. At this time, the delayed arrival signal LCHIT should be low. Figure 14 The signal LC_CLKEN in the delay unit 1410 is enabled, so that the clock signal of CLK can be turned into clock LC_CLK through AND gate AND2, and counter CNT3 starts to perform delay counting.

[0200] Simultaneously, as RD_ACCEN goes high, the pulse of CA0_INPNT causes the clock signal ADDR_OUTPNT_CLK to generate a corresponding pulse, thus causing counter CNT5 to perform a count. Furthermore, since counter CNT5 counts on the falling edge of ADDR_OUTPNT_CLK, during the first pulse of ADDR_OUTPNT_CLK, the count result of counter CNT5 is still the initial value 000, and its corresponding one-hot decoder signal CNT000 is enabled. Therefore, the first pulse of ADDR_OUTPNT_CLK correspondingly activates the first address output signal A0_OUTPNT.

[0201] After counter CNT3 counts the required delay, the delay arrival signal LCHIT is pulled high, thus disabling the signal LC_CLKEN and enabling the signal DEN. This allows the CLK clock signal to be converted into clock BLC_CLK through AND gate AND3. Counter CNT4 then begins counting the burst length and outputs the count result BL_CNT. With a burst length of 16, transmitting the data corresponding to each access address using DDR timing requires a total of 8 clock cycles. Therefore, a 3-bit falling edge triggered counter can be used as counter CNT4.

[0202] When the burst length count BL_CNT[7:0] is 8'h00, BLC000 is enabled, thereby activating the signal ADDR_OUTPNT_CLK and generating another pulse, which in turn triggers the counter CNT5 to count again.

[0203] The clock ADDR_OUTPNT_CLK is ANDed with the count result ADDR_OUTPNT_CNT of the counter CNT5, and the corresponding one-hot decoded signals are ANDed together. This enables the corresponding output pointer signals A1_OUTPNT and A2_OUTPNT in turn for each subsequent count result.

[0204] When the counting result ADDR_OUTPNT_CNT = CA_INPNT_CNT-1, the ADDR_CNT_HIT signal goes high, which causes the DEN signal to fail, and the counter CNT4 stops counting and is reset.

[0205] When the chip select signal CS# is pulled high, the reset signal RST is activated, thereby resetting the signals RD_ACCEN, LCHIT, and the corresponding counters. This read instruction ends.

[0206] It is understood that, unless clearly contradictory, the various details or variations mentioned in the above embodiments / examples can be combined with other embodiments / examples.

[0207] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A controller for a memory, the memory comprising a memory array, a mode register, and an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplex line for transmitting data and addresses in time division multiplexing; the controller comprising: a decoding section receiving an access instruction and a mode configuration value inputted in sequence via the data / address multiplex line, and configured to set the mode register based on the mode configuration value; and a buffer section configured to buffer at least one access address inputted after the mode configuration value via the data / address multiplex line in sequence, and output the at least one access address to the memory array in sequence at a specified time.

2. The controller of claim 1, wherein, the decoding section is configured to input the mode configuration value to the mode register so as to update a value of the mode register to the mode configuration value.

3. The controller of claim 1, wherein, the decoding section is further configured to generate a read enable signal or a write enable signal based on the access instruction, and the specified time is determined based on the read enable signal or the write enable signal.

4. The controller of claim 1, wherein, the access interface further comprises a transmission line; the decoding section further receives a first enable signal inputted via the transmission line, and is further configured to generate an address input signal based on the first enable signal, wherein the address input signal has signal edges corresponding to transmission periods of respective access addresses inputted before a falling edge of the first enable signal respectively; and the buffer section is configured to buffer the respective access addresses in response to the signal edges of the address input signal respectively.

5. The controller of claim 4, wherein, the transmission line is further for outputting a signal for synchronizing sampling of read data outputted on the data / address multiplex line, and / or inputting a signal for masking write data received on the data / address multiplex line.

6. The controller of claim 4, wherein, the access interface further comprises a chip select line and a clock line; the decoding section comprises an input pointer generation unit configured to receive a chip enable signal inputted via the chip select line, a first clock inputted via the clock line, and the first enable signal, and generate an access instruction enable signal, a mode configuration enable signal, and the address input signal based on the first enable signal, the chip enable signal, and the first clock, wherein the access instruction enable signal has a signal edge corresponding to a transmission period of the access instruction, and the mode configuration enable signal has a signal edge corresponding to a transmission period of the mode configuration value.

7. The controller of claim 6, wherein, the decoding section further comprises: a first register having a data input coupled to the data / address multiplex line, a clock input receiving the mode configuration enable signal, and a data output coupled to the mode register.

8. The controller of claim 6, wherein, the decoding section further comprises a read / write state generation unit, wherein the read / write state generation unit comprises: a second register having a data input coupled to the data / address multiplex line, and a clock input receiving the access instruction enable signal, a first pulse generator configured to generate one pulse triggered by a falling edge of the chip enable signal, and having an output coupled to a reset terminal of the second register, and a second pulse generator configured to generate one pulse triggered by a falling edge of the first clock, and having an output coupled to a clock terminal of the second register. an access instruction decoding unit coupled to a data output terminal of the second register and configured to enable a read enable signal or a write enable signal in response to a value of the access instruction.

9. The controller of claim 6, wherein, The address input signals include a group of row address input signals and a group of column address input signals, wherein each row address input signal or column address input signal has a signal edge corresponding to a transmission period of a row address or column address in each access address input before an invalid edge of the first enable signal, The input pointer generating unit includes: a first count clock generating unit configured to generate a first count clock based on the first enable signal, the chip enable signal and the first clock, wherein the first count clock has a clock signal synchronized with the first clock only between a valid edge of the chip enable signal and an invalid edge of the first enable signal, and a first count output unit configured to count rising edges and / or falling edges of the first count clock and sequentially enable the access instruction enable signal, the mode configuration enable signal, and each row address input signal and column address input signal in response to a result of each count.

10. The controller of claim 9, wherein, The first count clock generating unit includes: a second pulse generator configured to generate one pulse triggered by the valid edge of the chip enable signal, a third pulse generator configured to generate one pulse triggered by the invalid edge of the first enable signal, a first SR latch having one of outputs of the second pulse generator and the third pulse generator received at a set terminal, having the other of the two outputs received at a reset terminal, and a first AND gate having one of two outputs of the first SR latch and the first clock received at two input terminals respectively and outputting the first count clock.

11. The controller of claim 9, wherein, The first count output unit includes: a first counter having the first count clock received at a clock terminal and counting falling edges of the first count clock, a second counter having an inverse signal of the first count clock received at a clock terminal and counting falling edges of the inverse signal of the first count clock, a first one-hot decoder receiving a count result of the first counter and outputting a first group of one-hot decoding signals, a second one-hot decoder receiving a count result of the second counter and outputting a second group of one-hot decoding signals, a first group of AND gates receiving the first group of one-hot decoding signals and the first count clock respectively and outputting the access instruction enable signal and each row address input signal respectively, and a second group of AND gates receiving the second group of one-hot decoding signals and the inverse signal of the first count clock respectively and outputting the mode configuration enable signal and each column address input signal respectively.

12. The controller of claim 11, wherein, The input pointer generating unit further includes a fourth pulse generator configured to generate one pulse triggered by an invalid edge of the chip enable signal and having an output terminal coupled to a reset terminal of the first counter and a set terminal of the second counter.

13. The controller of claim 3, wherein, The access interface further includes a clock line; The decoding section includes an output pointer generation unit configured to receive a first clock input via the clock line and the read enable signal or the write enable signal, and generate an address output signal based on the first clock and the read enable signal or the write enable signal, wherein the address output signal has a signal edge indicating an output time of each access address cached by the cache section; The cache section is configured to output a corresponding access address in response to a signal edge of the address output signal.

14. The controller of claim 13, wherein, The address output signal includes a group of access address output signals, wherein each access address output signal has a signal edge indicating an output time of each access address cached by the cache section, The output pointer generation unit includes: a delay unit configured to enable a delay arrival signal after a predetermined number of clock cycles experienced during the read enable signal or the write enable signal is valid, wherein the clock cycle is the same as a clock cycle of the first clock, and an output unit configured to periodically enable each access address output signal according to a burst length after the delay arrival signal is enabled in a case that the write enable signal is enabled, and enable a first access address output signal immediately after the cache section has cached a first input access address and periodically enable each subsequent access address output signal according to the burst length after the delay arrival signal is enabled in a case that the read enable signal is enabled, wherein the burst length is set by the mode register based on the mode configuration value.

15. The controller of claim 14, wherein, The output unit includes: a burst count clock generation unit configured to enable an address count arrival signal when a number of output access addresses is equal to a number of cached access addresses, and generate a burst count clock based on the delay arrival signal, the address count arrival signal and the first clock, wherein the burst count clock only has a clock signal synchronized with the first clock between a valid edge of the delay arrival signal and a valid edge of the address count arrival signal, a burst length count unit configured to cyclically count rising edges and / or falling edges of the burst count clock, wherein a count number of each cycle is determined by the burst length, a second count clock generation unit configured to generate a second count clock based on the read enable signal, a count result of the burst length count unit and the burst count clock, wherein the second count clock has a clock signal synchronized with the burst count clock during the burst length count unit outputs a specific count result, and has a pulse immediately after the cache section has cached a first input access address during the read enable signal is valid, and a second count output unit configured to count rising edges or falling edges of the second count clock, and enable each access address output signal in sequence in response to a result of each count.

16. The controller of claim 14, wherein, The delay unit includes: a first logic unit configured to generate a delay control signal based on the read enable signal, the write enable signal and the delay arrival signal, which is valid only when the read enable signal or the write enable signal is valid and the delay arrival signal is invalid, a first low-pass latch having an input terminal receiving the delay control signal, a control terminal receiving the first clock, and an output terminal outputting a delay enable signal, a second AND gate having two input terminals receiving the delay enable signal and the first clock respectively, and outputting a delay count clock, and a third counter having a clock terminal receiving the delay count clock, counting rising edges or falling edges of the delay count clock, and enabling the delay arrival signal when the predetermined number is reached.

17. The controller of claim 15, wherein, The burst count clock generation unit includes: a comparator configured to compare the number of currently output access addresses with the number of buffered access addresses and enable the address count arrival signal when they are equal, a second low-pass latch having an input terminal receiving the delay arrival signal, a control terminal receiving the first clock, and an output terminal outputting a burst enable signal, a fifth pulse generator configured to generate one pulse triggered by a valid edge of the address count arrival signal, a sixth pulse generator configured to generate one pulse triggered by a valid edge of the burst enable signal, a second SR latch having a set terminal receiving one of the outputs of the fifth pulse generator and the sixth pulse generator, a reset terminal receiving the other of the two outputs, and a third AND gate having two input terminals receiving one of the two outputs of the second SR latch and the first clock respectively, and outputting the burst count clock; and The burst length count unit includes a fourth counter having a clock terminal receiving the burst count clock, and counting falling edges of the burst count clock cyclically.

18. The controller of claim 15, wherein, The second count clock generation unit includes: a third one-hot decoder receiving the count result of the burst length count unit and outputting a specific one-hot decode signal corresponding to the specific count result, a second logic unit configured to generate the second count clock based on the specific one-hot decode signal, the burst count clock, the read enable signal and a first signal indicating that the buffer unit has buffered the first input access address, which is valid only when the specific one-hot decode signal is valid and the burst count clock is valid, or when the read enable signal is valid and the first signal is valid.

19. The controller of claim 15, wherein, The second count output unit includes: a fifth counter having a clock terminal receiving the second count clock, counting falling edges of the second count clock, a fourth one-hot decoder receiving the count result of the fifth counter and outputting a third group of one-hot decode signals, and a third group of AND gates receiving the third group of one-hot decode signals and the second count clock respectively, and outputting respective access address output signals.

20. The controller according to any one of claims 1-19, wherein the memory is a PSRAM; and / or the memory is a PSRAM; and / or The access interface adopts a multi-IO SPI protocol; and / or The cache unit is a FIFO cache.

21. A control method of a memory, the memory comprising a memory array, a mode register, and an access interface for externally accessing the memory array, the access interface comprising at least one data / address multiplex line for multiplexing data and addresses for transmission; The method comprises: receiving, in sequence, an access instruction, a mode configuration value, and at least one access address via the data / address multiplex line; setting the mode register based on the mode configuration value; and storing the at least one access address in sequence and outputting the at least one access address to the memory array in sequence at a specified time. ​

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