Insulated gate bipolar transistor modeling method and device, storage medium and program product

Abstract

The embodiment of the invention discloses a modeling method and device of an insulated gate bipolar transistor, a storage medium and a program product. The modeling method of the insulated gate bipolar transistor comprises the following steps: acquiring capacitance test data between a grid electrode and a collector electrode of the insulated gate bipolar transistor; according to a preset circuit model, constructing dynamic capacitance piecewise functions of the insulated gate bipolar transistor in a turn-on stage and a turn-off stage; and carrying out parameter extraction on the piecewise function based on capacitance test data so as to describe capacitance change of the insulated gate bipolar transistor in a turn-on and / or turn-off process. According to the technical scheme provided by the embodiment of the invention, the behavior change analysis of the insulated gate bipolar transistor in the switching process is realized by setting the modeling method of the insulated gate bipolar transistor.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic simulation, and in particular to a modeling method, device, storage medium and program product of an insulated gate bipolar transistor. Background Art

[0002] Computer-aided design (CAD) based on the Simulation Program with Integrated Circuit Emphasis (SPICE) allows for extensive virtual experimentation and testing, assisting in the development of circuit systems and achieving greater cost-effectiveness and shorter development cycles. High-precision SPICE device models are crucial for improving the design efficiency and applicability of application circuits. Figure 1 It is the modeling and fitting curve of the insulated gate bipolar transistor in the related technology. Figure 1 As shown, C GE is the capacitance between the gate and emitter in the IGBT device; C CE is the capacitance between the collector and emitter in the IGBT device; C GC is the capacitance between the gate and collector of the IGBT device; V CE is the voltage between the collector and emitter in the IGBT device; V GE is the voltage between the gate and emitter of the IGBT device; I CE is the current between the collector and emitter in the IGBT device; the existing modeling method usually assumes that as long as the DC I CE -V CE Data and CV CE The data fits perfectly, and the model can accurately match the switching waveform obtained in the actual test. In fact, unlike unipolar devices, the insulated gate bipolar transistor (IGBT) has a unique conductivity modulation effect, which allows the collector region to inject a large number of hole carriers into the drift region in the on state. The dynamic change characteristics of the reverse transfer capacitance are not as good as those under the test conditions V GE = 0V, but instead shows a steeper change trend. Therefore, the existing modeling method cannot well simulate the dynamic capacitance change characteristics of IGBT devices.

[0003] In the simulation design process, noise suppression and switching loss optimization are both related to the improvement of the nonlinear characteristics of the capacitor. For example, a smaller C GE and C GCThese factors are the primary cause of increased device drain current and voltage oscillations or overshoot. Therefore, accurately modeling the nonlinear characteristics of the IGBT's dynamic capacitance is crucial for predicting its switching performance in application circuits. Current engineering applications of IGBTs are largely based on extensive experience and limited manual data. Therefore, research on IGBT device behavior under normal switching conditions is essential. Summary of the Invention

[0004] The present invention provides a modeling method, device, storage medium and program product of an insulated gate bipolar transistor, so as to realize analysis of behavioral changes of the insulated gate bipolar transistor during a switching process.

[0005] According to one aspect of the present invention, a modeling method for an insulated gate bipolar transistor is provided, the modeling method for the insulated gate bipolar transistor comprising:

[0006] Obtaining capacitance test data between the gate and collector of an insulated gate bipolar transistor;

[0007] Constructing a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the turn-on phase and the turn-off phase according to a preset circuit model;

[0008] Parameters of a piecewise function are extracted based on capacitance test data to describe the capacitance change of an insulated gate bipolar transistor during turn-on and / or turn-off processes.

[0009] Optionally, the preset circuit model includes a first circuit model and a second circuit model; the first circuit model includes an insulated gate bipolar transistor, a first voltage-controlled voltage source, a first capacitor, a second voltage-controlled voltage source, a second capacitor, a third capacitor and a first voltage source; the second circuit model includes a first current source, a first resistor, a fourth capacitor and a second voltage source; the collector of the insulated gate bipolar transistor is connected to one end of the first voltage source, the other end of the first voltage source is connected to one end of the first capacitor and one end of the second capacitor, and the connection point is a first node; the other end of the first capacitor is connected to one end of the first voltage-controlled voltage source; the other end of the first voltage-controlled voltage source is connected to the gate of the insulated gate bipolar transistor and one end of the third capacitor, and the connection point is a second node; the other end of the third capacitor is connected to the emitter of the insulated gate bipolar transistor and one end of the second voltage-controlled voltage source; the other end of the second voltage-controlled voltage source is connected to the other end of the second capacitor; one end of the first current source is connected to one end of the second voltage source and one end of the fourth capacitor; the other end of the second voltage source is connected to one end of the first resistor; the other end of the first resistor is connected to the other end of the first current source and the other end of the fourth capacitor and is grounded;

[0010] A dynamic capacitance piecewise function of an insulated gate bipolar transistor in the turn-on and turn-off phases is constructed based on a preset circuit model, including:

[0011] Establish a first function based on the first circuit model and the second circuit model:

[0012] E GC =V 12 -f(V 12 ) / C0;

[0013] Among them, E GC is the first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; f(V 12 ) is the first sub-function, the first sub-function f(V 12 ) According to the voltage V between the first node and the second node 12 Determine; C0 is the fourth capacitor;

[0014] determining a state of the insulated gate bipolar transistor based on a current relationship between the first circuit model and the second circuit model;

[0015] A piecewise function is determined based on the first function and the state of the insulated gate bipolar transistor.

[0016] Optionally, determining the state of the insulated gate bipolar transistor according to the current relationship between the first circuit model and the second circuit model includes:

[0017] When the difference between the current of the first current source and the current flowing through the second voltage source is greater than or equal to zero, determining that the insulated gate bipolar transistor is in an on state;

[0018] When the difference between the current of the first current source and the current flowing through the second voltage source is less than zero, it is determined that the insulated gate bipolar transistor is in the off state; wherein the current of the first current source is equal to the current flowing through the first voltage source.

[0019] Optionally, the first subfunction f(V 12 ) According to the voltage V between the first node and the second node 12 Determine, including:

[0020] When the voltage V between the first node and the second node 12 When it is less than or equal to zero, the first sub-function f(V 12 ) is equal to 0;

[0021] When the voltage V between the first node and the second node 12 When it is greater than zero, the first subfunction is: Among them, C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG* is the first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient;

[0022] Determining a piecewise function according to the first function and a state of the insulated gate bipolar transistor includes:

[0023]

[0024] Among them, E GC is the first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG * is the first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient; C0 is the fourth capacitance; V CG *′ is the second adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco' is the second fitting coefficient; I(G0) is the current of the first current source; and I(V0) is the current flowing through the second voltage source.

[0025] Optionally, obtaining capacitance test data between the gate and collector of an insulated gate bipolar transistor, including:

[0026] Building a switch test circuit, testing and obtaining first test data; wherein the first test data includes the voltage between the collector and the emitter, the voltage between the gate and the emitter, and the gate current;

[0027] Capacitance test data between the gate and the collector of the insulated gate bipolar transistor is calculated according to the first test data.

[0028] Optionally, calculating capacitance test data between the gate and collector of the insulated gate bipolar transistor according to the first test data includes:

[0029] The capacitance test data between the gate and collector of the insulated gate bipolar transistor is calculated according to the following formula:

[0030]

[0031] Among them, C GC.dynamic is the capacitance test data between the gate and collector of the insulated gate bipolar transistor; G is the gate current; C GE is the third capacitor; V GE is the voltage between the gate and the emitter; V CEis the voltage between the collector and emitter.

[0032] Optionally, after calculating the capacitance test data between the gate and the collector of the insulated gate bipolar transistor according to the first test data, the method further includes:

[0033] Process the test data and convert the independent variable from a time variable to the voltage change between the collector and the gate.

[0034] According to another aspect of the present invention, a modeling device for an insulated gate bipolar transistor is provided, the modeling device for the insulated gate bipolar transistor comprising:

[0035] A capacitance test data acquisition module is used to acquire capacitance test data between the gate and collector of the insulated gate bipolar transistor;

[0036] A piecewise function construction module, for constructing a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the on-phase and the off-phase according to a preset circuit model;

[0037] The parameter extraction module is used to extract parameters of the piecewise function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process.

[0038] According to another aspect of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores computer instructions, which are used to enable a processor to implement the insulated gate bipolar transistor modeling method according to any embodiment of the present invention when executed.

[0039] According to another aspect of the present invention, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the computer program implements the insulated gate bipolar transistor modeling method according to any embodiment of the present invention.

[0040] The technical solution of an embodiment of the present invention provides a modeling method for an insulated gate bipolar transistor. By obtaining capacitance test data between the gate and collector of the insulated gate bipolar transistor, a dynamic capacitance piecewise function of the insulated gate bipolar transistor in the turn-on and turn-off phases is constructed according to a preset circuit model. Parameters of the piecewise function are extracted based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process, thereby analyzing the behavioral changes of the insulated gate bipolar transistor during the switching process. By establishing the piecewise function, the turn-on and turn-off processes of the insulated gate bipolar transistor are analyzed separately, thereby improving the reliability of the analysis of the behavioral changes of the insulated gate bipolar transistor during the switching process.

[0041] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 It is the modeling of the insulated gate bipolar transistor and its fitting curve in the related art;

[0044] Figure 2 is a flow chart of a modeling method for an insulated gate bipolar transistor provided according to an embodiment of the present invention;

[0045] Figure 3 is a change in capacitance between the gate and collector of an insulated gate bipolar transistor under different test conditions provided by an embodiment of the present invention;

[0046] Figure 4 is a flow chart of another insulated gate bipolar transistor modeling method provided according to an embodiment of the present invention;

[0047] Figure 5 is a structural diagram of a first circuit model provided according to an embodiment of the present invention;

[0048] Figure 6 is a schematic structural diagram of a second circuit model provided according to an embodiment of the present invention;

[0049] Figure 7 is a flow chart of another insulated gate bipolar transistor modeling method provided according to an embodiment of the present invention;

[0050] Figure 8 1 is a schematic structural diagram of a modeling device for an insulated gate bipolar transistor provided according to an embodiment of the present invention;

[0051] Figure 9 It is a structural schematic diagram of an insulated gate bipolar transistor modeling device for implementing the insulated gate bipolar transistor modeling method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0054] Figure 2 This is a flow chart of a modeling method for an insulated gate bipolar transistor provided according to an embodiment of the present invention. The embodiment of the present invention is applicable to modeling an insulated gate bipolar transistor. The modeling method for an insulated gate bipolar transistor can be executed by a modeling device for an insulated gate bipolar transistor. The modeling device for an insulated gate bipolar transistor can be implemented in the form of hardware and / or software. Figure 2 As shown, the modeling method of the insulated gate bipolar transistor includes:

[0055] S110 , obtaining capacitance test data between the gate and collector of the insulated gate bipolar transistor.

[0056] Specifically, you can use C GC Represents the capacitance between the gate and collector of an insulated gate bipolar transistor. The capacitance test data between the gate and collector of an IGBT can be obtained using C GC.dynamic Indicates. C GC It is a key parasitic parameter that affects the switching characteristics of IGBT. GC The value of the voltage between the IGBT collector and emitter V CE , the voltage between the gate and emitter V GE As well as the dynamic changes of the working stage (on or off). For example, a double pulse test circuit can be built to drive the IGBT through the pulse signal and synchronously collect V GE and V CEDuring the switching transient process, the oscilloscope is used to capture the C GC For example, a switch test circuit can be built to test and obtain relevant data to obtain C GC Dynamically changing data. Figure 3 is the capacitance change between the gate and collector of the insulated gate bipolar transistor under different test conditions provided by the embodiment of the present invention. Figure 3 As shown, Crss@100kHz represents the voltage V between the gate and emitter of the IGBT GE =0V test condition C GC Changes; C GC (turn-on) indicates the C of the IGBT during the turn-on phase. GC Changes; C GC (turn-off) indicates the C of the IGBT during the turn-off phase. GC Changes. Figure 3 It can be seen that IGBT is in V GE = 0V test conditions, C during the turn-on and turn-off phases GC Therefore, in order to accurately describe the switching behavior of the IGBT, it is necessary to GC Accurate modeling.

[0057] S120 , constructing a dynamic capacitance piecewise function of the insulated gate bipolar transistor in the on-phase and the off-phase according to a preset circuit model.

[0058] Specifically, according to Figure 3 The test results shown in the figure show that dynamic C GC Accurate modeling is performed to accurately describe the switching behavior of the IGBT. For example, a piecewise function can be established to analyze the IGBT's turn-on and turn-off phases separately. The preset circuit model is a pre-set model topology. The preset circuit model can include two circuit models: one for placing the DC IGBT model and setting the capacitance and voltage representing different nodes of the DC IGBT model; the other for identifying the moment of turning on or off during model simulation.

[0059] S130 , extracting parameters of the piecewise function based on the capacitance test data to describe capacitance changes of the insulated gate bipolar transistor during a turn-on and / or turn-off process.

[0060] Specifically, the above steps can be used to obtain capacitance test data and a piecewise function of the dynamic capacitance of the IGBT during the turn-on and turn-off phases. Parameters of the piecewise function are extracted based on the capacitance test data to describe the capacitance change of the IGBT during the turn-on and / or turn-off process. Parameter extraction can be performed using software such as the Integrated Circuit Characterization and Analysis Program (ICCAP) or Matrix Laboratory (MATLAB).

[0061] The technical solution of an embodiment of the present invention provides a modeling method for an insulated gate bipolar transistor. By obtaining capacitance test data between the gate and collector of the insulated gate bipolar transistor, a dynamic capacitance piecewise function of the insulated gate bipolar transistor in the turn-on and turn-off phases is constructed according to a preset circuit model. Parameters of the piecewise function are extracted based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process, thereby analyzing the behavioral changes of the insulated gate bipolar transistor during the switching process. By establishing the piecewise function, the turn-on and turn-off processes of the insulated gate bipolar transistor are analyzed separately, thereby improving the reliability of the analysis of the behavioral changes of the insulated gate bipolar transistor during the switching process.

[0062] Figure 4 This is a flow chart of another insulated gate bipolar transistor modeling method provided according to an embodiment of the present invention. This embodiment of the present invention is a detailed description of the technical features of the above-mentioned embodiment of the invention. Figure 5 3 is a structural diagram of a first circuit model provided according to an embodiment of the present invention. Figure 6 : is a schematic diagram of the structure of the second circuit model provided according to an embodiment of the present invention. Figure 5 and Figure 6 As shown, the preset circuit model includes a first circuit model and a second circuit model. The first circuit model includes an IGBT, a first voltage-controlled voltage source E GC , the first capacitor C GC0 , the second voltage-controlled voltage source E CE , the second capacitor C CE0 , the third capacitor C GE and a first voltage source V1; the second circuit model includes a first current source G0, a first resistor R0, a fourth capacitor C0 and a second voltage source V0; the collector of the insulated gate bipolar transistor IGBT is connected to one end of the first voltage source V1, and the other end of the first voltage source V1 is connected to the first capacitor C GC0 One end of the second capacitor C CE0 One end of the first capacitor C is connected to the first node 1; GC0 The other end is connected to the first voltage-controlled voltage source EGC One end of the first voltage-controlled voltage source E GC The other end is connected to the gate of the insulated gate bipolar transistor IGBT and the third capacitor C GE One end of the third capacitor C is connected to the second node 2; GE The other end is connected to the emitter of the insulated gate bipolar transistor IGBT and the second voltage-controlled voltage source E CE One end of the second voltage-controlled voltage source E CE The other end of the second capacitor C CE0 The other end of the first current source G0 is connected to the other end of the second voltage source V0; one end of the first current source G0 is connected to one end of the second voltage source V0 and one end of the fourth capacitor C0; the other end of the second voltage source V0 is connected to one end of the first resistor R0; the other end of the first resistor R0 is connected to the other end of the first current source G0 and the other end of the fourth capacitor C0 and is grounded. The first circuit model and the second circuit model also include a third node 3 located at the second voltage-controlled voltage source E CE , the third capacitor C GE and the emitter of the IGBT; the fourth node 4 is located at the first voltage-controlled voltage source E GC With the first capacitor C GC0 A fifth node 5 is located between the collector of the IGBT and the first voltage source V1; a sixth node 6 is located between the second voltage-controlled voltage source E CE With the second capacitor C CE0 a seventh node 7, located at a connection point between one end of the first current source G0, one end of the second voltage source V0, and one end of the fourth capacitor C0; an eighth node 8, located between the second voltage source V0 and the first resistor R0; a ninth node 9, located at a connection point between the other end of the first resistor R0, the other end of the first current source G0, and the other end of the fourth capacitor C0.

[0063] Specifically, a DC IGBT model is placed between the second node 2, the third node 3 and the fifth node 5; a constant third capacitor C is placed between the second node 2 and the third node 3. GE Used to characterize the IGBT gate-emitter capacitance; a first voltage-controlled voltage source E is placed between the second node 2 and the first node 1 GC A constant first capacitor C is connected in series GC0 Used to characterize the IGBT gate-collector capacitance; a second voltage-controlled voltage source E is placed between the first node 1 and the third node 3 CE A second constant capacitor C is connected in series CE0 This is used to characterize the collector-emitter capacitance of the IGBT. In the second circuit model, the first current source G0, in parallel with the RC circuit module, is used to identify when the model enters the turn-on / turn-off phase during simulation. The first voltage source V1 and the second voltage source V0 are set to zero to detect the corresponding branch currents and are then incorporated into the corresponding function expressions.

[0064] like Figure 4 As shown, the modeling method of the insulated gate bipolar transistor includes:

[0065] S210, obtaining capacitance test data between the gate and collector of the insulated gate bipolar transistor. S220, establishing a first function based on the first circuit model and the second circuit model:

[0066] E GC =V 12 -f(V 12 ) / C0;

[0067] Among them, E GC is the first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; f(V 12 ) is the first sub-function, the first sub-function f(V 12 ) According to the voltage V between the first node and the second node 12 OK; C0 is the fourth capacitor.

[0068] Specifically, C GC.dynamic It can also represent the port equivalent capacitance. The derivation process of the port equivalent capacitance can be expressed by the following formula:

[0069]

[0070] From formula (3), we can see that the port equivalent capacitance C GC.dynamic The final expression is the first subfunction f(V 12 ) in the form of the first-order derivative of .

[0071] In an optional embodiment of the present invention, the first sub-function f(V 12 ) According to the voltage V between the first node and the second node 12 Determine, including:

[0072] When the voltage V between the first node and the second node 12 When it is less than or equal to zero, the first sub-function f(V 12 ) is equal to 0; when the voltage V between the first node and the second node 12 When it is greater than zero, the first subfunction is: Among them, C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG * is the first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient.

[0073] Specifically, when the voltage V between the first node and the second node 12 When it is less than or equal to zero, the voltage V between the IGBT gate and collector is GC <0, the first subfunction f(V 12 )=0, then the port equivalent capacitance C GC.dynamic Equal to the first capacitor C GC0 The first capacitor C GC0 is the equivalent capacitance of the port when the voltage across the capacitor is biased to 0 V to ensure the continuity of the function.

[0074] When the voltage V between the first node and the second node 12 When it is greater than zero, the voltage V between the IGBT gate and collector GC >0, the first subfunction is: Among them, C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG * is the first adjustment factor of the voltage between the collector and gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient. When the bias voltage across the capacitor is larger, the exponential function part is smaller. Its physical meaning is that the larger the bias voltage of the device, the wider the depletion region and the smaller the capacitance. The first adjustment factor V CG * and the first fitting coefficient mjco can be obtained through parameter extraction software.

[0075] S230 , determining a state of the insulated gate bipolar transistor according to a current relationship between the first circuit model and the second circuit model.

[0076] Specifically, the current I between the collector and emitter in the IGBT model can be captured by detecting the current of the first node 1 and the fifth node 5 on the branch by setting the zero voltage source. CE , that is, the current I(V1) flowing through the first voltage source V1, and let the current I(G0) of the first current source be equal to the current I(V1) flowing through the first voltage source V1. When the device is in the on state, the current I between the collector and the emitter CEIt gradually increases with time. In the second circuit model, it is manifested as the first current source G0 continuously charging the constant fourth capacitor C0 and also generating current on the first resistor R0. At this time, I(G0)=I(V0)+I(C0), and I(V0) is the current flowing through the second voltage source V0; when the device is turned off, the current generated by the first current source G0 gradually decreases, and the fourth capacitor C0 begins to discharge to the outside, generating a current on the branch where the seventh node 7 and the ninth node 9 are located, flowing through the first resistor R0 and being detected by the second voltage source V0. At this time, the loop satisfies: I(V0)=I(G0)+I(C0).

[0077] Therefore, the state of the IGBT device can be determined based on the magnitude relationship between the current of the first current source G0 and the current flowing through the second voltage source V0.

[0078] In an optional embodiment of the present invention, the state of the insulated gate bipolar transistor is determined based on the current relationship between the first circuit model and the second circuit model, including: when the difference between the current of the first current source and the current flowing through the second voltage source is greater than or equal to zero, determining that the insulated gate bipolar transistor is in the on state; when the difference between the current of the first current source and the current flowing through the second voltage source is less than zero, determining that the insulated gate bipolar transistor is in the off state; wherein the current of the first current source is equal to the current flowing through the first voltage source.

[0079] Specifically, when the difference between the current I(G0) of the first current source and the current I(V0) flowing through the second voltage source V0 is greater than or equal to zero, it is determined that the IGBT is in the on state; when the difference between the current I(G0) of the first current source and the current I(V0) flowing through the second voltage source V0 is less than zero, it is determined that the IGBT is in the off state.

[0080] S240 : Determine a piecewise function according to the first function and the state of the insulated gate bipolar transistor.

[0081] In an optional embodiment of the present invention, determining the piecewise function according to the first function and the state of the insulated gate bipolar transistor includes:

[0082]

[0083] Among them, E GC is the first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG * is the first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient; C0 is the fourth capacitance; V CG*′ is the second adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco' is the second fitting coefficient; I(G0) is the current of the first current source; and I(V0) is the current flowing through the second voltage source.

[0084] S250 , extracting parameters of the piecewise function based on the capacitance test data to describe capacitance changes of the insulated gate bipolar transistor during a turn-on and / or turn-off process.

[0085] Specifically, the IGBT on / off process is identified by connecting the current source in parallel with the RC circuit module in the second circuit model, and then the C GC.dynamic Different features of the turn-on / turn-off process are described separately, which avoids the seesaw effect of accurate turn-on process and inaccurate turn-off process or inaccurate turn-on process and accurate turn-off process during the fitting process.

[0086] Figure 7 FIG. 1 is a flow chart of another insulated gate bipolar transistor modeling method provided according to an embodiment of the present invention. Figure 7 As shown, the modeling method of the insulated gate bipolar transistor includes:

[0087] S310: Build a switch test circuit, test and obtain first test data; wherein the first test data includes the voltage between the collector and the emitter, the voltage between the gate and the emitter, and the gate current.

[0088] Specifically, the switch test circuit can be a dynamic parameter test (DPT) circuit. A DPT circuit is a specialized test system used to evaluate the electrical characteristics of electronic components (such as transistors or sensors) under dynamic operating conditions. Its core purpose is to simulate the signal variation scenarios (such as high-frequency clocks, pulse signals, or load fluctuations) encountered by the device during actual operation and accurately measure its dynamic parameters (such as switching delay, power consumption, or frequency response). The DPT circuit can be composed of a power supply and power supply control module, a signal stimulus generation module, a load simulation module, a measurement and data acquisition module, and an environmental control module. The power supply and power supply control module provides a stable and adjustable power supply voltage, supporting the simulation of voltage fluctuations (such as ripple or transients) during dynamic testing. The signal stimulus generation module is used to generate input signals (such as clocks, data pulses, or analog signals) that meet test conditions and control parameters such as signal frequency, amplitude, or edge time. The load simulation module is used to simulate the load effects of the device in an actual circuit, including capacitance, resistance, and current load. The measurement and data acquisition module is used to acquire the device's dynamic response signals in real time and convert them into analyzable data (such as voltage, current, or timing waveforms). The environmental control module is used to control the test environment parameters to ensure that the test conditions meet the requirements of the data sheet.

[0089] After building the switch test circuit, set the bus voltage and current when switching according to the device voltage and current level or application scenario simulation requirements, test and obtain the first test data. The first test data includes the voltage V between the collector and emitter. CE , the voltage between the gate and emitter V GE and the gate current I G The first test data also includes the current I between the collector and the emitter CE .

[0090] S320 , calculating capacitance test data between the gate and collector of the insulated gate bipolar transistor according to the first test data.

[0091] Specifically, the following relationship can be obtained based on the switch test circuit:

[0092] I G =I GC +I GE (4);

[0093]

[0094] Among them, I GC is the current between the gate and the collector; I GE is the current between the gate and the emitter; C GE is the capacitance between the gate and the emitter; VGE is the voltage between the gate and the emitter; C GC.dynamic is the capacitance test data between the gate and collector of the insulated gate bipolar transistor; GC.dynamic is the current test data between the gate and collector of the insulated gate bipolar transistor; V CE is the voltage between the collector and emitter.

[0095] In an optional embodiment of the present invention, the capacitance test data between the gate and the collector of the insulated gate bipolar transistor is calculated according to the following formula:

[0096]

[0097] Among them, C GC.dynamic is the capacitance test data between the gate and collector of the insulated gate bipolar transistor; G is the gate current; C GE is the third capacitor; V GE is the voltage between the gate and the emitter; V CE is the voltage between the collector and emitter.

[0098] Specifically, the expression can be calculated by the above formula (4), formula (5) and formula (6). Through this formula, the capacitance test data C between the gate and collector of the insulated gate bipolar transistor can be obtained according to the measured first test data. GC.dynamic .

[0099] S330 , process the test data and convert the independent variable from a time variable to a voltage change between the collector and the gate.

[0100] Specifically, the test data is processed and the independent variable is converted from a time variable to the voltage V between the collector and the gate. CG The variation is convenient for parameter extraction.

[0101] S340: Construct a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the on-phase and the off-phase according to the preset circuit model.

[0102] S350 , extracting parameters of the piecewise function based on the capacitance test data to describe capacitance changes of the insulated gate bipolar transistor during a turn-on and / or turn-off process.

[0103] Figure 8 FIG. 1 is a schematic structural diagram of a modeling device for an insulated gate bipolar transistor according to an embodiment of the present invention. Figure 8 As shown, the modeling device of the insulated gate bipolar transistor includes:

[0104] The capacitance test data acquisition module 100 is used to acquire capacitance test data between the gate and collector of an insulated gate bipolar transistor.

[0105] The piecewise function construction module 200 is used to construct a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the on-phase and the off-phase according to a preset circuit model.

[0106] The parameter extraction module 300 is used to extract parameters of the piecewise function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process.

[0107] The insulated gate bipolar transistor modeling device according to the embodiment of the present invention is used to execute the insulated gate bipolar transistor modeling method according to any embodiment of the present invention, and has corresponding beneficial effects.

[0108] Figure 9 1 is a schematic structural diagram of an insulated gate bipolar transistor modeling device for implementing the insulated gate bipolar transistor modeling method according to an embodiment of the present invention. Figure 9 As shown, the insulated gate bipolar transistor modeling device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the insulated gate bipolar transistor modeling device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0109] Multiple components in the insulated gate bipolar transistor modeling device 10 are connected to an I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the insulated gate bipolar transistor modeling device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0110] The processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors for running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the insulated gate bipolar transistor modeling method.

[0111] In some embodiments, the modeling method of the insulated gate bipolar transistor can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the modeling device 10 of the insulated gate bipolar transistor via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the modeling method of the insulated gate bipolar transistor described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the modeling method of the insulated gate bipolar transistor in any other appropriate manner (for example, by means of firmware).

[0112] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0113] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0114] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0115] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0116] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0117] A computing system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. The client-server relationship arises through computer programs running on the respective computers and establishing a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, a host product within a cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosts and virtual private server (VPS) services.

[0118] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0119] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A modeling method for an insulated gate bipolar transistor, characterized in that: include: Obtaining capacitance test data between the gate and collector of an insulated gate bipolar transistor; Constructing a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the on-phase and the off-phase according to a preset circuit model; Parameters are extracted from the piecewise function based on the capacitance test data to describe capacitance changes of the insulated gate bipolar transistor during a turn-on and / or turn-off process.

2. The modeling method of the insulated gate bipolar transistor according to claim 1, wherein: The preset circuit model includes a first circuit model and a second circuit model; the first circuit model includes an insulated gate bipolar transistor, a first voltage-controlled voltage source, a first capacitor, a second voltage-controlled voltage source, a second capacitor, a third capacitor and a first voltage source; the second circuit model includes a first current source, a first resistor, a fourth capacitor and a second voltage source; the collector of the insulated gate bipolar transistor is connected to one end of the first voltage source, the other end of the first voltage source is connected to one end of the first capacitor and one end of the second capacitor, and the connection point is a first node; the other end of the first capacitor is connected to one end of the first voltage-controlled voltage source; the other end of the first voltage-controlled voltage source is connected to the gate of the insulated gate bipolar transistor and one end of the third capacitor, and the connection point is a second node; the other end of the third capacitor is connected to the emitter of the insulated gate bipolar transistor and one end of the second voltage-controlled voltage source; the other end of the second voltage-controlled voltage source is connected to the other end of the second capacitor; one end of the first current source is connected to one end of the second voltage source and one end of the fourth capacitor; The other end of the second voltage source is connected to one end of the first resistor; the other end of the first resistor is connected to the other end of the first current source and the other end of the fourth capacitor and is grounded; The step of constructing a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the on-phase and the off-phase according to a preset circuit model includes: Establish a first function according to the first circuit model and the second circuit model: E GC =V 12 -f(V 12 ) / C0; Among them, E GC is the first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; f(V 12 ) is the first sub-function, the first sub-function f(V 12 ) According to the voltage V between the first node and the second node 12 Determine; C0 is the fourth capacitor; determining a state of the insulated gate bipolar transistor according to a current relationship between the first circuit model and the second circuit model; The piecewise function is determined according to the first function and a state of the insulated gate bipolar transistor.

3. The modeling method of the insulated gate bipolar transistor according to claim 2, wherein: Determining the state of the insulated gate bipolar transistor according to the current relationship between the first circuit model and the second circuit model includes: When a difference between a current of the first current source and a current flowing through the second voltage source is greater than or equal to zero, determining that the insulated gate bipolar transistor is in an on state; When the difference between the current of the first current source and the current flowing through the second voltage source is less than zero, it is determined that the insulated gate bipolar transistor is in an off state; wherein the current of the first current source is equal to the current flowing through the first voltage source.

4. The modeling method of the insulated gate bipolar transistor according to claim 3, characterized in that: The first sub-function f(V 12 ) According to the voltage V between the first node and the second node 12 Determine, including: When the voltage V between the first node and the second node 12 When the first sub-function f(V 12 ) is equal to 0; When the voltage V between the first node and the second node 12 When is greater than zero, the first sub-function is: Among them, C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG * is the first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient; Determining the piecewise function according to the first function and the state of the insulated gate bipolar transistor includes: Among them, E GC is the first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; C GC0 is the first capacitor; V CG is the voltage between the collector and gate of the insulated gate bipolar transistor; V CG * is the first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is the first fitting coefficient; C0 is the fourth capacitance; V CG * ' is a second adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco' is a second fitting coefficient; I(G0) is the current of the first current source; and I(V0) is the current flowing through the second voltage source.

5. The modeling method of the insulated gate bipolar transistor according to claim 1, wherein: The obtaining of capacitance test data between the gate and collector of the insulated gate bipolar transistor includes: Building a switch test circuit, testing and obtaining first test data; wherein the first test data includes the voltage between the collector and the emitter, the voltage between the gate and the emitter, and the gate current; Capacitance test data between the gate and collector of the insulated gate bipolar transistor is calculated according to the first test data.

6. The modeling method of the insulated gate bipolar transistor according to claim 5, characterized in that: The calculating the capacitance test data between the gate and the collector of the insulated gate bipolar transistor according to the first test data includes: The capacitance test data between the gate and collector of the insulated gate bipolar transistor is calculated according to the following formula: Among them, C GC.dynamic is the capacitance test data between the gate and collector of the insulated gate bipolar transistor; G is the gate current; C GE is the third capacitor; V GE is the voltage between the gate and the emitter; V CE is the voltage between the collector and emitter.

7. The modeling method of the insulated gate bipolar transistor according to claim 5, characterized in that: After calculating the capacitance test data between the gate and the collector of the insulated gate bipolar transistor according to the first test data, the method further includes: Process the test data and convert the independent variable from a time variable to the voltage change between the collector and the gate.

8. A modeling device for an insulated gate bipolar transistor, characterized in that: include: A capacitance test data acquisition module is used to acquire capacitance test data between the gate and collector of the insulated gate bipolar transistor; A piecewise function construction module, for constructing a piecewise function of the dynamic capacitance of the insulated gate bipolar transistor in the on-phase and the off-phase according to a preset circuit model; A parameter extraction module is used to extract parameters of the piecewise function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the insulated gate bipolar transistor modeling method according to any one of claims 1 to 7 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the modeling method of the insulated gate bipolar transistor according to any one of claims 1 to 7.

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