Memory, memory reading method and memory system

Abstract

The invention provides a memory, a reading method of the memory and a storage system, and relates to the technical field of storage. The problem that the read-write accuracy of a ferroelectric memory is low is solved. The memory includes a pre-charge transistor, a potential clamping transistor, a pre-charge capacitor isolation transistor, an energy storage element, an inverter, and a plurality of ferroelectric memory cells, a first end of each ferroelectric memory cell and a plate line are coupled to a first voltage node, and a second end of each ferroelectric memory cell is coupled to a second voltage node. The second end of the ferroelectric storage unit and the first end of the potential clamping transistor are coupled to a second voltage node through a bit line, and the second end of the potential clamping transistor, the first end of the precharge transistor and the first end of the precharge capacitor isolation transistor are coupled to a third voltage node. The second end of the pre-charge capacitor isolation transistor and the first end of the energy storage element are coupled at a fourth voltage node, the second end of the energy storage element is coupled with the first end of the phase inverter, the second end of the pre-charge capacitor isolation transistor is coupled with the first voltage end, and the second end of the phase inverter is coupled with the second voltage end.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of storage technology, and more particularly to a memory, a memory reading method, and a storage system. Background Art

[0002] Ferroelectric random access memory (FRAM) is a type of memory that uses ferroelectric materials as its storage medium. Ferroelectric materials have the characteristic of generating a polarization state under an applied electric field. This polarization state can be maintained for a long time without loss. FRAM is designed based on this polarization state. The operating principle of FRAM is to use the polarization state of the ferroelectric material to ferroelectrically determine the storage state. The stored data represented by the polarization state can be stored for a long time and can be retained even after power is removed. The specific operation of data processing is as follows: During the write operation, an electric field is applied to the ferroelectric material to change its polarization direction, thereby changing the stored data. During the read operation, the state of the ferroelectric memory cell is determined by measuring the charge of the capacitor, thereby reading the data.

[0003] Currently, the accuracy of reading the storage state of a ferroelectric memory cell is low. Summary of the Invention

[0004] Embodiments of the present application provide a memory, a memory reading method, and a storage system for improving the problem of low reading and writing accuracy of ferroelectric memory.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, the present application provides a memory comprising a pre-charge transistor, a potential clamping transistor, a pre-charge capacitor isolation transistor, an energy storage element, an inverter, and a plurality of ferroelectric memory cells, wherein the first end of each ferroelectric memory cell is coupled to a plate line at a first voltage node, the second end of each ferroelectric memory cell is coupled to a second voltage node via a bit line and the first end of the potential clamping transistor, the second end of the potential clamping transistor, the first end of the pre-charge capacitor isolation transistor, and the first end of the pre-charge capacitor isolation transistor are coupled to a third voltage node, the second end of the pre-charge capacitor isolation transistor and the first end of the energy storage element are coupled to a fourth voltage node, the second end of the energy storage element is coupled to the first end of the inverter, the second end of the pre-charge transistor is coupled to the first voltage end, and the second end of the inverter is coupled to the second voltage end.

[0007] The memory provided by this application can provide the polarization current required for flipping the ferroelectric memory cell during a read operation through a precharge transistor, a potential clamping transistor, a precharge capacitor isolation transistor, an energy storage element, and an inverter, thereby ensuring a stable bitline voltage. This avoids the coupling effect between bitlines caused by bitline voltage fluctuations, thereby improving the read and write performance of the memory.

[0008] In one possible implementation, the voltage of the second voltage node is higher than the voltage of the first voltage node. The memory provided herein, by setting the voltage of the second voltage node higher than the voltage of the first voltage node, allows the bit line voltage to be lower than the operating voltage during a read operation, thereby improving the read and write accuracy of the memory.

[0009] In one possible embodiment, the memory further includes an amplifier, wherein an input terminal of the amplifier is coupled to a fourth voltage node, and the amplifier is configured to determine the storage state of the ferroelectric memory cell based on a reference voltage and a voltage at the fourth voltage node. The memory provided herein uses the node voltage of the energy storage element as a basis for determining the storage state of the memory cell, rather than the node voltage of the bitline parasitic capacitance. Therefore, the memory is not affected by the capacitance of the bitline parasitic capacitance, further improving the read and write performance of the memory.

[0010] In a possible implementation, the energy storage element is a capacitor.

[0011] In a possible implementation, the ferroelectric memory cell includes any one of a single-transistor single-ferroelectric capacitor 1T1C, a single-transistor multi-ferroelectric capacitor 1TNC, a single-selector single-ferroelectric capacitor 1S1C, and a chain type.

[0012] In a second aspect, the present application provides a memory reading method, which is applied to the memory of the first aspect, wherein the memory includes a precharge transistor, a potential clamping transistor, a precharge capacitor isolation transistor, an energy storage element, an inverter, and a plurality of ferroelectric memory cells, wherein a first end of each ferroelectric memory cell is coupled to a plate line at a first voltage node, a second end of each ferroelectric memory cell is coupled to a first end of the potential clamping transistor at a second voltage node via a bit line, a second end of the potential clamping transistor, a first end of the precharge transistor, and a first end of the precharge capacitor isolation transistor are coupled to a third voltage node, a second end of the precharge capacitor isolation transistor and a first end of the energy storage element are coupled to a fourth voltage node, and a second end of the energy storage element is coupled to a first end of the inverter;

[0013] The method includes: in a pre-charging phase, turning on a pre-charging transistor, a potential clamping transistor, and a pre-charging capacitor isolation transistor to charge the bit line parasitic capacitance and the energy storage element, raising the voltages of the second voltage node and the fourth voltage node to a first voltage value; in a coupling phase, turning off the pre-charging capacitor isolation transistor, raising the voltage of the fourth voltage node to a second voltage value through an inverter, turning on the pre-charging capacitor isolation transistor; in a reading phase, applying a turn-on voltage to a word line coupled to a ferroelectric memory cell, the energy storage element providing a flip current to the ferroelectric memory cell to maintain the voltage of the second voltage node at the first voltage value, obtaining the voltage of the fourth voltage node, and determining the storage state of the ferroelectric memory cell according to a reference voltage and the voltage of the fourth voltage node.

[0014] In a possible implementation, the method further includes: in the reading phase, if the voltage of the fourth voltage node is less than or equal to a threshold, turning on the pre-charging transistor to charge the energy storage element.

[0015] In a possible implementation, after determining the storage state of the ferroelectric memory cell according to the reference voltage and the voltage of the fourth voltage node, the method further includes: in a decoupling phase, reducing the voltage of the fourth voltage node to a first voltage value.

[0016] In a third aspect, the present application provides a storage system comprising a memory controller and the memory of the first aspect, wherein the memory controller is configured to control the memory.

[0017] In a fourth aspect, the present application provides a computer-readable storage medium, which stores computer-executable instructions; after the computer-executable instructions are executed, any method of the second aspect can be implemented.

[0018] In a fifth aspect, the present application provides an electronic device comprising a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions, and when the executable instructions are executed by the processor, any method of the second aspect can be implemented.

[0019] The technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any of its embodiments and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a storage system provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of a memory provided in an embodiment of the present application Figure 1 ;

[0023] Figure 4 A schematic diagram of a read and write operation waveform provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the bit line voltage distribution corresponding to the storage state provided in the embodiment of the present application;

[0025] Figure 6 A schematic diagram of a memory provided in an embodiment of the present application Figure 2 ;

[0026] Figure 7 A schematic diagram of a memory provided in an embodiment of the present application Figure 3 ;

[0027] Figure 8 A schematic diagram of a memory provided in an embodiment of the present application Figure 4 ;

[0028] Figure 9 A schematic diagram of a memory provided in an embodiment of the present application Figure 5 ;

[0029] Figure 10 A schematic diagram of a memory provided in an embodiment of the present application Figure 6 ;

[0030] Figure 11 A schematic diagram of a memory provided in an embodiment of the present application Figure 7 ;

[0031] Figure 12 A flowchart of a reading method provided in an embodiment of the present application;

[0032] Figure 13 Another schematic diagram of read and write operation waveforms provided for an embodiment of the present application. DETAILED DESCRIPTION

[0033] The terms used in the following examples are only for the purpose of describing specific embodiments and are not intended to be limiting of the present application. As used in the specification and appended claims of the present application, the singular expressions "one", "a kind of", "above", "the" and "this" are intended to also include the "one or more" forms of expression of examples, unless there is clearly an opposite indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The character " / " generally represents that the objects before and after the association are a kind of "or" relationship.

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0035] In the following, the terms "first," "second," etc. are used for convenience of description only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more. For example, "plurality of processing units" refers to two or more processing units.

[0036] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "electrical connection" can mean direct electrical connection or indirect electrical connection through an intermediate medium.

[0037] In the embodiments of the present application, the term "module" generally refers to a functional structure divided according to logic. The "module" can be implemented by pure hardware or a combination of hardware and software. In the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, B exists alone, and A and B exist at the same time.

[0038] In the embodiments of this application, words such as "exemplary" or "exemplary" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "exemplary" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "exemplary" is intended to present the relevant concepts in a concrete manner.

[0039] The present application provides an electronic device. The electronic device may include a mobile phone, a tablet computer, a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and other electronic products, as well as a mobile base station, WiFi, and other communication equipment. The present application does not impose any particular restrictions on the specific form of the above-mentioned electronic device.

[0040] The following is a structural diagram of an electronic device used in the implementation of this application, taking a mobile phone as an example. Figure 1The mobile phone may include: a processor 110, an external memory interface 120, a storage system 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc.

[0041] It should be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0042] The storage system 121 can be used to store computer executable program codes, and the executable program codes include instructions. The processor 110 executes various functional applications and data processing of the mobile phone 200 by running the instructions stored in the storage system 121. For example, in an embodiment of the present application, the processor 110 can execute the instructions stored in the storage system 121, and the storage system 121 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area can store data created during the use of the mobile phone 200 (such as audio data, a phone book, etc.), etc.

[0043] See Figure 2 , Figure 2 A schematic diagram of a storage system provided in an embodiment of the present application is provided. The storage system 121 may include a memory controller 1210 and at least one memory 1211 . The memory controller 1210 is coupled to the memory 1211 to control the memory 1211 to store data.

[0044] See Figure 3 , Figure 3A schematic diagram of the structure of a memory provided in an embodiment of the present application, wherein the memory includes a memory array composed of a plurality of ferroelectric memory cells, and the structure of the ferroelectric memory cell is described as a single transistor and a single ferroelectric capacitor (1T1C). The gate of each transistor can be coupled to a word line (WL), and the drain of each transistor can be coupled to a bit line (BL). The ferroelectric capacitor can be a parallel plate capacitor comprising upper and lower plates, wherein the lower plate of the ferroelectric capacitor can be coupled to the source of the transistor, and the upper plate of the ferroelectric capacitor can be coupled to a plate line (PL), and the bit line and the word line are arranged orthogonally. The other end of the bit line is coupled to an input end of an amplifier (SA), and the other input end of the amplifier can be coupled to a power supply end for inputting a reference voltage V REF In an integrated circuit, the length of the bit line is long, so there will be a parasitic capacitance C between the bit line and the adjacent bit line. BL , but the bit line parasitic capacitance C BL It is not a real component in the circuit. The parasitic capacitance C BL The size of the bit line parasitic capacitance C is related to the number of ferroelectric memory cells coupled to the bit line. The more ferroelectric memory cells are coupled to the bit line, the larger the bit line parasitic capacitance C is. BL The larger the bit line parasitic capacitance C BL It can be equivalently regarded as a capacitor with one end coupled to the bit line and the other end coupled to the ground. BL That is equivalent to the bit line parasitic capacitance C BL The amplifier compares the voltage of the node coupled to the bit line with the reference voltage V REF and the bit line voltage V BL The size relationship determines the storage state of the ferroelectric memory cell.

[0045] Currently, when reading the storage state of a ferroelectric memory cell, a voltage reading method is used. For example, see Figure 4 As shown in the operation waveform diagram, in the voltage reading method, the bit line potential is first precharged to ground (GND), and the bit line is placed in a floating state, and then the plate line potential is charged to a high potential V PL , and then apply a turn-on voltage to the word line, so that the transistor of the ferroelectric memory cell to be read is in the on state. Since the voltage of the plate line is higher than the voltage of the bit line, the ferroelectric capacitor is equivalent to being in an electric field, and the direction of the electric field is from the plate line to the bit line. Since the ferroelectric memory cell has two polarization states, when the polarization state of the ferroelectric memory cell is consistent with the direction of the applied electric field, the bit line voltage V BL Slightly raise to V BL0When the polarization state of the ferroelectric memory cell is inconsistent with the direction of the applied electric field, the polarization state of the ferroelectric memory cell will be flipped, thereby generating a flip current, which flows through the bit line and increases the bit line voltage V BL Raised significantly to V BL1 . Reference voltage V REF The magnitude of the bit line voltage V BL0 and bit line V BL1 Therefore, by comparing the reference voltage and the bit line voltage V BL The relationship between the magnitude of the bit line voltage and the bit line voltage can be used to determine the storage state of the memory cell. It can be seen that in the voltage reading method, the bit line voltage will exhibit two different voltage change trends due to the two storage states of the ferroelectric memory cell. That is, during the read operation, the bit line voltage is not constant but varies. Therefore, during the write-back operation, the change trend of the bit line voltage is asymmetric with that during the read operation.

[0046] For example, see Figure 5 The bit line voltage distribution diagram corresponding to the storage state shown in the figure is as follows: REF Can be 1.0V, when the line voltage V BL When it is 0.5V, the bit line voltage V BL Less than the reference voltage V REF When the line voltage V BL When it is 1.5V, the bit line voltage V BL Greater than the reference voltage V REF At this time, the storage state corresponding to the ferroelectric memory cell can be a logic value "1".

[0047] In the voltage reading method, the bit line voltage is variable, and when the voltage of the bit line changes, it affects the adjacent bit lines, resulting in a coupling effect between the bit lines, which affects the storage window of the ferroelectric memory. In addition, in the voltage reading method, the reading and writing of the memory is also affected by the capacitance value of the bit line parasitic capacitance. When the bit line parasitic capacitance is large, the storage window of the ferroelectric memory is reduced, resulting in a decrease in the accuracy of the memory when reading the storage state. When the bit line parasitic capacitance is small, the bit line voltage is raised higher, which reduces the voltage difference between the upper and lower plates of the ferroelectric capacitor, thereby causing the ferroelectric capacitor to flip slowly and incompletely.

[0048] Therefore, in order to reduce the coupling effect between bit lines and improve the read and write performance of the memory, the embodiment of the present application provides a memory, see Figure 6A current reading module can be added between the bit line and the amplifier. The current reading module can be used to ensure that the bit line voltage is stable during the read operation, so that the ferroelectric memory cell is in a constant voltage flip. The constant voltage flip can provide a more stable polarization state, making the polarization state of the ferroelectric memory cell more reliable and less susceptible to external interference.

[0049] See Figure 7 , the specific circuit implementation of the current reading module may include a pre-charge transistor, a potential clamping transistor, a pre-charge capacitor isolation transistor, an energy storage element, an inverter and a plurality of ferroelectric memory cells. The pre-charge transistor, the potential clamping transistor and the pre-charge capacitor isolation transistor may be an N-channel MOS transistor or a P-channel MOS transistor, and the pre-charge transistor, the potential clamping transistor and the pre-charge capacitor isolation transistor are all N-channel MOS transistors, and the threshold voltage is the same for explanation. The first end of each ferroelectric memory cell is coupled to the plate line at node 1, and the second end of each ferroelectric memory cell is coupled to the drain of the potential clamping transistor at node 2 through the bit line. The source of the pre-charge transistor can be coupled to the first voltage terminal, and the first voltage terminal can be V DD The drain of the pre-charge transistor can be coupled to the source of the potential clamp transistor and the source of the pre-charge capacitor isolation transistor at node 3. The drain of the pre-charge capacitor isolation transistor can be coupled to one end of the energy storage element at node 4. The other end of the energy storage element is coupled to one end of the inverter. The other end of the inverter is coupled to the second voltage end. The second voltage end can be V Boost end.

[0050] The working principle of the memory of the application is described in detail below. When reading the storage state of the ferroelectric memory cell, the entire reading process can be divided into three stages.

[0051] The first stage is the pre-charge stage. In the pre-charge stage, the gate voltage provided to the pre-charge transistor, the potential clamping transistor and the pre-charge capacitor isolation transistor is controlled so that the pre-charge transistor, the potential clamping transistor and the pre-charge capacitor isolation transistor are turned on, and the bit line parasitic capacitance and the energy storage element are charged to raise the voltage of node 2 and node 4.

[0052] The second stage is the coupling stage. In the coupling stage, the pre-charge capacitor isolation transistor is turned off, and the upper and lower plate potentials of the charging capacitor are coupled upward through the inverter, and then the pre-charge capacitor isolation transistor is turned on again, thereby further raising the voltage of node 4.

[0053] The third phase is the read phase. During this phase, a turn-on voltage is applied to the word line coupled to the ferroelectric memory cell, turning on the ferroelectric memory cell's transistor. Then, due to the potential difference, the energy storage element and the ferroelectric capacitor share dielectric charge, causing the voltage at node 4 to drop, providing a polarization current for the ferroelectric capacitor. Furthermore, during the read phase, the voltage at node 2 remains stable, meaning the bit line voltage remains constant.

[0054] The memory provided in the present application ensures that the bit line voltage remains stable during a read operation, thereby avoiding the coupling effect between bit lines and further improving the read and write performance of the memory.

[0055] During the read operation, the voltage of node 1 is always 0, and the voltage of node 2 is always stable and unchanged. The voltage of node 2 is always higher than the voltage of node 1, thereby ensuring that the polarization current required for the ferroelectric memory cell to flip can be provided by the energy storage element.

[0056] Continue reading Figure 7 The memory further includes an amplifier, one input terminal of the amplifier is coupled to node 4, and the other input terminal is used to input a reference voltage. The amplifier is configured to determine the storage state of the ferroelectric memory cell according to the reference voltage and the voltage of node 4.

[0057] When the storage state of the ferroelectric memory cell is a logical value of "1," the energy storage element only needs to share dielectric charge with the ferroelectric capacitor. Therefore, the voltage drop of the energy storage element is small, and the voltage drop of the fourth voltage node is low. In other words, the voltage of the fourth voltage node is greater than the reference voltage. When the storage state of the ferroelectric memory cell is a logical value of "0," the charging capacitor provides the polarization current required for the ferroelectric capacitor to flip. Therefore, the voltage drop of the energy storage element is large, and the voltage drop of the fourth voltage node is high. In other words, the voltage of the fourth voltage node is less than or equal to the reference voltage.

[0058] The memory provided in the present application uses the node voltage of the energy storage element as the basis for determining the storage state of the memory cell, rather than the node voltage of the bit line parasitic capacitance. Therefore, it is not affected by the capacitance value of the bit line parasitic capacitance, which greatly reduces the design difficulty and volume of the memory, and can more accurately read the storage state of the memory, further improving the read and write performance of the memory.

[0059] The primary function of energy storage components is to store energy in circuits and provide the switching current for ferroelectric memory cells. Capacitors are a common and important type of energy storage component. As an energy storage element, capacitors are widely used in many electronic systems. In AC circuits, capacitors smooth voltage fluctuations and provide a stable output voltage. In DC circuits, capacitors provide instantaneous energy supply, ensuring stable circuit operation.

[0060] The ferroelectric memory cell of the memory provided by the present application can be implemented in a variety of ways. It is understandable that the connection relationship between the ferroelectric memory cell and the plate line and the word line is different under different structures. In a feasible embodiment, the ferroelectric memory cell can be as follows Figure 7 The 1T1C structure shown can also be Figure 8 The structure of one selector one capacitor (1S1C) can also be as shown. Figure 9 The one transistor n capacitor (1TnC) structure shown in FIG. Figure 10 The chain-type single-transistor single-ferroelectric capacitor shown in Figure 1 is a 1TnC structure. In the 1TnC structure, a specific 1TnC ferroelectric memory cell is selected by the wordline potential voltage, and then the target ferroelectric capacitor among the n ferroelectric capacitors is selected by the plateline voltage. The remaining ferroelectric capacitors are in a semi-selected state. In the chain-type single-transistor single-ferroelectric capacitor structure, which includes multiple parallel 1T1C structures, a ferroelectric memory cell is selected by the gate voltage of the parallel transistors. When the transistor is turned off, the ferroelectric memory cell is selected. When the remaining transistors in the chain are turned on, the ferroelectric capacitor connected in parallel with it is not selected and is short-circuited by the transistor source and drain, thus avoiding crosstalk.

[0061] In one possible implementation, see Figure 11 The memory provided by the present application may also include a ferroelectric memory having a two transistor two capacitor (2T2C) architecture. In the ferroelectric memory of the 2T2C architecture, one end of the two ferroelectric capacitors is coupled to the same plate line, and the other end is coupled to different bit lines through a transistor. The two bit lines are connected to the two input terminals of the amplifier. The two ferroelectric capacitors store opposite polarization states at the same time, and the two transistors are connected to the same gate and turned on and off at the same time. The precharge transistors of the two bit lines are connected to the same V DD At the end, the precharge transistors charge the bitline parasitic capacitance and energy storage element of their respective branches through the voltage clamping transistors and precharge capacitance isolation transistors in their respective branches. The inverters can be shared, simultaneously coupling the potential of the energy storage elements in their respective branches upward. Because the two bitline branches store different state information and serve as a reference for each other, the storage window can be doubled.

[0062] The following is an introduction to the reading method provided in the embodiments of the present application.

[0063] like Figure 12 As shown, Figure 12 This is a flow chart of a memory reading method provided in an embodiment of the present application. The method may include S1201, S1202, and S1203.

[0064] The specific steps include:

[0065] S1201: In the pre-charge phase, the pre-charge transistor, the potential clamping transistor, and the pre-charge capacitance isolation transistor are turned on to charge the bit line parasitic capacitance and the energy storage element, and raise the voltages of the second voltage node and the fourth voltage node to the first voltage value.

[0066] The main purpose of the pre-charge phase is to increase the voltage of the second voltage node and the fourth voltage node. First, by controlling the gate voltage provided to the pre-charge transistor, the potential clamping transistor and the pre-charge capacitor isolation transistor, the pre-charge transistor, the potential clamping transistor and the pre-charge capacitor isolation transistor are turned on, and the parasitic capacitance of the bit line and the energy storage element are charged. The energy storage element is described below as a charging capacitor. The voltage of the second voltage node is clamped at V by the potential clamping transistor. BLCLAMP -V th , V BLCLAMP refers to the gate voltage of the potential clamping transistor, while V th Refers to the threshold voltage of the potential clamping transistor. In order to ensure that during the read operation, the pre-charge capacitor isolation transistor provides the polarization current, while the non-potential clamping transistor provides the polarization current, it is necessary to ensure that the gate voltage V ISO Greater than the gate voltage of the precharge transistor V PRE , so the pre-charge capacitor isolates the gate voltage of the transistor V ISO Need to follow the gate voltage V of the precharge transistor PRE Make dynamic changes.

[0067] For example, V DD The voltage at the end can be 3.3V, then the gate voltage of the precharge transistor V PRE It can be 2.1V, the threshold voltage of the pre-charge transistor is 0.3V, then the voltage of the third voltage node is clamped at about 1.8V, and the gate voltage of the potential clamping transistor V BLCLAMP It can be 1.8V, and the threshold voltage of the pre-charge transistor is 0.3V, so the voltage of the second voltage node is clamped at about 1.5V. The gate voltage of the pre-charge capacitor isolation transistor needs to be greater than 2.1V, so the gate voltage V ISO It can be 2.5V, so the voltage of the fourth voltage node can be 1.8V.

[0068] S1202: In the coupling phase, the pre-charge capacitor isolation transistor is turned off, and the voltage of the fourth voltage node is raised to a second voltage value through the inverter, and the pre-charge capacitor isolation transistor is turned on.

[0069] If the coupling operation is not performed, the voltages of the third voltage node and the fourth voltage node are both 1.8V, and the charging capacitor cannot provide a flip current for the ferroelectric capacitor during the read operation. Therefore, it is necessary to further raise the voltage of the fourth voltage node to which the charging capacitor is coupled. First, turn off the pre-charge capacitor isolation transistor, and couple the upper and lower plate potentials of the charging capacitor upward through the inverter, thereby raising the voltage of the fourth voltage node. Assuming the coupling efficiency is 100%, the upper plate of the charging capacitor, that is, the fourth voltage node, will be coupled to V PRE -V th +V Boost Then the pre-charge capacitor isolation transistor is turned on again. In the instantaneous state, the voltage of the fourth voltage node is at V PRE -V th +V Boos The voltage of the third voltage node is clamped at V by the pre-charge capacitor isolation transistor. ISO -V th The voltage of the second voltage node is clamped to V by the potential clamping crystal. BLCLAMP -V th .

[0070] For example, V Boost The voltage value of the terminal can be 3V. After coupling, the voltage of the fourth voltage node will be raised from 1.8V to 4.8V, the voltage of the third voltage node will be raised to 2.2V, and the voltage of the second voltage node will be clamped at 1.5V.

[0071] S1203: In the reading phase, a turn-on voltage is applied to the word line coupled to the ferroelectric memory cell, and the charging capacitor provides a flipping current to the ferroelectric memory cell so that the voltage of the second voltage node maintains the first voltage value; the voltage of the fourth voltage node is obtained, and the storage state of the ferroelectric memory cell is determined based on the reference voltage and the voltage of the fourth voltage node.

[0072] During the process of reading the storage state of a ferroelectric memory cell, a polarization current is provided to the ferroelectric capacitor by sharing dielectric charge between the charging capacitor and the ferroelectric capacitor, thereby ensuring that the bit line voltage, i.e., the voltage at the second voltage node, remains stable, thereby causing the ferroelectric capacitor to undergo constant voltage flipping. First, a turn-on voltage is applied to a word line coupled to the ferroelectric memory cell to turn on the transistor of the ferroelectric memory cell. Then, under the action of a potential difference, the charging capacitor and the ferroelectric capacitor share dielectric charge, causing the voltage at the fourth voltage node to drop. Then, after a preset time, an amplifier is turned on, and one input terminal of the amplifier acquires the voltage of the fourth voltage node in real time, while the other input terminal acquires a reference voltage. The voltage at the fourth voltage node is compared with the reference voltage to determine the storage state of the ferroelectric memory cell.

[0073] When the storage state of the ferroelectric memory cell is a logical value "1", the charging capacitor only needs to share dielectric charge with the ferroelectric capacitor, so the voltage drop of the upper plate of the charging capacitor is small, that is, the voltage drop of the fourth voltage node is low, that is, the voltage of the fourth voltage node is greater than the reference voltage. When the storage state of the ferroelectric memory cell is a logical value "0", the charging capacitor provides the polarization current required for the ferroelectric capacitor to flip, so the voltage drop of the upper plate of the charging capacitor is large, that is, the voltage drop of the fourth voltage node is high, that is, the voltage of the fourth voltage node is less than or equal to the reference voltage. During the above operation, the voltage of the second voltage node is always clamped at V BLCLAMP -V th .

[0074] For example, the reference voltage V REF It can be 4.0V. If the voltage of the fourth voltage node is 4.2V, the storage state of the ferroelectric memory cell can be a logic value "1". If the voltage of the fourth voltage node is 3V, the storage state of the ferroelectric memory cell can be a logic value "0", and the voltage of the second voltage node is always clamped at 1.5V.

[0075] To ensure that the charging capacitor does not over-discharge, in a feasible implementation, the method further includes: in the reading phase, if the voltage of the fourth voltage node is less than or equal to the threshold, turning on the pre-charging transistor to charge the charging capacitor.

[0076] Due to the two polarization states of the ferroelectric capacitor, two different discharge states will occur during the discharge of the charging capacitor. When the storage state of the ferroelectric memory cell is a logical value "1", the charging capacitor only needs to share dielectric charge with the ferroelectric capacitor, so the voltage drop of the upper plate of the charging capacitor is small, that is, the voltage drop degree of the fourth voltage node is low, so there is no need to charge the charging capacitor. When the storage state of the ferroelectric memory cell is a logical value "0", the charging capacitor provides the polarization current required for the ferroelectric capacitor to flip, so the voltage drop of the upper plate of the charging capacitor is large, that is, the voltage drop degree of the fourth voltage node is high. In order to ensure that the charging capacitor does not over-discharge, it is necessary to wait until the voltage of the fourth voltage node drops to the threshold value V PRE When the pre-charging transistor is turned off, the charging capacitor is recharged. If the pre-charging transistor is turned off, the charging capacitor can continue to over-discharge, and the voltage of the fourth voltage node will continue to drop.

[0077] In order to smoothly read the storage state of the next ferroelectric memory cell, the voltage of the fourth voltage node needs to be reduced. Only when the voltage of the fourth voltage node is reduced can the charging capacitor be smoothly charged when the storage state of the next ferroelectric memory cell is read.

[0078] In a feasible implementation, the method further includes: in the decoupling phase, reducing the voltage of the fourth voltage node to the first voltage value.

[0079] The decoupling stage may be performed before or after reading the storage state of the target ferroelectric memory cell.

[0080] After the read operation is completed, the ferroelectric memory cell needs to be written back. When the storage state of the ferroelectric memory cell is the logic value "0", the polarization state of the ferroelectric memory cell changes, and the voltage of the fourth voltage node is lower than the reference voltage. After differential amplification by the amplifier, the voltage of the fourth voltage node is set to 0 by the amplifier, and the plate line voltage is charged to V PL , plate line voltage V PL Can be equal to V BLCLAMP -V th , write back the storage state "0". When the storage state of the ferroelectric memory cell is the logic value "1", the polarization state of the ferroelectric memory cell does not flip, the voltage of the fourth voltage node is higher than the reference voltage, and after differential amplification by the amplifier, the voltage of the fourth voltage node is pulled to V DD , the potential clamp transistor still clamps the bit line voltage at V BLCLAMP -Vth, the potential is the same as the plate line voltage V PL The storage state of the ferroelectric memory cell maintains the logic value "1".

[0081] See Figure 13 , the operating waveform diagram of this application can be as follows Figure 13 As shown, it can be seen that during the entire read operation, the bit line voltage remains stable, thereby avoiding the coupling effect between bit lines and improving the read and write performance of the memory.

[0082] An embodiment of the present application further provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the driving method of the display device in the above-mentioned embodiment.

[0083] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the display device driving method executed by the electronic device in the above-mentioned embodiment.

[0084] In addition, an embodiment of the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor can execute the computer execution instructions stored in the memory to enable the chip to execute the driving method of the display device executed by the electronic device in the above-mentioned method embodiments.

[0085] Among them, the display device, display equipment, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0086] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0087] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0088] Units described as separate components may or may not be physically separate, and components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0089] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0090] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for making a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk. The above content is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A memory, characterized in that: It includes a pre-charge transistor, a potential clamping transistor, a pre-charge capacitance isolation transistor, an energy storage element, an inverter and a plurality of ferroelectric memory cells; The first end of each ferroelectric memory cell is coupled to a plate line at a first voltage node, the second end of each ferroelectric memory cell is coupled to a first end of the potential clamping transistor at a second voltage node via a bit line, the second end of the potential clamping transistor, the first end of the precharge transistor, and the first end of the precharge capacitor isolation transistor are coupled to a third voltage node, the second end of the precharge capacitor isolation transistor and the first end of the energy storage element are coupled to a fourth voltage node, and the second end of the energy storage element is coupled to the first end of the inverter; The second terminal of the pre-charging transistor is coupled to the first voltage terminal, and the second terminal of the inverter is coupled to the second voltage terminal.

2. The memory according to claim 1, wherein The voltage of the second voltage node is higher than the voltage of the first voltage node.

3. The memory according to claim 1 or 2, characterized in that The memory further includes a differential amplifier, an input terminal of the differential amplifier is coupled to the fourth voltage node, and the differential amplifier is configured to determine a storage state of the ferroelectric memory cell according to a reference voltage and a voltage of the fourth voltage node.

4. The memory according to claim 3, wherein: The energy storage element is a capacitor.

5. The memory according to any one of claims 1 to 4, characterized in that: The ferroelectric memory cell includes any one of a single-transistor single-ferroelectric capacitor 1T1C, a single-transistor multi-ferroelectric capacitor 1TNC, a single-selector single-ferroelectric capacitor 1S1C, and a chain-type single-transistor single-ferroelectric capacitor Chain 1T1C.

6. A method for reading a memory, characterized in that: Applied to a memory, the memory includes a precharge transistor, a potential clamping transistor, a precharge capacitance isolation transistor, an energy storage element, an inverter and a plurality of ferroelectric memory cells; The first end of each ferroelectric memory cell is coupled to a plate line at a first voltage node, the second end of each ferroelectric memory cell is coupled to a first end of the potential clamping transistor at a second voltage node via a bit line, the second end of the potential clamping transistor, the first end of the precharge transistor, and the first end of the precharge capacitor isolation transistor are coupled to a third voltage node, the second end of the precharge capacitor isolation transistor and the first end of the energy storage element are coupled to a fourth voltage node, and the second end of the energy storage element is coupled to the first end of the inverter; The method comprises: In the pre-charging stage, the pre-charging transistor, the potential clamping transistor, and the pre-charging capacitance isolation transistor are turned on to charge the energy storage element and the energy storage element, and raise the voltage of the second voltage node and the fourth voltage node to the first voltage value; In the coupling phase, the pre-charge capacitor isolation transistor is turned off, and the voltage of the fourth voltage node is raised to the second voltage value through the inverter, and the pre-charge capacitor isolation transistor is turned on; In the reading phase, a conduction voltage is applied to the word line coupled to the ferroelectric memory cell, and the energy storage element provides a polarization current to the ferroelectric memory cell so that the voltage of the second voltage node maintains the first voltage value; the voltage of the fourth voltage node is obtained, and the storage state of the ferroelectric memory cell is determined based on the reference voltage and the voltage of the fourth voltage node.

7. The reading method according to claim 6, characterized in that: The method further comprises: In the reading phase, if the voltage of the fourth voltage node is less than or equal to a threshold, the pre-charging transistor is turned on to charge the energy storage element.

8. The reading method according to claim 6 or 7, characterized in that: After determining the storage state of the ferroelectric memory cell according to the reference voltage and the voltage of the fourth voltage node, the method further includes: In the decoupling phase, the voltage of the fourth voltage node is reduced to the first voltage value.

9. A storage system, characterized in that: The device comprises a memory controller and the memory according to any one of claims 1 to 5, wherein the memory controller is configured to control the memory.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, the method according to any one of claims 6 to 8 can be implemented.

11. An electronic device, characterized in that: The method comprises a processor and a readable storage medium coupled to the processor, wherein the readable storage medium stores executable instructions. When the executable instructions are executed by the processor, the method according to any one of claims 6 to 8 can be implemented.

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