Semiconductor memory device and method for controlling semiconductor memory device

Abstract

A semiconductor memory device capable of suppressing expansion of threshold distribution even under the influence of NWI. The memory device includes: a plurality of memory cell arrays; a plurality of memory cells included in the first memory cell array; a plurality of word lines connected to the gates of the plurality of memory cells; a bit line connected to a first end of the first memory cell array; and a control circuit that executes one or more cycles in response to an instruction sequence for writing data to a first memory cell, the first memory cell being one of the memory cells connected to the first word line, each loop includes a first program action for writing data to the first memory cell and a verification action for verifying the data written to the first memory cell, the instruction sequence includes threshold voltage information, and the control circuit, after exiting the loop, controls the first memory cell based on a level of a threshold voltage set for the second memory cell connected to the second word line. It is determined whether to execute an operation of adjusting the threshold voltage of the first memory cell.

Description

Technical Field

[0001] The present embodiment relates to a semiconductor memory device and a method for controlling the semiconductor memory device. Background Art

[0002] In recent years, NAND memories have become increasingly popular as semiconductor memory devices. In such semiconductor memory devices, when data is written to a word line WLn and then to a word line WLn+1, neighboring word-line interference (NWI) occurs, causing the threshold voltage of each memory cell on the previously written word line WLn to rise.

[0003] Due to the influence of NWI, the threshold distribution of each memory cell on word line WLn widens, reducing the margin between threshold distributions and increasing the fail bit count (FBC). The influence of NWI increases as the spacing between gates decreases to increase memory density and as multi-valued memory becomes more common. Summary of the Invention

[0004] One embodiment provides a semiconductor memory device and a method for controlling the semiconductor memory device that can suppress the spread of threshold distribution even when affected by NWI.

[0005] A semiconductor memory device according to one embodiment includes: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array, one of the plurality of memory cell arrays; a plurality of word lines connected to gates of the plurality of memory cells; a bit line connected to a first end of the first memory cell array; and a control circuit configured to execute one or more loops in response to a command sequence for writing data to a first memory cell, the first memory cell being one of the memory cells connected to a first word line, one of the plurality of word lines; each loop including a first programming operation for writing data to the first memory cell and a verification operation for verifying the data written to the first memory cell; the command sequence including threshold voltage information related to a threshold voltage level to be set for a second memory cell, the second memory cell being connected to a second word line, one of the plurality of word lines adjacent to the first word line; and after exiting the loop, the control circuit determines whether to execute an operation to adjust the threshold voltage of the first memory cell based on the threshold voltage level set for the second memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing an example of the configuration of a memory system.

[0007] Figure 2Yes Figure 1 A block diagram showing an example of the configuration of the nonvolatile memory 2.

[0008] Figure 3 1 is a diagram showing a configuration example of a block of a three-dimensional memory cell array 20 .

[0009] Figure 4 Yes Figure 2 A block diagram showing an example of the configuration of the sense amplifier unit group 28 and the data register 29 in FIG.

[0010] Figure 5 Yes Figure 4 A circuit diagram showing an example of a specific configuration of the sense amplifier unit SAU in FIG.

[0011] Figure 6 This is an explanatory diagram showing 2-3-2 coding as an example of coding.

[0012] Figure 7 This is a diagram showing an example of a basic command sequence for data writing.

[0013] Figure 8 This is a diagram showing an example of potential changes of a bit line and a selected word line during a programming operation.

[0014] Figure 9 This is an explanatory diagram showing an example of a write sequence from the A to G state.

[0015] Figure 10 This is a flowchart for explaining the operation of this embodiment.

[0016] Figure 11 This is a diagram for explaining changes in threshold value distribution in the operation of this embodiment.

[0017] Description of Reference Numerals

[0018] 1…Memory system, 2…Non-volatile memory, 3…Memory controller, 4…Host device, 10…Host I / F circuit, 11…Processor, 12…RAM, 13…Buffer memory, 14…Memory I / F circuit, 15…ECC circuit, 20…Memory cell array, 21…Input / output circuit, 22…Logic control circuit, 23…Register, 24…Control circuit, 25…Voltage generation circuit, 26…Row decoder, 27…Column decoder, 28…Sense amplifier unit group, 29…Data register DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0020] In this embodiment, when writing data to the memory cells of word line WLn, the data written to the memory cells of word line WLn+1 is confirmed in advance, and the threshold of the data written to the memory cells of word line WLn is adjusted according to the data pattern, thereby suppressing the influence of NWI.

[0021] (Memory System Configuration)

[0022] Figure 1 This is a block diagram showing an example of a memory system configuration. A memory system 1 in this embodiment includes a nonvolatile memory 2 and a memory controller 3. Furthermore, the nonvolatile memory 2 may include multiple memory chips. The memory system 1 can be connected to a host device 4. The host device 4 is, for example, an electronic device such as a personal computer or a portable terminal.

[0023] The memory system 1 may be configured by mounting multiple chips constituting the memory system 1 on a motherboard equipped with the host device 4, or the memory system 1 may be configured as a system LSI (Large-Scale Integrated Circuit) or SoC (System-on-a-Chip) implemented as a single module. Examples of the memory system 1 include memory cards such as SD cards, SSDs (Solid-State-Drives), and eMMCs (embedded-Multi-Media-Cards).

[0024] The nonvolatile memory 2 is a NAND memory having a plurality of memory cells and stores data in a nonvolatile manner. The specific configuration of the nonvolatile memory 2 will be described below.

[0025] The memory controller 3, for example, responds to commands from the host device 4 to write (also called program), read, and erase data to the nonvolatile memory 2. The memory controller 3 also manages the memory space of the nonvolatile memory 2. The memory controller 3 includes a host interface (host I / F) circuit 10, a processor 11, RAM (Random Access Memory) 12, a buffer memory 13, a memory interface circuit (memory I / F) circuit 14, and an ECC (Error Checking and Correcting) circuit 15.

[0026] The host I / F circuit 10 is connected to the host device 4 via a host bus and performs interface processing with the host device 4. The host I / F circuit 10 also transmits and receives commands, addresses, and data to and from the host device 4.

[0027] The processor 11 is comprised of, for example, a CPU (Central Processing Unit). The processor 11 controls the overall operation of the memory controller 3. For example, upon receiving a write command from the host device 4, the processor 11 issues a write command corresponding to the write command from the host device 4 to the non-volatile memory 2 via the memory I / F circuit 14. The same applies to reading and erasing operations. Furthermore, the processor 11 performs various processes for managing the non-volatile memory 2, such as wear leveling.

[0028] The RAM 12 is used as a work area of ​​the processor 11 and stores firmware data loaded from the nonvolatile memory 2 and various tables created by the processor 11. The RAM 12 is composed of, for example, a DRAM or an SRAM.

[0029] The buffer memory 13 temporarily stores data transmitted from the host device 4 and temporarily stores data transmitted from the nonvolatile memory 2 .

[0030] The memory I / F circuit 14 is connected to the nonvolatile memory 2 via a bus and performs interface processing with the nonvolatile memory 2. The memory I / F circuit 14 also transmits and receives commands, addresses, and data to and from the nonvolatile memory 2.

[0031] When writing data, the ECC circuit 15 generates an error correction code for the write data, appends the error correction code to the write data, and transmits the error correction code to the memory I / F circuit 14. Furthermore, when reading data, the ECC circuit 15 uses the error correction code included in the read data to detect and / or correct errors in the read data. Alternatively, the ECC circuit 15 may be provided within the memory I / F circuit 14.

[0032] (Configuration of Nonvolatile Memory)

[0033] Figure 2 Yes Figure 1 A block diagram showing an example of the configuration of a nonvolatile memory 2 in FIG. The nonvolatile memory 2 includes a memory cell array 20, an input / output circuit 21, a logic control circuit 22, a register 23, a control circuit 24, a voltage generation circuit 25, a row decoder 26, a column decoder 27, a sense amplifier unit group 28, and a data register (data cache memory) 29.

[0034] The memory cell array 20 includes j blocks BLK0 to BLK(j-1) and a block BLKX. j is an integer greater than or equal to 1. Each of the multiple blocks BLK includes multiple memory cell transistors. The memory cell transistors constitute electrically rewritable memory cells. In order to control the voltage applied to the memory cell transistors, the memory cell array 20 is provided with multiple bit lines BL, multiple word lines WL, and a source line CELSRC. The specific structure of the block BLK will be described below.

[0035] The input / output circuit 21 and the logic control circuit 22 are connected to the memory controller 3 via a bus. The input / output circuit 21 transmits and receives signals DQ (eg, DQ0 to DQ7) to and from the memory controller 3 via the bus.

[0036] The logic control circuit 22 receives external control signals (e.g., chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, and write protect signal WPn) from the memory controller 3 via the bus. The "n" in the signal name indicates active low. The logic control circuit 22 also transmits a ready / busy signal R / Bn to the memory controller 3 via the bus.

[0037] The chip enable signal CEn is a signal used to select and enable a specific non-volatile memory 2 in a system configuration using multiple non-volatile memories 2. The chip enable signal CLE can latch the instruction sent as the signal DQ into the register 23. The address latch enable signal ALE can latch the address sent as the signal DQ into the register 23. The write enable signal WEn enables writing. The read enable signal REn enables reading. The write protect signal WPn prohibits writing and erasing. The ready / busy signal R / Bn indicates whether the non-volatile memory 2 is in a ready state (a state in which commands from the outside can be accepted) or a busy state (a state in which commands from the outside cannot be accepted) when using basic operation instructions.

[0038] The register 23 includes a command register, an address register, and a status register. The command register temporarily stores commands. The address register temporarily stores addresses. The status register temporarily stores data required for the operation of the nonvolatile memory 2. The register 23 is composed of, for example, an SRAM.

[0039] The control circuit 24 receives instructions from the register 23 and centrally controls the nonvolatile memory 2 according to a sequence based on the instructions.

[0040] The voltage generation circuit 25 receives a power supply voltage from outside the nonvolatile memory 2 and uses this power supply voltage to generate multiple voltages required for programming, reading, and erasing operations. The voltage generation circuit 25 supplies the generated multiple voltages to the memory cell array 20, the row decoder 26, the sense amplifier unit group 28, and the like.

[0041] The row decoder 26 receives the row address from the register 23 and decodes it. Based on the decoded row address, the row decoder 26 selects a word line. The word line connecting the memory cell transistors MT to which data is written and read is referred to as a selected word line. The row decoder 26 then transmits the multiple voltages required for write, read, and erase operations to the selected block BLK.

[0042] The column decoder 27 receives and decodes the column address from the register 23. The column decoder 27 supplies a specific voltage to each bit line BL based on the decoded column address.

[0043] The sense amplifier cell group 28 detects and amplifies data read from the memory cell transistor MT to the bit line BL when reading data, and supplies write data to the bit line BL when writing data.

[0044] The data register 29 temporarily stores data transmitted from the sense amplifier cell group 28 during data reading and serially transmits the data to the input / output circuit 21. Furthermore, the data register 29 temporarily stores data transmitted serially from the input / output circuit 21 during data writing and transmits the data to the sense amplifier cell group 28. The data register 29 is composed of an SRAM or the like.

[0045] (Block Structure of Memory Cell Array)

[0046] Figure 3 1 is a diagram showing a configuration example of a block of a three-dimensional memory cell array 20 . Figure 3 1 block BLK among the multiple blocks constituting the memory cell array 20. The other blocks of the memory cell array also have the same Figure 3 Same composition.

[0047] As shown in the figure, the block BLK includes, for example, four string units SU0 to SU3 (hereinafter, they are representatively referred to as string units SU). In addition, each string unit SU has a NAND string NS including a plurality of memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. In addition, the number of memory cell transistors MT included in the NAND string NS is Figure 3 The number of select gate transistors ST1 and ST2 is set to 8, but it can be more. The select gate transistors ST1 and ST2 are shown as a single transistor in the circuit, but their structure can be the same as that of the memory cell transistor. In addition, multiple select gate transistors can be used as the select gate transistors ST1 and ST2 respectively. Furthermore, dummy cell transistors can be provided between the memory cell transistor MT and the select gate transistors ST1 and ST2.

[0048] Memory cell transistors MT are connected in series between select gate transistors ST1 and ST2. Memory cell transistor MT7 on one end (bit line side) is connected to select gate transistor ST1, and memory cell transistor MT0 on the other end (source line side) is connected to select gate transistor ST2.

[0049] The gates of the select gate transistors ST1 in each of the string units SU0-SU3 are connected to select gate lines SGD0-SGD3 (hereinafter, these are representatively referred to as select gate lines SGD), respectively. Furthermore, the gates of the select gate transistors ST2 in each of the string units SU0-SU3 are connected to select gate lines SGS0-SGS3 (hereinafter, these are representatively referred to as select gate lines SGS), respectively. Furthermore, the gates of the multiple select gate transistors ST2 in each block BLK may be connected to a common select gate line SGS.

[0050] The gates of memory cell transistors MT0-MT7 within the same block BLK are commonly connected to word lines WL0-WL7. In other words, word lines WL0-WL7 are commonly connected across multiple string units SU0-SU3 within the same block BLK. In contrast, select gate line SGD is independent for each string unit SU0-SU3 within the same block BLK. The gates of memory cell transistors MTi within the same row within a block BLK are commonly connected to word line WLi.

[0051] Each NAND string NS is connected to a corresponding bit line. Therefore, each memory cell transistor MT is connected to a bit line via the select gate transistors ST1, ST2 or other memory cell transistors MT included in the NAND string NS. Generally speaking, the data of the memory cell transistors MT located in the same block BLK is erased at once. On the other hand, data is typically read and written to multiple memory cell transistors MT that are commonly connected to a word line WL provided in a string unit SU. This group of memory cell transistors MT that share a word line WL in a string unit SU is called a unit group CU.

[0052] Writing to a cell group CU is performed in units of pages. For example, if each cell is a TLC (Triple Level Cell) capable of storing 3 bits (8 values) of data, one cell group CU can store three pages of data. The 3 bits that each memory cell transistor MT can store correspond to each of the three pages.

[0053] (Configuration of Sense Amplifier Unit and Data Register)

[0054] Figure 4 Yes Figure 2A block diagram showing an example of the configuration of the sense amplifier unit group 28 and the data register 29 in FIG.

[0055] Sense amplifier unit group 28 includes sense amplifier units SAU0 to SAU(m-1) corresponding to bit lines BL0 to BL(m-1) (hereinafter referred to as sense amplifier units SAU). Each sense amplifier unit SAU includes a sense amplifier SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier SA and the data latch circuits SDL, ADL, BDL, and CDL are connected so that data can be transferred between them.

[0056] Data latch circuits SDL, ADL, BDL, and CDL temporarily store data. During a write operation, the sense amplifier SA controls the voltage of the bit line BL based on the data stored in the data latch circuit SDL. The data latch circuits ADL, BDL, and CDL are used for multi-value operations in which the memory cell transistor MT stores data of two or more bits. Specifically, the data latch circuit ADL stores data written to the lower page. The data latch circuit BDL stores data written to the middle page. The data latch circuit CDL stores data written to the upper page. The number of data latch circuits included in the sense amplifier unit SAU is determined by the number of bits stored in each memory cell transistor MT.

[0057] During a read operation, the sense amplifier SA detects data read to the corresponding bit line BL and determines whether the data is 0 or 1. During a write operation, the sense amplifier SA applies a voltage to the bit line BL based on the write data.

[0058] The data register 29 includes data latch circuits XDL, the number of which corresponds to the number of sense amplifier units SAU0 to SAU(m-1). The data latch circuits XDL are connected to the input / output circuit 21. The data latch circuits XDL temporarily store write data sent from the input / output circuit 21 and also temporarily store read data sent from the sense amplifier unit SAU. More specifically, data transfer between the input / output circuit 21 and the sense amplifier unit group 28 occurs via the data latch circuits XDL for one page. Write data received by the input / output circuit 21 is transferred to any of the data latch circuits ADL, BDL, or CDL via the data latch circuits XDL. Read data read by the sense amplifier SA is transferred to the input / output circuit 21 via the data latch circuits XDL.

[0059] Furthermore, as will be described later, the data latch circuit XDL stores threshold information corresponding to the data pattern of the word line WLn+1 when writing data to the memory cell of the word line WLn.

[0060] (Sense Amplifier Circuit)

[0061] Figure 5 Yes Figure 4 A circuit diagram showing an example of a specific configuration of the sense amplifier unit SAU in FIG.

[0062] like Figure 5 As shown, the sense amplifier unit SAU includes a sense amplifier section SA and data latch circuits SDL, ADL, BDL, and CDL. The sense amplifier section SA and the data latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS so as to be able to receive data from each other.

[0063] Data latch circuit SDL includes, for example, inverters 60 and 61 and n-channel MOS transistors 62 and 63. The input node of inverter 60 and the output node of inverter 61 are connected to node LAT. The input node of inverter 61 and the output node of inverter 60 are connected to node / LAT. Inverters 60 and 61 store data at nodes / LAT and LAT. Write data is supplied to node LAT. The data stored in node / LAT is the inverse of the data stored in node LAT.

[0064] One end of the drain-source path of transistor 62 is connected to node / LAT, and the other end is connected to bus line LBUS. Furthermore, one end of the drain-source path of transistor 63 is connected to node LAT, and the other end is connected to bus line LBUS. A control signal STL is input to the gate of transistor 63, and a control signal STI is input to the gate of transistor 62.

[0065] The circuit configurations of the data latch circuits ADL, BDL, CDL, and XDL are the same as those of the data latch circuit SDL, and thus their description is omitted. Various control signals supplied to the sense amplifier unit SAU are provided from the control circuit 24 .

[0066] The sense amplifier unit SA includes, for example, a p-channel MOS transistor 50 , n-channel MOS transistors 51 to 58 , and a capacitor 59 .

[0067] During a read operation, the sense amplifier unit SA reads the data read from the corresponding bit line BL and determines whether the read data is "0" or "1." Furthermore, during a program operation, the sense amplifier unit SA is set to a voltage value corresponding to the data "0" or "1" written to the corresponding bit line BL.

[0068] In the sense amplifier section SA, transistors 50 to 54 are involved in the programming operation. The source / drain path of transistor 50, a second transistor, and the drain-source path of transistor 51 are connected in series between a power supply line supplying voltage VDD (an internal power supply voltage) and node COM. Furthermore, the drain-source path of transistor 54, a third transistor, is connected between node COM and node CELSRC, supplying voltage VSS (a ground voltage). Furthermore, the drain-source path of transistor 52, a first transistor, and the drain-source path of transistor 53 are connected in series between node COM and bit line BL.

[0069] The gates of transistors 50 and 54 are connected to node / LAT. Therefore, when node LAT is at a low level (hereinafter referred to as an L level) corresponding to "0" data, node / LAT remains at a high level (hereinafter referred to as an H level), transistor 50 is turned off, and transistor 54 is turned on. Conversely, when node LAT is at an H level corresponding to "1" data, node / LAT remains at an L level, transistor 50 is turned on, and transistor 54 is turned off.

[0070] During programming, control signals HLL and XXL supplied to the gates of transistors 55 and 56 are at L level, turning off transistors 55 and 56. Control signal BLX supplied to transistor 51 is at H level, turning on transistor 51. Furthermore, during normal programming, control signals BLC and BLS turn on transistors 52 and 53.

[0071] Therefore, when data "0" is stored at node LAT, transistor 50 is turned off and transistor 54 is turned on, and a bit line voltage such as voltage VSS (e.g., 0V) from node CELSRC is supplied to bit line BL. Conversely, when data "1" is stored at node LAT, transistor 50 is turned on and transistor 54 is turned off, and a bit line voltage such as, for example, 2.5V is supplied to bit line BL in accordance with control signals BLC and BLS given to transistors 52 and 53.

[0072] Figure 6 This is an explanatory diagram showing 2-3-2 coding as an example of coding. Figure 6 Indicates the values ​​of the UPPER bit, MIDDLE bit, and LOWER bit of data distributed for each threshold value.

[0073] exist Figure 6In the example, the memory cell transistor at the Er level stores data (1, 1, 1), the memory cell transistor at the A level stores data (1, 1, 0), the memory cell transistor at the B level stores data (1, 0, 0), the memory cell transistor at the C level stores data (0, 0, 0), the memory cell transistor at the D level stores data (0, 1, 0), the memory cell transistor at the E level stores data (0, 1, 1), the memory cell transistor at the F level stores data (0, 0, 1), and the memory cell transistor at the G level stores data (1, 0, 1).

[0074] Along with the data written to the memory cells on word line WLn, threshold information corresponding to the data pattern written to the memory cells on word line WLn+1 is transmitted to the data latch circuit XDL. The data pattern written to the memory cells on word line WLn+1 is binarized using a "high" threshold and a "low" threshold. For example, if the data pattern written to the memory cells on word line WLn+1 is between Er and C levels, the threshold is determined to be "low," while if it is between D and G levels, the threshold is determined to be "high." Then, if the threshold for the data written to the memory cells on word line WLn+1 is "low," "1" is input as the threshold information, and if the threshold for the data written to the memory cells on word line WLn+1 is "high," "0" is input as the threshold information. The memory controller 3 calculates the threshold information based on the data pattern written to the memory cells on word line WLn+1. Alternatively, the data pattern written to the memory cells of word line WLn+1 may be temporarily stored in the memory cells of the memory cell array 20, and the control circuit 24 of the nonvolatile memory 2 may calculate the threshold information based on the stored data pattern. Alternatively, the control circuit 24 may temporarily store the calculated threshold information in the memory cells.

[0075] The input of the threshold information corresponding to the data pattern of the word line WLn+1 is performed by Figure 7 The instruction sequence shown is performed. Figure 7 This is a diagram showing an example of a basic command sequence for data writing.

[0076] like Figure 7 As shown, the instruction sequence sequentially inputs the lower-order bit data, the middle-order bit data, and the upper-order bit data. Then, after the upper-order bit data is input, the threshold information indicating whether the threshold of word line WLn+1 is "high" or "low" is input.

[0077] As described above, the lower-order bit data, the middle-order bit data, and the upper-order bit data are temporarily stored in the data latch circuit XDL and then transferred to the data latch circuits ADL, BDL, and CDL, respectively.

[0078] Therefore, when writing data, once the write data is transferred from data latch circuit XDL to data latch circuits ADL, BDL, and CDL, data latch circuit XDL is no longer used and enters an idle state. Therefore, after the input of the upper bit data, the threshold information for word line WLn+1 is input and stored in the idle (unused) data latch circuit XDL. This eliminates the need for a new data latch circuit to store the threshold information for word line WLn+1, preventing an increase in circuit size.

[0079] In this embodiment, when writing data to the selected word line WLn, which is the write target, whether to apply a weak program pulse is determined based on the threshold information of the adjacent word line WLn+1 adjacent to the word line WLn, and the threshold when writing data to the word line WLn is adjusted.

[0080] Application of this weak programming pulse is performed by adjusting the voltage of the bit line BL, similar to the QPW (Quick Pass Write) operation. The QPW operation applies a voltage, for example, higher than the "L" level (ground voltage Vss, e.g., 0V) and lower than the "H" level (write inhibit voltage Vdd, e.g., 2.5V), to the bit line BL corresponding to the memory cell whose threshold is to be increased with a small increment. Thus, during the QPW operation, three types of control are performed on the multiple memory cells included in the memory cell group: increasing the threshold, maintaining the threshold, or increasing the threshold with a small increment.

[0081] Figure 8 This is a diagram showing an example of potential changes of a bit line and a selected word line during a programming operation.

[0082] During a programming operation (write operation), ground voltage Vss is applied to the bit lines BL connected to memory cells where writing has not yet completed. Furthermore, during programming, a program voltage VPGM is applied to the selected word lines. The program voltage VPGM increases in stages by a specific voltage amplitude (ΔVPGM) as the cycle progresses. Furthermore, a write pass voltage VPASS is applied to unselected word lines. The write pass voltage VPASS is a voltage lower than the program voltage VPGM.

[0083] Here, the cycle in which verification passes is referred to as cycle N. In cycle N+1, which is the next cycle after cycle N, the threshold information corresponding to the data pattern of word line WLn+1 is confirmed. In cycle N+1, the voltage of the bit line BL of the memory cell connected to word line WLn, which is adjacent to the memory cell with a high threshold value on word line WLn+1, is increased to the write-inhibit voltage Vdd to prevent additional writing.

[0084] On the other hand, the bit line BL of the memory cell connected to word line WLn, which is adjacent to the memory cell with a lower threshold on word line WLn+1, has its voltage slightly raised to voltage Vm in cycle N+1, making the potential difference from programming voltage VPGM smaller than in cycle N, thereby applying a weaker programming pulse. In this way, similar to the QPW operation, by controlling the voltage applied to the bit line BL, the threshold can be raised with a smaller amplitude. Voltage Vm is a voltage that is higher than ground voltage Vss and lower than write-inhibit voltage Vdd. Thus, an additional programming operation (application of a weak programming pulse) can be performed by simply adding one cycle to the number of cycles in the normal programming operation.

[0085] This will be described in more detail. Figure 9 This is an explanatory diagram showing an example of a write sequence from the A to G state. For example, assume that a memory cell connected to word line WLn passes verification of threshold voltage A in the third cycle. This memory cell is referred to as memory cell M. A memory cell adjacent to memory cell M and connected to word line WLn+1 is referred to as memory cell X. In this case, as a comparative example, when program voltage VPGM_4 is applied to WLn in the fourth cycle, a write-inhibit voltage Vdd is applied to bit line B connected to memory cell M, regardless of the threshold voltage to be written to memory cell X. In this embodiment, if the threshold voltage to be written to memory cell X is low, voltage Vm is applied to bit line B, and a weak write is performed on memory cell M. If the threshold voltage to be written to memory cell X is high, write-inhibit voltage Vdd is applied to bit line B, inhibiting writes to memory cell M.

[0086] Assume that the memory cell connected to word line WLn passes verification of threshold voltage G in the 18th cycle, the final cycle scheduled. This memory cell is referred to as memory cell N. The memory cell adjacent to memory cell N and connected to word line WLn+1 is referred to as memory cell Y. Since this is the final cycle, the threshold voltage to be written to memory cell Y is irrelevant, and thus weak writing to memory cell N is not performed in the 19th cycle.

[0087] As described above, in this embodiment, the number of cycles is not increased further than the predetermined number of cycles, and therefore the programming time is not increased.

[0088] Alternatively, as the nineteenth cycle, weak programming corresponding to the threshold voltage to be written into the memory cell Y may be performed on the memory cell N.

[0089] Figure 10 This is a flowchart for explaining the operation of this embodiment. Figure 11 This is a diagram for explaining changes in threshold value distribution based on the operation of this embodiment.

[0090] First, data is input to the memory cells on word line WLn (S1). The data written to the memory cells on word line WLn is transferred to the data latch circuits ADL, BDL, and CDL via the data latch circuit XDL and stored in the data latch circuits ADL, BDL, and CDL. Next, threshold information is input to the memory cells on word line WLn+1 (S2). The threshold information for the memory cells on word line WLn+1 is stored in the unused data latch circuit XDL.

[0091] Next, a programming pulse (programming voltage VPGM) is applied to the word line corresponding to the page to be written (S3), and the programming operation is performed. After the programming operation, a program verification is performed to determine whether the threshold voltage has reached the desired target voltage. The result of the program verification is determined to be verification pass or verification fail (S4).

[0092] If the verification is determined to be failed (S4: NG), the process returns to S3 and executes multiple cycles of programming and program verification. On the other hand, if the verification is determined to be passed (S4: OK), the process proceeds to S5. Figure 11 The threshold distribution D1 represents the threshold distribution when the memory cells of the word line WLn are determined to have passed verification.

[0093] Next, in the process of S4 , if it is determined that the verification has passed, the threshold information of the word line WLn+1 is confirmed ( S5 ).

[0094] If the threshold value of the memory cell on word line WLn+1 is determined to be low based on the threshold value information on word line WLn+1, a weak programming pulse is applied to the memory cell on word line WLn (S6), and the process ends. On the other hand, if the threshold value of the memory cell on word line WLn+1 is determined to be high based on the threshold value information on word line WLn+1, the process ends immediately.

[0095] like Figure 11 As shown in FIG. 1 , when a weak programming pulse is applied to perform additional programming, the threshold value of the memory cell subjected to the additional programming rises. Threshold distribution D2 shows the threshold value distribution of the memory cell subjected to the additional programming.

[0096] On the other hand, when no weak programming pulse is applied and no additional programming is performed, the threshold values ​​of the memory cells not undergoing additional programming remain unchanged. Threshold distribution D3 represents the threshold value distribution of the memory cells not undergoing additional programming. As a result, at the time the programming operation on word line WLn is completed, the threshold value distribution of word line WLn is expanded.

[0097] When the programming operation for word line WLn is completed, the programming operation for word line WLn+1 is performed. When the threshold value of the data written to the memory cells on word line WLn+1 is low, the impact of NWI is minimal, and the threshold values ​​of the memory cells on word line WLn remain largely unchanged. Threshold distribution D4 shows the threshold value distribution of the memory cells on word line WLn, where the impact of NWI is minimal.

[0098] On the other hand, when the threshold of the data written to the memory cells of word line WLn+1 is high, the threshold of the memory cells of word line WLn is increased due to the influence of NWI. Threshold distribution D5 shows the threshold distribution of the memory cells of word line WLn whose threshold is increased due to the influence of NWI.

[0099] Thus, when the programming operation on word line WLn+1 is completed, the threshold values ​​of the memory cells on word line WLn adjacent to the memory cells with high threshold values ​​on word line WLn+1 are increased due to the influence of NWI. As a result, when the programming operation on word line WLn+1 is completed, the threshold value distribution on word line WLn becomes narrower.

[0100] As described above, after verification passes, the threshold information corresponding to the data pattern of word line WLn+1 is confirmed. If the threshold is "High," the process ends; if the threshold is "Low," a weak programming pulse is applied. Through this process, after the write (programming) operation on word line WLn+1 is completed, the thresholds of the memory cells on word line WLn, to which the weak programming pulses were not applied, are raised due to the influence of NWI.

[0101] As a result, the thresholds of the memory cells on word line WLn are similar whether the thresholds of the memory cells on word line WLn+1 are low or high, thereby suppressing the spread (thickening) of the threshold distribution. Furthermore, since a margin can be maintained between threshold distributions, an increase in the fail bit count (FBC) can be suppressed.

[0102] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope and gist of the invention and are within the scope of the invention described in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array that is one of the plurality of memory cell arrays; a plurality of word lines connected to the gates of the plurality of memory cells; a bit line connected to a first end portion of the first memory cell array; and A control circuit executes one or more loops in response to a command sequence for writing data to a first memory cell, the first memory cell being one of the memory cells connected to a first word line that is one of the plurality of word lines, each loop including a first programming operation and a verification operation, the first programming operation being for writing data to the first memory cell and the verification operation being for verifying the data written to the first memory cell. The command sequence includes threshold voltage information related to a threshold voltage level to be set for a second memory cell, the second memory cell being connected to a second word line that is one of the plurality of word lines adjacent to the first word line, and After exiting the loop, the control circuit determines whether to adjust the threshold voltage of the first memory cell based on the threshold voltage level set for the second memory cell.

2. The semiconductor memory device according to claim 1, wherein The control circuit exits the loop when determining that the data has been normally written into the first memory unit.

3. The semiconductor memory device according to claim 1, wherein The threshold voltage information indicates whether the threshold voltage level set for the second memory cell is high or low, The control circuit performs an operation of adjusting the threshold voltage of the first memory cell when the threshold voltage information indicates that the threshold voltage set for the second memory cell is at a low level.

4. The semiconductor memory device according to claim 3, wherein The control circuit does not perform an operation of adjusting the threshold voltage of the first memory cell when the threshold voltage information indicates that the threshold voltage set for the second memory cell is at a high level.

5. The semiconductor memory device according to claim 3, wherein The control circuit performs a second programming operation on the first memory cell to increase a threshold voltage. The semiconductor memory device according to claim 5 , wherein: The semiconductor memory device further includes a sense amplifier circuit capable of applying a bit line voltage to the bit line. The sense amplifier circuit applies the bit line voltage of a first value in the first programming operation, and applies the bit line voltage of a second value lower than the first value in the second programming operation.

7. The semiconductor memory device according to claim 6, wherein The second value is higher than the ground voltage value and lower than the write-inhibit voltage value.

8. The semiconductor memory device according to claim 6, wherein The control circuit generates the threshold voltage information based on a data pattern of data written to a memory cell connected to the second word line.

9. The semiconductor memory device according to claim 8, wherein The control circuit stores information representing the data pattern in a portion of the plurality of memory cell arrays.

10. The semiconductor memory device according to claim 8, wherein The control circuit stores the threshold voltage information in a portion of the plurality of memory cell arrays.

11. A method for controlling a semiconductor memory device, The semiconductor memory device comprises: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array that is one of the plurality of memory cell arrays; a plurality of word lines connected to the gates of the plurality of memory cells; and A bit line connected to a first end of the first memory cell array, The control method of the semiconductor memory device includes: executing one or more loops in response to a command sequence for writing data to a first memory cell, the first memory cell being one of the plurality of memory cells connected to a first word line that is one of the plurality of word lines, Each loop includes a first programming action and a verification action, wherein the first programming action is used to write data to the first memory cell, and the verification action is used to verify the data written to the memory cell. The instruction sequence includes threshold voltage information related to the level of a threshold voltage set for a second memory cell, the second memory cell being connected to a second word line that is one of the plurality of word lines adjacent to the first word line, and, after exiting the loop, determines whether to perform an action of adjusting the threshold voltage of the first memory cell based on the level of the threshold voltage to be set for the second memory cell.

12. The method for controlling a semiconductor memory device according to claim 11, wherein: When the data is normally written into the first memory cell, the loop is ended.

13. The method for controlling a semiconductor memory device according to claim 11, wherein: The threshold voltage information indicates whether the threshold voltage level set for the second memory cell is high or low, When the threshold voltage information indicates that the threshold voltage set for the second memory cell is at a low level, the threshold voltage of the first memory cell is adjusted.

14. The method for controlling a semiconductor memory device according to claim 13, wherein: When the threshold voltage information indicates that the threshold voltage set for the second memory cell is at a high level, the threshold voltage of the first memory cell is not adjusted.

15. The method for controlling a semiconductor memory device according to claim 13, wherein: include: In order to increase the threshold voltage, a second programming action is performed on the first memory cell.

16. The method for controlling a semiconductor memory device according to claim 15, wherein: During the first programming operation, a bit line voltage of a first value is applied to the bit line. During the second programming operation, a bit line voltage of a second value is applied to the bit line. The second value is lower than the first value.

17. The method for controlling a semiconductor memory device according to claim 16, wherein: The second value is higher than the ground voltage value and lower than the write-inhibit voltage value.

18. The method for controlling a semiconductor memory device according to claim 11, wherein: The threshold voltage information is generated based on a data pattern of data written to a memory cell connected to the second word line.

19. The method for controlling a semiconductor memory device according to claim 18, wherein: Information representing the data pattern is stored in a portion of the plurality of memory cell arrays.

20. The method for controlling a semiconductor memory device according to claim 11, wherein: The threshold voltage information is stored in a portion of the plurality of memory cell arrays.

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