Laminated ceramic electronic component and method for manufacturing laminated ceramic electronic component

Abstract

The present invention provides a laminated ceramic electronic component capable of suppressing squeal while maintaining high capacitance, and a method for manufacturing the same. The laminated ceramic electronic component has a laminated body including: a plurality of dielectric layers laminated along a first axis; a plurality of internal electrode layers disposed between the dielectric layers adjacent to each other along the first axis; and an intermediate region disposed between the dielectric layer and the internal electrode layer, the dielectric layer containing barium titanate and copper, the internal electrode layer and the intermediate region containing nickel and copper, the metal concentration A (at%) of nickel in the intermediate region satisfying 3at% < A < 50at%, the metal concentration B (at%) of nickel in the internal electrode layer satisfying B > A, and the metal concentration A (at%) of nickel in the intermediate region satisfying 3at% < A < 50at%. The average metal concentration D12 (at%) of copper in the internal electrode layer, the average metal concentration D11 (at%) of copper in the dielectric layer, and the average metal concentration D40 (at%) of copper in the intermediate region satisfy D12 > D11 and D11 < D40, D12 satisfies 0.1 at% < D12 < = 35 at%, and D11 satisfies 0.01 at% < D11 < 5 at%.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component and a method for manufacturing the multilayer ceramic electronic component. Background Art

[0002] In recent years, with the advancement of IT equipment, cloud services, and the evolution of communication standards, demand for electronic components, such as multilayer ceramic capacitors, which are core components of the electronics industry, has increased significantly. Against this backdrop, there is a growing demand for electronic components that maintain high capacitance while maintaining essential performance, such as dielectric constant and insulation properties, while also improving yield.

[0003] Patent Document 1 discloses a laminated electronic component having excellent warpage strength and capable of suppressing the occurrence of radial cracks. The component comprises a main body and external electrodes, the main body including dielectric layers and internal electrodes stacked in a first direction with the dielectric layers interposed therebetween. The external electrodes are connected to the internal electrodes and include a first electrode layer containing Ni and a second electrode layer comprising a Ni-Cu alloy disposed on the first electrode layer. The Cu content of the second electrode layer is 70 mol to 90 mol relative to 100 mol of the total content of Ni and Cu.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2023-106310 Summary of the Invention

[0007] Technical problem to be solved by the invention

[0008] An object of the present invention is to provide a multilayer ceramic electronic component capable of suppressing squeal while maintaining high electrostatic capacitance.

[0009] Means for solving technical problems

[0010] The present invention provides a multilayer ceramic electronic component, characterized in that:

[0011] A laminated body comprising: a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers respectively arranged between the dielectric layers adjacent to each other along the first axis; and an intermediate region arranged between the dielectric layers and the internal electrode layers.

[0012] The dielectric layer contains barium titanate and copper,

[0013] The internal electrode layers and the intermediate region contain nickel and copper,

[0014] The nickel metal concentration A (at%) in the middle region satisfies 3at%<A<50at%,

[0015] The nickel metal concentration B (at%) of the internal electrode layer satisfies B>A,

[0016] The average metal concentration D12 (at%) of copper in the internal electrode layer, the average metal concentration D11 (at%) of copper in the dielectric layer, and the average metal concentration D40 (at%) of copper in the intermediate region satisfy D12>D11 and D11<D40,

[0017] The D12 satisfies 0.1 at % < D12 ≤ 35 at %, and the D11 satisfies 0.01 at % < D11 < 5 at %.

[0018] Effects of the Invention

[0019] According to the present invention, it is possible to provide a multilayer ceramic electronic component capable of suppressing howling while maintaining high electrostatic capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a perspective view of a multilayer ceramic capacitor according to one embodiment of the present invention.

[0021] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line AA.

[0022] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor along line BB.

[0023] Figure 4 This is a cross-sectional view illustrating details of a main body of one embodiment of the present invention.

[0024] Figure 5 This is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.

[0025] Figure 6 1 and 2 are views illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.

[0026] Figure 7 Schematic diagram of a portion of the cross section of the multilayer ceramic capacitor produced in Example 1 and a graph obtained by line analysis of the average metal concentration (at %) of various metals in the cross section using TEM-EDS.

[0027] Figure 8A This is a graph obtained by line analysis using TEM-EDS of the average metal concentration (at %) of various metals in the cross section of the multilayer ceramic capacitor produced in Example 1.

[0028] Figure 8B It will Figure 8A An enlarged view of area M in the figure.

[0029] Description of Reference Numerals

[0030] 100 multilayer ceramic capacitor, 10 main body, 10a first side surface, 10b second side surface, 11 dielectric layer, 12 internal electrode layer, 12a first internal electrode layer, 12b second internal electrode layer, 13 covering layer, 14 capacitor portion, 15a first end edge portion, 15b second end edge portion, 16 side edge portion, 20a first external electrode, 20b second external electrode, 40 intermediate region, 60 flow chart, S1 raw material powder preparation process, S2 coating process, S3 internal electrode layer forming process, S4 pressing process, S5 singulation process, S6 firing process, S7 external electrode forming process, 71 ceramic green sheet, 72a first internal electrode layer pattern, 72b second internal electrode layer pattern, 73 dielectric pattern, L line, M region, D region. DETAILED DESCRIPTION

[0031] When an electric field is applied to a multilayer ceramic capacitor, which is a type of multilayer ceramic electronic component, an electrostrictive effect occurs in the dielectric layer in the direction of the electric field application perpendicular to the internal electrode layer and the dielectric layer. In addition, due to the Poisson's ratio of the ceramic as a dielectric, an electrostrictive effect also occurs in the direction perpendicular to the direction of the electric field application and parallel to the internal electrode layer and the dielectric layer. Due to these electrostrictive effects, there is a problem of vibration caused by AC voltage driving, which produces whistling. In addition, for extremely extreme individuals, there is a problem of stress generated at the connection points between the main body (the strained part) and the cover layer, side edge portion, end edge portion, etc. (the non-strained part), and cracks are generated starting from these connection points, causing a decrease in electrostatic capacitance and failure.

[0032] Therefore, the inventors conducted in-depth research and found that by controlling the copper concentration in the internal electrode layer and the copper concentration in the dielectric layer to form a dense intermediate region between the internal electrode layer and the dielectric layer, the rigidity around the internal electrode layer is strengthened, the strain generated mainly in the direction perpendicular to the direction of electric field application can be suppressed, and a stacked ceramic electronic component can be provided that can maintain high electrostatic capacitance while suppressing the occurrence of squeal and cracks.

[0033] That is, the present invention provides a laminated ceramic electronic component comprising: a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers respectively arranged between the dielectric layers adjacent to each other along the first axis; and an intermediate region arranged between the dielectric layers and the internal electrode layers, wherein the dielectric layers contain barium titanate and copper, the internal electrode layers and the intermediate region contain nickel and copper, a nickel metal concentration A (at %) in the intermediate region satisfies 3 at % < A < 50 at %, and a nickel metal concentration B (at %) in the internal electrode layers satisfies B > A, an average copper metal concentration D12 (at %) in the internal electrode layers, an average copper metal concentration D11 (at %) in the dielectric layers, and an average copper metal concentration D40 (at %) in the intermediate region satisfy D12 > D11 and D11 < D40, D12 satisfies 0.1 at % < D12 ≤ 35 at %, and D11 satisfies 0.01 at % < D11 < 5 at %.

[0034] Hereinafter, the embodiments of the present invention will be described in detail, but the present invention is not limited thereto. In addition, in this specification and the drawings, for components having substantially the same functional structure, repeated descriptions are sometimes omitted by marking the same figure marks. In addition, in the drawings, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are appropriately indicated. The X-axis, Y-axis, and Z-axis are used to define a fixed coordinate system fixed relative to a stacked ceramic capacitor as an example of a stacked ceramic electronic component. When the outer shape of a stacked ceramic capacitor as an example of a stacked ceramic electronic component is a roughly rectangular parallelepiped, the X-axis, Y-axis, and Z-axis can be equivalent to its length, width, and height. Hereinafter, the stacked ceramic electronic component of this embodiment will be described using a stacked ceramic capacitor as an example of a stacked ceramic electronic component.

[0035] (Multilayer Ceramic Capacitors)

[0036] <Structure of Multilayer Ceramic Capacitors>

[0037] Figure 1 This is a perspective view of a multilayer ceramic capacitor according to one embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken along line AA. Figure 3 It is along Figure 1 Cross-sectional view of line BB of a multilayer ceramic capacitor.

[0038] As in Figures 1 to 3As shown in the example, the multilayer ceramic capacitor 100 includes a body 10 having a substantially rectangular parallelepiped shape. In the body 10, the two opposite surfaces of the body are referred to as the upper surface and the lower surface, and the four surfaces connecting the upper surface and the lower surface are referred to as side surfaces. Generally, when the multilayer ceramic capacitor is mounted on a circuit board, the surface on the circuit board side is referred to as the lower surface, but this is not limited to this. Figures 1 to 3 In the example of the main body 10, the first side surface 10a and the second side surface 10b (refer to Figure 2 ) are provided with a first external electrode 20a and a second external electrode 20b. The first external electrode 20a extends from the first side surface 10a to the four adjacent sides. The second external electrode 20b extends from the second side surface 10b to the four adjacent sides. However, the first external electrode 20a and the second external electrode 20b are separated from each other. As long as the external electrodes are provided on the surface of the main body 10, they are not limited to being provided on two opposing side surfaces.

[0039] The stacking direction of the dielectric layer 11 and the internal electrode layer 12 is the first axis. Figures 1 to 3 In FIG, the first axis, which is the stacking direction of the internal electrode layers 12 and the dielectric layers 11, is the Z axis, which is the direction in which the internal electrode layers face each other.

[0040] The axis perpendicular to the first axis as the stacking direction is the second axis. Figures 1 to 3 In the embodiment, the second axis, which is perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis is along the longitudinal direction of the main body 10 and is an axis along the direction in which the first side surface 10a and the second side surface 10b of the main body 10 oppose each other, or along the direction in which the first external electrode 20a and the second external electrode 20b oppose each other.

[0041] The axis perpendicular to the first axis as the stacking direction and perpendicular to the second axis is the third axis. The third axis is an axis along the width of the internal electrode layer 12. Figures 1 to 3 The third axis, which is perpendicular to the first axis as the stacking direction and the second axis, is the Y axis, which is an axis along the direction in which two sides other than the first side 10a and the second side 10b of the four sides of the main body 10 are opposite to each other, namely, the third side 10c and the fourth side 10d (see Figure 3 ). The X-axis, Y-axis, and Z-axis are orthogonal to each other.

[0042] The stacking direction is not limited to the Z direction, but may be any direction. Therefore, for example, the first axis of the stacking direction may be the X-axis in the X direction or the Y-axis in the Y direction.

[0043] In this application, for the purpose of explaining general embodiments, a figure illustrating a specific embodiment is sometimes used. However, the contents described in the coordinate axis system used in one embodiment can be applied instead to the general coordinate system with the stacking direction as the first axis in the general embodiment. For example, in a specific embodiment, the stacking direction is consistent with the Z direction. Figures 1 to 3 The contents described with reference to the X-axis, Y-axis, and Z-axis may be replaced with the second axis, the third axis, and the first axis in general implementations.

[0044] The main body 10 has a structure in which internal electrode layers 12 and dielectric layers 11 containing a ceramic material that functions as a dielectric are alternately stacked. The internal electrode layers 12 include a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The end edges of the first internal electrode layers 12a are drawn out to the surface of the main body 10 where the first external electrode 20a is provided. Figures 1 to 3 In the example, the second internal electrode layer 12b is led out to the first side surface 10a. The edge of the second internal electrode layer 12b is led out to the surface of the main body 10 provided with the second external electrode 20b. Figures 1 to 3 In the example, it is led out to the second side surface 10b. As a result, the first internal electrode layer 12a and the second internal electrode layer 12b are alternately conductive with the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a structure in which capacitor units are stacked. In addition, in the stack of the internal electrode layer 12 and the dielectric layer 11, the internal electrode layer 12 is arranged on the outermost layer in the stacking direction, and the outer surface of the stack in the stacking direction is Figures 1 to 3 In the example, the upper and lower surfaces are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the composition of the cover layer 13 can be the same as that of the dielectric layer 11 or different from that of the dielectric layer 11. In addition, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different areas on the surface of the laminate and are electrically connected to different external electrodes, they are not limited to Figures 1 to 3 The structure shown. The different regions on the surface of the laminate may be surface regions on opposing sides of the laminate, surface regions on adjacent sides of the laminate, or different surface regions on the same side of the laminate. Different external electrodes may extend from the surfaces of the first and second internal electrode layers 12a, 12b exposed in the surface regions of the laminate to other surfaces, as long as they are spaced apart from each other.

[0045] The main body 10 has a plurality of intermediate regions 40 between the dielectric layer 11 and the internal electrode layer 12 (see Figure 4 ), the details will be explained later. Figures 1 to 3, the description of the intermediate region 40 is omitted. The main body 10 can be regarded as a laminate having a plurality of dielectric layers stacked along a first axis, a plurality of internal electrode layers respectively arranged between adjacent dielectric layers along the first axis, and an intermediate region arranged between the dielectric layers and the internal electrode layers.

[0046] The dimensions of the multilayer ceramic capacitor 100 are not particularly limited. For example, the dimensions may be 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height; 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height; 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height; 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height; 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height; or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height. However, the dimensions of the multilayer ceramic capacitor 100 listed above are merely examples, and the multilayer ceramic capacitor is not limited to the above dimensions. The dimensions of the multilayer ceramic capacitor 100 may be, for example, length>width≥height, width>length≥height, height>length≥width, or height>width≥length. In addition, for example, length represents the dimension in the X-axis direction, width represents the dimension in the Y-axis direction, and height represents the dimension in the Z-axis direction.

[0047] As described above, the multilayer ceramic capacitor 100 of this embodiment includes a plurality of dielectric layers 11 stacked along the Z-axis, which serves as a first axis, and a plurality of internal electrode layers 12 disposed between adjacent dielectric layers 11 along the first axis. Furthermore, the multilayer ceramic capacitor 100 of this embodiment includes an intermediate region 40 disposed between the internal electrode layers 12 and the dielectric layers 11.

[0048] Next, the internal electrode layer 12 , the dielectric layer 11 , and the intermediate region 40 will be described.

[0049] Internal electrode layer

[0050] As in Figure 2 As illustrated in FIG, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is the region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where capacitance is generated is referred to as the capacitor portion 14. That is, the capacitor portion 14 is the region where adjacent internal electrode layers connected to different external electrodes face each other via a dielectric layer.

[0051] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without interposing the second internal electrode layers 12b connected to the second external electrode 20b is referred to as the first end edge portion 15a. Furthermore, the region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without interposing the first internal electrode layers 12a connected to the first external electrode 20a is referred to as the second end edge portion 15b. Each end edge portion is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without interposing internal electrode layers connected to different external electrodes. The first end edge portion 15a and the second end edge portion 15b are regions where no capacitance is generated.

[0052] The side edge portion 16 is on a third axis perpendicular to the stacking direction and perpendicular to the second axis. Figure 3 In the example shown in FIG, side edge portion 16 is provided outside capacitor portion 14 in the direction along the Y axis. In other words, side edge portion 16 is an area outside capacitor portion 14 when viewed in the stacking direction, and is an area outside capacitor portion 14 on the side where internal electrode layer 12 is not extended. Side edge portion 16 is also an area that does not generate capacitance.

[0053] The internal electrode layers 12 are respectively disposed between dielectric layers adjacent to each other along the first axis, and contain nickel (Ni) and copper (Cu).

[0054] The average metal concentration D12 (at %) of copper in the internal electrode layer 12 satisfies 0.1 at % < D12 ≤ 35 at %.

[0055] When the average metal concentration D12 of copper in the internal electrode layer 12 is less than 0.1 at%, the copper concentration near the internal electrode layer 12 obtained by copper diffusion becomes insufficient, and the rigidity improvement effect caused by the densification of the internal electrode layer 12 cannot be obtained. When the average metal concentration D12 of copper in the internal electrode layer 12 is greater than 35 at%, the magnetic properties of the internal electrode layer 12 are reduced, and the operability of the magnetic field arrangement process in the manufacture of the stacked ceramic capacitor deteriorates.

[0056] The average metal concentration D12 (at%) of copper in the internal electrode layer 12 is preferably 1 at% ≤ D12 ≤ 30 at%, more preferably 1 at% ≤ D12 ≤ 20 at%, and further preferably 1 at% ≤ D12 ≤ 10 at%.

[0057] The average metal concentration D12 of copper in the internal electrode layer 12 can be determined as follows by line analysis using energy dispersive X-ray spectroscopy (EDS) analysis (TEM-EDS analysis) using a transmission electron microscope (TEM).

[0058] exist Figure 1 、 Figure 2 In the example shown, the first axis, which serves as the lamination direction, is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis, which serves as the third axis, to expose the XZ plane where the internal electrode layers 12 and dielectric layers 11 are stacked. Of the exposed XZ planes, the pairs of internal electrode layers 12 and dielectric layers 11 located third to tenth from the end of the top surface, the pair of internal electrode layers 12 and dielectric layers 11 located in the center, which total ten layers, and the pair of internal electrode layers 12 and dielectric layers 11 located third to tenth from the end of the bottom surface, along the Z-axis, which serves as the first axis, are selected.

[0059] In each of the groups of internal electrode layers 12 and dielectric layers 11 located in the third to tenth layers from the end of the upper surface along the Z-axis (the first axis), the group of internal electrode layers 12 and dielectric layers 11 located in the center, and the group of internal electrode layers 12 and dielectric layers 11 located in the third to tenth layers from the end of the lower surface, along the X-axis (the second axis), three arbitrary measurement points were selected within 70% of the range from the center, with the spacing between one measurement point and the center of the nearest measurement point being 30 to 100 μm. Line analysis using TEM-EDS was performed at each measurement point to measure the copper (Cu) metal concentration (at %) on the line. Each measurement point was selected from within the capacitor section 14. The measurement point size was 1.0 to 3.0 μm square.

[0060] At each measurement portion, the copper metal concentration over a 70% range from the center of the internal electrode layer 12 is measured at regular intervals along the Z-axis (the first axis) for each internal electrode layer 12 whose cross section is fully observable. The average value is taken as the copper metal concentration of the internal electrode layer 12 at that measurement portion. The average value of the copper metal concentration of the internal electrode layer 12 at all measurement portions is taken as the average copper metal concentration D12 (at %) of the internal electrode layer 12 in the multilayer ceramic capacitor 100.

[0061] The internal electrode layer 12 may contain nickel as a main component. By containing nickel, the internal electrode layer 12 has excellent electrical characteristics and can reduce costs.

[0062] Furthermore, the inclusion of copper in the internal electrode layer 12 creates a dense intermediate region around the internal electrode layer, improving the rigidity of the internal electrode layer 12. This increased rigidity of the internal electrode layer 12 suppresses electrostriction, which primarily occurs in a direction perpendicular to the direction of electric field application, and thus suppresses cracks caused by this electrostriction. This structure enables the provision of a multilayer ceramic electronic component that maintains high capacitance while suppressing whistling.

[0063] In addition to nickel and copper, internal electrode layer 12 may also contain components commonly used in internal electrode layers of multilayer ceramic capacitors. Internal electrode layer 12 may particularly contain base metals such as tin (Sn) and / or alloys containing these. Internal electrode layer 12 may also contain precious metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), and / or alloys containing these.

[0064] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same, or may be different. As an example, the main component of the first internal electrode layer 12a and the second internal electrode layer 12b is nickel.

[0065] -Thickness of internal electrode layer-

[0066] The thickness of the internal electrode layer 12 is not particularly limited, but is preferably 0.5 μm or less, and more preferably 0.4 μm or less, for example, from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 and increasing the number of layers to increase the capacitance.

[0067] The thickness of the internal electrode layer 12 can be 0.4 μm or greater when formed by printing a metal conductive paste as the internal electrode layer paste using a printing method such as screen printing or gravure printing. When formed by a thin film process such as sputtering or vapor deposition, the thickness can be 0.1 μm or greater, which is thinner than the printing method.

[0068] When evaluating the thickness of the internal electrode layer 12, the evaluation is performed on a cross section that includes the first axis, which is the stacking direction. For example, from the perspective of ease of grinding and measurement, it is preferable to evaluate on either a cross section that also includes a second axis set perpendicular to the stacking direction, or a cross section that also includes a third axis set perpendicular to the stacking direction and also perpendicular to the second axis. In the former case, the ceramic capacitor 100 is ground in the direction of the third axis, and in the latter case, the ceramic capacitor 100 is ground in the direction of the second axis. The thickness of each of the five layers of the exposed internal electrode layer 12 located in the center, top end, and bottom end of the first axis (when the number of layers of the internal electrode layer 12 is an even number, the center can be six layers) is measured at the center and three locations on the left and right sides of each layer. The thickness of each internal electrode layer 12 can be taken as the average thickness of the entire layer.

[0069] exist Figure 1 、 Figure 2 In the example shown, the first axis serving as the stacking direction is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis, serving as the third axis, to expose the XZ plane where the internal electrode layers 12 and dielectric layers 11 are stacked. Of the exposed XZ plane, five (or six if the number of internal electrode layers 12 is even) internal electrode layers 12 located at the center along the Z-axis, serving as the first axis, are selected, and five (or five) internal electrode layers 12 located at the top and bottom ends along the Z-axis, serving as the first axis, are selected. In this case, the selected internal electrode layers 12 are selected from within the capacitor portion 14.

[0070] Then, for each selected internal electrode layer 12, the thickness is measured at three locations along the X-axis, serving as the second axis, namely, 1 / 4, 1 / 2, and 3 / 4 of the length of the X-axis. The average value of the measured values ​​is used as the thickness of the internal electrode layer 12. Following the same procedure, the thickness of all selected internal electrode layers 12 is measured, and the average value is used as the thickness of the internal electrode layer 12 in the evaluated multilayer ceramic capacitor 100.

[0071] Furthermore, the thickness of the selected internal electrode layer 12 can be measured at the center along the X-axis, which serves as the second axis, and this thickness can be used as the thickness of the internal electrode layer 12. Following the same procedure, the thicknesses of all selected internal electrode layers 12 can be measured, and the average value of these measurements can be used as the thickness of the internal electrode layer 12 in the evaluated multilayer ceramic capacitor 100.

[0072] <Dielectric layer>

[0073] The dielectric layers 11 are stacked along the first axis.

[0074] The dielectric layer 11 contains barium titanate (BaTiO 3 ) and copper (Cu).

[0075] Barium titanate has excellent dielectric properties, such as a very high dielectric constant and low dielectric loss. The average copper metal concentration D11 (at%) in dielectric layer 11 satisfies 0.01 at% < D11 < 5 at%, and the average copper metal concentration D12 (at%) in internal electrode layer 12 satisfies D12 > D11. When D12 ≤ D11, the copper near internal electrode layer 12, which contains nickel, reacts with the nickel to form an alloy, resulting in a lower copper concentration in intermediate region 40 than in dielectric layer 11, potentially reducing the rigidity of internal electrode layer 12. Furthermore, increasing the copper concentration in dielectric layer 11 to ensure the density of intermediate region 40 may reduce capacitance.

[0076] When the average metal concentration D11 of copper in the dielectric layer 11 is less than 0.01 at %, the density of the dielectric layer 11 may be reduced. When the average metal concentration D11 of copper in the dielectric layer 11 is greater than 5 at %, the overall density of the dielectric layer increases but the dielectric constant may decrease. Copper is easily dissolved in the dielectric layer, generating oxygen defects, reducing insulation, increasing leakage current, and making it difficult to maintain the required voltage.

[0077] The average metal concentration D11 (at %) of copper in the dielectric layer 11 preferably satisfies 0.1 at % ≤ D11 ≤ 3 at %, and more preferably satisfies 0.1 at % ≤ D11 ≤ 1 at %.

[0078] The average metal concentration D11 of copper in dielectric layer 11 can be determined as follows.

[0079] exist Figure 1 、 Figure 2 In the example shown, the first axis, which serves as the lamination direction, is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis, which serves as the third axis, to expose the XZ plane where the internal electrode layers 12 and dielectric layers 11 are stacked. Of the exposed XZ planes, the pairs of internal electrode layers 12 and dielectric layers 11 located third to tenth from the end of the top surface, the pair of internal electrode layers 12 and dielectric layers 11 located in the center, which total ten layers, and the pair of internal electrode layers 12 and dielectric layers 11 located third to tenth from the end of the bottom surface, along the Z-axis, which serves as the first axis, are selected.

[0080] In each of the sets of internal electrode layers 12 and dielectric layers 11 located in the third to tenth layers from the end of the upper surface along the Z-axis (first axis), the set of internal electrode layers 12 and dielectric layers 11 located in the center, and the set of internal electrode layers 12 and dielectric layers 11 located in the third to tenth layers from the end of the lower surface, three arbitrary measurement points were selected within a range 70% from the center along the X-axis (second axis), with the spacing between one measurement point and the center of the nearest measurement point being 30 to 100 μm. Line analysis using TEM-EDS was performed at each measurement point to measure the copper (Cu) metal concentration (at %) on the line. Each measurement point was selected from within the capacitor section 14. The measurement point size was 1.0 to 3.0 μm square.

[0081] At each measurement portion, for dielectric layer 11 whose cross section is fully observable, the copper metal concentration is measured at regular intervals over a 70% range from the center of dielectric layer 11 in the direction along the Z-axis, which serves as the first axis. The average value is taken as the copper metal concentration of dielectric layer 11 at that measurement portion. The average value of the copper metal concentration of dielectric layer 11 at all measurement portions is taken as the average copper metal concentration D11 (at %) of dielectric layer 11 in multilayer ceramic capacitor 100.

[0082] The dielectric layer 11 may further contain additives as optional components.

[0083] The additives that the dielectric layer 11 may contain are not particularly limited, and examples thereof include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), manganese (Mn), vanadium (V), chromium (Cr), and rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)); or oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); or glass containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0084] -Thickness of dielectric layer-

[0085] The thickness of dielectric layer 11 is not particularly limited, but is preferably 1.0 μm or less, and more preferably 0.8 μm or less, for example, from the viewpoint of miniaturizing multilayer ceramic capacitor 100 and increasing the number of layers to increase capacitance.

[0086] The lower limit of the thickness of dielectric layer 11 is not particularly limited. From the perspective of improving productivity and yield, the minimum thickness can be 2 to 4 times the average diameter of the dielectric material particles used. For example, when the average diameter of the dielectric material particles used is 0.1 μm, the lower limit of the thickness of dielectric layer 11 can be 0.2 μm to 0.4 μm.

[0087] When evaluating the thickness of the dielectric layer 11, the evaluation is performed on a cross section including the first axis, which is the stacking direction. For example, from the perspective of ease of grinding and measurement, it is preferable to evaluate on either a cross section including a second axis set perpendicular to the stacking direction, or a cross section including a third axis set perpendicular to the stacking direction and also perpendicular to the second axis. In the former case, the ceramic capacitor 100 is ground in the direction of the third axis, and in the latter case, the ceramic capacitor 100 is ground in the direction of the second axis. The thickness of each of the five layers (if the number of layers of the dielectric layer 11 is an even number, the center can be six layers) located in the center, top, and bottom of the exposed dielectric layer 11 in the first axis direction is measured. The thickness of each layer is measured at three locations, including the center and the left and right. The average thickness of the entire layer can be used as the thickness of the dielectric layer 11.

[0088] exist Figure 1 、 Figure 2 In the example shown, the first axis, which serves as the stacking direction, is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis, which serves as the third axis, to expose the XZ plane where the internal electrode layers 12 and dielectric layers 11 are stacked. In the exposed XZ plane, five (or six if the number of dielectric layers 11 is even) dielectric layers 11 are selected from the center along the Z-axis, which serves as the first axis. Five (or five) dielectric layers 11 are selected from the top and bottom ends along the Z-axis, which serves as the first axis. In this case, the selected dielectric layers 11 are selected from within the capacitor portion 14.

[0089] Then, for each selected dielectric layer 11, the thickness is measured at three locations along the X-axis, serving as the second axis, at 1 / 4, 1 / 2, and 3 / 4 of the length of the X-axis, and the average value is used as the thickness of the dielectric layer 11. Following the same procedure, the thickness of all selected dielectric layers 11 is measured, and the average value can be used as the thickness of the dielectric layer 11 in the evaluated multilayer ceramic capacitor 100.

[0090] Furthermore, the thickness of the selected dielectric layer 11 can be measured at the center along the X-axis, which serves as the second axis, and this thickness can be used as the thickness of the dielectric layer 11. Following the same procedure, the thicknesses of all selected dielectric layers 11 can be measured, and the average value of these measurements can be used as the thickness of the dielectric layer 11 in the evaluated multilayer ceramic capacitor 100.

[0091] <Middle Area>

[0092] The intermediate region 40 contains nickel and copper, and its composition is not particularly limited. The intermediate region 40 is defined as a region where the nickel metal concentration A (at%) satisfies 3at%<A<50at% in line analysis using TEM-EDS analysis.

[0093] To ensure greater density than the surrounding dielectric layers, the average copper metal concentration D40 (at%) in the middle region 40 preferably satisfies 0.05 at% ≤ D40 (at%) ≤ 15 at%, and D11 < D40 relative to the average copper metal concentration D11 (at%) in the dielectric layer 11. If D11 is greater than D40, the capacitance of the multilayer ceramic capacitor 100 may be significantly reduced.

[0094] The average metal concentration D40 of copper in the intermediate region 40 can be determined as follows.

[0095] exist Figure 1 、 Figure 2 In the example shown, the first axis serving as the lamination direction is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis serving as the third axis to expose the XZ plane where the internal electrode layers 12 and dielectric layers 11 are laminated. Of the exposed XZ planes, the pairs of internal electrode layers 12 and dielectric layers 11 located third to tenth from the end of the top surface, the pair of internal electrode layers 12 and dielectric layers 11 located in the center, comprising a total of ten layers, are selected along the Z-axis serving as the first axis. Furthermore, the pairs of internal electrode layers 12 and dielectric layers 11 located third to tenth from the end of the bottom surface are selected.

[0096] In each of the groups of internal electrode layers 12 and dielectric layers 11 located in the third to tenth layers from the end of the upper surface along the Z-axis (the first axis), the group of internal electrode layers 12 and dielectric layers 11 located in the center, and the group of internal electrode layers 12 and dielectric layers 11 located in the third to tenth layers from the end of the lower surface, three arbitrary measurement points were selected within a range of 70% from the center along the X-axis (the second axis), with the spacing between one measurement point and the center of the nearest measurement point being 30 to 100 μm. Line analysis using TEM-EDS was performed at each measurement point to measure the metal concentration (at %) of nickel (Ni) and copper (Cu) on the line. Each measurement point was selected from within the capacitor section 14. The measurement point size was 1.0 to 3.0 μm square.

[0097] In this case, the measurement sections in the third to tenth sets of internal electrode layers 12 and dielectric layers 11, counted from the end of the upper surface, are designated as measurement sections 1 to 3. The measurement sections in the ten central sets of internal electrode layers 12 and dielectric layers 11 are designated as measurement sections 4 to 6. The measurement sections in the third to tenth sets of internal electrode layers 12 and dielectric layers 11, counted from the end of the lower surface, are designated as measurement sections 7 to 9. The above-described operation is performed in measurement sections 1 to 9, and the metal concentrations (at %) of nickel (Ni) and copper (Cu) on the wire are measured at each measurement section.

[0098] In each measurement section, for middle region 40 where a nickel metal concentration A (at%) of 3 at % to 50 at % is observed, the copper metal concentration is measured at regular intervals over a 70% range from the center of middle region 40 in the direction along the Z-axis, which serves as the first axis. The average value is taken as the copper metal concentration of middle region 40 in that measurement section. The average value of the copper metal concentration of middle region 40 in all measurement sections (measurement sections 1 to 9) is taken as the average copper metal concentration D40 (at %) of middle region 40 in multilayer ceramic capacitor 100.

[0099] In a multilayer ceramic capacitor, preferably, the average copper metal concentration D40E (at %) in the intermediate regions of the groups of internal electrode layers and dielectric layers located between the third and tenth layers, counted from the end of the upper surface of the multilayer body in the stacking direction, and in the intermediate regions of the groups of internal electrode layers and dielectric layers located between the third and tenth layers, counted from the end of the lower surface of the multilayer body in the stacking direction, is higher than the average copper metal concentration D40M (at %) in the intermediate regions of the groups of internal electrode layers and dielectric layers located at the center of the multilayer body in the stacking direction, totaling ten layers. The multilayer body includes a plurality of dielectric layers stacked along a first axis, a plurality of internal electrode layers respectively arranged between adjacent dielectric layers along the first axis, and an intermediate region arranged between the dielectric layers and the internal electrode layers.

[0100] Because D40E (at%) is higher than D40M (at%), the rigidity of the internal electrode layers located on the upper and lower surface sides of the stacked ceramic capacitor is higher than the rigidity of the internal electrode layer located in the center of the stacked ceramic capacitor. Therefore, by suppressing the electrostrictive effect generated in the center of the stacked ceramic capacitor from the top and bottom, the reduction in electrostatic capacitance and howling caused by the generation of cracks can be suppressed.

[0101] Regarding average copper metal concentration D40E in intermediate region 40 , the average value of the copper metal concentrations in intermediate region 40 at measurement portions 1 to 3 and 7 to 9 is defined as average copper metal concentration D40E (at %) in intermediate region 40 of multilayer ceramic capacitor 100 .

[0102] Regarding the average copper metal concentration D40M in the intermediate region 40 , the average value of the copper metal concentrations in the intermediate region 40 in the measurement sections 4 to 6 is defined as the average copper metal concentration D40M (at %) in the intermediate region 40 in the multilayer ceramic capacitor 100 .

[0103] In a multilayer ceramic capacitor, the average metal concentration (at %) of copper in each of a plurality of intermediate regions preferably varies in a stacking direction of a multilayer body, wherein the multilayer body comprises a plurality of dielectric layers stacked along a first axis, a plurality of internal electrode layers respectively arranged between adjacent dielectric layers along the first axis, and an intermediate region arranged between the dielectric layers and the internal electrode layers. The average metal concentration (at %) of copper in each of a plurality of intermediate regions preferably varies in a linear manner, in a curved manner, or in a discontinuous manner in the stacking direction of the multilayer body.

[0104] When the average copper metal concentration (at%) in each of the plurality of intermediate regions varies in the stacking direction of the stack, the strain amounts of both the internal electrode layer in the unstrained portion and the dielectric layer that strains when an electric field is applied are connected in stages. This can alleviate local stress caused by the strain and function as a stress relief layer, thereby suppressing the occurrence of cracks. More preferably, the average copper metal concentration (at%) in each of the plurality of intermediate regions varies continuously in a linear or curved pattern in the stacking direction of the stack, thereby enabling continuous and gradual stress relief.

[0105] Figure 4 This is a cross-sectional view illustrating details of a main body of one embodiment of the present invention.

[0106] Figure 4 A partially enlarged view of the internal electrode layer 12 and the dielectric layer 11 in the main body 10 is shown. Figure 4 For example Figure 3 Magnified view of area D.

[0107] The multilayer ceramic capacitor 100 includes an intermediate region 40 containing nickel and copper between the internal electrode layer 12 and the dielectric layer 11 . Figure 4 This diagram is schematic, and thus shows the intermediate region 40 as a continuous layer of constant thickness. However, this is not limiting. The intermediate region 40 may also be discontinuous, a discrete layer, or have varying thickness depending on the location. Furthermore, the intermediate region 40 formed near the boundary between a single internal electrode layer 12 and a single dielectric layer 11 can be considered a single intermediate region, regardless of whether it is continuous or discontinuous.

[0108] The intermediate region 40 may contain nickel and copper, and the nickel metal concentration A (at%) may satisfy 3 at% < A < 50 at%. The state of the nickel and copper in the intermediate region 40 is not particularly limited. In the intermediate region 40, the nickel and copper may form a compound, or the nickel and copper may each form a compound with another element. Furthermore, in the intermediate region 40, at least one of the nickel and copper may exist in an elemental state rather than forming a compound.

[0109] (Method for Manufacturing Multilayer Ceramic Capacitor)

[0110] Next, a method for manufacturing the multilayer ceramic capacitor 100 will be described. Figure 5 Flowchart 60 illustrates a method for manufacturing the multilayer ceramic capacitor 100 . Figure 6 1 and 2 are views illustrating a method for manufacturing the multilayer ceramic capacitor 100 .

[0111] (1) Raw material powder preparation step (S1)

[0112] In the raw material powder preparation step, a dielectric material containing barium titanate and copper is first prepared to form dielectric layer 11. Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods are known for synthesizing the ceramic, the main component of dielectric layer 11, including solid-phase methods, sol-gel methods, and hydrothermal methods. In this embodiment, any of these methods can be employed.

[0113] In the raw material powder preparation step, copper and / or a copper-containing compound is added as an additive to the resulting ceramic raw material powder. Examples of copper-containing compounds include copper oxide and copper carbonate. Predetermined additive compounds may also be added to the resulting ceramic raw material powder depending on the intended purpose. Examples of additive compounds include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), molybdenum (Mo), manganese (Mn), vanadium (V), chromium (Cr) and rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)), or oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) and silicon (Si), or glasses containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium and silicon.

[0114] For example, a ceramic material can be prepared by wet-mixing a copper-containing additive and / or a compound containing an additive compound with a ceramic raw material powder, followed by drying and pulverization. For example, the ceramic material obtained as described above can be pulverized as needed to adjust the particle size, or by combining it with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

[0115] (2) Coating step (S2)

[0116] Next, in the coating step, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer may be added to the obtained raw material powder for wet mixing. Alternatively, in the raw material powder preparation step (S1), a binder may be added simultaneously with the mixing of the ceramic raw material powder and the like for wet mixing.

[0117] In the coating step, the resulting slurry can be used to apply a ceramic green sheet 71 containing the ceramic raw material powder prepared above onto a substrate by, for example, a die coating method or a doctor blade method, and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film. Figures illustrating the coating step are omitted. Ceramic green sheet 71 is an example of a dielectric green sheet.

[0118] (3) Internal electrode layer forming step (S3)

[0119] The first and second internal electrode layers 12a and 12b contain nickel (Ni) and copper (Cu), and may contain base metals such as tin (Sn) or alloys thereof. The internal electrode layers 12 may also contain precious metals such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or alloys thereof.

[0120] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same, or may be different. As an example, the main components of the first internal electrode layer 12a and the second internal electrode layer 12b may be the same, namely nickel.

[0121] The metallic conductive paste, which serves as the internal electrode layer slurry for forming the precursors of the first and second internal electrode layers 12a and 12b, can be prepared by kneading the aforementioned main components, nickel, copper, an organic binder, and a solvent. Copper can be added as a single substance or as a compound containing copper. Examples of copper compounds include copper oxide and copper carbonate.

[0122] In the internal electrode layer forming step, Figure 6 As illustrated in (A), a metal conductive paste for forming an internal electrode layer containing an organic binder is printed on the surface of the ceramic green sheet 71 by screen printing, gravure printing, etc. As a result, a first internal electrode layer pattern 72a for the first internal electrode layer 12a or a second internal electrode layer pattern 72b for the second internal electrode layer 12b is arranged on the surface of the ceramic green sheet 71. Ceramic particles can also be added to the metal conductive paste as a common material. The main component of the ceramic particles is not particularly limited, and is preferably the same as the main component ceramic of the dielectric layer 11. When ceramic particles are added as a common material, they can be added during the mixing of the metal conductive paste. The method for forming the internal electrode layer is not limited to printing, and plating, vacuum evaporation, sputtering, and CVD methods can also be used.

[0123] Alternatively, a dielectric pattern paste for the reverse pattern layer may be obtained by adding a binder such as ethyl cellulose and an organic solvent such as terpineol to the dielectric pattern material obtained in the raw material powder preparation step and kneading the mixture using a roll mill. Figure 6 As shown in (A), a dielectric pattern paste is printed on a ceramic green sheet 71 in the peripheral area where the internal electrode layer pattern is not printed, thereby forming a dielectric pattern 73 and filling the step difference with the internal electrode layer pattern. The ceramic green sheet 71 printed with the internal electrode layer pattern and the dielectric pattern 73 is referred to as a stacking unit.

[0124] Afterwards, you can Figure 6 As shown in (B), the stacking units are stacked (stacking step) in a manner such that the internal electrode layers and the dielectric layers alternate, and the edges of the internal electrode layers are alternately exposed at both end surfaces in the longitudinal direction of the dielectric layer and alternately led to a pair of external electrodes. Specifically, ceramic green sheets 71 printed with first internal electrode layer patterns 72a and dielectric patterns 73 and ceramic green sheets 71 printed with second internal electrode layer patterns 72b and dielectric patterns 73 are stacked in sequence, with the internal electrode layers sandwiched between the ceramic green sheets 71. For example, the number of stacking units can be 100 to 500.

[0125] (4) Pressing process (S4)

[0126] In the pressure bonding step, a predetermined number of cover sheets, for example, 2 to 10 layers, may be stacked on top and bottom of the laminated body obtained by stacking the lamination units and then thermally press-bonded.

[0127] (5) Singulation process (S5)

[0128] In the singulation step, the press-bonded body obtained by press-bonding can be singulated. Existing methods such as dicing with a dicing machine or laser cutting can be used as appropriate for the singulation method.

[0129] (6) Firing process (S6)

[0130] In the firing step, the laminated body after being separated into individual pieces can be fired. The firing conditions are not particularly limited, and for example, the laminated body can be fired at an oxygen partial pressure of 10 -12 ATM above 10 -8 Firing is performed in a reducing atmosphere at a temperature of at most 5000°C / h, within a temperature range of 1100°C to 1350°C, for a period of 5 minutes to 10 hours. The preferred temperature range is 1150°C to 1350°C. A heating rate of 600°C or higher can control the diffusion of copper contained in the internal electrode paste, so the heating rate is preferably adjusted to 10000°C / h or higher.

[0131] More preferably, in order to strongly suppress the excessive diffusion of copper contained in the internal electrode layer paste toward the dielectric layer side, the heating rate from 600°C to 1300°C is preferably 30,000°C / h or higher, and the oxygen partial pressure in this temperature range is more preferably 10 -12 ATM above 10 -11Atm or less, the duration of the maximum temperature in the firing process is less than 10 seconds. In addition, in order to prevent the occurrence of atmosphere changes and cracks caused by the gas generated by the degreasing residue during the heating process, it is preferred to reduce the amount of fired sheets by 1 / 2 than usual. Even if the amount of gas generated increases, the firing atmosphere can be appropriately adjusted by the oxygen partial pressure.

[0132] (7) External electrode forming step (S7)

[0133] In the external electrode forming step, the first external electrode 20 a and the second external electrode 20 b can be formed by plating, etc. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0134] The above steps are merely examples, and the method for manufacturing a multilayer ceramic capacitor according to this embodiment is not limited to the above embodiment.

[0135] (Other methods)

[0136] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

[0137] For example, the above-described embodiment is applied to a multilayer ceramic capacitor having two terminal electrodes, but may also be applied to a multilayer ceramic capacitor having three or more terminals.

[0138] In the above embodiment, a multilayer ceramic capacitor is described as an example of a multilayer ceramic electronic component, but the present invention is applicable to all multilayer ceramic electronic components. Examples of such multilayer ceramic electronic components include chip varistors and chip thermistors.

[0139] [Example]

[0140] The following describes the present invention with reference to specific examples, but the present invention is not limited to these examples.

[0141] (1) Fabrication of multilayer ceramic capacitors

[0142] [Example 1]

[0143] Figure 5 This is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention.

[0144] according to Figure 5 According to the flowchart 60 described in FIG. 6 , a multilayer ceramic capacitor is manufactured.

[0145] Specifically, first, barium titanate powder, polyvinyl butyral (PVB) resin, a solvent, a plasticizer, and SiO 2 -containing glass powder as a sintering aid are wet-mixed to obtain a slurry (raw material powder preparation step).

[0146] The obtained slurry is applied on a base film, and the slurry applied on the base film is dried to obtain a ceramic green sheet (coating step).

[0147] Next, a copper-containing organic metal complex solution and fine powder are added and mixed with Ni powder, the main metal element, to achieve a metal concentration of 5 at% when forming a multilayer ceramic capacitor. Polyvinyl butyral (PVB) resin, a solvent, and a plasticizer are added to the prepared mixed powder and wet-mixed to form an internal electrode layer slurry. The internal electrode layer slurry is then printed on a portion of the surface of the ceramic green sheet to form an internal electrode layer pattern on each ceramic green sheet, thereby forming a stacking unit (internal electrode layer formation step). This stacking unit comprises a ceramic green sheet and an internal electrode layer pattern formed on the surface of the ceramic green sheet.

[0148] Next, 470 stacking units were stacked to form a stacked body, and the stacked body was pressure-bonded and then individualized to obtain sheet-shaped green stacked bodies (pressure-bonding step, individualization step).

[0149] Next, the sheet-like green laminate was degreased in a nitrogen atmosphere. The degreased sheet-like green laminate was placed in a firing furnace, and the oxygen partial pressure was maintained at 10 -12 atm to 10 -11 Atm, the sintering was performed in a reducing atmosphere at a temperature of 1300° C. for a furnace time of 20 minutes (sintering step).

[0150] At this time, in order to strongly suppress the excessive diffusion of copper contained in the internal electrode layer paste toward the dielectric layer side, the heating rate from 600°C to 1300°C was set to 30,000°C / h, and the oxygen partial pressure in this temperature range was maintained at 1×10 - 12 ATM and above 5×10 -12 Atm or less, the duration of the maximum temperature in the firing process is set to 10 seconds. In addition, in order to prevent the occurrence of atmosphere fluctuations and cracks caused by the gas generated by the degreasing residue during the temperature increase, the amount of fired tablets charged is reduced by 1 / 2 compared to the usual amount. Even if the amount of gas generated increases, the firing atmosphere can be appropriately adjusted by adjusting the oxygen partial pressure.

[0151] The first external electrode 20 a and the second external electrode 20 b are formed on the fired laminate by plating (external electrode forming step).

[0152] The resulting multilayer ceramic capacitor had a chip shape of 1.0 mm × 0.5 mm × 0.5 mm, a thickness T1 of 0.4 μm for the internal electrode layer 12, a thickness T2 of 0.8 μm for the dielectric layer 11, and 470 layers. The thicknesses of the internal electrode layer 12 and dielectric layer 11 were evaluated according to the procedure described above.

[0153] The obtained multilayer ceramic capacitor was evaluated as follows. The evaluation results are shown in Table 1.

[0154] (2) Evaluation methods

[0155] (2-1) Determination of the intermediate region and measurement of average metal concentrations D12 to D40E (at%)

[0156] When observing the area near the boundary between the internal electrode layer and the dielectric layer, Figure 1 、 Figure 2 In the example shown, the first axis, which serves as the lamination direction, is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis, which serves as the third axis, to expose the XZ plane where the internal electrode layers 12 and dielectric layers 11 are laminated. From this exposed XZ plane, the pairs of internal electrode layers 12 and dielectric layers 11 located between the third and tenth layers, counting from the end of the top surface, the pair of internal electrode layers 12 and dielectric layers 11 located in the center, a total of ten layers, and the pair of internal electrode layers 12 and dielectric layers 11 located between the third and tenth layers, counting from the end of the bottom surface, along the Z-axis, which serves as the first axis, are selected. The selected pairs of internal electrode layers 12 and dielectric layers 11 are observed using a TEM.

[0157] In each of the groups of internal electrode layers 12 and dielectric layers 11 located at the third to tenth layers from the end of the upper surface along the Z axis as the first axis, the group of internal electrode layers 12 and dielectric layers 11 located at the center with a total of 10 layers, and the group of internal electrode layers 12 and dielectric layers 11 located at the third to tenth layers from the end of the lower surface, three arbitrary measurement sections were selected in a range of 70% from the center along the X axis as the second axis so that the interval between the center of one measurement section and the center of the other measurement section closest to it was 30 to 100 μm. In one measurement section, TEM-EDS was used to analyze the Figure 7 Line analysis was performed along the arrow direction on the line L in the schematic diagram of a portion of the cross section of the multilayer ceramic capacitor shown in (A), and the metal concentrations (at%) of barium (Ba), titanium (Ti), oxygen (O), nickel (Ni), and copper (Cu) on the line were measured (( Figure 7 (B) Figure 8A 、 8B) In addition, each measuring portion is selected from the capacitor portion 14. In addition, the size of each measuring portion is 2 μm square.

[0158] Furthermore, the measurement sections in the third to tenth sets of internal electrode layers 12 and dielectric layers 11, counted from the end of the upper surface, are designated as measurement sections 1 to 3. The measurement sections in the ten-layer set of internal electrode layers 12 and dielectric layers 11, located in the center, are designated as measurement sections 4 to 6. The measurement sections in the third to tenth sets of internal electrode layers 12 and dielectric layers 11, counted from the end of the lower surface, are designated as measurement sections 7 to 9. The above-described operation is performed in measurement sections 1 to 9, and the metal concentrations (at %) of barium (Ba), titanium (Ti), oxygen (O), nickel (Ni), and copper (Cu) on the line are measured in each measurement section.

[0159] In the measurement sections 1 to 9, in the region near the boundary between the internal electrode layer 12 and the dielectric layer 11 where the distribution of nickel and copper can be confirmed, the region where the nickel metal concentration A (at%) satisfies 3at% < A < 50at% is defined as the intermediate region 40 ( Figure 8B ).

[0160] At each of measurement sections 1 to 9, the copper metal concentration over a 70% area from the center of the internal electrode layer 12, whose cross section is fully observable, is measured at 25 nm intervals along the Z-axis (the first axis). The average value is taken as the copper metal concentration of the internal electrode layer 12 at that measurement section. Furthermore, the average value of the copper metal concentration of the internal electrode layer 12 at all measurement sections (measurement sections 1 to 9) is taken as the average copper metal concentration D12 (at %) of the internal electrode layer 12 in the multilayer ceramic capacitor 100.

[0161] At each of measurement sections 1 to 9, for dielectric layer 11 whose cross section is fully observable, the copper metal concentration is measured at 25 nm intervals over a 70% area from the center of dielectric layer 11 in the direction along the Z-axis, which serves as the first axis. The average value is taken as the copper metal concentration of dielectric layer 11 at that measurement section. Furthermore, the average value of the copper metal concentration of dielectric layer 11 at all measurement sections (measurement sections 1 to 9) is taken as the average copper metal concentration D11 (at %) of dielectric layer 11 in multilayer ceramic capacitor 100.

[0162] In each of measurement sections 1 to 9, for middle region 40 where a nickel metal concentration A (at %) of 3 at % to 50 at % is observed, the copper metal concentration is measured at 25 nm intervals over a 70% range from the center of middle region 40 in the direction along the Z-axis, which serves as the first axis. The average value is taken as the copper metal concentration of middle region 40 in that measurement section. Furthermore, the average value of the copper metal concentration of middle region 40 in all measurement sections (measurement sections 1 to 9) is taken as the average copper metal concentration D40 (at %) of middle region 40 in multilayer ceramic capacitor 100.

[0163] The average value of the copper metal concentration in the intermediate region 40 at measurement portions 1 to 3 and measurement portions 7 to 9 is defined as the average copper metal concentration D40E (at %) in the intermediate region 40 of the multilayer ceramic capacitor 100 .

[0164] (2-2) Measurement of electrostatic capacitance

[0165] The capacitance of the manufactured multilayer ceramic capacitors was measured.

[0166] The following describes a method for measuring the capacitance of the multilayer ceramic capacitors used in the present invention. An arbitrary number of 200 multilayer ceramic capacitors were selected, and the average value of the measured capacitance was used as a representative value for comparison. The measurement conditions were to clamp the terminals of the multilayer ceramic capacitor using Texture 16034E and measure with an LCR meter. At this time, an AC voltage source with a frequency of 120 Hz and an amplitude of 0.5 Vrms was connected. The AC voltage was applied for 10 seconds. The temperature of the measurement environment was set to 25°C ± 3°C.

[0167] The electrostatic capacitance of the multilayer ceramic capacitor was measured by the above-mentioned method.

[0168] Furthermore, in this embodiment, the measurement frequency is 120 Hz, but the present invention is not limited thereto, and other frequencies are applicable, of course.

[0169] (2-3) Howling Measurement

[0170] The produced multilayer ceramic capacitors were evaluated for acoustic noise.

[0171] An arbitrary number of 0.8 mm thick epoxy resin substrates with copper conductor pads were prepared. The fabricated multilayer ceramic capacitors were mounted on these substrates using solder to a coating thickness of 0.05 mm to create evaluation samples. A total of 200 evaluation samples were prepared. A 5 V AC voltage at 1 kHz was applied to the conductor pads of the evaluation samples for 5 seconds. The sound level generated 10 cm above the evaluation samples was measured in an anechoic chamber. The number of evaluation samples whose sound level exceeded 20 dB was determined.

[0172] (2-4) Magnet transport properties

[0173] 1000 samples, after undergoing the firing process and before forming external electrodes, were transported horizontally for 1.5 m with their top surfaces attached to the transport surface of a transport magnet coated with a 1 mm thick layer of resin. Nickel-copper alloys become non-magnetic when the copper concentration exceeds a certain level (at%), making them less likely to be attracted to the magnet. Therefore, if the sample adheres to the magnet and does not fall off before the end of transport, the magnet transport performance is rated "A." If even a single instance of adsorption failure occurs or the sample falls off before the end of transport, the magnet transport performance is rated "B."

[0174] [Examples 2 to 5, Comparative Examples 1 and 2]

[0175] Multilayer ceramic capacitors of Examples 2 to 5 and Comparative Examples 1 and 2 were manufactured by following the same procedures as in Example 1, except that the amount of copper added to the raw materials of the internal electrode layer 12 and the dielectric layer 11 was changed so that the average metal concentration of copper in the internal electrode layer and the dielectric layer reached the values ​​and relationship shown in Table 1.

[0176] Furthermore, the above-described evaluation was also performed on the multilayer ceramic capacitors of Examples 2 to 5 and Comparative Examples 1 and 2.

[0177] The multilayer ceramic capacitors for which no howling occurred in all the evaluation samples and whose relative values ​​of the electrostatic capacitance of each multilayer ceramic capacitor were 85 or greater when the electrostatic capacitance of the multilayer ceramic capacitor of Comparative Example 1 was set to 100 were judged to be multilayer ceramic capacitors capable of suppressing howling while maintaining high electrostatic capacitance.

[0178] [Table 1]

[0179]

[0180] According to the results shown in Table 1, in Examples 1 to 5, the relative value of the electrostatic capacitance of each of the multilayer ceramic capacitors was 85 or greater when the electrostatic capacitance of the multilayer ceramic capacitor of Comparative Example 1 was set to 100, and no howling occurred.

[0181] In Comparative Example 1, howling occurred in three evaluation samples.

[0182] In Comparative Example 2, the relative value of the electrostatic capacitance of each multilayer ceramic capacitor is less than 85 when the electrostatic capacitance of the multilayer ceramic capacitor of Comparative Example 1 is set to 100.

[0183] The above-mentioned contents have shown that a multilayer ceramic electronic component meeting the technical aspects of the present invention can provide a multilayer ceramic electronic component capable of suppressing howling while maintaining high electrostatic capacitance.

[0184] As embodiments of the present invention, for example, the following are described.

[0185] <1> A laminated ceramic electronic component, characterized in that:

[0186] A laminated body comprising: a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers respectively arranged between the dielectric layers adjacent to each other along the first axis; and an intermediate region arranged between the dielectric layers and the internal electrode layers.

[0187] The dielectric layer contains barium titanate and copper,

[0188] The internal electrode layers and the intermediate region contain nickel and copper,

[0189] The nickel metal concentration A (at%) in the middle region satisfies 3at%<A<50at%,

[0190] The nickel metal concentration B (at%) of the internal electrode layer satisfies B>A,

[0191] The average metal concentration D12 (at%) of copper in the internal electrode layer, the average metal concentration D11 (at%) of copper in the dielectric layer, and the average metal concentration D40 (at%) of copper in the intermediate region satisfy D12>D11 and D11<D40,

[0192] The D12 satisfies 0.1 at % < D12 ≤ 35 at %, and the D11 satisfies 0.01 at % < D11 < 5 at %.

[0193] <2> The multilayer ceramic electronic component according to <1> above, characterized in that:

[0194] The average metal concentration D40E (at %) of copper in the intermediate regions of the group of the internal electrode layer and the dielectric layer located between the third and tenth layers, counted from the end of the upper surface in the stacking direction of the stack, and in the intermediate regions of the group of the internal electrode layer and the dielectric layer located between the third and tenth layers, counted from the end of the lower surface in the stacking direction of the stack, is higher than the average metal concentration D40M (at %) of copper in the intermediate regions of the group of the internal electrode layer and the dielectric layer located in the center of the stack in the stack, which is a total of 10 layers.

[0195] <3> The multilayer ceramic electronic component according to <1> or <2> above, characterized in that:

[0196] An average metal concentration (at %) of copper in each of the plurality of intermediate regions varies in a stacking direction of the stacked body.

[0197] <4> The multilayer ceramic electronic component according to any one of <1> to <3> above, characterized in that:

[0198] The D40 (at%) satisfies 0.05 at%≤D40≤15 at%.

[0199] <5> A method for manufacturing a multilayer ceramic electronic component, comprising:

[0200] a raw material powder preparation step of preparing ceramic raw material powder containing barium titanate and copper for forming a dielectric layer;

[0201] a coating step of coating a slurry containing the ceramic raw material powder on a substrate to obtain a ceramic green sheet;

[0202] an internal electrode layer forming step of printing an internal electrode layer paste containing nickel and copper on the surface of the ceramic green sheet to form an internal electrode layer;

[0203] a press-bonding step of press-bonding a laminated body obtained by laminating the ceramic green sheets on which the internal electrode layers are formed so as to sandwich the internal electrode layers between the ceramic green sheets;

[0204] a singulation step of singulating the laminated body after compression bonding; and

[0205] The firing step is to fire the laminated body after being separated into individual pieces.

[0206] In the firing step, the heating rate from 600° C. to 1300° C. is 30,000° C. / h or higher.

[0207] The multilayer ceramic electronic component according to any one of <1> to <4> and the method for manufacturing a multilayer ceramic electronic component according to <5> can solve various conventional problems and achieve the object of the present invention.

Claims

1. A laminated ceramic electronic component, characterized in that: A laminated body comprising: a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers respectively arranged between the dielectric layers adjacent to each other along the first axis; and an intermediate region arranged between the dielectric layers and the internal electrode layers. The dielectric layer contains barium titanate and copper, The internal electrode layers and the intermediate region contain nickel and copper, The metal concentration A of nickel in the middle region in at% satisfies 3at%<A<50at%, The metal concentration B of nickel in at% of the internal electrode layer satisfies B>A, an average metal concentration D12 of copper in the internal electrode layer in at %, an average metal concentration D11 of copper in the dielectric layer in at %, and an average metal concentration D40 of copper in the intermediate region in at % satisfy D12>D11 and D11<D40, The D12 satisfies 0.1 at % < D12 ≤ 35 at %, and the D11 satisfies 0.01 at % < D11 < 5 at %.

2. The multilayer ceramic electronic component according to claim 1, wherein: The average metal concentration D40E, in at %, of copper in the intermediate regions formed in the group of the internal electrode layer and the dielectric layer located between the third and tenth layers, counted from the end of the upper surface in the stacking direction of the stack, and in the intermediate regions formed in the group of the internal electrode layer and the dielectric layer located between the third and tenth layers, counted from the end of the lower surface in the stacking direction of the stack, is higher than the average metal concentration D40M, in at %, of copper in the intermediate regions formed in the group of the internal electrode layer and the dielectric layer located in the center of the stack in the stack, for a total of ten layers.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein: An average metal concentration in at% of copper in each of the plurality of intermediate regions varies in a stacking direction of the stacked body.

4. The multilayer ceramic electronic component according to claim 1 or 2, wherein: The D40 satisfies 0.05 at % ≤ D40 ≤ 15 at %.

5. A method for manufacturing a laminated ceramic electronic component, characterized in that: include: a raw material powder preparation step of preparing ceramic raw material powder containing barium titanate and copper for forming a dielectric layer; a coating step of coating a slurry containing the ceramic raw material powder on a substrate to obtain a ceramic green sheet; an internal electrode layer forming step of printing an internal electrode layer paste containing nickel and copper on the surface of the ceramic green sheet to form an internal electrode layer; a press-bonding step of press-bonding a laminated body obtained by laminating the ceramic green sheets on which the internal electrode layers are formed so as to sandwich the internal electrode layers between the ceramic green sheets; a singulation step of singulating the laminated body after compression bonding; and The firing step is to fire the laminated body after being separated into individual pieces. In the firing step, the heating rate from 600° C. to 1300° C. is 30,000° C. / h or higher.

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