Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for preventing electric leakage of a parasitic channel and improving the working performance of the semiconductor device. The semiconductor device comprises a first semiconductor substrate, a ring gate transistor and an isolation structure, wherein the ring gate transistor and the isolation structure are arranged on the first semiconductor substrate. The isolation structure is arranged between the gate-all-around transistor and the first semiconductor substrate, and the isolation structure is at least located below a channel region included in the gate-all-around transistor and used for isolating the first semiconductor substrate from a gate stack structure included in the gate-all-around transistor. The gate stack structure comprises a gate dielectric layer and a gate located on the gate dielectric layer. At least part of the surface of the side, away from the first semiconductor substrate, of the isolation structure located below the channel region is in direct contact with the grid electrode.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, more powerful semiconductor devices such as gate-all-around transistors have emerged. Compared with planar transistors and fin field-effect transistors, gate-all-around transistors have higher gate control capabilities, which helps to suppress short-channel effects.

[0003] However, the parasitic channel leakage problem has always been one of the bottlenecks in improving the performance of all-around gate transistors, affecting the working performance of semiconductor devices. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to prevent parasitic channel leakage and improve the working performance of the semiconductor device.

[0005] To achieve the above-mentioned objectives, in a first aspect, the present invention provides a semiconductor device comprising: a first semiconductor substrate, and a ring-gate transistor and an isolation structure disposed on the first semiconductor substrate. The isolation structure is disposed between the ring-gate transistor and the first semiconductor substrate, and the isolation structure is located at least below the channel region included in the ring-gate transistor, for isolating the first semiconductor substrate from the gate stack structure included in the ring-gate transistor. The gate stack structure includes a gate dielectric layer and a gate located on the gate dielectric layer. At least a portion of a surface of the isolation structure located below the channel region, facing away from the first semiconductor substrate, is in direct contact with the gate.

[0006] When the above technical solution is adopted, in the semiconductor device provided by the present invention, an isolation structure is provided between the gate-all-around transistor and the first semiconductor substrate. This isolation structure is located at least below the channel region included in the gate-all-around transistor and can isolate the first semiconductor substrate from the gate stack structure included in the gate-all-around transistor, thereby preventing parasitic channel leakage and improving the electrical performance of the gate-all-around transistor.

[0007] In addition, at least a portion of the surface of the isolation structure located below the channel region that is away from the first semiconductor substrate can be in direct contact with the gate included in the ring-gate transistor. At this time, after forming the gate stack structure, the bottom side of the source and drain regions included in the ring-gate transistor can be set upward, the pre-prepared second semiconductor substrate can be removed, and the bottom of the gate stack structure can be corrected. An isolation structure can be manufactured on the bottom of the gate stack structure, and then the first semiconductor substrate can be formed by connecting on the isolation structure. There is no need to use ion implantation and precisely control the implantation parameters to only dope the middle and lower parts of the fin-shaped structure used to manufacture the channel region as in the existing manufacturing method, which leads to greater manufacturing difficulty. This is beneficial to improving the yield of the ring-gate transistor, and thus improving the working performance of the semiconductor device including the ring-gate transistor; there is also no need to introduce BDI technology as in the existing technology, which leads to problems such as high process difficulty, thereby reducing the manufacturing difficulty of the semiconductor device.

[0008] In one example, an isolation structure is entirely disposed on a first semiconductor substrate. The isolation structure includes a first isolation portion, a second isolation portion, and a third isolation portion. Furthermore, the first isolation portion is disposed below the source and drain regions of the gate-all-around transistor, the second isolation portion is disposed below the channel region, and the third isolation portion is located on at least two sides of the first isolation portion and the second isolation portion along the width direction of the channel region.

[0009] In one example, the thickness of the first isolation portion is greater than or equal to the thickness of the second isolation portion, and the thickness of the second isolation portion is greater than the thickness of the third isolation portion.

[0010] In one example, the thickness of the second isolation portion is greater than the thickness of the third isolation portion, and the difference in thickness between the second isolation portion and the third isolation portion is greater than or equal to 10 nm and less than or equal to 50 nm.

[0011] In one example, a connection layer is provided between the isolation structure and the first semiconductor substrate, and the isolation structure and the first semiconductor substrate are connected together through the connection layer.

[0012] In one example, the material of the channel region includes silicon germanium or germanium.

[0013] In one example, a surface of a first semiconductor substrate includes an active region and an isolation region between different active regions. A gate-all-around transistor is located on the active region. Furthermore, the semiconductor device further includes a shallow trench isolation structure disposed on the isolation region. A top height of the isolation structure below the channel region is less than or equal to a top height of the shallow trench isolation structure, and an interface is defined between the isolation structure and the shallow trench isolation structure.

[0014] In one example, the isolation structure is located in a portion below the channel region, and all regions along the thickness direction of the first semiconductor substrate are in direct contact with the shallow trench isolation structure. Alternatively, the isolation structure is located in a portion below the channel region, and a region close to the first semiconductor substrate along the thickness direction of the first semiconductor substrate is in direct contact with the shallow trench isolation structure, with a gate dielectric layer and / or gate electrode between the remaining region and the shallow trench isolation structure.

[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, comprising: first, forming a semiconductor structure on a second semiconductor substrate; the semiconductor structure includes at least one stacked layer, and source and drain regions located on both sides of the at least one stacked layer along the length direction; each stacked layer includes a sacrificial layer, and a channel layer located on the sacrificial layer. Next, the sacrificial layer is removed so that the channel layer included in the at least one stacked layer forms a channel region; and a recess is formed in the portion of the second semiconductor substrate located below the channel region. Next, a gate stack structure is formed surrounding the periphery of the channel region and filling the recess to obtain a ring-gate transistor. Next, the second semiconductor substrate is removed; and the bottom of the source and drain regions is set upward. Next, at least a portion of the thickness of the gate stack structure located in the recess is removed; and an isolation structure is formed at least on the gate stack structure. Next, the first semiconductor substrate is bonded to the isolation structure.

[0016] In one example, the material of the sacrificial layer is substantially the same as that of the second semiconductor substrate. Furthermore, when the sacrificial layer is removed, a recess is formed in a portion of the second semiconductor substrate below the channel region.

[0017] In one example, forming an isolation structure at least on the gate stack structure includes forming an isolation structure that completely covers the gate-all-around transistor. Next, planarizing a surface of the isolation structure that faces away from the gate-all-around transistor.

[0018] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 1 ;

[0021] Figure 2 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 2 ;

[0022] Figure 3 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 3 ;

[0023] Figure 4 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 4 ;

[0024] Figure 5 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 5 ;

[0025] Figure 6 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 6 ;

[0026] Figure 7 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 7 ;

[0027] Figure 8 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 8 ;

[0028] Figure 9 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 9 ;

[0029] Figure 10 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 ;

[0030] Figure 11 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 one;

[0031] Figure 12 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 two;

[0032] Figure 13 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 three;

[0033] Figure 14 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 Four;

[0034] Figure 15Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 five;

[0035] Figure 16 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 six;

[0036] Figure 17 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 seven;

[0037] Figure 18 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 eight;

[0038] Figure 19 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 10 Nine;

[0039] Figure 20 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 2 ten;

[0040] Figure 21 Schematic diagram of the structure of the semiconductor device during the manufacturing process provided by the embodiment of the present invention Figure 2 eleven.

[0041] Figure numerals: 11 is the first semiconductor substrate, 12 is the ring-gate transistor, 13 is the isolation structure, 14 is the channel region, 15 is the gate stack structure, 16 is the gate dielectric layer, 17 is the gate, 18 is the source and drain region, 19 is the first isolation part, 20 is the second isolation part, 21 is the third isolation part, 22 is the connecting layer, 23 is the shallow trench isolation structure, 24 is the gate sidewall, 25 is the insulating dielectric layer, 26 is the semiconductor structure, 27 is the sacrificial layer, 28 is the channel layer, 29 is the recessed part, 30 is the second semiconductor substrate, and 31 is the carrier wafer. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0043] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0044] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0046] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0047] With the development of semiconductor technology, gate-all-around transistors have emerged. Because the gate stack structure of gate-all-around transistors is formed not only on the top and sidewalls of the channel region, but also on the bottom of the channel region, compared with planar transistors and FinFETs, gate-all-around transistors have stronger gate control capabilities, which helps suppress the short channel effect and gives gate-all-around transistors higher operating performance.

[0048] However, it is difficult to suppress the parasitic channel leakage of the all-around gate transistor using existing manufacturing methods. Specifically, existing manufacturing methods generally use the following two processes to suppress the parasitic channel leakage in the all-around gate transistor:

[0049] The first method is to form at least one stack on a semiconductor substrate. Each stack includes a sacrificial layer and a channel layer located on the sacrificial layer; and etching is performed from the top of the stack down to a portion of the semiconductor substrate to form a fin. Next, after forming a shallow trench isolation structure on the portion of the semiconductor substrate exposed outside the fin, a halo ion implantation process is used to implant impurity ions of opposite conductivity type to the source and drain regions included in the fin corresponding to the ring-gate transistor to form a highly doped layer in the middle and lower part of the fin (i.e., the etched portion of the semiconductor substrate included in the fin). The highly doped layer is then used to form a reverse-biased PN junction with the subsequently formed source and drain regions, thereby suppressing leakage in the parasitic channel.

[0050] The second method involves forming a layer to be oxidized before forming at least one stacked layer on the semiconductor substrate. In this case, after the fins are formed, a remaining portion of the layer to be oxidized remains between the fins and the semiconductor substrate. Next, before forming the source and drain regions, a selective oxidation process is used to oxidize only the layer to be oxidized to form an isolation layer. In this case, after forming the active structure comprising the source, drain, and channel regions, the active structure can be isolated from the semiconductor substrate by the isolation layer, thereby suppressing parasitic channel leakage.

[0051] However, the first method of suppressing leakage using a halo ion implantation process is prone to implantation damage, which can affect device performance. Furthermore, the impurity distribution within the highly doped layer is easily affected by subsequent heat treatment processes, resulting in poor suppression of parasitic channel leakage. Furthermore, the second method of suppressing parasitic channel leakage using a dielectric isolation process is overly complex, resulting in complex operations such as selective oxidation of the oxidized layer, making semiconductor device integration more difficult. Furthermore, the second method also presents more serious issues such as self-heating of the isolation layer, impacting the performance of the ring-gate transistor.

[0052] To address the above technical issues, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiments of the present invention, an isolation structure is provided between the gate-all-around transistor and the first semiconductor substrate. This isolation structure is located at least below the channel region of the gate-all-around transistor and isolates the first semiconductor substrate from the gate stack structure of the gate-all-around transistor, thereby preventing parasitic channel leakage.

[0053] In a first aspect, an embodiment of the present invention provides a semiconductor device. Figures 19 to 21As shown, the semiconductor device includes: a first semiconductor substrate 11, and a gate-all-around transistor 12 and an isolation structure 13 disposed on the first semiconductor substrate 11. The isolation structure 13 is disposed between the gate-all-around transistor 12 and the first semiconductor substrate 11, and the isolation structure 13 is located at least below the channel region 14 included in the gate-all-around transistor 12, and is used to isolate the first semiconductor substrate 11 from the gate stack structure 15 included in the gate-all-around transistor 12. The gate stack structure 15 includes a gate dielectric layer 16 and a gate 17 located on the gate dielectric layer 16. At least a portion of the surface of the isolation structure 13 located below the channel region 14, facing away from the first semiconductor substrate 11, is in direct contact with the gate 17.

[0054] When the above technical solution is adopted, Figures 19 to 21 As shown, in the semiconductor device provided by the embodiment of the present invention, an isolation structure 13 is provided between the ring-gate transistor 12 and the first semiconductor substrate 11. The isolation structure 13 is located at least below the channel region 14 included in the ring-gate transistor 12, and can isolate the first semiconductor substrate 11 from the gate stack structure 15 included in the ring-gate transistor 12, thereby preventing parasitic channel leakage and improving the electrical performance of the ring-gate transistor 12. In addition, as Figures 1 to 21 As shown, in the side surface of the isolation structure 13 located below the channel region 14 that is away from the first semiconductor substrate 11, at least a portion of the area can be in direct contact with the gate 17 included in the ring-gate transistor 12. At this time, after forming the gate stack structure 15, the bottom side of the source and drain regions 18 included in the ring-gate transistor 12 can be set upward, the pre-prepared second semiconductor substrate 30 can be removed, and the bottom of the gate stack structure 15 can be corrected. The isolation structure 13 is manufactured on the bottom of the gate stack structure 15, and then the first semiconductor substrate 11 is formed by connecting on the isolation structure 13. There is no need to use ion implantation and precisely control the implantation parameters to only dope the middle and lower parts of the fin structure used to manufacture the channel region 14 as in the existing manufacturing method, which leads to greater manufacturing difficulty. This is beneficial to improving the yield of the ring-gate transistor 12, and further improving the working performance of the semiconductor device including the ring-gate transistor 12. There is also no need to introduce BDI technology as in the existing technology, which leads to problems such as high process difficulty, thereby reducing the manufacturing difficulty of the semiconductor device.

[0055] With respect to the first semiconductor substrate, the embodiment of the present invention does not impose any specific restrictions on the structure and material of the first semiconductor substrate, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention. For example, the first semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, or a germanium substrate. It should be noted that because the semiconductor device provided by the embodiment of the present invention includes an isolation structure for preventing parasitic channel leakage, the first semiconductor substrate provided by the embodiment of the present invention can be a substrate without a buried oxide layer to reduce the manufacturing cost of the semiconductor device.

[0056] In some cases, such as Figure 21 As shown, the surface of the first semiconductor substrate 11 includes an active area and an isolation area between different active areas. In addition, the ring-gate transistor 12 is located on the active area. The semiconductor device also includes a shallow trench isolation structure 23 arranged on the isolation area to reduce leakage and improve the electrical reliability of the semiconductor device. There is an interface between the isolation structure 13 and the shallow trench isolation structure 23. The top height of the isolation structure 13 located below the channel region 14 can be less than or equal to the top height of the shallow trench isolation structure 23, so that the thickness of the gate stack structure 15 surrounding the periphery of the underlying nanostructure meets the requirements, thereby improving the yield of the ring-gate transistor 12.

[0057] The material of the shallow trench isolation structure may include any insulating dielectric material such as silicon oxide, silicon nitride or silicon oxynitride. Specifically, the material of the shallow trench isolation structure may be different from the material of the isolation structure. Among them, when the materials of the shallow trench isolation structure and the isolation structure are different, selective etching of the back side of the device can be achieved based on the material difference between the two (for example, selective etching of the isolation structure when manufacturing the back contact structure), which is beneficial to improving the yield of the semiconductor device. As for the height of the isolation structure and the shallow trench isolation structure, it can be set according to actual needs. In addition, there is an interface between the shallow trench isolation structure and the isolation structure, which means that the shallow trench isolation structure and the isolation structure are two different structures. In the actual manufacturing process, the shallow trench isolation structure and the isolation structure are formed separately in different manufacturing steps, and are not continuous as a whole.

[0058] For gate-all-around transistors, Figures 19 to 21 As shown, the gate-all-around transistor 12 may include a channel region 14, source and drain regions 18, and a gate stack structure 15. The source and drain regions 18 are disposed on both sides of the channel region 14. The gate stack structure 15 surrounds the periphery of each layer of nanostructures included in the channel region 14.

[0059] The channel region may include at least one layer of nanostructures. Each layer of nanostructures has a gap between it and the isolation structure. When the channel region includes multiple layers of nanostructures, gaps also exist between adjacent layers of nanostructures. The embodiments of the present invention do not specifically limit the number of layers or morphology of the nanostructures included in the channel region.

[0060] The materials of the source and drain regions and the channel region may include any semiconductor material such as silicon, silicon germanium or germanium. The material of the source and drain regions may be the same as or different from the material of the channel region. Optionally, the material of the channel region may include silicon germanium or germanium to improve the carrier mobility of the channel region and improve the driving performance of the ring-gate transistor. In addition, when the material of the channel region includes silicon germanium or germanium, and the second semiconductor substrate is a silicon substrate, in the actual manufacturing process, a silicon material different from silicon germanium or germanium material can be used as a sacrificial layer. However, in this case, the material of the sacrificial layer and the silicon substrate is the same, such as Figures 10 to 21 As shown, in the process of releasing the channel region 14, the etchant for etching the sacrificial layer 27 will also damage the silicon substrate, forming a depression. The gate stack structure 15 manufactured subsequently will also be filled in the depression. Although this situation can increase the control capability of the gate stack structure 15, it will also lead to higher parasitic capacitance, which is not conducive to improving the working performance of the semiconductor device. The semiconductor device provided by the embodiment of the present invention can reduce the parasitic capacitance by etching the gate stack structure 15 located in the depression to remove at least part of the thickness of the gate stack structure 15 located in the depression. At the same time, an isolation structure 13 is formed to prevent parasitic channel leakage and improve the working performance of the semiconductor device.

[0061] The gate dielectric layer of the gate stack structure may be made of insulating materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate may be made of conductive materials such as TiN, TaN, or TiSiN.

[0062] In addition, in some cases, such as Figure 19 and Figure 20 As shown, the all-around gate transistor 12 may further include a gate spacer 24. The gate spacer 24 is provided on at least two sides of the gate stack structure 15 along the length direction to facilitate the formation of the gate stack structure 15 and reduce the risk of leakage. The material of the gate spacer 24 may include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0063] As for the isolation structure, the material of the isolation structure may include insulating dielectric materials such as silicon oxide, silicon nitride or silicon oxynitride, etc. The formation range of the isolation structure can be set according to actual needs.

[0064] The isolation structure may be located only below the channel region included in the gate-all-around transistor. Alternatively, the isolation structure may be located only below the source / drain region and the channel region included in the gate-all-around transistor. Alternatively, Figures 19 to 21 As shown, the isolation structure 13 can be provided as a whole layer on the first semiconductor substrate 11. In this case, the formation range of the isolation structure 13 is relatively large, which can not only prevent the parasitic channel leakage, but also help to suppress the leakage of the source and drain regions 18, thereby improving the working performance of the semiconductor device. Figures 19 to 21 As shown, the isolation structure 13 includes a first isolation portion 19, a second isolation portion 20, and a third isolation portion 21. Furthermore, the first isolation portion 19 is disposed below the source / drain region 18 of the gate-all-around transistor 12, the second isolation portion 20 is disposed below the channel region 14, and the third isolation portion 21 is located at least on both sides of the first isolation portion 19 and the second isolation portion 20 along the width direction of the channel region 14.

[0065] In the case where the isolation structure is provided as a whole layer, the thickness of different parts of the isolation structure can be set according to actual needs, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.

[0066] For example, Figure 19 and Figure 20 As shown, the thickness of the first isolation portion 19 can be greater than or equal to the thickness of the second isolation portion 20. The thickness of the second isolation portion 20 can be greater than the thickness of the third isolation portion 21. In this case, the second isolation portion 20 can be prevented from having a poor anti-leakage effect due to its smaller thickness. In addition, the gate stack structure 15 located at the periphery of the nanostructure can be prevented from having a smaller thickness due to the larger thickness of the second isolation portion 20, thereby enabling the all-around gate transistor 12 to have a higher gate control capability.

[0067] As for the thickness difference between the second isolation part and the first isolation part and the third isolation part, it can be set according to the size of the ring-gate transistor in the actual application scenario and actual needs, and is not specifically limited here.

[0068] For example, when the thickness of the second isolation portion is greater than that of the third isolation portion, the thickness difference between the second isolation portion and the third isolation portion may be greater than or equal to 10 nm and less than or equal to 50 nm. For example, the thickness difference between the second isolation portion and the third isolation portion may be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm.

[0069] In addition, if Figure 21 As shown, in the portion of the isolation structure 13 located below the channel region 14, all regions along the thickness direction of the first semiconductor substrate 11 can be in direct contact with the shallow trench isolation structure 23. In this case, the influence of the parasitic channel can be completely eliminated by the isolation structure 13, which is conducive to higher driving performance of the all-around gate transistor 12.

[0070] Alternatively, the isolation structure is located in a portion below the channel region, with the region proximal to the first semiconductor substrate along the thickness direction of the first semiconductor substrate being in direct contact with the shallow trench isolation structure, and a gate dielectric layer and / or gate electrode being located between the remaining region and the shallow trench isolation structure. In this case, when etching the gate stack structure within the recessed portion, the degree of etching of the gate stack structure is relatively low, which facilitates increasing the thickness of the gate stack structure located outside the underlying nanostructure, thereby improving the yield of the all-around gate transistor.

[0071] For example, Figures 19 to 21 As shown, there may be a bonding surface between the isolation structure 13 and the first semiconductor substrate 11. In this case, the isolation structure 13 and the first semiconductor substrate 11 are fixedly connected together through a bonding process. Based on this, in the actual manufacturing process, Figures 11 to 21 As shown, after forming a ring-gate transistor 12 on another second semiconductor substrate 30, the second semiconductor substrate 30 can be removed and the gate stack structure 15 can be etched. Then, the above-mentioned isolation structure 13 can be formed on the flipped ring-gate transistor 12, and the first semiconductor substrate 11 can be formed on the side of the isolation structure 13 away from the ring-gate transistor 12 through a bonding process, thereby obtaining a semiconductor device. In this case, a relatively mature manufacturing process can be used to form the ring-gate transistor 12 according to a conventional manufacturing method. In addition, the above-mentioned removal of the second semiconductor substrate 30, the formation of the isolation structure 13, and the bonding process between the isolation structure 13 and the first semiconductor substrate 11 are also mature and commonly used semiconductor manufacturing processes. There is no need to use a demanding selective oxidation method to form the isolation structure 13, thereby reducing the difficulty of manufacturing semiconductor devices.

[0072] like Figures 19 to 21 As shown, the material of the bonding layer provided between the isolation structure 13 and the first semiconductor substrate 11 can be determined according to the type of bonding process specifically adopted between the isolation structure 13 and the first semiconductor substrate 11 during the actual manufacturing process, as well as actual requirements.

[0073] For example, Figures 19 to 21 As shown, a connection layer 22 is provided between the isolation structure 13 and the first semiconductor substrate 11 . The isolation structure 13 and the first semiconductor substrate 11 are connected together via the connection layer 22 .

[0074] For example, Figures 19 to 21 As shown, the connection layer 22 may include an oxide layer. Specifically, the oxide layer may be made of silicon oxide or aluminum oxide.

[0075] Of course, the bonding layer between the isolation structure and the first semiconductor substrate may also be made of materials such as silicon nitride and silicon oxynitride.

[0076] In some cases, such as Figure 19 and Figure 20 As shown, the semiconductor device may further include an insulating dielectric layer 25 covering the all-around gate transistor 12 to reduce the leakage risk of the all-around gate transistor 12 and improve the yield of the all-around gate transistor 12. The material of the insulating dielectric layer 25 may include any insulating material such as silicon oxide or silicon nitride, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.

[0077] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 21 The manufacturing process is described by a perspective view or a cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0078] First, if Figures 1 to 9 As shown, a semiconductor structure 26 is formed on the second semiconductor substrate 30 ; the semiconductor structure 26 includes at least one stacked layer, and source and drain regions 18 located on both sides of the at least one stacked layer along the length direction; each stacked layer includes a sacrificial layer 27 and a channel layer 28 located on the sacrificial layer 27 .

[0079] Specifically, the embodiments of the present invention do not impose any specific restrictions on the structure and material of the second semiconductor substrate, as long as they can be applied to the semiconductor device manufacturing method provided by the embodiments of the present invention. For example, the second semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, or a germanium substrate. Because the isolation structure will be formed later to prevent parasitic channel leakage, the second semiconductor substrate can be a semiconductor substrate without a buried oxide layer (such as a silicon-on-insulator substrate) to reduce the manufacturing cost of the semiconductor device.

[0080] For the semiconductor structure, the stacked layers in the semiconductor structure include a channel layer used to manufacture the channel region included in the ring-gate transistor. Therefore, the number of layers and materials of the channel layer included in the semiconductor structure can be determined based on the number of layers of nanostructures in the channel region included in the ring-gate transistor and the material of each layer of nanostructures. As for the sacrificial layer, the channel layer will be released later by selectively removing the sacrificial layer, and a gate stack structure surrounding the periphery of each channel layer will be formed. Therefore, the thickness of the sacrificial layer can be determined based on the size of the gate stack structure. The material of the sacrificial layer can be any semiconductor material different from the channel layer material, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0081] For example, the material of the sacrificial layer can be substantially the same as that of the second semiconductor substrate. In this case, when the sacrificial layer is subsequently removed, a recess can be formed in the portion of the second semiconductor substrate below the channel region, thereby simplifying the semiconductor device manufacturing process and improving semiconductor device manufacturing efficiency.

[0082] The material of the sacrificial layer is substantially the same as the material of the second semiconductor substrate, which may mean that the material of the sacrificial layer is exactly the same as the material of the second semiconductor substrate, or that the material of the sacrificial layer has the same elements as the material of the second semiconductor substrate, but the contents of different elements are different (and the difference in the contents of different elements is less than or equal to 5%).

[0083] In the actual manufacturing process, Figure 1 As shown, epitaxial growth or other processes may be used to first form a sacrificial layer 27 and a channel layer 28 alternately stacked on the second semiconductor substrate 30. Next, as shown in FIG. Figure 2 As shown, the sacrificial layer 27 and the channel layer 28, as well as a portion of the second semiconductor substrate 30, can be etched by photolithography and etching processes to form a fin structure. Figure 3As shown, a shallow trench isolation structure 23 can be formed on the second semiconductor substrate 30 by using deposition and etching processes. The top height of the shallow trench isolation structure 23 is less than or equal to the bottom height of the sacrificial layer 27 located at the bottom. Figure 4 As shown, deposition and etching processes are used to form a mask structure across the fin structure; the mask structure may include a sacrificial gate and gate sidewalls 24 located on both sides of the sacrificial gate along the length direction. Figures 5 to 7 As shown, dry etching or wet etching can be used to remove the portion of the fin structure exposed outside the mask structure. Figure 8 As shown in FIG, epitaxial growth or other processes can be used to form source and drain regions 18 on both sides of the remaining fin structure. Figure 9 As shown, deposition and planarization processes are used to form an insulating dielectric layer 25 covering the formed structure. Figure 10 As shown, the sacrificial gate is selectively removed to expose the stack.

[0084] It should be noted that the semiconductor structure described above can be formed in a variety of ways. How to form the semiconductor structure described above is not a key feature of the present invention, and therefore, this specification only briefly describes it so that those skilled in the art can easily implement the present invention. Those skilled in the art can readily devise other methods for fabricating the semiconductor structure described above.

[0085] Next, if Figure 10 As shown, the sacrificial layer 27 can be removed by dry etching or wet etching to form the channel region 14 in the channel layer 28 included in at least one stack; and a recess 29 is formed in the portion of the second semiconductor substrate 30 located below the channel region 14 .

[0086] The operation of removing the sacrificial layer and the operation of forming the recessed portion can be performed separately. Alternatively, if the material of the sacrificial layer is substantially the same as that of the second semiconductor substrate, the recessed portion can be formed in the portion of the second semiconductor substrate located below the channel region while the sacrificial layer is removed.

[0087] Next, if Figure 11 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 15 surrounding the channel region 14 and filling the recess to obtain a gate-all-around transistor 12. The material of the gate stack structure 15 can be referred to above and will not be repeated here.

[0088] Next, if Figure 11 and Figure 12 As shown, the second semiconductor substrate is removed, and the bottom of the source and drain regions 18 are arranged upward.

[0089] In the actual manufacturing process, at least one of dry etching, chemical mechanical polishing and wet etching can be used to remove the second semiconductor substrate. Secondly, the flipping operation can be performed before removing the second semiconductor substrate, or after removing the second semiconductor substrate, or during the process of removing the second semiconductor substrate. In addition, if Figure 12 As shown, before flipping the second semiconductor substrate 30 on which the gate-all-around transistor 12 is formed, a carrier wafer 31 can be formed on the side of the gate-all-around transistor 12 facing away from the second semiconductor substrate 30 through the connection layer 22 to facilitate subsequent operations. The present embodiment does not specifically limit the materials of the connection layer 22 and the carrier wafer 31.

[0090] Next, if Figure 14 and Figure 15 As shown, a dry etching or wet etching process can be used to remove at least a portion of the thickness of the gate stack structure 15 located in the recess. The gate stack structure 15 located in the recess can be completely removed to reduce parasitic capacitance. Alternatively, only a portion of the thickness of the gate stack structure 15 located in the recess can be removed to facilitate greater gate control capability of the gate stack structure 15 located outside the underlying nanostructure.

[0091] Next, if Figure 16 and Figure 17 As shown, deposition and planarization processes may be used to form an isolation structure 13 at least on the gate stack structure 15. The formation range of the isolation structure 13 may refer to the above description.

[0092] For example, a deposition process or the like can be used to form an isolation structure covering the entire gate-all-around transistor. Figure 16 and Figure 17 As shown, a chemical mechanical polishing process may be used to planarize the surface of the isolation structure 13 on the side facing away from the gate-all-around transistor 12 .

[0093] Next, if Figure 18 As shown, the first semiconductor substrate 11 is bonded on the isolation structure 13 .

[0094] The embodiment of the present invention does not specifically limit the bonding method between the isolation structure and the first semiconductor substrate. For example, Figure 18 As shown, a process such as thermal oxidation can be used to first form a connection layer 22 on the first semiconductor substrate 11. The connection layer 22 is then used to bond the isolation structure 13 and the first semiconductor substrate 11 together.

[0095] like Figure 19 and Figure 21 As shown, after bonding the first semiconductor substrate 11 , a debonding process may be used to remove the connecting layer and the carrier wafer.

[0096] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0097] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0098] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A first semiconductor substrate, and a gate-all-around transistor and an isolation structure disposed on the first semiconductor substrate; The isolation structure is provided between the gate-all-around transistor and the first semiconductor substrate, and the isolation structure is located at least below the channel region included in the gate-all-around transistor, and is used to isolate the first semiconductor substrate from the gate stack structure included in the gate-all-around transistor; the gate stack structure includes a gate dielectric layer and a gate located on the gate dielectric layer; At least a portion of a surface of the isolation structure located below the channel region and facing away from the first semiconductor substrate is in direct contact with the gate.

2. The semiconductor device according to claim 1, wherein The isolation structure is entirely provided on the first semiconductor substrate; the isolation structure comprises a first isolation portion, a second isolation portion and a third isolation portion; The first isolation portion is arranged below the source and drain regions of the all-around gate transistor, the second isolation portion is arranged below the channel region, and the third isolation portion is located at least on both sides of the first isolation portion and the second isolation portion along the width direction of the channel region.

3. The semiconductor device according to claim 2, wherein The thickness of the first isolation portion is greater than or equal to the thickness of the second isolation portion; The thickness of the second isolation portion is greater than the thickness of the third isolation portion.

4. The semiconductor device according to claim 2, wherein The thickness of the second isolation portion is greater than that of the third isolation portion, and a thickness difference between the second isolation portion and the third isolation portion is greater than or equal to 10 nm and less than or equal to 50 nm.

5. The semiconductor device according to claim 1, wherein A connection layer is provided between the isolation structure and the first semiconductor substrate; the isolation structure and the first semiconductor substrate are connected together through the connection layer. The semiconductor device according to claim 1 , wherein: The material of the channel region includes silicon germanium or germanium.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The surface of the first semiconductor substrate includes active regions and isolation regions between different active regions; the gate-all-around transistor is located on the active regions; The semiconductor device also includes a shallow trench isolation structure arranged on the isolation region; the top height of the isolation structure located below the channel region is less than or equal to the top height of the shallow trench isolation structure, and an interface is provided between the isolation structure and the shallow trench isolation structure.

8. The semiconductor device according to claim 7, wherein: The isolation structure is located in a portion below the channel region, and each region along the thickness direction of the first semiconductor substrate is in direct contact with the shallow trench isolation structure; Alternatively, the isolation structure is located in the portion below the channel region, and the region close to the first semiconductor substrate along the thickness direction of the first semiconductor substrate is in direct contact with the shallow trench isolation structure, and the gate dielectric layer and / or the gate are between the remaining region and the shallow trench isolation structure.

9. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor structure on a second semiconductor substrate; the semiconductor structure comprising at least one stacked layer and source and drain regions located on both sides of the at least one stacked layer along a length direction; each stacked layer comprising a sacrificial layer and a channel layer located on the sacrificial layer; removing the sacrificial layer so that the channel layer included in at least one layer of the stack forms a channel region; and forming a recessed portion in a portion of the second semiconductor substrate located below the channel region; forming a gate stack structure surrounding the periphery of the channel region and filling the recessed portion to obtain a gate-all-around transistor; removing the second semiconductor substrate; and arranging the bottom of the source and drain regions upward; removing at least a portion of the thickness of the gate stack structure located in the recess; and forming an isolation structure at least on the gate stack structure; A first semiconductor substrate is bonded on the isolation structure.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The material of the sacrificial layer is substantially the same as that of the second semiconductor substrate; The recess is formed in a portion of the second semiconductor substrate below the channel region while the sacrificial layer is removed.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming the isolation structure at least on the gate stack structure includes: forming an isolation structure covering the entire gate-all-around transistor; A surface of the isolation structure facing away from the ring-gate transistor is planarized.

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