Semiconductor device

Abstract

Provided is a semiconductor device that achieves high withstand voltage with high reliability. In a semiconductor substrate (10) having a first semiconductor region (11) of a first conductivity type and a second semiconductor region (12) of a second conductivity type opposite to the first conductivity type on the first semiconductor region (11), an element region and a termination region closer to an end portion side of the semiconductor substrate than the element region are formed in plan view. A semiconductor element is formed in the element region, and a plurality of trench structures (T2) are formed in the termination region so as to penetrate the second semiconductor region (12) from the upper surface side and reach the first semiconductor region (11), and a conductive layer in a floating state is formed in the interior of the trench structures (T2), and the trench structures (T2) are formed in parallel in a plan view. A third semiconductor region (41) of the first conductivity type having a higher impurity concentration than the first semiconductor region (11) is provided in the bottom of the plurality of trench structures (T2) in the semiconductor substrate (10).

Description

Technical Field

[0001] The present invention relates to a structure of a semiconductor device having a termination region on the termination side of a chip of a power semiconductor element for suppressing a local increase in electric field intensity. Background Art

[0002] In order to improve the withstand voltage of the switching element, a terminal region is provided so as to surround the outside of a region (element region) where the switching element is formed. A structure for suppressing a local increase in electric field intensity is provided in the terminal region.

[0003] When using a trench-type IGBT (insulated gate bipolar transistor) as a switching element (where conduction and cutoff are controlled by the potential of the gate electrode within the trench), it is preferable to use the same trench structure within the termination region to simplify the manufacturing process. Patent Documents 1 and 2 describe semiconductor devices having such a termination region.

[0004] Figure 9 is a cross-sectional view of a portion of the element region in the semiconductor device 9. Figure 10 This is a cross-sectional view of a portion of the terminal area. In the component area ( Figure 9 ) in the semiconductor substrate 70, the thicker n-type layer that becomes the drift layer in the IGBT - On the surface side of the semiconductor substrate 70, a p-layer (a second semiconductor region of the p-type (second conductivity type)) 12 serving as a base region is formed on the n-type (first conductivity type) first semiconductor region) 11. - The groove structure (trench structure) T1 of the layer 11 is formed to extend in the vertical direction of the paper, and n-type electrodes serving as emitter regions are locally formed adjacent to both side surfaces of the trench structure T1. + Layer 13. On the inside of the trench structure T1, a relatively thin oxide film (gate insulating film) 14 is formed, and a conductive layer made of polysilicon, namely a gate electrode 21, is formed in such a way as to embed the trench structure T1. In addition, an interlayer insulating layer 16 is partially formed on the upper side of the trench structure T1 in such a way as to seal the trench structure T1 on the upper side. An emitter electrode 22 is formed on the surface of the semiconductor substrate 70. Between the interlayer insulating layer 16, the emitter electrode 22 and the n + The p-layer 13 and the p-layer 12 are electrically connected, and the emitter electrode 22 and the gate electrode 21 are separated.

[0005] In addition, in n - The back side of layer 11 ( Figure 9 The lower side of the collector layer is formed with a p + Layer 17, in p +The collector electrode 23 is formed in the layer 17. In addition, the gate electrodes 21 in all the trench structures T1 are connected outside the illustrated range and a control voltage is applied. Through this structure, the potentials of the gate electrode 21, emitter electrode 22, and collector electrode 23 are given, thereby operating the IGBT. Figure 9 , only four groove structures T1 are described; however, in reality, more groove structures T1 are similarly formed in parallel.

[0006] In fact, Figure 10 The terminal area shown is structured in Figure 9 Outside of the component area shown. Figure 10 In the embodiment, a common semiconductor substrate 70 is also used, and similarly, n - Layer (n-type first semiconductor region) 11, p layer 12, etc., are formed in parallel with a plurality of trench structures T2. Here, a common p layer 12 is provided in the element region and the terminal region, but in fact, the impurity concentration of the p layer 12 may be different in the element region and the terminal region. Inside the trench structure T2, an oxide film 14 is formed in the same manner as in the element region, and a conductive layer made of polysilicon, which is the same as the gate electrode 21 mentioned above, is also formed in the same manner. However, the conductive layer formed here is insulated from the surroundings and is not electrically connected to the gate electrode 21, and is provided as a virtual gate electrode 31 (a conductive layer in a floating state) that is electrically independent of each trench structure T2. In addition, no conductive layer connected to the emitter region (n-type first semiconductor region) is formed on the side of the trench structure T2. + Furthermore, in the terminal region, unlike the element region, the interlayer insulating layer 16 is formed to also cover the upper portion of the semiconductor region between the plurality of trench structures T2. Figure 10 Although only five groove structures T2 are described, in reality, more groove structures T2 are arranged outside the range shown in the figure on the left.

[0007] In addition, the groove structure T2 in the terminal area is closer to the terminal side ( Figure 10 The right side of the position, through n - n is locally formed on the surface of layer 11 + layer 18 and connected to the terminal electrode 32.

[0008] When n of the semiconductor device 9 - When a reverse bias is applied between layer 11 and p layer 12, Figure 10 In the structure, such as Figure 11 As shown schematically, a capacitance is generated. Here, the capacitance is generated by the p-layer 12 and the n-layer directly below it. - The capacitance generated by the expansion of the depletion layer between the layers 11 is defined as C1, and the capacitance generated by the dummy gate electrode 31 in the trench structure T2 and the n -The capacitance generated by the expansion of the depletion layer between the p-layer 11 is defined as C2, and the capacitance generated by the expansion of the depletion layer between the dummy gate electrode 31 and the p-layer 12 to its left and right sides is defined as C3 and C4. Through these capacitive junctions, the potential at each point between the element region X and the end portion (terminal electrode 32) of the semiconductor substrate 70 is distributed through the capacitive connection, thereby suppressing the generation of regions where the electric field (potential gradient) locally increases.

[0009] Patent Document 1: Japanese Patent Application Laid-Open No. 9-283754

[0010] Patent Document 2: Japanese Patent No. 5315638

[0011] Sometimes, the mobile ions are captured by the surface of the semiconductor substrate 70 or the protective film thereon. Since the potential of the dummy gate electrode 31 is not fixed, the charge of the mobile ions affects the potential of the dummy gate electrode 31. - The problem is that the region of layer 11 that contacts the bottom of trench structure T2 is inverted to the opposite conductivity type (p-type). When this inverted region is connected to p-layers 12 on both sides of trench structure T2, capacitances C2 and C3 are not generated between dummy gate electrode 31 and p-layer 12, and voltage distribution cannot be properly achieved.

[0012] Therefore, there is a demand for a semiconductor device that can achieve a high withstand voltage with high reliability. Summary of the Invention

[0013] The present invention has been made in view of this problem, and an object of the present invention is to provide an invention that solves the above-mentioned problem.

[0014] In order to solve the above-mentioned problems, the present invention has the following configurations.

[0015] The present invention is a semiconductor device, in which, in a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type on the first semiconductor region, an element region and a terminal region closer to the end side of the semiconductor substrate than the element region are formed when viewed from above, and a semiconductor element is formed in the element region, wherein the terminal region has a plurality of groove structures, the plurality of groove structures being formed to penetrate the second semiconductor region from the upper surface side and reach the first semiconductor region, and a floating conductive layer being formed inside, the plurality of groove structures being formed in parallel when viewed from above, and in the terminal region, a third semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is provided at the bottom of the plurality of groove structures in the semiconductor substrate.

[0016] The third semiconductor region may be formed in a ring shape so as to surround the element region in a plan view.

[0017] The third semiconductor region may not be provided at the bottom of the trench structure located on the end side among the plurality of trench structures.

[0018] The third semiconductor region may not be provided at the bottom of the trench structure located on the device region side among the plurality of trench structures.

[0019] The present invention is a semiconductor device, in which, in a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type on the first semiconductor region, an element region and a terminal region closer to the end side of the semiconductor substrate than the element region are formed when viewed from above, and a semiconductor element is formed in the element region, wherein the terminal region has a plurality of groove structures, wherein the plurality of groove structures are formed to penetrate the second semiconductor region from the upper surface side and reach the first semiconductor region, and a floating conductive layer is formed inside, the plurality of groove structures are formed in parallel when viewed from above, and a shallow junction region is provided in the terminal region, wherein the shallow junction region is a region formed so that the depth of the second semiconductor region between the groove structures adjacently provided between the element region side and the end side is shallower than the depth of the second semiconductor region between the groove structures adjacently provided on the element region side and the second semiconductor region between the groove structures adjacently provided on the end side.

[0020] The shallow junction region may also be formed between at least three adjacent trench structures.

[0021] The shallow junction region may be formed in a ring shape surrounding the device region in a plan view.

[0022] A terminal electrode electrically connected to the first semiconductor region may be provided, and the terminal electrode may be located closer to the end portion than the plurality of trench structures in a plan view.

[0023] The terminal electrode may include a field plate portion facing the first semiconductor region via an insulating layer on the element region side, and the field plate portion may not extend above the trench structure on the end side.

[0024] The distance between two adjacent groove structures may be wider on the device region side than on the end side.

[0025] Effects of the Invention

[0026] Since the present invention is constructed as described above, it is possible to obtain a semiconductor device that achieves a high withstand voltage with high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.

[0028] Figure 2 This is a diagram showing a simplified portion of the planar structure of the semiconductor device according to the first embodiment of the present invention.

[0029] Figure 3 These are results obtained by calculating the potential distribution in the first semiconductor region in the conventional semiconductor device and the semiconductor device of the embodiment.

[0030] Figure 4 It is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

[0031] Figure 5 It is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

[0032] Figure 6 It is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.

[0033] Figure 7 It is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment of the present invention.

[0034] Figure 8 These are the results of calculating the potential distribution and the shape of the depletion layer in the first semiconductor region based on the position of the terminal electrode and the presence or absence of trapped charges in the semiconductor device according to the fifth embodiment of the present invention.

[0035] Figure 9 This is a cross-sectional view showing a portion of the structure of a device region in a conventional semiconductor device.

[0036] Figure 10 This is a cross-sectional view showing a portion of the structure of a termination region in a conventional semiconductor device.

[0037] Figure 11 Schematic diagram showing the capacitance component of a depletion layer generated in a termination region of a conventional semiconductor device.

[0038] Description of Reference Numerals

[0039] 1, 2, 3, 4, 5, 9: semiconductor device; 10, 70, 110, 120, 130, 140: semiconductor substrate; 11: n - Layer (first semiconductor region); 12: p layer (second semiconductor region); 13, 18: n + layer; 14: oxide film (insulating film); 16: interlayer insulating layer; 17: p +Layer; 21: gate electrode; 22: emitter electrode; 23: collector electrode; 31: dummy gate electrode; 32: terminal electrode; 41-43: n-layer (third semiconductor region); 121: shallow junction p-layer (p-layer: second semiconductor region); L1: shallow junction region; T1, T2: trench structure; X: element region; Y: terminal region. DETAILED DESCRIPTION

[0040] The following describes a semiconductor device as an embodiment of the present invention. In addition, in the description of the following drawings, the same or similar parts are marked with the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane size, the ratio of the length of each part, etc. are different from the actual ones. Therefore, the specific dimensions should be judged in consideration of the following description. In addition, of course, the drawings also include parts with different dimensional relationships or proportions. In addition, the embodiments shown below illustrate the device for concretizing the technical concept of the present invention. The technical concept of the present invention does not limit the shape, structure, configuration, etc. of the structural components to the following content. The embodiments of the present invention can be modified in various ways in the claims. In addition, in the present invention, the terms "upper" and "lower" to determine upper and lower are used for the convenience of description. Even if they are set on the side, as long as they are substantially the same as the structural elements of the present invention, they fall within the scope of the rights of the present invention. In addition, "upper" not only includes the case where it is formed in contact with the object, but also includes the case where it is formed through other layers. In the present invention, "connection" is not limited to direct connection. Even when connecting with certain components such as resistors interposed therebetween, as long as the structural requirements are substantially the same as those of the present invention, it falls within the scope of the present invention.

[0041] This semiconductor device, like the aforementioned semiconductor device 9, includes a termination region having a trench structure T2 and the like. However, this device prevents the p-layers 12, which should otherwise be separated, from being electrically connected due to the inversion layer generated directly beneath the trench structure T2. Consequently, a higher withstand voltage can be achieved more reliably than with conventional technologies.

[0042] (First embodiment)

[0043] Figure 1 It is a diagram showing a semiconductor device 1 according to the first embodiment. Figure 1 The left side of the component area X( Figure 9 ) corresponds to the terminal area Y( Figure 10 ) corresponds to. Here, the record is simplified and omitted Figure 9 and Figure 10 n in + layer 13, the internal structure of each trench structure T1, T2 (oxide film 14, gate electrode 21, dummy gate electrode 31), the ratio n -The structure of the lower side of layer 11 is described. In addition, the structure in the element region X is different from the prior art ( Figure 9 )same.

[0044] Figure 2 This is a simplified top view showing the planar structure of the trench structures T1, T2, and the terminal electrode 32 in the semiconductor device 1. Here, it is assumed that there are only five trench structures T1 and T2. When viewed from above, the semiconductor device 1 (chip) is generally rectangular in shape. However, only the structure around one vertex (the lower right vertex) is shown here. The center of the chip is relative to the center. Figure 2 Located on the upper left side. Regarding the structures around the other three vertices, Figure 2 In the same manner, the groove structure T1 extends in the vertical direction of the paper, and the groove structure T2 and the terminal electrode 32 each change their orientation by 90°.

[0045] exist Figure 1 In the Figure 2 The cross section in the AA direction. Figure 2 As shown, the trench structure T2 and the terminal electrode 32 (terminal region Y) are formed in a ring shape so as to surround the entire trench structure T1 (element region X).

[0046] like Figure 2 As shown, since the groove structure T2 is formed into a closed ring, Figure 1 The p-layer 12 in is divided by the trench structure T2. For example, Figure 1 The p-layer 12A between the leftmost trench structure T2A and the trench structure T2B on its right and the p-layer 12B between the trench structure T2B and the trench structure T2C on its right are separated from each other. Therefore, if an inversion layer is not formed directly below the trench structure T2, Figure 11 The capacitors shown.

[0047] The structure of the termination region Y in the semiconductor substrate 10 used here is different from that of the semiconductor device 70 described above. Figure 1 In the impurity concentration ratio n - The n-layer (third semiconductor region) 41 having a height of 11 is formed near the bottom of the four trench structures T2 on the central side of the termination region Y. - Between the n layer 11 and the p layer 12, the p layer 12 above the n layer 41 becomes a shallow junction p layer 121. - The impurity concentration of the layer 11 is set to 2×10 15 cm -3 On the other hand, the impurity concentration of the n-layer 41 is set to, for example, 2×10 16 cm -3As a result, the portion of the trench structure T2 that touches each other at the bottom side becomes the n-layer 41 with a high impurity concentration, making it difficult for an inversion layer to form at the bottom side of the trench structure T2. As described above, this prevents the p-layers 121 on both sides of the trench structure T2 from being electrically connected due to the inversion layer, thereby achieving good potential distribution.

[0048] Figure 3 These results are calculated through simulations of the potential distribution of the n-type layer (first semiconductor region or third semiconductor region) in the termination region at a depth near the bottom of the trench structure T2 in conventional semiconductor devices 9 without an n-layer 41 and semiconductor devices (including embodiments described later) with an n-layer 41. The horizontal axis represents position, with the left side representing the device region (emitter electrode 22) and the right side representing the end portion (termination electrode 32). The vertical axis represents potential.

[0049] exist Figure 3 In the figure, (1) is the simulation result when there is no trapped charge in the conventional semiconductor device 9 (ideal case), and (2) is the simulation result when there is trapped charge. Here, the saturation value (maximum value) of the potential on the right corresponds to the breakdown voltage. In (1), a high breakdown voltage is obtained by distributing the potential approximately evenly in the terminal region. In contrast, in (2), an inversion layer is generated at the bottom of the adjacent trench structure T2, electrically connecting the p-layers 12 on both sides of the trench structure T2. The potential is approximately constant across the plurality of trench structures T2. Accordingly, the potential rises sharply near the p-layer 12 on the end (terminal electrode 32) side, resulting in a lower breakdown voltage.

[0050] In contrast, (3) is Figure 1 The simulation results for the case where a semiconductor device 1 with a structure having trapped charges are shown. This result is close to that of (1), and the breakdown voltage is significantly improved compared to (2). In other words, even with trapped charges, a high breakdown voltage is achieved by distributing the potential approximately evenly in the terminal region Y. This confirms that the above-described structure is effective.

[0051] exist Figure 1 In the embodiment, it is preferable that the n layer 41 is not provided on the element region X side of the terminal region Y. - The potential difference between the layer 11 and the dummy gate electrode 31 is relatively large. However, by not providing the n layer 41 on the element region X side of the terminal region Y, the n layer 41 can be further expanded. - A depletion layer is generated between the layer 11 and the dummy gate electrode 31 .

[0052] Furthermore, it is also preferable not to provide the n-layer 41 on the terminal electrode 32 side of the terminal region Y. Since the terminal electrode 32 side of the terminal region Y is easily broken down, when the n-layer (third semiconductor region) 41 is provided, the n-layer 41 is preferably not provided.- The depletion layer generated between the layer 11 and the dummy gate electrode 31 in the trench structure T2 connected to the n-layer 41 is difficult to expand and is more likely to break down.

[0053] In order to suppress the bonding of the p-layers 121 to each other due to the inversion layer as described above, Figure 2 In accordance with the trench structure T2 in FIG, the n-layer (third semiconductor region) 41 is preferably formed in a ring shape when the semiconductor device 1 is viewed from above. However, in cases where the formation of an inversion layer as described above is particularly prone to occur locally due to a structure on the top surface other than the structure of the semiconductor device 1 described above, the n-layer 41 may be formed only locally in that region. In other words, unlike the trench structure T2, the n-layer 41 does not necessarily need to be formed in a closed ring shape and may be formed locally and dispersedly in the circumferential direction.

[0054] The position, size (height, width, thickness, etc.), impurity concentration, etc. of the n-layer 41 are appropriately set together with other layers according to the characteristics required of the semiconductor device 1. In addition, the n-layer 41 may be formed separately on the side of the terminal region Y closer to the element region X and the side of the terminal region Y closer to the terminal electrode 32. Figure 1 In the embodiment, the number of trench structures T2 with n-layer 41 at the bottom is four, but the number can be greater or less than this. Furthermore, n-layer 41 can be suitably formed, for example, by dry etching the trenches used to form trench structures T1 and T2 and then performing ion implantation toward the bottom of the trenches. This also applies to the other embodiments described below.

[0055] exist Figure 1 In the structure of , if the structures of all the slot structures T2 are the same and the intervals of the slot structures T2 are also uniform, then Figure 3 As in the case where there is no trapped charge, the potential gradient (electric field strength) is roughly uniform. At this time, for example, when the spacing is enlarged on the element region X side, the electric field on the element region X side can be particularly weakened and the electric field concentration in that part can be suppressed. As described in Patent Document 2, since suppressing the electric field concentration on the element region X side is particularly effective in improving the withstand voltage, from the perspective of improving the withstand voltage, it is preferred to make the spacing of the groove structure T2 wider on the element region X side and narrower on the end side. On the other hand, making the spacing uniform on the element region X side without enlarging the spacing is effective in miniaturizing the semiconductor device 1. The above matters are also applicable to the other embodiments described below.

[0056] Furthermore, it is preferable to gradually increase the spacing between trench structures T2 from the trench structure T2 having the n-layer 41 at the bottom toward the device region X, so that the spacing between trench structures T2 having the n-layer 41 at the bottom is uniform. Furthermore, it is preferable to also uniformize the spacing between trench structures T2 closer to the terminal electrode 32 than the trench structure T2 having the n-layer 41 at the bottom. This allows the semiconductor device 1 to be miniaturized and achieve a higher withstand voltage with higher reliability.

[0057] (Second embodiment)

[0058] Figure 4 The semiconductor device 2 of the second embodiment is Figure 1 In the semiconductor substrate 110 used in this case, an n-layer (third semiconductor region) 42 having the same impurity concentration as the n-layer 41 is also formed. However, the n-layer 42 is only formed in the n-layer. - Layer 11 is formed on the side, with Figure 1 Unlike the structure, the p-layer 12 is not locally shallowed due to the formation of the n-layer 42 (shallow junction p-layer 121). The bottom of the trench structure T2 is easily broken down. The closer (deeper) the depth of the p-layer 12 on the trench structure T2 side is to the depth of the bottom of the trench structure T2, the less likely it is to break down. Therefore, based on this concept, the withstand voltage of the semiconductor device 2 can be improved.

[0059] Even in this case, similarly to the above-described semiconductor device 1 , the formation of an inversion layer on the bottom side of the trench structure T2 can be significantly suppressed.

[0060] (Third embodiment)

[0061] Figure 5 The semiconductor device 3 of the third embodiment is Figure 1 Corresponding cross-sectional view. Even in the semiconductor substrate 120 used in this case, an n-layer (third semiconductor region) 43 having the same impurity concentration as the n-layer 41 is formed. However, the n-layer 43 is formed only at the bottom of each trench structure T2, more locally than the n-layer 42 described above. Therefore, in this case, no n-layer is formed to connect the bottoms of the trench structures T2. In addition, adjacent n-layers 43 are partially connected to each other, and when the terminal region Y is viewed from above, Figure 1 n-layer 41 or Figure 4 The n-layer 42 part is Figure 5 Part of the n-layer 43 may also be mixed.

[0062] Even in this case, similarly to the above-described semiconductor device 1 , the formation of an inversion layer on the bottom side of the trench structure T2 can be significantly suppressed.

[0063] (Fourth embodiment)

[0064] By lengthening the conduction path between the p layers 12 adjacent to the trench structure T2 due to the inversion of the n layer in contact with the bottom of the trench structure T2 , conduction between the p layers 12 adjacent to the trench structure T2 can also be suppressed. Figure 6 The semiconductor device 4 of the fourth embodiment is Figure 1 In the terminal region Y of the semiconductor substrate 130, the p-layer 12 and the shallow junction p-layer 121 shallower than the p-layer 12 are formed, but the n-layer 41 in the semiconductor device 1 is not formed. Figure 4 In the figure, the shallow junction region L1 indicates the location where the shallow junction p-layer 121 is provided. This allows for a longer path from the shallow junction p-layer 121 adjacent to the trench structure T2 to the shallow junction p-layer 121 on the other side, thereby suppressing conduction between the shallow junction p-layers 121 on both sides of the trench structure T2 due to the inversion layer. Furthermore, the shallow junction p-layer 121 need not be present between adjacent trench structures T2. If the shallow junction p-layer 121 is present between the trench structures T2, the p-layer 12 can be present between the adjacent trench structures T2. Alternatively, the shallow junction p-layer 121 and the p-layer 12 can be alternately provided.

[0065] The situations in which the shallow junction region L1 can be formed locally in the circumferential direction instead of being formed into a ring shape when viewed from above, the situations in which the shallow junction region L1 can be provided on the inner or outer side of the terminal region Y, and the situations in which the shallow junction region L1 can be divided into the element region X side and the terminal electrode 32 side in the terminal region Y are also the same as the above-mentioned n-layer (third semiconductor region).

[0066] Thus, the p-layer 12 partially serving as the shallow junction p-layer 121 can be formed by, for example, changing the energy of the ion implantation for forming the p-layer 121. Any of the structures of the semiconductor devices of the first to fourth embodiments may be combined with each other.

[0067] (Fifth embodiment)

[0068] Figure 7 The semiconductor device 5 of the fifth embodiment is shown. Here, the structure of the terminal region Y, especially the end side (near the terminal electrode 32), is described. Compared with the structures of the first to fourth embodiments, in the semiconductor substrate 140, the gap between the terminal electrode 32 and the n - The part where the layers 11 meet (or n + The distance M from the p-layer 18 to the end of the p-layer 12 is relatively large.

[0069] Furthermore, by extending the terminal electrode 32 toward the p-layer 12 side on the interlayer insulating layer 16, a portion of the terminal electrode 32 functions as a field plate. However, the portion of the terminal electrode 32 that functions as a field plate (the field plate portion) does not extend above the outermost trench structure T2 (on the right side in the figure). For example, the distance N from the portion that functions as a field plate to the top of the trench structure T2 is greater than the spacing S between adjacent trench structures T2.

[0070] Figure 8 (a) and (b) are calculated by simulation. Figure 7 Figure 2 shows the state (a) without trapped charge and the state (b) with trapped charge when the field plate portion of the terminal electrode 32 extends to the trench structure T2 on its left side (N<0). - The results are obtained by plotting the equipotential lines (black lines) and depletion layer (white lines) in layer 11. Figure 8 (c) and (d) are Figure 7 Results of the state without trapped charges (c) and the state with trapped charges (d) in the structure (N>0).

[0071] In (c) and (d) where the field plate portion (terminal electrode 32 ) is separated from the trench structure T2 at the end, the equipotential lines on the semiconductor surface on the outermost p-layer 12 side are more gentle than in (a) and (b).

[0072] Figure 3 (4) is the potential distribution when there is trapped charge in the semiconductor device 5. Here, the trench structure T2 and the surrounding structure are the same as those in the first embodiment. In addition to the uniform distribution of potential as in (3), the highest withstand voltage among (1) to (4) is achieved due to the above-mentioned effects.

[0073] In the above example, an IGBT is formed in the element region X. However, the element formed in the element region X can be any element, such as a diode or a MOSFET. However, similar to the above-mentioned IGBT, forming this element using a trench structure (groove structure) can simplify the manufacturing process, which is particularly preferred. In addition, other layers can be added to the semiconductor substrate as appropriate. In the above example, even if the p-type and n-type in the semiconductor substrate are completely reversed, the same structure can obviously be applied.

Claims

1. A semiconductor device comprising a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type on the first semiconductor region, wherein, when viewed from above, a device region and a termination region located closer to an end of the semiconductor substrate than the device region are formed, wherein a semiconductor device is formed in the device region, wherein: The terminal region includes a plurality of groove structures, the plurality of groove structures being formed to penetrate the second semiconductor region from the upper surface side and reach the first semiconductor region, and having a conductive layer in a floating state formed therein, the plurality of groove structures being formed in parallel in a plan view. In the termination region, a third semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor region is provided at the bottom of the plurality of trench structures in the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein The third semiconductor region is formed in a ring shape so as to surround the element region in a plan view.

3. The semiconductor device according to claim 1, wherein The third semiconductor region is not provided at the bottom of the trench structure located on the end side among the plurality of trench structures.

4. The semiconductor device according to claim 1, wherein The third semiconductor region is not provided at the bottom of the trench structure located on the device region side among the plurality of trench structures.

5. A semiconductor device comprising a semiconductor substrate having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type on the first semiconductor region, wherein, when viewed from above, a device region and a termination region located closer to an end of the semiconductor substrate than the device region are formed, wherein a semiconductor device is formed in the device region, wherein: The terminal region includes a plurality of groove structures, the plurality of groove structures being formed to penetrate the second semiconductor region from the upper surface side and reach the first semiconductor region, and having a conductive layer in a floating state formed therein, the plurality of groove structures being formed in parallel in a plan view. A shallow junction region is provided in the terminal region, wherein The shallow junction region is a region formed so that the depth of the second semiconductor region between the groove structures adjacent to the element region side and the end side is shallower than the depth of the second semiconductor region between the groove structures adjacent to the element region side and the depth of the second semiconductor region between the groove structures adjacent to the end side.

6. The semiconductor device according to claim 5, wherein The shallow junction region is formed between at least three adjacent trench structures.

7. The semiconductor device according to claim 5, wherein The shallow junction region is formed in a ring shape surrounding the device region in a plan view.

8. The semiconductor device according to claim 1 or 5, wherein: The semiconductor device includes a terminal electrode electrically connected to the first semiconductor region, and the terminal electrode is located closer to the end portion than the plurality of trench structures in a plan view.

9. The semiconductor device according to claim 8, wherein The terminal electrode includes a field plate portion facing the first semiconductor region via an insulating layer on the element region side. The field plate portion does not extend above the groove structure on the end side.

10. The semiconductor device according to any one of claims 1 to 7, wherein The distance between two adjacent groove structures is wider on the device region side than on the end side.

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