Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body, a gate drive circuit and a plurality of sub-pixels, wherein the gate drive circuit and the sub-pixels are arranged on the substrate body. The display substrate further comprises a heat dissipation hole structure, and at least part of the orthographic projection, on the substrate, of the heat dissipation hole structure is located between the orthographic projection, on the substrate, of the gate drive circuit and the orthographic projection, on the substrate, of the sub-pixel.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous advancement of display technology, narrower bezels and simplified manufacturing processes are becoming the key trends in the display industry. To adapt to these trends, current display products often utilize a technology called Gate on Array (GOA), which integrates transistor-based gate drive circuits on a substrate.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a gate drive circuit and a plurality of sub-pixels arranged on the base substrate; the display substrate further comprises a heat dissipation hole structure, at least a portion of the orthographic projection of the heat dissipation hole structure on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the sub-pixels on the base substrate.

[0007] Optionally, the display substrate includes a display area and a frame area surrounding the display area, the multiple sub-pixels are located in the display area, and the gate driving circuit and the heat dissipation hole structure are both located in the frame area.

[0008] Optionally, the display substrate further includes a cathode layer, the cathode layer is located on a side of the gate driving circuit facing away from the base substrate, and a portion of the cathode layer is located within the heat dissipation hole structure.

[0009] Optionally, the cathode layer located in the heat dissipation hole structure is in contact with the base substrate.

[0010] Optionally, the display substrate further includes a heat conductive pattern, the heat conductive pattern is located in the heat dissipation hole structure, the heat conductive pattern is located between the cathode layer and the base substrate, and the heat conductive pattern is in contact with the cathode layer and the base substrate respectively.

[0011] Optionally, a chamfered corner portion of an orthographic projection of the heat-conducting pattern on the substrate is designed.

[0012] Optionally, the thermal conductive pattern includes at least two stacked sub-thermal conductive patterns, the sub-thermal conductive pattern closest to the base substrate contacts the base substrate, and the sub-thermal conductive pattern farthest from the base substrate contacts the cathode layer.

[0013] Optionally, the heat conductive pattern includes a first heat conductive sub-pattern and a second heat conductive sub-pattern stacked together, the first heat conductive sub-pattern contacts the base substrate, and the second heat conductive sub-pattern contacts the cathode layer;

[0014] The first sub-heat-conducting pattern is provided on the same layer and with the same material as the gate metal layer in the display substrate, and the second sub-heat-conducting pattern is provided on the same layer and with the same material as the source / drain metal layer in the display substrate; and the area of ​​the cathode layer in the heat dissipation hole structure is larger than the area of ​​the first sub-heat-conducting pattern and larger than the area of ​​the second sub-heat-conducting pattern.

[0015] Optionally, the display substrate includes a buffer layer, an interlayer insulating layer, a passivation layer, an organic insulating layer and a pixel defining layer stacked in sequence on the base substrate in a direction away from the base substrate, and the heat dissipation hole structure passes through the buffer layer, the interlayer insulating layer, the passivation layer, the organic insulating layer and the pixel defining layer.

[0016] Optionally, the display substrate further includes:

[0017] A metal packaging layer is located on a side of the cathode layer facing away from the substrate, and a portion of the metal packaging layer is located within the heat dissipation hole structure.

[0018] Optionally, the display substrate further includes a first low-level signal line and a second low-level signal line, the first low-level signal line includes at least a portion extending along the first direction, the second low-level signal line includes at least a portion extending along the first direction, and an orthographic projection of the second low-level signal line on the base substrate is located between the orthographic projection of the first low-level signal line on the base substrate and the display area;

[0019] The heat dissipation hole structure includes a plurality of first heat dissipation holes, and at least a portion of the orthographic projection of the first heat dissipation holes on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the first low-level signal line on the base substrate.

[0020] Optionally, the display substrate further includes a plurality of first signal transmission lines, a plurality of second signal transmission lines, and a plurality of first scan lines, the first signal transmission lines include at least a portion extending along a second direction, the second signal transmission lines include at least a portion extending along the second direction, and the first scan lines include at least a portion extending along the second direction, and the second direction intersects the first direction;

[0021] The first signal transmission line is coupled to the corresponding gate drive circuit and the first low-level signal line respectively, and the second signal transmission line is coupled to the corresponding gate drive circuit and the corresponding first scan line respectively;

[0022] The orthographic projection of the first heat dissipation hole on the base substrate is located between the orthographic projection of the first signal transmission line and the orthographic projection of the second signal transmission line on the base substrate.

[0023] Optionally, the orthographic projection of the first heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 145 μm and 155 μm, and the short side of the rectangle is between 25 μm and 35 μm.

[0024] Optionally, the gate drive circuit includes a pull-down transistor, and at least a portion of the positive projection of the first heat dissipation hole on the base substrate is located between the positive projection of the corresponding pull-down transistor on the base substrate and the positive projection of the first low-level signal line on the base substrate.

[0025] Optionally, the gate drive circuit includes an output transistor, and at least a portion of an orthographic projection of the first heat dissipation hole on the base substrate is located between orthographic projections of adjacent output transistors on the base substrate.

[0026] Optionally, the heat dissipation hole structure includes a plurality of second heat dissipation holes, at least part of the orthographic projection of the second heat dissipation holes on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the first low-level signal line on the base substrate, and the second heat dissipation holes and the first heat dissipation holes are alternately arranged along the first direction.

[0027] Optionally, the display substrate further includes a plurality of first signal transmission lines, a plurality of third signal transmission lines, and a plurality of second scan lines, the first signal transmission lines include at least a portion extending along a second direction, the third signal transmission lines include at least a portion extending along the second direction, and the second scan lines include at least a portion extending along the second direction, and the second direction intersects the first direction;

[0028] The first signal transmission line is coupled to the corresponding gate drive circuit and the first low-level signal line respectively, and the third signal transmission line is coupled to the corresponding gate drive circuit and the corresponding second scan line respectively;

[0029] The orthographic projection of the second heat dissipation hole on the base substrate is located between the orthographic projection of the first signal transmission line and the orthographic projection of the third signal transmission line on the base substrate.

[0030] Optionally, the orthographic projection of the second heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 145 μm and 155 μm, and the short side of the rectangle is between 10 μm and 20 μm.

[0031] Optionally, the gate drive circuit includes a pull-down transistor, and at least a portion of the positive projection of the second heat dissipation hole on the base substrate is located between the positive projection of the corresponding pull-down transistor on the base substrate and the positive projection of the first low-level signal line on the base substrate.

[0032] Optionally, the gate drive circuit includes an output transistor, and at least a portion of an orthographic projection of the second heat dissipation hole on the base substrate is located between orthographic projections of adjacent output transistors on the base substrate.

[0033] Optionally, the heat dissipation hole structure includes a plurality of third heat dissipation holes, and at least a portion of the orthographic projection of the third heat dissipation holes on the base substrate is located between the orthographic projection of the second low-level signal line on the base substrate and the display area.

[0034] Optionally, the display substrate further includes a plurality of second signal transmission lines, a plurality of third signal transmission lines, a plurality of first scan lines, and a plurality of second scan lines; the second signal transmission lines include at least a portion extending along a second direction, the third signal transmission lines include at least a portion extending along the second direction, the first scan lines include at least a portion extending along the second direction, and the second scan lines include at least a portion extending along the second direction; the second direction intersects the first direction;

[0035] The second signal transmission line is coupled to the corresponding gate driving circuit and the corresponding first scan line respectively, and the third signal transmission line is coupled to the corresponding gate driving circuit and the corresponding second scan line respectively;

[0036] The orthographic projection of the third heat dissipation hole on the base substrate is located between the orthographic projection of the second signal transmission line and the orthographic projection of the third signal transmission line on the base substrate.

[0037] Optionally, the orthographic projection of the third heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 150 μm and 160 μm, and the short side of the rectangle is between 60 μm and 70 μm.

[0038] Optionally, at least a portion of the orthographic projection of the third heat dissipation hole on the base substrate is located between the orthographic projection of the second low-level signal transmission line on the base substrate and the orthographic projection of the corresponding first scan line on the base substrate; and / or, at least a portion of the orthographic projection of the third heat dissipation hole on the base substrate is located between the orthographic projection of the second low-level signal transmission line on the base substrate and the orthographic projection of the corresponding second scan line on the base substrate.

[0039] Optionally, the heat dissipation hole structure includes a plurality of fourth heat dissipation holes, and at least a portion of the orthographic projection of the fourth heat dissipation holes on the base substrate is located between the orthographic projection of the second low-level signal line on the base substrate and the display area; the fourth heat dissipation holes and the third heat dissipation holes are alternately arranged along the first direction.

[0040] Optionally, the orthographic projection of the fourth heat dissipation hole on the base substrate is located between the orthographic projection of the second signal transmission line and the orthographic projection of the third signal transmission line on the base substrate.

[0041] Optionally, the orthographic projection of the fourth heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 55 μm and 65 μm, and the short side of the rectangle is between 30 μm and 40 μm.

[0042] Optionally, the heat dissipation hole structure includes a plurality of fifth heat dissipation holes, and at least a portion of the orthographic projection of the fifth heat dissipation holes on the base substrate is located between the orthographic projection of the fourth heat dissipation hole on the base substrate and the display area.

[0043] Optionally, the orthographic projection of the fifth heat dissipation hole on the base substrate is located between the orthographic projection of the first scanning line and the orthographic projection of the second scanning line on the base substrate.

[0044] Optionally, the orthographic projection of the fifth heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 170 μm and 180 μm, and the short side of the rectangle is between 110 μm and 120 μm.

[0045] Optionally, the gate drive circuit includes a first output transistor and a first capacitor, a first plate of the first capacitor is coupled to the gate of the first output transistor, and a second plate of the first capacitor is coupled to the second electrode of the first output transistor;

[0046] The heat dissipation hole structure includes a plurality of sixth heat dissipation holes, and the sixth heat dissipation holes penetrate the first electrode plate and the second electrode plate.

[0047] Optionally, the gate drive circuit includes a second output transistor and a second capacitor, the third plate of the second capacitor is coupled to the gate of the second output transistor, and the fourth plate of the second capacitor is coupled to the second electrode of the second output transistor;

[0048] The heat dissipation hole structure includes a plurality of seventh heat dissipation holes, and the seventh heat dissipation holes penetrate the third electrode plate and the fourth electrode plate.

[0049] Optionally, the gate drive circuit includes a first output transistor and a first capacitor, a first plate of the first capacitor is coupled to the gate of the first output transistor, and a second plate of the first capacitor is coupled to the second electrode of the first output transistor;

[0050] A first boundary of the cathode layer is located between an orthographic projection of the first electrode plate on the base substrate and an orthographic projection of the third electrode plate on the base substrate.

[0051] Optionally, the orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate are both located between the orthographic projection of the first output transistor on the substrate and the orthographic projection of the second output transistor on the substrate.

[0052] Based on the technical solution of the display substrate, a second aspect of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0054] FIG1 is a circuit structure diagram of a sub-pixel driving circuit provided by an embodiment of the present disclosure;

[0055] FIG2 is a schematic diagram of the basic structure of a display substrate provided by an embodiment of the present disclosure;

[0056] FIG3 is a first structural diagram of a heat dissipation hole structure provided by an embodiment of the present disclosure;

[0057] FIG4 is a second structural diagram of a heat dissipation hole structure provided by an embodiment of the present disclosure;

[0058] FIG5 is a schematic diagram of the layout of sub-pixels and gate driving circuits provided in an embodiment of the present disclosure;

[0059] FIG6 is a schematic diagram of the layout of the first heat dissipation holes and the second heat dissipation holes provided in an embodiment of the present disclosure;

[0060] FIG7 is a schematic diagram of the layout of the first to third heat dissipation holes provided in an embodiment of the present disclosure;

[0061] FIG8 is a schematic diagram of a first heat dissipation hole to a third heat dissipation hole provided with a heat conductive pattern according to an embodiment of the present disclosure;

[0062] FIG9 is a schematic diagram of the layout of the first to fifth heat dissipation holes provided in an embodiment of the present disclosure;

[0063] FIG10 is a schematic diagram of a thermal conductive pattern with a chamfered design according to an embodiment of the present disclosure;

[0064] FIG11 is a schematic diagram of the layout of the sixth heat dissipation hole and the seventh heat dissipation hole provided in an embodiment of the present disclosure;

[0065] FIG12 is a schematic diagram of a sixth heat dissipation hole and a seventh heat dissipation hole provided with heat conductive patterns according to an embodiment of the present disclosure;

[0066] FIG13 is a schematic diagram of the circuit structure of the gate drive circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0068] As shown in FIG5 , the display substrate provided by the present disclosure includes a gate drive circuit GOA and a plurality of sub-pixels 50. The gate drive circuit GOA is configured to provide gate drive signals to the sub-pixels 50. The output transistor To included in the gate drive circuit GOA has a large channel width-to-length ratio, which causes the output transistor To to generate a large amount of heat during operation. This heat dissipation can cause sub-pixels 50 near the gate drive circuit GOA to drift negatively, resulting in localized bright sub-pixels 50, which affects the display brightness uniformity of the display substrate.

[0069] Referring to Figures 3, 4, 6 to 12, an embodiment of the present disclosure provides a display substrate, including: a base substrate 10, and a gate drive circuit GOA and a plurality of sub-pixels 50 arranged on the base substrate 10; the display substrate also includes a heat dissipation hole structure 60 (including a first heat dissipation hole 601 to a seventh heat dissipation hole 607), and at least a part of the orthographic projection of the heat dissipation hole structure 60 on the base substrate 10 is located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the sub-pixel 50 on the base substrate 10.

[0070] Exemplarily, the sub-pixel 50 includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element. A gate driving circuit GOA is coupled to the sub-pixel driving circuit and is configured to provide a gate driving signal to the sub-pixel driving circuit. The sub-pixel driving circuit is configured to provide a driving signal to the light-emitting element based on the gate driving signal, thereby driving the light-emitting element to emit light.

[0071] Exemplarily, the heat dissipation hole structure 60 can be disposed around the gate drive circuit GOA, for example, around the output transistor To included in the gate drive circuit GOA, but is not limited thereto. The specific structure of the heat dissipation hole structure 60 varies. For example, the heat dissipation hole structure 60 can penetrate at least a portion of the insulating layer or at least a portion of the conductive film layer on the display substrate. Heat generated during operation of the gate drive circuit GOA can be dissipated through the heat dissipation hole structure 60.

[0072] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, at least a portion of the orthographic projection of the heat dissipation hole structure 60 on the base substrate 10 is arranged to be located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the sub-pixel 50 on the base substrate 10, so that the gate drive circuit GOA can effectively dissipate heat through the heat dissipation hole structure 60, thereby avoiding the heat generated during the operation of the gate drive circuit GOA from affecting the sub-pixel 50, thereby ensuring the uniformity of the display brightness of the sub-pixel 50 in the display substrate.

[0073] Please refer to Figures 2, 3, 4, 6 to 12. In some embodiments, the display substrate includes a display area 101 and a border area 102 surrounding the display area 101. The multiple sub-pixels 50 are located in the display area 101, and the gate drive circuit GOA and the heat dissipation hole structure 60 are both located in the border area 102.

[0074] Exemplarily, the gate driving circuit GOA may be arranged on the left frame and the right frame of the display substrate, but is not limited thereto.

[0075] Exemplarily, the heat dissipation hole structure 60 can be arranged on the left frame and the right frame, and the orthographic projection of the heat dissipation hole structure 60 on the base substrate 10 is set between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the sub-pixel 50 on the base substrate 10.

[0076] In the display substrate provided by the above embodiment, by setting the heat dissipation hole structure 60 in the frame area 102, not only the heat dissipation hole structure 60 is closer to the gate drive circuit GOA, which is beneficial to the heat dissipation of the gate drive circuit GOA, but also the heat dissipation hole structure 60 can be avoided from occupying the space of the display area 101, thereby ensuring the resolution of the display substrate.

[0077] As shown in Figures 3 and 4, in some embodiments, the display substrate further includes a cathode layer 20, which is located on the side of the gate drive circuit GOA facing away from the base substrate 10, and a portion of the cathode layer 20 is located in the heat dissipation hole structure 60.

[0078] Exemplarily, the cathode layer 20 is made of metal material, but is not limited thereto.

[0079] Exemplarily, the cathode layer 20 includes a portion located in the display area 101 and a portion located in the frame area 102. The portion of the cathode layer 20 located in the frame area 102 can be filled in the heat dissipation hole structure 60. For example, the cathode layer 20 and the cathode layer of the display area 101 are independent of each other.

[0080] Exemplarily, the cathode layer 20 can extend from the display area 101 to the frame area 102 .

[0081] In the display substrate provided by the above embodiment, by arranging a portion of the cathode layer 20 to be located in the heat dissipation hole structure 60 , the heat inside the heat dissipation hole structure 60 can be dissipated through the cathode layer 20 , thereby achieving a better heat dissipation effect.

[0082] As shown in FIG. 3 and FIG. 4 , in some embodiments, the cathode layer 20 located in the heat dissipation hole structure 60 is in contact with the base substrate 10 .

[0083] Illustratively, after the heat dissipation hole structure 60 is formed and before the cathode layer 20 is fabricated, the heat dissipation hole structure 60 can expose the base substrate 10 , and the cathode layer 20 can contact the base substrate 10 through the heat dissipation hole structure 60 .

[0084] The cathode layer 20 disposed in the heat dissipation hole structure 60 contacts the base substrate 10 , so that the cathode layer 20 fully contacts the inner wall of the heat dissipation hole structure 60 , which is beneficial to improving the heat dissipation effect.

[0085] As shown in Figure 4, in some embodiments, the display substrate further includes a thermal conductive pattern 40, which is located within the heat dissipation hole structure 60. The thermal conductive pattern 40 is located between the cathode layer 20 and the base substrate 10, and the thermal conductive pattern 40 is in contact with the cathode layer 20 and the base substrate 10 respectively.

[0086] Exemplarily, the heat conductive pattern 40 is in contact with or not in contact with the inner wall of the heat dissipation hole structure 60 .

[0087] Exemplarily, the heat conductive pattern 40 is provided in the same layer and material as a portion of the conductive film layer in the display substrate, and can be formed simultaneously in the same patterning process.

[0088] Exemplarily, the thermal conductive pattern 40 is made of metal material.

[0089] In the display substrate provided in the above embodiment, a thermal conductive pattern 40 is provided inside the heat dissipation hole structure 60, and the thermal conductive pattern 40 is provided to contact the cathode layer 20 and the base substrate 10 respectively, so that the heat generated by the gate drive circuit GOA can be dissipated through the heat dissipation hole structure 60, the thermal conductive pattern 40 and the cathode layer 20, thereby effectively improving the heat dissipation capability of the heat generated by the gate drive circuit GOA.

[0090] For example, the thermal conductive patterns 40 disposed within adjacent heat dissipation hole structures 60 are independent of each other, thereby enabling better independent control of heat dissipation of the gate drive circuit adjacent to the heat dissipation structure. For example, the thermal conductive patterns 40 disposed within the first heat dissipation hole 601 and the second heat dissipation hole 602 are independent of each other.

[0091] As shown in FIG. 10 , in some embodiments, the corner portion of the orthographic projection of the heat conductive pattern 40 on the base substrate 10 adopts a chamfer design X1 .

[0092] Exemplarily, the orthographic projection of the heat conducting pattern 40 on the base substrate 10 includes a rectangle, and the corner portion of the heat conducting pattern 40 adopts a chamfer design X1.

[0093] The chamfer design X1 is adopted for the corner portion of the orthographic projection of the thermal conductive pattern 40 on the base substrate 10, thereby avoiding the electrostatic breakdown phenomenon caused by the accumulation of static charge due to the overly sharp corner portion of the thermal conductive pattern 40.

[0094] As shown in Figure 4, in some embodiments, the thermal conductive pattern 40 includes at least two sub-thermal conductive patterns stacked together, the sub-thermal conductive pattern closest to the base substrate 10 contacts the base substrate 10, and the sub-thermal conductive pattern farthest from the base substrate 10 contacts the cathode layer 20.

[0095] Exemplarily, the sub-heat conductive pattern is provided in the same layer and made of the same material as a portion of the conductive film layer in the display substrate, and can be formed simultaneously in the same patterning process. Exemplarily, the sub-heat conductive pattern is made of metal material.

[0096] In the display substrate provided in the above embodiment, by setting the thermal conductive pattern including the at least two stacked sub-thermal conductive patterns, the heat generated by the gate drive circuit GOA can be dissipated through the heat dissipation hole structure 60, the at least two sub-thermal conductive patterns and the cathode layer 20, thereby effectively improving the heat dissipation capacity of the heat generated by the gate drive circuit GOA.

[0097] As shown in FIG4 , in some embodiments, the thermal conductive pattern 40 includes a first thermal conductive sub-pattern 41 and a second thermal conductive sub-pattern 42 stacked together, wherein the first thermal conductive sub-pattern 41 contacts the base substrate 10 , and the second thermal conductive sub-pattern 42 contacts the cathode layer 20 .

[0098] The first sub-heat-conducting pattern 41 is provided on the same layer and material as the gate metal layer in the display substrate, and the second sub-heat-conducting pattern 42 is provided on the same layer and material as the source / drain metal layer in the display substrate; and the area of ​​the cathode layer in the heat dissipation hole structure is larger than the area of ​​the first sub-heat-conducting pattern 41 and larger than the area of ​​the second sub-heat-conducting pattern 42.

[0099] In some embodiments, the first sub-heat conducting pattern 41 is formed in the same layer and material as the light shielding layer SHL in the display substrate, and the second sub-heat conducting pattern 42 is formed in the same layer and material as the gate metal layer GT or the source / drain metal layer SD in the display substrate.

[0100] In some embodiments, the thermal conductive pattern 40 includes a third sub-thermal conductive pattern (not shown) stacked together, a first sub-thermal conductive pattern 41, and a second sub-thermal conductive pattern 42; the third sub-thermal conductive pattern is in contact with the base substrate 10, and the third sub-thermal conductive pattern is arranged in the same layer and material as the light-shielding layer SHL in the display substrate; the first sub-thermal conductive pattern 41 is located above the third sub-thermal conductive pattern, and the first sub-thermal conductive pattern 41 is arranged in the same layer and material as the gate metal layer GT in the display substrate; the second sub-thermal conductive pattern 42 is located above the first sub-thermal conductive pattern 41, and is arranged in the same layer and material as the source / drain metal layer SD in the display substrate.

[0101] Exemplarily, the display substrate includes a light-shielding layer SHL, a buffer layer BUF, an active layer ACT, a gate insulating layer GI, a gate metal layer GT, an interlayer insulating layer ILD, a source-drain metal layer SD, a passivation layer PVX, an organic insulating layer RES, an anode layer, a pixel defining layer PDL, a light-emitting functional layer, a cathode layer 20, an inorganic encapsulation layer and a metal encapsulation layer 30, which are stacked in sequence on the base substrate 10 in a direction away from the base substrate 10.

[0102] The first sub-thermal conductive pattern 41 is provided in the same layer and material as the gate metal layer in the display substrate, so that the first sub-thermal conductive pattern 41 can be formed simultaneously with the gate metal layer in the same patterning process, thereby effectively simplifying the manufacturing process flow of the display substrate and reducing the manufacturing cost of the display substrate.

[0103] The second sub-thermal conductive pattern 42 is provided in the same layer and material as the source / drain metal layer, so that the second sub-thermal conductive pattern 42 can be formed simultaneously with the source / drain metal layer in the same patterning process, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0104] As shown in Figures 3 and 4, in some embodiments, the display substrate includes a buffer layer BUF, an interlayer insulating layer ILD, a passivation layer PVX, an organic insulating layer RES, and a pixel defining layer PDL, which are sequentially stacked on the base substrate 10 in a direction away from the base substrate 10. The heat dissipation hole structure 60 penetrates at least one of the buffer layer BUF, the interlayer insulating layer ILD, the passivation layer PVX, the organic insulating layer RES, and the pixel defining layer PDL. For example, the heat dissipation hole structure 60 penetrates the passivation layer PVX, the organic insulating layer RES, and the pixel defining layer PDL. In the display substrate provided by the above embodiment, by providing the heat dissipation hole structure 60 through the buffer layer BUF, the interlayer insulating layer ILD, the passivation layer PVX, the organic insulating layer RES, and the pixel defining layer PDL, the heat dissipation hole structure 60 has a deeper depth, effectively preventing heat accumulation between layers and enabling timely heat dissipation, thereby effectively improving the heat dissipation capability of the heat dissipation hole structure 60.

[0105] Of course, it is understandable that when there is another insulating layer or metal layer between the cathode layer of the display substrate and the base substrate 10 , the heat dissipation hole structure 60 may also penetrate the insulating layer or metal layer to expose the base substrate 10 .

[0106] As shown in FIG3 and FIG4 , in some embodiments, the display substrate further includes:

[0107] The metal packaging layer 30 is located on a side of the cathode layer 20 facing away from the base substrate 10 , and a portion of the metal packaging layer 30 is located within the heat dissipation hole structure 60 .

[0108] Exemplarily, the display substrate further includes an inorganic packaging layer (not shown in the figure), which is located between the cathode layer 20 and the metal packaging layer 30 , and a portion of the inorganic packaging layer and the metal packaging layer 30 are both located within the heat dissipation hole structure 60 .

[0109] As shown in Figures 4 to 12, in some embodiments, the cathode layers 20 between the heat dissipation hole structures 60 are independent of each other (for example, the cathode layers 20 in the third heat dissipation hole 603, the fourth heat dissipation hole 604, and the fifth heat dissipation hole 605 are independent of each other); and the area of ​​the cathode layer in the heat dissipation hole structure 60 is larger than the area of ​​the first sub-heat conductive pattern 41, and larger than the area of ​​the second sub-heat conductive pattern 42; such an independent design helps to prevent the heat of the gate drive circuits adjacent to each heat dissipation hole from spreading to other surrounding gate drive circuits.

[0110] Optionally, the area of ​​the second sub-heat conducting pattern 42 is larger than the area of ​​the first sub-heat conducting pattern 41 .

[0111] In the display substrate provided in the above embodiment, a portion of the metal packaging layer 30 is arranged to be located within the heat dissipation hole structure 60, so that the heat generated by the gate drive circuit GOA can be dissipated through the heat dissipation hole structure 60, the metal packaging layer 30 and the cathode layer 20, thereby effectively improving the heat dissipation capacity of the heat generated by the gate drive circuit GOA.

[0112] As shown in FIG4 to FIG9, in some embodiments, the display substrate further includes a first low-level signal line VGL1 and a second low-level signal line VGL2, the first low-level signal line VGL1 includes at least a portion extending along the first direction, the second low-level signal line VGL2 includes at least a portion extending along the first direction, and the orthographic projection of the second low-level signal line VGL2 on the base substrate 10 is located between the orthographic projection of the first low-level signal line VGL1 on the base substrate 10 and the display area 101;

[0113] The heat dissipation hole structure 60 includes a plurality of first heat dissipation holes 601 , at least part of the orthographic projection of the first heat dissipation holes 601 on the base substrate 10 is located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10 .

[0114] Exemplarily, a level value of a first low-level signal transmitted by the first low-level signal line VGL1 is smaller than a level value of a second low-level signal transmitted by the second low-level signal line VGL2 .

[0115] Exemplarily, the first low-level signal line VGL1 is used to transmit a first low-level signal, and the second low-level signal line VGL2 is used to transmit a second low-level signal. Exemplarily, at the left and right borders of the display substrate, the orthographic projection of the second low-level signal line VGL2 on the base substrate 10 is located between the orthographic projection of the first low-level signal line VGL1 on the base substrate 10 and the display area 101.

[0116] Exemplarily, the first low-level signal line VGL1 and / or the second low-level signal line VGL2 include two layers of metal patterns that are stacked and coupled to each other, the first metal pattern is made of a gate metal layer, the second metal pattern is made of a source-drain metal layer, the first metal pattern includes multiple hollow areas, the second metal pattern includes multiple sub-patterns, the multiple sub-patterns are arranged along the second direction, and the multiple sub-patterns are respectively coupled to the first metal pattern.

[0117] Exemplarily, the plurality of first heat dissipation holes 601 are arranged along the first direction. The plurality of first heat dissipation holes 601 are evenly distributed along the first direction.

[0118] In the display substrate provided by the above embodiment, by setting at least a part of the orthographic projection of the first heat dissipation hole 601 on the base substrate 10, it is located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10, so that the first heat dissipation hole 601 is closer to the gate drive circuit GOA, which is more conducive to dissipating the heat generated in the gate drive circuit GOA, and effectively improves the heat dissipation effect of the first heat dissipation hole 601.

[0119] As shown in FIG4 to FIG9, in some embodiments, the display substrate further includes a plurality of first signal transmission lines 71, a plurality of second signal transmission lines 72, and a plurality of first scan lines G1, the first signal transmission lines 71 include at least a portion extending along a second direction, the second signal transmission lines 72 include at least a portion extending along the second direction, and the first scan lines G1 include at least a portion extending along the second direction, where the second direction intersects the first direction;

[0120] The first signal transmission line 71 is coupled to the corresponding gate drive circuit GOA and the first low-level signal line VGL1, respectively. The second signal transmission line 72 is coupled to the corresponding gate drive circuit GOA and the corresponding first scan line G1, respectively.

[0121] The orthographic projection of the first heat dissipation hole 601 on the base substrate 10 is located between the orthographic projection of the first signal transmission line 71 and the orthographic projection of the second signal transmission line 72 on the base substrate 10 .

[0122] Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0123] As shown in FIG. 1 , illustratively, the sub-pixel driving circuit adopts a 3T1C structure, ie, includes three transistors and one capacitor, but is not limited thereto.

[0124] The sub-pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst. The display substrate includes a plurality of power lines VDD, a plurality of data lines Data, a plurality of sensing lines Sense, a plurality of first scan lines G1 and a plurality of second scan lines G2.

[0125] A first electrode of the first transistor T1 is coupled to the corresponding power line VDD, a second electrode of the first transistor T1 is coupled to the anode of the corresponding light emitting element, and a cathode of the light emitting element receives a negative power signal VSS.

[0126] The gate of the second transistor T2 is coupled to the corresponding first scan line G1, the first electrode of the second transistor T2 is coupled to the corresponding data line Data, and the second electrode of the second transistor T2 is coupled to the gate of the first transistor T1. The first scan line G1 is coupled to the corresponding gate drive circuit and receives a first scan signal provided by the corresponding gate drive circuit. The first scan signal controls the conduction and cut-off of the second transistor T2, thereby controlling whether the data signal provided by the data line Data is written to the gate of the first transistor T1.

[0127] The gate of the third transistor T3 is coupled to the corresponding second scan line G2, the first electrode of the third transistor T3 is coupled to the second electrode of the first transistor T1, and the second electrode of the third transistor T3 is coupled to the corresponding sensing line Sense. The second scan line G2 is coupled to the corresponding gate drive circuit and receives a second scan signal provided by the corresponding gate drive circuit. The second scan signal controls the conduction and cutoff of the third transistor T3, thereby realizing whether to sense the potential of the second electrode of the first transistor T1, and then realizing compensation of the sub-pixel driving circuit according to the potential.

[0128] A first terminal of the storage capacitor Cst is coupled to the gate of the first transistor T1 , and a second terminal of the storage capacitor Cst is coupled to the second electrode of the first transistor T1 .

[0129] Exemplarily, the first signal transmission line 71 and the second signal transmission line 72 are made of a source / drain metal layer, and the first scan line G1 and the second scan line G2 are made of a gate metal layer.

[0130] Exemplarily, the first signal transmission line 71 and the second signal transmission line 72 are both located in the frame area 102 , and the first scan line G1 and the second scan line G2 both include a portion located in the display area 101 and a portion located in the frame area 102 .

[0131] Exemplarily, the orthographic projection of the second signal transmission line 72 on the base substrate 10 at least partially overlaps with the orthographic projection of the first low-level signal transmission line on the base substrate 10. The orthographic projection of the second signal transmission line 72 on the base substrate 10 at least partially overlaps with the orthographic projection of the second low-level signal transmission line on the base substrate 10. The orthographic projection of the first scan line G1 on the base substrate 10 does not overlap with the orthographic projection of the first low-level signal transmission line on the base substrate 10. The orthographic projection of the second scan line G2 on the base substrate 10 does not overlap with the orthographic projection of the first low-level signal transmission line on the base substrate 10. The orthographic projection of the first scan line G1 on the base substrate 10 does not overlap with the orthographic projection of the second low-level signal transmission line on the base substrate 10. The orthographic projection of the second scan line G2 on the base substrate 10 does not overlap with the orthographic projection of the second low-level signal transmission line on the base substrate 10.

[0132] In the display substrate provided by the above embodiment, there is a larger layout space between the adjacent first signal transmission lines 71 and the second signal transmission lines 72. By setting the orthographic projection of the first heat dissipation hole 601 on the base substrate 10, which is located between the orthographic projection of the adjacent first signal transmission line 71 on the base substrate 10 and the orthographic projection of the second signal transmission line 72 on the base substrate 10, not only the layout difficulty of the first heat dissipation hole 601 is reduced, but also the first heat dissipation hole 601 can be larger in size, which is beneficial to improving the heat dissipation performance of the first heat dissipation hole 601.

[0133] As shown in Figures 4 to 9, in some embodiments, the positive projection of the first heat dissipation hole 601 on the base substrate 10 is a rectangle, the long side of the rectangle is between 145 μm and 155 μm, including the endpoint values, and the short side of the rectangle is between 25 μm and 35 μm, including the endpoint values.

[0134] Exemplarily, the long side of the orthographic projection of the first heat dissipation hole 601 on the base substrate 10 may take values ​​such as 147 μm, 149 μm, 150 μm, 152 μm, and 154 μm, but is not limited thereto.

[0135] Exemplarily, the short side of the orthographic projection of the first heat dissipation hole 601 on the base substrate 10 may take values ​​such as 27 μm, 29 μm, 30 μm, 32 μm, and 34 μm, but is not limited thereto.

[0136] Arranging the first heat dissipation holes 601 according to the above-mentioned dimensions can reduce the difficulty of arranging the first heat dissipation holes 601 while ensuring the heat dissipation performance of the first heat dissipation holes 601 .

[0137] As shown in Figures 4 to 9, in some embodiments, the gate drive circuit GOA includes a pull-down transistor Tx, and at least a portion of the orthographic projection of the first heat dissipation hole 601 on the base substrate 10 is located between the orthographic projection of the corresponding pull-down transistor Tx on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10.

[0138] Exemplarily, the number of pull-down transistors Tx included in the gate drive circuit GOA can be set according to actual needs, and one gate drive signal output terminal of the gate drive circuit GOA can correspond to at least one pull-down transistor Tx. Exemplarily, a first electrode of the pull-down transistor Tx is coupled to the corresponding gate drive signal output terminal, and a second electrode of the pull-down transistor Tx is coupled to the second low-level signal line VGL2. The pull-down transistor Tx is configured to control the electrical connection between the corresponding gate drive signal output terminal and the second low-level signal line VGL2 under the control of a signal received at its control terminal.

[0139] Exemplarily, the gate drive circuit GOA includes two gate drive signal output terminals, each gate drive signal output terminal corresponds to two pull-down transistors Tx, and the pull-down transistors Tx have a large channel width-to-length ratio.

[0140] In the display substrate provided by the above embodiment, by arranging at least a portion of the orthographic projection of the first heat dissipation hole 601 on the base substrate 10 to be located between the orthographic projection of the corresponding pull-down transistor Tx on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10, the first heat dissipation hole 601 can better dissipate the heat generated during the operation of the pull-down transistor Tx, thereby better ensuring the display brightness uniformity of the display substrate.

[0141] In some embodiments, the gate driving circuit GOA includes an output transistor To, and at least a portion of an orthographic projection of the first heat dissipation via 601 on the base substrate 10 is located between orthographic projections of adjacent output transistors To on the base substrate 10 .

[0142] Exemplarily, the number of output transistors To included in the gate drive circuit GOA can be set according to actual needs, and each gate drive signal output terminal of the gate drive circuit GOA can correspond to one output transistor To. Exemplarily, a first electrode of the output transistor To is coupled to a corresponding clock signal line, and a second electrode of the output transistor To is coupled to a corresponding gate drive signal output terminal. The output transistor To is configured to control the electrical connection between the corresponding gate drive signal output terminal and the clock signal line under the control of a signal received at its control terminal.

[0143] Exemplarily, the gate drive circuit GOA includes two gate drive signal output terminals, each gate drive signal output terminal corresponds to an output transistor To, and the output transistor To has a large channel width-to-length ratio.

[0144] In the display substrate provided in the above embodiment, by arranging at least a portion of the orthographic projection of the first heat dissipation hole 601 on the base substrate 10 to be located between the orthographic projections of adjacent output transistors To on the base substrate 10, the first heat dissipation hole 601 can better dissipate the heat generated during the operation of the output transistors To, thereby better ensuring the display brightness uniformity of the display substrate.

[0145] As shown in Figures 4 to 9, in some embodiments, the heat dissipation hole structure 60 includes a plurality of second heat dissipation holes 602, and at least a portion of the orthographic projection of the second heat dissipation holes 602 on the base substrate 10 is located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10, and the second heat dissipation holes 602 and the first heat dissipation holes 601 are alternately arranged along the first direction.

[0146] Exemplarily, the plurality of second heat dissipation holes 602 are arranged along the first direction. The plurality of second heat dissipation holes 602 are evenly distributed along the first direction.

[0147] In the display substrate provided by the above embodiment, by setting at least a part of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10, it is located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10, so that the second heat dissipation hole 602 is closer to the gate drive circuit GOA, which is more conducive to dissipating the heat generated in the gate drive circuit GOA, and effectively improves the heat dissipation effect of the second heat dissipation hole 602.

[0148] In the display substrate provided in the above embodiment, the second heat dissipation holes 602 and the first heat dissipation holes 601 are alternately arranged along the first direction, so that the first heat dissipation holes 601 and the second heat dissipation holes 602 can be evenly distributed along the first direction, thereby better improving the heat dissipation performance of the heat dissipation hole structure 60.

[0149] As shown in FIG4 to FIG9, in some embodiments, the display substrate further includes a plurality of first signal transmission lines 71, a plurality of third signal transmission lines 73, and a plurality of second scan lines G2, the first signal transmission lines 71 include at least a portion extending along the second direction, the third signal transmission lines 73 include at least a portion extending along the second direction, and the second scan lines G2 include at least a portion extending along the second direction, where the second direction intersects the first direction;

[0150] The first signal transmission line 71 is coupled to the corresponding gate drive circuit GOA and the first low-level signal line VGL1, respectively. The third signal transmission line 73 is coupled to the corresponding gate drive circuit GOA and the corresponding second scan line G2, respectively.

[0151] The orthographic projection of the second heat dissipation hole 602 on the base substrate 10 is located between the orthographic projection of the first signal transmission line 71 and the orthographic projection of the third signal transmission line 73 on the base substrate 10 .

[0152] Exemplarily, the third signal transmission line 73 is made of a source-drain metal layer.

[0153] Exemplarily, the third signal transmission line 73 is located in the border area 102 .

[0154] Exemplarily, the orthographic projection of the third signal transmission line 73 on the base substrate 10 at least partially overlaps with the orthographic projection of the first low-level signal transmission line on the base substrate 10. The orthographic projection of the third signal transmission line 73 on the base substrate 10 at least partially overlaps with the orthographic projection of the second low-level signal transmission line on the base substrate 10.

[0155] In the display substrate provided by the above embodiment, there is a larger layout space between the adjacent first signal transmission lines 71 and the third signal transmission lines 73. By setting the orthographic projection of the second heat dissipation hole 602 on the base substrate 10, it is located between the orthographic projection of the adjacent first signal transmission line 71 on the base substrate 10 and the orthographic projection of the third signal transmission line 73 on the base substrate 10. This not only reduces the layout difficulty of the second heat dissipation hole 602, but also enables the second heat dissipation hole 602 to achieve a larger size, which is beneficial to improving the heat dissipation performance of the second heat dissipation hole 602.

[0156] As shown in Figures 4 to 9, in some embodiments, there is a larger layout space between the adjacent second signal transmission lines 72 and the third signal transmission lines 73, and at least the first heat dissipation holes 601 and / or the second heat dissipation holes 602 can be set. For example, the second signal transmission line 72 is electrically connected to the first scanning line G1 of the corresponding M-th row of pixels, and the third signal transmission line 73 is electrically connected to the second scanning line G2 of the corresponding M+1-th row of pixels. Designing the heat dissipation structure in this way helps to dissipate heat from the gate drive circuits corresponding to different rows of pixels.

[0157] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 is a rectangle, the long side of the rectangle is between 145 μm and 155 μm, including the endpoint values, and the short side of the rectangle is between 10 μm and 20 μm, including the endpoint values.

[0158] Exemplarily, the long side of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 may be 147 μm, 149 μm, 150 μm, 152 μm, 154 μm, etc., but is not limited thereto.

[0159] Exemplarily, the short side of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 may be 12 μm, 14 μm, 16 μm, 18 μm, 19 μm, etc., but is not limited thereto.

[0160] Arranging the second heat dissipation holes 602 according to the above-mentioned dimensions can reduce the difficulty of arranging the second heat dissipation holes 602 while ensuring the heat dissipation performance of the second heat dissipation holes 602 .

[0161] As shown in Figures 4 to 9, in some embodiments, the gate drive circuit GOA includes a pull-down transistor Tx, and at least a portion of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 is located between the orthographic projection of the corresponding pull-down transistor Tx on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10.

[0162] In the display substrate provided by the above embodiment, by arranging at least a portion of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 to be located between the orthographic projection of the corresponding pull-down transistor Tx on the base substrate 10 and the orthographic projection of the first low-level signal line VGL1 on the base substrate 10, the second heat dissipation hole 602 can better dissipate the heat generated by the pull-down transistor Tx during operation, thereby better ensuring the display brightness uniformity of the display substrate.

[0163] As shown in Figures 4 to 9, in some embodiments, the gate driving circuit GOA includes an output transistor To, and at least part of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 is located between the orthographic projections of adjacent output transistors To on the base substrate 10.

[0164] In the display substrate provided in the above embodiment, by arranging at least a portion of the orthographic projection of the second heat dissipation hole 602 on the base substrate 10 to be located between the orthographic projections of adjacent output transistors To on the base substrate 10, the second heat dissipation hole 602 can better dissipate the heat generated during the operation of the output transistors To, thereby better ensuring the display brightness uniformity of the display substrate.

[0165] As shown in Figures 4 to 9, in some embodiments, the heat dissipation hole structure 60 includes a plurality of third heat dissipation holes 603, and at least a portion of the orthographic projection of the third heat dissipation holes 603 on the base substrate 10 is located between the orthographic projection of the second low-level signal line VGL2 on the base substrate 10 and the display area 101.

[0166] Exemplarily, at least a portion of the orthographic projection of the third heat dissipation hole 603 on the base substrate 10 is located between the orthographic projection of the output transistor To on the base substrate 10 and the display area 101 .

[0167] In the display substrate provided by the above embodiment, at least a portion of the orthographic projection of the third heat dissipation hole 603 on the base substrate 10 is located between the orthographic projection of the second low-level signal line VGL2 on the base substrate 10 and the display area 101. The heat near the display area 101 can be dissipated through the third heat dissipation hole 603, effectively blocking the path for heat transmission to the display area, which is conducive to further improving the display brightness uniformity of the display substrate.

[0168] As shown in FIG4 to FIG9, in some embodiments, the display substrate further includes a plurality of second signal transmission lines 72, a plurality of third signal transmission lines 73, a plurality of first scan lines G1, and a plurality of second scan lines G2; the second signal transmission lines 72 include at least a portion extending along a second direction, the third signal transmission lines 73 include at least a portion extending along the second direction, the first scan lines G1 include at least a portion extending along the second direction, and the second scan lines G2 include at least a portion extending along the second direction; the second direction intersects the first direction;

[0169] The second signal transmission line 72 is respectively coupled to the corresponding gate drive circuit GOA and the corresponding first scan line G1, and the third signal transmission line 73 is respectively coupled to the corresponding gate drive circuit GOA and the corresponding second scan line G2;

[0170] The orthographic projection of the third heat dissipation hole 603 on the base substrate 10 is located between the orthographic projection of the second signal transmission line 72 and the orthographic projection of the third signal transmission line 73 on the base substrate 10 .

[0171] In the display substrate provided by the above embodiment, there is a larger layout space between the adjacent second signal transmission lines 72 and the third signal transmission lines 73. By setting the orthographic projection of the third heat dissipation hole 603 on the base substrate 10, it is located between the orthographic projection of the adjacent second signal transmission line 72 on the base substrate 10 and the orthographic projection of the third signal transmission line 73 on the base substrate 10. This not only reduces the layout difficulty of the third heat dissipation hole 603, but also enables the third heat dissipation hole 603 to achieve a larger size, which is beneficial to improving the heat dissipation performance of the third heat dissipation hole 603.

[0172] As shown in Figures 4 to 9, in some embodiments, the third heat dissipation hole 603 corresponds to the via-hole layer-changing coupling point between the second signal transmission line 72 and the first scan line G1 on the base substrate 10, and corresponds to the via-hole layer-changing coupling point between the third signal transmission line 73 and the second scan line G2, which helps to dissipate the heat generated by the metal at the via-hole layer-changing coupling point.

[0173] As shown in Figures 4 to 9, in some embodiments, the positive projection of the third heat dissipation hole 603 on the base substrate 10 is a rectangle, the long side of the rectangle is between 150 μm and 160 μm, including the endpoint values, and the short side of the rectangle is between 60 μm and 70 μm, including the endpoint values.

[0174] Exemplarily, the long side of the orthographic projection of the third heat dissipation hole 603 on the base substrate 10 may be 152 μm, 154 μm, 156 μm, 158 μm, 159 μm, etc., but is not limited thereto.

[0175] Exemplarily, the short side of the orthographic projection of the third heat dissipation hole 603 on the base substrate 10 may have values ​​such as 62 μm, 64 μm, 66 μm, 68 μm, and 69 μm, but is not limited thereto.

[0176] Arranging the third heat dissipation holes 603 according to the above-mentioned size can reduce the difficulty of arranging the third heat dissipation holes 603 while ensuring the heat dissipation performance of the third heat dissipation holes 603 .

[0177] As shown in Figures 4 to 9, in some embodiments, at least a portion of the orthographic projection of the third heat dissipation hole 603 on the base substrate 10 is located between the orthographic projection of the second low-level signal transmission line on the base substrate 10 and the orthographic projection of the corresponding first scan line G1 on the base substrate 10; and / or, at least a portion of the orthographic projection of the third heat dissipation hole 603 on the base substrate 10 is located between the orthographic projection of the second low-level signal transmission line on the base substrate 10 and the orthographic projection of the corresponding second scan line G2 on the base substrate 10.

[0178] The above arrangement can dissipate the heat near the display area 101 through the third heat dissipation holes 603 , which is beneficial for further improving the display brightness uniformity of the display substrate.

[0179] As shown in Figures 4 to 9, in some embodiments, the heat dissipation hole structure 60 includes a plurality of fourth heat dissipation holes 604, and at least a portion of the orthographic projection of the fourth heat dissipation holes 604 on the base substrate 10 is located between the orthographic projection of the second low-level signal line VGL2 on the base substrate 10 and the display area 101; the fourth heat dissipation holes 604 and the third heat dissipation holes 603 are alternately arranged along the first direction.

[0180] Exemplarily, the plurality of fourth heat dissipation holes 604 are arranged along the first direction. The plurality of fourth heat dissipation holes 604 are evenly distributed along the first direction.

[0181] In the display substrate provided in the above embodiment, at least a portion of the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 is provided, and is located between the orthographic projection of the second low-level signal line VGL2 on the base substrate 10 and the display area 101. The heat near the display area 101 can be dissipated through the fourth heat dissipation hole 604, which is beneficial to further improve the display brightness uniformity of the display substrate.

[0182] In the display substrate provided in the above embodiment, the fourth heat dissipation holes 604 and the third heat dissipation holes 603 are alternately arranged along the first direction, so that the third heat dissipation holes 603 and the fourth heat dissipation holes 604 can be evenly distributed along the first direction, thereby better improving the heat dissipation performance of the heat dissipation hole structure 60.

[0183] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 is located between the orthographic projection of the adjacent second signal transmission line 72 on the base substrate 10 and the orthographic projection of the third signal transmission line 73 on the base substrate 10.

[0184] In the display substrate provided by the above embodiment, there is a larger layout space between the adjacent second signal transmission line 72 and the third signal transmission line 73. By setting the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10, it is located between the orthographic projection of the adjacent second signal transmission line 72 on the base substrate 10 and the orthographic projection of the third signal transmission line 73 on the base substrate 10. This not only reduces the layout difficulty of the fourth heat dissipation hole 604, but also enables the fourth heat dissipation hole 604 to achieve a larger size, which is beneficial to improving the heat dissipation performance of the fourth heat dissipation hole 604.

[0185] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 is located between the orthographic projection of the second signal transmission line 72 and the orthographic projection of the third signal transmission line 73 connecting the same row of pixels on the base substrate 10; or the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 is located between the orthographic projection of the first scan line G1 and the orthographic projection of the second scan line G2 connecting the same row of pixels on the base substrate 10, thereby dissipating heat when the same row of pixels is in operation. For example, the first scan line G1 and the second scan line G2 of the same row of pixels use the same timing.

[0186] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 is a rectangle, the long side of the rectangle is between 55 μm and 65 μm, including the endpoint values, and the short side of the rectangle is between 30 μm and 40 μm, including the endpoint values.

[0187] Exemplarily, the long side of the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 may have values ​​such as 57 μm, 59 μm, 60 μm, 62 μm, and 64 μm, but is not limited thereto.

[0188] Exemplarily, the short side of the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 may have values ​​such as 32 μm, 34 μm, 36 μm, 38 μm, 39 μm, etc., but is not limited thereto.

[0189] Arranging the fourth heat dissipation holes 604 according to the above-mentioned dimensions can reduce the difficulty of arranging the fourth heat dissipation holes 604 while ensuring the heat dissipation performance of the fourth heat dissipation holes 604 .

[0190] As shown in Figures 4 to 9, in some embodiments, the heat dissipation hole structure 60 includes a plurality of fifth heat dissipation holes 605, and at least part of the orthographic projection of the fifth heat dissipation holes 605 on the base substrate 10 is located between the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 and the display area 101.

[0191] Illustratively, the orthographic projection area of ​​at least some of the heat dissipation hole structures near the display area 101 on the base substrate is larger than the orthographic projection area of ​​the heat dissipation hole structures farther from the display area 101, because heat dissipation is more required near the display area 101. For example, the orthographic projection area of ​​the fifth heat dissipation hole 605 on the base substrate 10 is larger than the orthographic projection area of ​​the fourth heat dissipation hole 604 on the base substrate 10.

[0192] Exemplarily, an orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 is at least partially offset from an orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 along the first direction.

[0193] In the display substrate provided in the above embodiment, at least a portion of the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 is located between the orthographic projection of the fourth heat dissipation hole 604 on the base substrate 10 and the display area 101. The heat near the display area 101 can be dissipated through the fifth heat dissipation hole 605, which is beneficial to further improve the display brightness uniformity of the display substrate.

[0194] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 is located between the orthographic projections of the adjacent first scanning line G1 and the orthographic projections of the second scanning line G2 on the base substrate 10.

[0195] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 is located between the orthographic projection of the first scan line G1 and the orthographic projection of the second scan line G2 corresponding to the same row of pixels on the base substrate 10, which facilitates heat dissipation when the same row of pixels is in operation. For example, the first scan line G1 and the second scan line G2 corresponding to the same row of pixels use the same timing.

[0196] In the display substrate provided by the above embodiment, there is a large layout space between the adjacent first scan line G1 and the second scan line G2. By arranging the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 to be located between the orthographic projection of the adjacent first scan line G1 on the base substrate 10 and the orthographic projection of the second scan line G2 on the base substrate 10, not only is the layout difficulty of the fifth heat dissipation hole 605 reduced, but the fifth heat dissipation hole 605 can also be larger in size, which is conducive to improving the heat dissipation performance of the fifth heat dissipation hole 605.

[0197] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 is a rectangle, the long side of the rectangle is between 170 μm and 180 μm, including endpoint values, and the short side of the rectangle is between 110 μm and 120 μm, including endpoint values.

[0198] Exemplarily, the long side of the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 may be 172 μm, 174 μm, 176 μm, 178 μm, 179 μm, etc., but is not limited thereto.

[0199] Exemplarily, the short side of the orthographic projection of the fifth heat dissipation hole 605 on the base substrate 10 may have values ​​such as 112 μm, 114 μm, 116 μm, 118 μm, and 119 μm, but is not limited thereto.

[0200] Arranging the fifth heat dissipation holes 605 according to the above-mentioned dimensions can reduce the difficulty of arranging the fifth heat dissipation holes 605 while ensuring the heat dissipation performance of the fifth heat dissipation holes 605 .

[0201] As shown in FIG11 and FIG12 , in some embodiments, the gate drive circuit GOA includes a first output transistor To1 and a first capacitor C1, wherein a first plate of the first capacitor C1 is coupled to the gate of the first output transistor To1, and a second plate of the first capacitor C1 is coupled to the second electrode of the first output transistor To1;

[0202] The heat dissipation hole structure 60 includes a plurality of sixth heat dissipation holes 606 , and the sixth heat dissipation holes 606 pass through the first electrode plate and the second electrode plate.

[0203] Illustratively, the larger the areas of the first electrode plate and the second electrode plate are, the larger the area of ​​the orthographic projection of the sixth heat dissipation hole 606 on the substrate is.

[0204] Exemplarily, the gate drive circuit GOA includes a first gate drive signal output terminal, a first electrode of the first output transistor To1 is coupled to the corresponding clock signal line, and a second electrode of the first output transistor To is coupled to the first gate drive signal output terminal.

[0205] Illustratively, the orthographic projection of the first electrode plate on the base substrate 10 at least partially overlaps with the orthographic projection of the second electrode plate on the base substrate 10 .

[0206] Exemplarily, one of the first electrode plate and the second electrode plate is made of the gate metal layer, and the other of the first electrode plate and the second electrode plate is made of the source / drain metal layer.

[0207] Since the first capacitor C1 is coupled to the first output transistor To1, the sixth heat dissipation hole 606 is provided to pass through the first electrode plate and the second electrode plate, so that the sixth heat dissipation hole 606 can dissipate the heat generated by the first capacitor C1 and the first output transistor To1, thereby better improving the heat dissipation effect of the display substrate.

[0208] As shown in FIG11 and FIG12 , in some embodiments, the gate drive circuit GOA includes a second output transistor To2 and a second capacitor C2, wherein the third plate of the second capacitor C2 is coupled to the gate of the second output transistor To2, and the fourth plate of the second capacitor C2 is coupled to the second electrode of the second output transistor To2;

[0209] The heat dissipation hole structure 60 includes a plurality of seventh heat dissipation holes 607 , and the seventh heat dissipation holes 607 pass through the third electrode plate and the fourth electrode plate.

[0210] Illustratively, the larger the areas of the third electrode plate and the fourth electrode plate are, the larger the area of ​​the orthographic projection of the seventh heat dissipation hole 607 on the substrate is.

[0211] Exemplarily, the gate drive circuit GOA includes a second gate drive signal output terminal, a first electrode of the second output transistor To2 is coupled to the corresponding clock signal line, and a second electrode of the second output transistor To2 is coupled to the second gate drive signal output terminal.

[0212] Illustratively, the orthographic projection of the third electrode plate on the base substrate 10 at least partially overlaps with the orthographic projection of the fourth electrode plate on the base substrate 10 .

[0213] Exemplarily, one of the third electrode plate and the fourth electrode plate is made of the gate metal layer, and the other of the third electrode plate and the fourth electrode plate is made of the source / drain metal layer.

[0214] Since the second capacitor C2 is coupled to the second output transistor To2, the seventh heat dissipation hole 607 is provided to pass through the third plate and the fourth plate, so that the seventh heat dissipation hole 607 can dissipate the heat generated by the second capacitor C2 and the second output transistor To2, thereby better improving the heat dissipation effect of the display substrate.

[0215] As shown in FIG11 and FIG12 , in some embodiments, the gate drive circuit GOA includes a first output transistor To1 and a first capacitor C1, wherein a first plate of the first capacitor C1 is coupled to the gate of the first output transistor To1, and a second plate of the first capacitor C1 is coupled to the second electrode of the first output transistor To1;

[0216] A first boundary of the cathode layer 20 is located between an orthographic projection of the first electrode plate on the base substrate 10 and an orthographic projection of the third electrode plate on the base substrate 10 .

[0217] Exemplarily, the cathode layer 20 fills the interior of one of the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607 .

[0218] Illustratively, a heat conducting pattern 40 is provided in the sixth heat dissipation hole 606 and / or the seventh heat dissipation hole 607 , and the heat conducting pattern 40 is in contact with or not in contact with the inner wall of the sixth heat dissipation hole 606 and / or the seventh heat dissipation hole 607 .

[0219] As shown in Figures 11 and 12, in some embodiments, the orthographic projection of the first capacitor C1 on the base substrate 10 and the orthographic projection of the second capacitor C2 on the base substrate 10 are set to be located between the orthographic projection of the first output transistor To1 on the base substrate 10 and the orthographic projection of the second output transistor To2 on the base substrate 10.

[0220] The above-mentioned setting method enables the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607 to better dissipate the heat generated by the first capacitor C1, the second capacitor C2, the first output transistor To1 and the second output transistor To2 during operation, thereby better improving the heat dissipation effect of the display substrate.

[0221] As shown in FIG13 , a circuit structure diagram of a gate driving circuit is shown. The circuit structure of the gate driving circuit used in the display substrate provided in the embodiment of the present disclosure is not limited thereto, and a simpler or more complex circuit structure may be used.

[0222] Figure 13 illustrates the gate drive circuit including a fourth transistor M4, an eighth transistor M8, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M22_b, a twenty-fourth transistor M24, a twenty-fifth transistor M24_b, a thirty-fifth transistor M35, a thirty-sixth transistor M36, a thirty-seventh transistor M37, a thirty-ninth transistor M39, a fortieth transistor M39_b, a forty-first transistor M41, a forty-second transistor M41_b, a first output transistor To1, a second output transistor To2, a first capacitor C1, a second capacitor C2, a first pull-down transistor Tx1, a second pull-down transistor Tx2, a third pull-down transistor Tx3, and a fourth pull-down transistor Tx4.

[0223] Figure 13 also illustrates the power line VDD, the second power line VDD_B, the first input signal line STU1, the first reset line TRST, the second reset line STD, the first clock signal line CLKA, the second clock signal line CLKD, the third clock signal line CLKF, the first low-level signal line VGL1, the second low-level signal line VGL2, the first node N, the second node Q2, the third node OF, the fourth node QB_B, the fifth node H, the sixth node QB_A, the first gate drive signal output terminal OP2, and the second gate drive signal output terminal OP4.

[0224] In some embodiments, at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607 satisfies at least a portion of the orthographic projection on the base substrate 10, and is located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the sub-pixel 50 on the base substrate 10.

[0225] In some embodiments, at least one of the first heat dissipation hole 601 , the second heat dissipation hole 602 , the third heat dissipation hole 603 , the fourth heat dissipation hole 604 , the fifth heat dissipation hole 605 , the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607 is located in the frame area 102 .

[0226] In some embodiments, a portion of the cathode layer 20 is located inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607.

[0227] In some embodiments, the cathode layer 20 contacts the base substrate 10 inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607.

[0228] In some embodiments, the thermal conductive pattern is located inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607, and the thermal conductive pattern is in contact with the cathode layer 20 and the base substrate 10 respectively.

[0229] In some embodiments, inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607, the corner portion of the positive projection of the thermal conductive pattern on the base substrate 10 adopts a chamfer design X1.

[0230] In some embodiments, inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607, the thermal conductive pattern includes at least two sub-thermal conductive patterns stacked together, the sub-thermal conductive pattern closest to the base substrate 10 contacts the base substrate 10, and the sub-thermal conductive pattern farthest from the base substrate 10 contacts the cathode layer 20.

[0231] In some embodiments, inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607, the thermal conductive pattern includes a first sub-thermal conductive pattern 41 and a second sub-thermal conductive pattern 42 arranged in a stacked manner, the first sub-thermal conductive pattern 41 contacts the base substrate 10, and the second sub-thermal conductive pattern 42 contacts the cathode layer 20; the first sub-thermal conductive pattern 41 is arranged in the same layer and material as the gate metal layer in the display substrate, and the second sub-thermal conductive pattern 42 is arranged in the same layer and material as the source and drain metal layer in the display substrate.

[0232] In some embodiments, at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607 can penetrate the buffer layer, the interlayer insulating layer, the passivation layer, the organic insulating layer and the pixel defining layer.

[0233] In some embodiments, a portion of the metal packaging layer 30 is located inside at least one of the first heat dissipation hole 601, the second heat dissipation hole 602, the third heat dissipation hole 603, the fourth heat dissipation hole 604, the fifth heat dissipation hole 605, the sixth heat dissipation hole 606 and the seventh heat dissipation hole 607.

[0234] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0235] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0236] In the display substrate provided by the above embodiment, at least a portion of the orthographic projection of the heat dissipation hole structure 60 on the base substrate 10 is arranged to be located between the orthographic projection of the gate drive circuit GOA on the base substrate 10 and the orthographic projection of the sub-pixel 50 on the base substrate 10, so that the gate drive circuit GOA can effectively dissipate heat through the heat dissipation hole structure 60, thereby avoiding the heat generated during the operation of the gate drive circuit GOA from affecting the sub-pixel 50, thereby ensuring the uniformity of the display brightness of the sub-pixel 50 in the display substrate.

[0237] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0238] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extended along the certain direction is greater than the length of the secondary part extended along other directions.

[0239] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0240] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0241] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0242] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0243] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0244] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0245] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate, and a gate drive circuit and a plurality of sub-pixels arranged on the base substrate; the display substrate also includes a heat dissipation hole structure, at least part of the orthographic projection of the heat dissipation hole structure on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the sub-pixels on the base substrate.

2. The display substrate according to claim 1, wherein The display substrate includes a display area and a frame area surrounding the display area. The multiple sub-pixels are located in the display area. The gate driving circuit and the heat dissipation hole structure are both located in the frame area.

3. The display substrate according to claim 2, wherein: The display substrate further includes a cathode layer, which is located on a side of the gate driving circuit facing away from the base substrate, and a portion of the cathode layer is located within the heat dissipation hole structure.

4. The display substrate according to claim 3, wherein: The cathode layer located in the heat dissipation hole structure contacts the base substrate.

5. The display substrate according to claim 3, wherein: The display substrate further includes a heat-conducting pattern, which is located in the heat dissipation hole structure, between the cathode layer and the base substrate, and in contact with the cathode layer and the base substrate respectively. The display substrate according to claim 5 , wherein: The corner portion of the orthographic projection of the heat-conducting pattern on the base substrate adopts a chamfer design.

7. The display substrate according to claim 5, wherein: The heat conducting pattern includes at least two stacked sub-heat conducting patterns, the sub-heat conducting pattern closest to the base substrate contacts the base substrate, and the sub-heat conducting pattern farthest from the base substrate contacts the cathode layer.

8. The display substrate according to claim 7, wherein: The heat-conducting pattern includes a first heat-conducting sub-pattern and a second heat-conducting sub-pattern stacked together, wherein the first heat-conducting sub-pattern contacts the base substrate, and the second heat-conducting sub-pattern contacts the cathode layer; The first sub-heat-conducting pattern is provided on the same layer and with the same material as the gate metal layer in the display substrate, and the second sub-heat-conducting pattern is provided on the same layer and with the same material as the source / drain metal layer in the display substrate; and the area of ​​the cathode layer in the heat dissipation hole structure is larger than the area of ​​the first sub-heat-conducting pattern and larger than the area of ​​the second sub-heat-conducting pattern.

9. The display substrate according to claim 1, wherein: The display substrate includes a buffer layer, an interlayer insulating layer, a passivation layer, an organic insulating layer and a pixel defining layer stacked in sequence on the base substrate in a direction away from the base substrate, and the heat dissipation hole structure passes through the buffer layer, the interlayer insulating layer, the passivation layer, the organic insulating layer and the pixel defining layer.

10. The display substrate according to claim 3, wherein: The display substrate further includes: A metal packaging layer is located on a side of the cathode layer facing away from the substrate, and a portion of the metal packaging layer is located within the heat dissipation hole structure.

11. The display substrate according to any one of claims 1 to 10, wherein The display substrate further includes a first low-level signal line and a second low-level signal line, the first low-level signal line includes at least a portion extending along a first direction, the second low-level signal line includes at least a portion extending along the first direction, and an orthographic projection of the second low-level signal line on the base substrate is located between the orthographic projection of the first low-level signal line on the base substrate and the display area; The heat dissipation hole structure includes a plurality of first heat dissipation holes, and at least a portion of the orthographic projection of the first heat dissipation holes on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the first low-level signal line on the base substrate.

12. The display substrate according to claim 11, wherein: The display substrate further includes a plurality of first signal transmission lines, a plurality of second signal transmission lines, and a plurality of first scan lines, wherein the first signal transmission lines include at least a portion extending along a second direction, the second signal transmission lines include at least a portion extending along the second direction, and the first scan lines include at least a portion extending along the second direction, wherein the second direction intersects the first direction; The first signal transmission line is coupled to the corresponding gate drive circuit and the first low-level signal line respectively, and the second signal transmission line is coupled to the corresponding gate drive circuit and the corresponding first scan line respectively; The orthographic projection of the first heat dissipation hole on the base substrate is located between the orthographic projection of the first signal transmission line and the orthographic projection of the second signal transmission line on the base substrate.

13. The display substrate according to claim 12, wherein: The orthographic projection of the first heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 145 μm and 155 μm, and the short side of the rectangle is between 25 μm and 35 μm.

14. The display substrate according to claim 12, wherein: The gate drive circuit includes a pull-down transistor, and at least a portion of the orthographic projection of the first heat dissipation hole on the base substrate is located between the orthographic projection of the corresponding pull-down transistor on the base substrate and the orthographic projection of the first low-level signal line on the base substrate.

15. The display substrate according to claim 12, wherein: The gate driving circuit includes an output transistor, and at least a portion of an orthographic projection of the first heat dissipation via on the base substrate is located between orthographic projections of adjacent output transistors on the base substrate.

16. The display substrate according to claim 11, wherein The heat dissipation hole structure includes a plurality of second heat dissipation holes, at least part of the orthographic projection of the second heat dissipation holes on the base substrate is located between the orthographic projection of the gate drive circuit on the base substrate and the orthographic projection of the first low-level signal line on the base substrate, and the second heat dissipation holes and the first heat dissipation holes are alternately arranged along the first direction.

17. The display substrate according to claim 16, wherein: The display substrate further includes a plurality of first signal transmission lines, a plurality of third signal transmission lines, and a plurality of second scan lines, wherein the first signal transmission lines include at least a portion extending along a second direction, the third signal transmission lines include at least a portion extending along the second direction, and the second scan lines include at least a portion extending along the second direction, wherein the second direction intersects the first direction; The first signal transmission line is coupled to the corresponding gate drive circuit and the first low-level signal line respectively, and the third signal transmission line is coupled to the corresponding gate drive circuit and the corresponding second scan line respectively; The orthographic projection of the second heat dissipation hole on the base substrate is located between the orthographic projection of the first signal transmission line and the orthographic projection of the third signal transmission line on the base substrate.

18. The display substrate according to claim 17, wherein: The orthographic projection of the second heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 145 μm and 155 μm, and the short side of the rectangle is between 10 μm and 20 μm.

19. The display substrate according to claim 17, wherein: The gate drive circuit includes a pull-down transistor, and at least a portion of the orthographic projection of the second heat dissipation hole on the base substrate is located between the orthographic projection of the corresponding pull-down transistor on the base substrate and the orthographic projection of the first low-level signal line on the base substrate.

20. The display substrate according to claim 17, wherein The gate driving circuit includes an output transistor, and at least a portion of an orthographic projection of the second heat dissipation via on the base substrate is located between orthographic projections of adjacent output transistors on the base substrate.

21. The display substrate according to claim 11, wherein The heat dissipation hole structure includes a plurality of third heat dissipation holes, and at least a portion of the orthographic projection of the third heat dissipation holes on the base substrate is located between the orthographic projection of the second low-level signal line on the base substrate and the display area.

22. The display substrate according to claim 21, wherein The display substrate further includes a plurality of second signal transmission lines, a plurality of third signal transmission lines, a plurality of first scan lines, and a plurality of second scan lines; the second signal transmission lines include at least a portion extending along a second direction, the third signal transmission lines include at least a portion extending along the second direction, the first scan lines include at least a portion extending along the second direction, and the second scan lines include at least a portion extending along the second direction; the second direction intersects the first direction; The second signal transmission line is coupled to the corresponding gate driving circuit and the corresponding first scan line respectively, and the third signal transmission line is coupled to the corresponding gate driving circuit and the corresponding second scan line respectively; The orthographic projection of the third heat dissipation hole on the base substrate is located between the orthographic projection of the second signal transmission line and the orthographic projection of the third signal transmission line on the base substrate.

23. The display substrate according to claim 22, wherein: The orthographic projection of the third heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 150 μm and 160 μm, and the short side of the rectangle is between 60 μm and 70 μm.

24. The display substrate according to claim 22, wherein: At least a portion of the orthographic projection of the third heat dissipation hole on the base substrate is located between the orthographic projection of the second low-level signal transmission line on the base substrate and the orthographic projection of the corresponding first scanning line on the base substrate; And / or, at least a portion of the orthographic projection of the third heat dissipation hole on the base substrate is located between the orthographic projection of the second low-level signal transmission line on the base substrate and the orthographic projection of the corresponding second scan line on the base substrate.

25. The display substrate according to claim 22, wherein: The heat dissipation hole structure includes a plurality of fourth heat dissipation holes, at least part of the orthographic projection of the fourth heat dissipation holes on the base substrate is located between the orthographic projection of the second low-level signal line on the base substrate and the display area; the fourth heat dissipation holes and the third heat dissipation holes are alternately arranged along the first direction.

26. The display substrate according to claim 25, wherein: The orthographic projection of the fourth heat dissipation hole on the base substrate is located between the orthographic projection of the second signal transmission line and the orthographic projection of the third signal transmission line on the base substrate.

27. The display substrate according to claim 25, wherein: The orthographic projection of the fourth heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 55 μm and 65 μm, and the short side of the rectangle is between 30 μm and 40 μm.

28. The display substrate according to claim 25, wherein: The heat dissipation hole structure includes a plurality of fifth heat dissipation holes, and at least a portion of the orthographic projection of the fifth heat dissipation holes on the base substrate is located between the orthographic projection of the fourth heat dissipation hole on the base substrate and the display area.

29. The display substrate according to claim 28, wherein: The orthographic projection of the fifth heat dissipation hole on the base substrate is located between the orthographic projection of the first scanning line and the orthographic projection of the second scanning line on the base substrate.

30. The display substrate according to claim 28, wherein The orthographic projection of the fifth heat dissipation hole on the base substrate is a rectangle, the long side of the rectangle is between 170 μm and 180 μm, and the short side of the rectangle is between 110 μm and 120 μm.

31. The display substrate according to any one of claims 1 to 10, wherein The gate drive circuit includes a first output transistor and a first capacitor, wherein a first plate of the first capacitor is coupled to the gate of the first output transistor, and a second plate of the first capacitor is coupled to the second electrode of the first output transistor; The heat dissipation hole structure includes a plurality of sixth heat dissipation holes, and the sixth heat dissipation holes penetrate the first electrode plate and the second electrode plate.

32. The display substrate according to any one of claims 1 to 10, wherein The gate drive circuit includes a second output transistor and a second capacitor, the third plate of the second capacitor is coupled to the gate of the second output transistor, and the fourth plate of the second capacitor is coupled to the second electrode of the second output transistor; The heat dissipation hole structure includes a plurality of seventh heat dissipation holes, and the seventh heat dissipation holes penetrate the third electrode plate and the fourth electrode plate.

33. The display substrate according to claim 32, wherein: The gate drive circuit includes a first output transistor and a first capacitor, wherein a first plate of the first capacitor is coupled to the gate of the first output transistor, and a second plate of the first capacitor is coupled to the second electrode of the first output transistor; A first boundary of the cathode layer is located between an orthographic projection of the first electrode plate on the base substrate and an orthographic projection of the third electrode plate on the base substrate.

34. The display substrate according to claim 32, wherein: The orthographic projection of the first capacitor on the substrate and the orthographic projection of the second capacitor on the substrate are both located between the orthographic projection of the first output transistor on the substrate and the orthographic projection of the second output transistor on the substrate.

35. A display device comprising the display substrate according to any one of claims 1 to 34.

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