Two-channel multi-mode radio frequency receiver and navigation positioning system thereof
By designing a dual-channel multi-mode RF receiver and adopting a new on-chip receiver architecture, a highly integrated, small-sized navigation and positioning system with low noise and low power consumption is achieved, solving the size and power consumption problems in existing technologies.
Patent Information
- Application Number
- CN202511010729.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-22
- Publication Date
- 2025-09-26
AI Technical Summary
Existing navigation and positioning systems have problems of large size and high power consumption, especially the integration and power consumption of RF receivers are difficult to further improve at new process nodes.
A dual-channel multi-mode RF receiver is designed with a new on-chip receiver architecture, including a low-noise amplifier module, an intermediate frequency processing module, a gain amplifier module, a conversion clock module, an analog-to-digital conversion module, and an automatic gain control module. Through low-noise amplification, differential signal conversion, and gain control, it achieves high integration, small size, and low power consumption.
It realizes the simultaneous reception of navigation satellite signals of different frequency bands under low noise and low power consumption, and converts them into differential signals, achieving the goals of high integration, small size and low power consumption, and solving the size and power consumption problems in the existing technology.
Smart Images
Figure CN120703786A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of wireless navigation and positioning, and in particular to a dual-channel multi-mode radio frequency receiver and a navigation and positioning system thereof. Background Art
[0002] With the continuous advancement of technology and the increasing use of new electronic products, people's requirements for navigation and positioning systems are becoming increasingly higher. Currently, there are four major global navigation and positioning systems. These systems can provide accurate navigation information anytime, anywhere, 24 / 7. In addition to receiving as many navigation satellite signals as possible to improve positioning accuracy, they also have high requirements for small size and low power consumption. Therefore, low-power, highly integrated navigation and positioning systems are becoming increasingly important, especially RF receivers.
[0003] Over the past decade or so, with the continuous evolution of process nodes and the research of new architectures, semiconductor products have become increasingly smaller and more integrated. However, new process nodes also come with higher costs, especially with the latest processes where the cost per square meter of wafer has doubled. Furthermore, while new process nodes can significantly reduce the power consumption and area of digital circuits, the reductions in power consumption and area for analog circuits (such as RF receivers) are relatively small.
[0004] Due to the inherent characteristics of navigation satellite signals, the signals received on the ground are very weak and easily interfered with by other external signals. Therefore, the RF receiver requires high gain for signal amplification to meet demodulation requirements. To meet this amplification factor, an off-chip low-noise amplifier is typically used for signal amplification, and passive inductors and capacitors are typically used for matching. This results in an oversized system and high power consumption. Furthermore, off-chip circuits such as power management and clock generation not only reduce integration but also pose size and power consumption issues. Therefore, providing a small-sized, low-power, highly integrated RF receiver and its associated navigation and positioning system has become a technical issue that those skilled in the art are eager to address.
[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a dual-channel multi-mode radio frequency receiver and a navigation and positioning system thereof, so as to solve the problems of large size and high power consumption in the existing navigation and positioning systems.
[0007] To achieve the above objectives and other related objectives, the present invention provides a dual-channel multi-mode radio frequency receiver, wherein the dual-channel multi-mode radio frequency receiver includes at least two receiving channels, and the receiving channels include:
[0008] a low-noise amplifier module, receiving a single-ended RF voltage signal and performing voltage-to-current conversion and gain amplification operations to generate a single-ended RF current signal;
[0009] an intermediate frequency processing module connected to the low-noise amplification module, generating a differential intermediate frequency current signal by performing frequency conversion on the single-ended RF current signal, and performing current-to-voltage conversion to generate a differential intermediate frequency voltage signal;
[0010] a gain amplification module connected to the intermediate frequency processing module, generating a differential analog signal by performing a gain amplification operation on the differential intermediate frequency voltage signal, and receiving a first gain control instruction and performing a gain control operation;
[0011] A conversion clock module receives a local oscillator signal and performs frequency division processing on the local oscillator signal to generate a conversion clock signal;
[0012] an analog-to-digital conversion module, connected to the gain amplification module and the conversion clock module respectively, and performing analog-to-digital conversion on the differential analog signal to generate a digital signal according to the conversion clock signal;
[0013] An automatic gain control module is connected to the analog-to-digital conversion module and generates the first gain adjustment instruction by performing amplitude judgment on the digital signal.
[0014] Optionally, the low-noise amplification module further receives a second gain control instruction and performs a gain control operation, wherein the automatic gain control module generates the second gain control instruction while generating the first gain control instruction.
[0015] Optionally, the low-noise amplification module is implemented by cascading at least two stages of amplification structures.
[0016] Optionally, the intermediate frequency processing module includes:
[0017] a frequency mixing unit connected to the low-noise amplification module, and performing orthogonal frequency conversion on the single-ended RF current signal through the local oscillator signal to generate the differential intermediate frequency current signal;
[0018] The intermediate frequency filtering unit is connected to the mixing unit, and generates the differential intermediate frequency voltage signal by performing current-to-voltage conversion, filtering, and gain amplification operations on the differential intermediate frequency current signal, and completes a bandwidth switching operation.
[0019] Optionally, the frequency mixing unit is implemented by an NMOS tube passive switch structure.
[0020] Optionally, the intermediate frequency filtering unit further receives a third gain control instruction and performs a gain control operation, wherein the automatic gain control module generates the third gain control instruction while generating the first gain control instruction.
[0021] Optionally, the intermediate frequency filtering unit is implemented by a capacitor array and a resistor array.
[0022] Optionally, the analog-to-digital conversion module is implemented by a successive approximation analog-to-digital converter.
[0023] Optionally, the automatic gain control module performs amplitude judgment and mismatch judgment on the digital signal, and generates a corresponding gain control instruction according to the two judgment results.
[0024] Optionally, the receiving channel further includes a local oscillation module, configured to provide the local oscillation signal.
[0025] Optionally, the dual-channel multi-mode radio frequency receiver further includes at least one of a reference providing module, an interface module, and a power management module;
[0026] The reference providing module provides a reference clock signal by driving an external crystal oscillator, wherein the local oscillation module generates the local oscillation signal according to the reference clock signal;
[0027] The interface module is used for communication between the intermediate frequency filter unit and the external register, and at least performs bandwidth switching control on the intermediate frequency filter unit by configuring the external register;
[0028] The power management module is used to provide power to each module.
[0029] The present invention also provides a navigation and positioning system, which includes: a dual-channel multi-mode radio frequency receiver as described in any one of the above.
[0030] As described above, the dual-channel multi-mode RF receiver and its navigation and positioning system of the present invention propose a new on-chip receiver architecture. The two receiving channels can simultaneously receive navigation satellite signals of different frequency bands, and can also achieve gain control under low noise and low power consumption. It can also convert single-ended signals into differential signals without using a balun, thereby achieving the goals of high integration, small size and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 Shown is a structural diagram of a dual-channel multi-mode radio frequency receiver according to an embodiment of the present invention.
[0032] Figure 2 Shown is a structural schematic diagram of a low-noise amplification module in an embodiment of the present invention.
[0033] Figure 3 Shown is another structural schematic diagram of a low-noise amplifier module in an embodiment of the present invention.
[0034] Figure 4 Shown is a schematic diagram of a specific implementation of a dual-channel multi-mode radio frequency receiver in an embodiment of the present invention.
[0035] Figure 5 Shown is a structural diagram of a navigation and positioning system in an embodiment of the present invention.
[0036] Figure 6 Shown is a schematic diagram of reflection coefficient simulation of the first receiving channel in an embodiment of the present invention.
[0037] Figure 7 Shown is a schematic diagram of reflection coefficient simulation of the second receiving channel in an embodiment of the present invention.
[0038] Figure 8 Shown is a schematic diagram of a simulation of the working process of the first receiving channel in an embodiment of the present invention.
[0039] Figure 9 Shown is a schematic diagram of a simulation of the working process of the second receiving channel in an embodiment of the present invention.
[0040] Component number description
[0041] 10 Navigation and positioning system
[0042] 100 Dual-Channel Multimode RF Receiver
[0043] 100a First receiving channel
[0044] 100b Second receiving channel
[0045] 110 low noise amplifier module
[0046] 111 Input stage amplifier structure
[0047] 112 Output stage amplifier structure
[0048] 113 Control Level Output Structure
[0049] 114 Intermediate stage amplifier structure
[0050] 120 IF processing module
[0051] 121 Mixing Unit
[0052] 1211 Local Oscillator Conversion Structure
[0053] 1212 NMOS tube passive switch structure
[0054] 122 IF filter unit
[0055] 1221 capacitor array
[0056] 1222 First resistor array
[0057] 1223 Second resistor array
[0058] 1224 Third Resistor Array
[0059] 130 Gain Amplifier Module
[0060] 131 Fourth resistor array
[0061] 132 Fifth resistor array
[0062] 140 conversion clock module
[0063] 150 analog-to-digital conversion module
[0064] 160 Automatic Gain Control Module
[0065] 170 Local Oscillator Module
[0066] 100c Benchmark Module
[0067] 100d interface module
[0068] 100e Power Management Module DETAILED DESCRIPTION
[0069] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0070] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.
[0071] like Figure 1As shown, this embodiment provides a dual-channel multi-mode RF receiver 100, which includes at least two receiving channels, which are respectively denoted as a first receiving channel 100a and a second receiving channel 100b; wherein the first receiving channel 100a and the second receiving channel 100b respectively include a low-noise amplifier module 110, an intermediate frequency processing module 120, a gain amplifier module 130, a conversion clock module 140, an analog-to-digital conversion module 150 and an automatic gain control module 160, and further include a local oscillation module 170.
[0072] The low-noise amplifier module 110 receives a single-ended RF voltage signal and performs voltage-to-current conversion and gain amplification to generate a single-ended RF current signal. Furthermore, the low-noise amplifier module 110 receives a second gain control instruction CG2 and performs gain control to achieve adjustable gain. Furthermore, as the input stage module of the dual-channel multi-mode RF receiver 100, the low-noise amplifier module 110 should also implement impedance matching. In practical applications, the low-noise amplifier module 110 can receive navigation satellite signals in multiple modes to improve system positioning accuracy; the navigation satellite signals are single-ended RF voltage signals.
[0073] In one embodiment, Figure 2 and Figure 3 As shown, the low noise amplification module 110 is implemented by cascading at least two stages of amplification structures. In this embodiment, a cascade structure is used for low noise and high gain amplification, and each stage can perform gain control, thereby achieving a wide range of gain adjustment.
[0074] In one example, Figure 2 As shown, the low-noise amplifier module 110 includes an input stage amplifier structure 111, an output stage amplifier structure 112 and a control stage output structure 113; wherein, the second gain control instruction CG2 includes an input stage gain control instruction CG21, an output stage gain control instruction CG22 and a control stage output instruction CG23. The specific settings are as follows: an input stage amplification structure 111, which receives a single-ended RF voltage signal and performs voltage-to-current conversion and input stage gain amplification operation to generate an input stage single-ended RF current signal, and receives an input stage gain control instruction CG21 and performs a gain control operation; an output stage amplification structure 112, which is connected to the input stage amplification structure 111, receives an input stage single-ended RF current signal and performs an output stage gain amplification operation to generate an output stage single-ended RF current signal, and receives an output stage gain control instruction CG22 and performs a gain control operation; a control stage output structure 113, which is respectively connected to the input stage amplification structure 111 and the output stage amplification structure 112, and selects and outputs the input stage single-ended RF current signal and the output stage single-ended RF current signal according to the control stage output instruction CG23 as the final output single-ended RF current signal.
[0075] In another example, Figure 3 As shown, the low-noise amplification module 110 includes an input-stage amplification structure 111, an intermediate-stage amplification structure 114, an output-stage amplification structure 112, and a control-stage output structure 113; wherein, the second gain control instruction CG2 includes an input-stage gain control instruction CG21, an intermediate-stage gain control instruction CG24, an output-stage gain control instruction CG22, and a control-stage output instruction CG23. The specific settings are as follows: the input-stage amplification structure 111 receives a single-ended RF voltage signal and performs voltage-to-current conversion and input-stage gain amplification operation to generate an input-stage single-ended RF current signal, and receives the input-stage gain control instruction CG21 and performs a gain control operation; the intermediate-stage amplification structure 114 is connected to the input-stage amplification structure 111, receives the input-stage single-ended RF current signal and performs an intermediate-stage gain amplification operation to generate an intermediate-stage single-ended RF current signal, and receives the intermediate-stage gain control instruction CG24 and performs a gain control operation; the output-stage amplification structure 112 is connected to the intermediate-stage The amplifier structure 114 is connected to receive the intermediate-stage single-ended RF current signal and perform an output-stage gain amplification operation on it to generate an output-stage single-ended RF current signal, and receives the output-stage gain control instruction CG22 and performs a gain control operation. The control-stage output structure 113 is respectively connected to the input-stage amplifier structure 111, the intermediate-stage amplifier structure 114, and the output-stage amplifier structure 112, and selects and outputs the input-stage single-ended RF current signal, the intermediate-stage single-ended RF current signal, and the output-stage single-ended RF current signal according to the control-stage output instruction CG23 to serve as the final output single-ended RF current signal. It should be noted that the number of intermediate-stage amplifier structures 114 can be one or more, and there are no excessive restrictions on this. When the number of intermediate-stage amplifier structures 114 is multiple, each intermediate-stage amplifier structure 114 is cascaded between the input-stage amplifier structure 111 and the output-stage amplifier structure 112. In actual applications, the number of intermediate-stage amplifier structures 114 is usually designed based on specific needs.
[0076] The intermediate frequency processing module 120 is connected to the low noise amplifier module 110, and generates a differential intermediate frequency current signal by frequency conversion of the single-ended RF current signal, and performs current-to-voltage conversion to generate a differential intermediate frequency voltage signal. By replacing the balun with the intermediate frequency processing module 120 to convert the single-ended signal into a differential signal, it is conducive to achieving a design with high integration and small size. Specifically, Figure 1 As shown, the intermediate frequency processing module 120 includes a frequency mixing unit 121 and an intermediate frequency filtering unit 122 .
[0077] The mixing unit 121 is connected to the low-noise amplifier module 110, and performs orthogonal frequency conversion on the single-ended RF current signal through the local oscillator signal to generate a differential intermediate frequency current signal; specifically, the mixing unit 121 performs orthogonal frequency conversion on the single-ended RF current signal through the differential local oscillator signal to generate two differential intermediate frequency current signals, including an I differential intermediate frequency current signal and a Q differential intermediate frequency current signal.
[0078] In one embodiment, the frequency mixing unit 121 is implemented by an NMOS passive switch structure to achieve high linearity; wherein the NMOS is an N-type metal oxide semiconductor field effect transistor. Figure 4 As shown, the mixing unit 121 includes a local oscillator conversion structure 1211 and an NMOS tube passive switch structure 1212, wherein: the local oscillator conversion structure 1211 receives the differential local oscillator signal and converts it into an I-channel differential local oscillator signal and a Q-channel differential local oscillator signal; in specific design, the local oscillator conversion structure 1211 can be implemented by an orthogonal signal generator or a passive filtering network. The NMOS transistor passive switch structure 1212 includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4. The gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 respectively receive I differential local oscillator signals, the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 respectively receive single-ended RF current signals, and the source of the first NMOS transistor N1 and the source of the second NMOS transistor N2 output I differential intermediate frequency current signals. The gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 respectively receive Q differential local oscillator signals, the drain of the third NMOS transistor N3 and the drain of the fourth NMOS transistor N4 respectively receive single-ended RF current signals, and the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 output Q differential intermediate frequency current signals.
[0079] The intermediate frequency filtering unit 122 is connected to the mixing unit 121, and generates a differential intermediate frequency voltage signal by performing current-to-voltage conversion on the differential intermediate frequency current signal and performing filtering and gain amplification operations. Specifically, the I-channel differential intermediate frequency current signal and the Q-channel differential intermediate frequency current signal are converted from current to voltage and filtered and gain amplified to generate an I-channel differential intermediate frequency voltage signal and a Q-channel differential intermediate frequency voltage signal respectively, and complete the bandwidth switching operation, specifically, complete the switching between the low-pass mode and the band-pass mode; further, the intermediate frequency filtering unit 122 also receives the third gain control instruction CG3 and performs a gain control operation.
[0080] In one embodiment, the intermediate frequency filter unit 122 is implemented by a capacitor array and a resistor array to meet the multi-mode and multi-frequency requirements of the system. In practical applications, the order of the intermediate frequency filter unit 122 needs to be designed according to the out-of-band suppression requirements. Of course, it is also necessary to consider the area and power consumption to make a compromise design. Usually, the intermediate frequency filter unit 122 adopts a five-order cascade structure. In one example, Figure 4 As shown, the intermediate frequency filtering unit 122 includes two capacitor arrays 1221, two first resistor arrays 1222, a second resistor array 1223 and a third resistor array 1224, wherein: the first capacitor array 1221 and the first first resistor array 1222 constitute a first array structure, the second capacitor array 1221 and the second first resistor array 1222 constitute a second array structure, and the second resistor array 1223 and the third resistor array 1224 are respectively located between the first array structure and the second array structure; the first array structure converts the received I-channel differential intermediate frequency current signal into a current-to-voltage and performs filtering and amplification. The first array structure and the second array structure further perform a gain control operation according to the received third gain control instruction CG3 to achieve adjustable gain; the second resistor array 1223 and the third resistor array 1224 are used to achieve switching between low-pass mode and band-pass mode, wherein the second resistor array 1223 and the third resistor array 1224 are usually designed with resistance values through external registers to achieve bandwidth switching.
[0081] The gain amplification module 130 is connected to the intermediate frequency processing module 120, and generates a differential analog signal by performing a gain amplification operation on the differential intermediate frequency voltage signal. Specifically, it generates an I-channel differential analog signal and a Q-channel differential analog signal by performing a gain amplification operation on the I-channel differential intermediate frequency voltage signal and the Q-channel differential intermediate frequency voltage signal respectively, and receives a first gain control instruction CG1 and performs a gain control operation.
[0082] In one embodiment, Figure 4 As shown, the gain amplification module 130 includes a fourth resistor array 131 and a fifth resistor array 132; the fourth resistor array 131 receives an I-channel differential intermediate frequency voltage signal and performs a gain amplification operation on it to generate an I-channel differential analog signal, and the fifth resistor array 132 receives a Q-channel differential intermediate frequency voltage signal and performs a gain amplification operation on it to generate a Q-channel differential analog signal, wherein the fourth resistor array 131 and the fifth resistor array 132 also perform a gain control operation according to the received first gain control instruction CG1 to achieve adjustable gain.
[0083] The conversion clock module 140 receives the local oscillator signal and divides it to generate the conversion clock signal. In practical applications, the local oscillator signal is typically provided by the local oscillator module 170, which has relatively good phase noise. Therefore, the conversion clock module 140 divides the local oscillator signal to generate the low-jitter clock required by the analog-to-digital conversion module 150, thereby avoiding the use of a phase-locked loop (PLL) module and reducing power consumption and area. In practical applications, the frequency division ratio of the conversion clock module 140 is typically designed based on the required system frequency, and no further restrictions are imposed on this.
[0084] The analog-to-digital conversion module 150 is connected to the gain amplification module 130 and the conversion clock module 140, respectively, and performs analog-to-digital conversion on the differential analog signal according to the conversion clock signal to generate a digital signal; specifically, the analog-to-digital conversion is performed on the I-channel differential analog signal and the Q-channel differential analog signal according to the conversion clock signal to generate an I-channel digital signal and a Q-channel digital signal.
[0085] In one embodiment, the analog-to-digital conversion module 150 is implemented by a successive approximation analog-to-digital converter (SAR-ADC), which can support multiple clock signals according to the bandwidth and intermediate frequency requirements of the dual-channel multi-mode RF receiver 100. In addition, it can also select an appropriate number of bits and sampling rate as needed to achieve a relatively large dynamic range, reduce the amplification factor of the previous module, and have certain anti-interference performance and low power consumption performance.
[0086] Automatic gain control module 160, connected to analog-to-digital conversion module 150, generates a first gain control instruction CG1 by determining the amplitude of the digital signal. Specifically, it generates the first gain control instruction CG1 by determining the amplitude of the I-channel digital signal and the Q-channel digital signal. Furthermore, while generating the first gain control instruction CG1, automatic gain control module 160 also generates at least one of a second gain control instruction CG2 and a third gain control instruction CG3. In practical applications, both the second gain control instruction CG2 and the third gain control instruction CG3 are typically generated. To prevent the influence of burst signals and other interference signals, automatic gain control module 160 first applies hysteresis to the received digital signals (including the I-channel digital signal and the Q-channel digital signal) within a hysteresis window before making the determination, thereby improving system stability.
[0087] In one embodiment, the automatic gain control module 160 performs amplitude judgment and mismatch judgment on the digital signal, and generates corresponding gain control instructions based on the two judgment results, for example, generating a first gain control instruction CG1, a second gain control instruction CG2, and a third gain control instruction CG3, so that the dual-channel multi-mode RF receiver 100 can ensure a fixed amplitude output regardless of the strength of the input signal. Specifically, the automatic gain control module 160 performs amplitude and mismatch determinations on the I-channel digital signal and the Q-channel digital signal, and generates corresponding gain control instructions based on the two determination results. The automatic gain control module 160 calculates the current amplitude based on the I-channel digital signal and the Q-channel digital signal and compares the current amplitude with a preset amplitude. Simultaneously, the automatic gain control module 160 calculates the current amplitude difference based on the I-channel digital signal and the Q-channel digital signal and compares the current amplitude difference with a preset amplitude difference. If the current amplitude is greater than the preset amplitude and the current amplitude difference is greater than the preset amplitude difference, the automatic gain control module 160 generates three gain control instructions to reduce the amplification factor. If the current amplitude is less than the preset amplitude and the current amplitude difference is less than the preset amplitude difference, the automatic gain control module 160 generates three gain control instructions to increase the amplification factor. In practical applications, repeated determination and adjustment until the system output meets the requirements can improve the system's anti-interference performance to a certain extent.
[0088] Local oscillator module 170 is used to provide a local oscillator signal. Specifically, local oscillator module 170 generates the local oscillator signal based on the reference clock signal. The local oscillator signal is a set of differential signals, which can be referred to as differential local oscillator signals. It should be noted that local oscillator module 170 can be implemented using a variety of existing circuit structures capable of generating local oscillator signals. In addition, the duty cycle of the local oscillator signal should be designed based on specific needs and is not subject to further restrictions.
[0089] Further, such as Figure 1 and Figure 4 As shown, the dual-channel multi-mode RF receiver 100 includes, in addition to a first receiving channel 100a and a second receiving channel 100b, at least one of a reference providing module 100c, an interface module 100d, and a power management module 100e. By integrating at least one of the reference providing module 100c, the interface module 100d, and the power management module 100e within the receiver, the integration level is improved. In this embodiment, the dual-channel multi-mode RF receiver 100 includes the reference providing module 100c, the interface module 100d, and the power management module 100. Among them:
[0090] The reference providing module 100c provides a reference clock signal by driving an external crystal oscillator, so that the local oscillation module 170 can generate a local oscillation signal based on the reference clock signal. The interface module 100d is used for communication between the intermediate frequency filter unit 122 and the external register, and by configuring the external register, at least the bandwidth switching control of the intermediate frequency filter unit 122 is performed to improve the flexibility of the system; of course, the gain of the intermediate frequency filter unit 122 can also be set by configuring the external register, usually the initial gain setting. In one embodiment, the interface module 100d is an SPI (serial peripheral interface) module. The power management module 100e is used to power each module, for example, to provide the voltage and current required for the operation of each module; in actual applications, the power management module 100e not only supports voltage adjustment, but also has functions such as low power consumption.
[0091] It should be noted that the dual-channel multi-mode RF receiver 100 of this embodiment can also be expanded in channels based on actual application requirements to include a larger number of receiving channels. The structures of the receiving channels are usually the same, and the receiving channels can receive signals of different modes mainly by adjusting relevant parameters.
[0092] like Figure 5 As shown, this embodiment also provides a navigation and positioning system 10, including a dual-channel multi-mode RF receiver 100. Of course, other structures may also be included, and this is not limited to any particular embodiment. The dual-channel multi-mode RF receiver 100 is implemented using the receiver structure described above, with each receiving channel capable of receiving navigation satellite signals in multiple modes and supporting multiple crystal oscillator frequencies. In practical applications, the dual-channel multi-mode RF receiver 100 of this embodiment operates in a frequency band ranging from 1.1 GHz to 1.7 GHz, supporting nearly all frequency bands of navigation and positioning systems.
[0093] Taking the GPS satellite navigation system and Beidou satellite navigation system as examples, their corresponding signals are GPS L1C / A and BDS B1I, as well as GPS L5 and BDS B2I; according to relevant regulations, the radio frequency of GPS L1C / A is 1575.42MHz and the signal bandwidth is 2.046MHz, the radio frequency of BDS B1I is 1561.098MHz and the signal bandwidth is 4.092MHz, the radio frequency of GPS L5 is 1176.45MHz and the signal bandwidth is 20.46MHz, and the radio frequency of BDS B2I is 1207.14MHz and the signal bandwidth is 20.46MHz.
[0094] The dual-channel, multi-mode RF receiver 100 of this embodiment was simulated and verified using simulation software based on a 22nm FDSOI (fully depleted silicon on insulator) process. By adjusting relevant parameters, the first receiving channel 100a was configured to operate in the GPS L1C / A and BDS B1I frequency bands, while the second receiving channel 100b was configured to operate in the GPS L5 and BDS B2I frequency bands. Furthermore, the first receiving channel 100a and the second receiving channel 100b operated simultaneously.
[0095] The dual-channel multi-mode RF receiver 100 uses an antenna to receive signals, so it is necessary to perform antenna port impedance matching so that the reflection coefficient S11 is less than -10dB within the operating frequency band. From the verification results, it can be seen that the reflection coefficient S11 of the first receiving channel 100a is less than -10dB within the corresponding frequency band. Figure 6 As shown, the reflection coefficient S11 of the second receiving channel 100b is less than -10dB within the corresponding frequency band. Figure 7 shown.
[0096] In order to better verify whether each receiving channel can reasonably adjust the amplification factor according to the strength of the received signal, ensure that the signal is output according to the preset amplitude, and achieve a larger dynamic range. The following design is made: the first receiving channel 100a operates in the BDS B1I frequency band, and the second receiving channel 100b operates in the BDS In the B2I frequency band, in the two receiving channels, the received signal amplitude is -100dBm, the receiver link gain is 100dB, and the output signal amplitude is fixed at 0dBm. The RF frequency of the first receiving channel 100a is 1561.098MHz, the frequency of the local oscillator signal provided by the local oscillator module 170 is 1571.328MHz, and the conversion clock module 140 divides the local oscillator signal by 16, converting the clock signal frequency to 98.208MHz. Therefore, the intermediate frequency is 10.23MHz, and the signal output amplitude is 0dBm. The RF frequency of the second receiving channel 100b is 1207.14MHz, the frequency of the local oscillator signal provided by the local oscillator module 170 is 1194.864MHz, and the conversion clock module 140 divides the local oscillator signal by 12, converting the clock signal frequency to 99.572MHz. Therefore, the intermediate frequency is 12.276MHz, and the signal output amplitude is 0dBm. After setting 2μs, the input signal amplitude becomes -80dBm. If the receiver chain cannot automatically adjust the amplification factor, the output signal amplitude will change significantly. Therefore, check whether the output signal amplitude is 0dBm, that is, whether there is a significant change in the output signal amplitude before and after 2μs. This can determine whether the receiver chain can automatically adjust the amplification factor.
[0097] The specific simulation verification results are as follows Figure 8 and Figure 9As shown, the verification result of the first receiving channel 100a running the BDS B1I frequency band is as follows Figure 8 As shown, the verification result of the second receiving channel 100b operating the BDS B2I frequency band is as follows Figure 9 As shown. Figure 8 , the upper part is the input single-ended RF voltage signal, the middle part is the intermediate frequency voltage signal output by the intermediate frequency filter unit 122, and the lower part is the output digital signal; Figure 8 As can be seen from the upper part of the graph, the input signal amplitude changes from -100dBm to -80dBm around 2μs, which is a significant change. Although the RF frequency is relatively high and the signal cannot be fully displayed, the amplitude change is relatively clear and discernible. Figure 8 It can be seen from the middle and lower parts that the output signal amplitude does not change significantly before and after 2μs, achieving the expected effect. The slight fluctuation is normal. Figure 9 , the upper part is the input single-ended RF voltage signal, the middle part is the intermediate frequency voltage signal output by the intermediate frequency filter unit 122, and the lower part is the output digital signal; Figure 9 As can be seen from the upper part of the graph, the input signal amplitude changes from -100dBm to -80dBm around 2μs, which is a significant change. Although the RF frequency is relatively high and the signal cannot be fully displayed, the amplitude change is relatively clear and discernible. Figure 9 It can be seen from the middle and lower parts that the output signal amplitude does not change significantly before and after 2μs, achieving the expected effect. The slight fluctuation is normal.
[0098] In summary, the dual-channel, multi-mode RF receiver and its navigation and positioning system of the present invention propose a novel on-chip receiver architecture. Its two receiving channels can simultaneously receive navigation satellite signals from different frequency bands, achieve gain control with low noise and low power consumption, and convert single-ended signals into differential signals without the use of a balun, thereby achieving high integration, compact size, and low power consumption. Therefore, the present invention effectively overcomes the shortcomings of the existing technology and has high industrial application value.
[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A dual-channel multi-mode radio frequency receiver, characterized in that: The dual-channel multi-mode radio frequency receiver includes at least two receiving channels, and the receiving channels include: a low-noise amplifier module, receiving a single-ended RF voltage signal and performing voltage-to-current conversion and gain amplification operations to generate a single-ended RF current signal; an intermediate frequency processing module connected to the low-noise amplification module, generating a differential intermediate frequency current signal by performing frequency conversion on the single-ended RF current signal, and performing current-to-voltage conversion to generate a differential intermediate frequency voltage signal; a gain amplification module connected to the intermediate frequency processing module, generating a differential analog signal by performing a gain amplification operation on the differential intermediate frequency voltage signal, and receiving a first gain control instruction and performing a gain control operation; A conversion clock module receives a local oscillator signal and performs frequency division processing on the local oscillator signal to generate a conversion clock signal; an analog-to-digital conversion module, connected to the gain amplification module and the conversion clock module respectively, and performing analog-to-digital conversion on the differential analog signal to generate a digital signal according to the conversion clock signal; An automatic gain control module is connected to the analog-to-digital conversion module and generates the first gain adjustment instruction by performing amplitude judgment on the digital signal.
2. The dual-channel multi-mode radio frequency receiver according to claim 1, wherein: The low noise amplification module further receives a second gain control instruction and performs a gain control operation, wherein the automatic gain control module generates the second gain control instruction while generating the first gain control instruction.
3. The dual-channel multi-mode radio frequency receiver according to claim 2, wherein: The low noise amplification module is realized by cascading at least two stages of amplification structures.
4. The dual-channel multi-mode radio frequency receiver according to claim 1, wherein: The intermediate frequency processing module includes: a frequency mixing unit connected to the low-noise amplification module, and performing orthogonal frequency conversion on the single-ended RF current signal through the local oscillator signal to generate the differential intermediate frequency current signal; The intermediate frequency filtering unit is connected to the mixing unit, and generates the differential intermediate frequency voltage signal by performing current-to-voltage conversion, filtering, and gain amplification operations on the differential intermediate frequency current signal, and completes a bandwidth switching operation.
5. The dual-channel multi-mode radio frequency receiver according to claim 4, characterized in that: The frequency mixing unit is implemented by an NMOS tube passive switch structure.
6. The dual-channel multi-mode radio frequency receiver according to claim 4, characterized in that: The intermediate frequency filtering unit further receives a third gain control instruction and performs a gain control operation, wherein the automatic gain control module generates the third gain control instruction while generating the first gain control instruction.
7. The dual-channel multi-mode radio frequency receiver according to claim 6, characterized in that: The intermediate frequency filtering unit is implemented by a capacitor array and a resistor array.
8. The dual-channel multi-mode radio frequency receiver according to claim 1, wherein: The analog-to-digital conversion module is implemented by a successive approximation analog-to-digital converter.
9. The dual-channel multi-mode radio frequency receiver according to claim 1, wherein: The automatic gain control module performs amplitude judgment and mismatch judgment on the digital signal and generates a corresponding gain control instruction according to the two judgment results.
10. The dual-channel multi-mode radio frequency receiver according to claim 1, wherein: The receiving channel further includes a local oscillation module for providing the local oscillation signal.
11. The dual-channel multi-mode radio frequency receiver according to any one of claims 1 to 10, characterized in that: The dual-channel multi-mode radio frequency receiver further includes at least one of a reference providing module, an interface module, and a power management module; The reference providing module provides a reference clock signal by driving an external crystal oscillator, wherein the local oscillation module generates the local oscillation signal according to the reference clock signal; The interface module is used for communication between the intermediate frequency filter unit and the external register, and at least performs bandwidth switching control on the intermediate frequency filter unit by configuring the external register; The power management module is used to provide power to each module.
12. A navigation and positioning system, characterized in that: The navigation and positioning system includes: the dual-channel multi-mode radio frequency receiver according to any one of claims 1 to 11.