On-chip integration and digital manufacturing method of photocurrent chip based on vertical micromirror

Abstract

The invention discloses an on-chip integration and digital manufacturing method of a photocurrent chip based on a vertical micromirror, which comprises the following steps of: manufacturing a passive optical device and an active optical device based on the vertical micromirror with the roughness of less than 1 nanometer on a drivable micro-electro-mechanical system structure; an optical chip with adjustable parameters and functions of calculation, sensing, communication and the like is formed in the horizontal direction; manufacturing an integrated circuit on at least one surface of the top, the bottom and the side wall of the silicon wafer by adopting a three-dimensional-two-dimensional patterning method to obtain a concave-convex three-dimensional integrated circuit, namely an electrical chip; a plurality of concave-convex three-dimensional integrated circuits are bonded through micro convex points and bonding rings to form micro-channels, and a plurality of micro-channels are connected through through holes to form a micro-fluidic unit; and carrying out on-chip integration on an optical chip, an electrical chip and a micro-fluidic unit to form an on-chip system which is used for realizing complex function processing capabilities such as calculation, sensing, communication, signal processing, data storage and the like and comprises the light current chip based on the vertical micromirror.

Description

Technical Field

[0001] The present invention belongs to the fields of integrated circuits, optoelectronics, advanced packaging and digital manufacturing technology, and in particular relates to an on-wafer integration and digital manufacturing method of a photocurrent chip based on vertical micromirrors. Background Art

[0002] As integrated circuit (IC) manufacturing processes enter the sub-10nm range, Moore's Law's progress gradually slowed and eventually became obsolete. How to integrate more transistors into a limited chip area to achieve more powerful functionality has become a hot topic in the integrated circuit (IC) research field. Advanced packaging technologies, such as 2.5D / 3D packaging and wafer-level packaging, have become effective routes to further enhance the performance of integrated circuit systems in the post-Moore era. Through advanced packaging, multi-chip devices can achieve high-density, high-bandwidth, low-latency, and low-power heterogeneous integrated systems at the wafer level. However, traditional advanced packaging technologies, whether 2.5D / 3D or wafer-level packaging, increase the total number of transistors by horizontally tiling or vertically stacking them without changing the chip's unit area efficiency. Generally speaking, whether field-effect transistors (FETs) fabricated at the 28nm node and above, or fin-type FETs (FinFETs) fabricated at node levels below 28nm, the transistors are fabricated on the surface of the wafer, effectively eliminating the internal wafer space. Even 3D stacking, exemplified by through-silicon via (TSV) technology, involves fabricating integrated circuit chips on a silicon plane and then stacking them. This is essentially a reconstruction of planar integrated circuit chips, rather than a direct 3D manufacturing approach. Fabricating 3D integrated circuit chips fully utilizes the internal space of the silicon wafer to integrate more transistors within the same footprint. However, the manufacturing of such integrated circuit chips is limited by various manufacturing techniques, including the creation of 3D deep trench structures with smooth sidewalls, 3D sidewall patterning, 3D doping, and 3D thin film deposition. Summary of the Invention

[0003] In view of the problems existing in the prior art, the purpose of the embodiments of the present application is to provide an on-wafer integration and digital manufacturing method of a photocurrent chip based on vertical micromirrors.

[0004] According to a first aspect of an embodiment of the present application, a method for on-wafer integration of a photocurrent chip based on a vertical micromirror is provided, comprising: On a drivable micro-electromechanical system structure, based on deep etching, sidewall smoothing and 3D-2D patterning methods, passive and active optical devices based on vertical micromirrors are manufactured to form optical chips. On at least one of the top, bottom, and sidewall surfaces of a silicon wafer, a 3D-2D patterning method is used to manufacture an integrated circuit to obtain a concave-convex 3D integrated circuit, i.e., an electrical chip; Bonding a plurality of concave-convex three-dimensional integrated circuits through micro-bumps and bonding rings to form microchannels, and connecting the plurality of microchannels through through-holes to form a microfluidic unit; The optical chip, the electrical chip and the microfluidic unit are integrated on-wafer to form an on-wafer system including a photocurrent chip based on a vertical micromirror.

[0005] Furthermore, the manufacturing process of the passive optical device includes: Deep etching and sidewall smoothing step: deep etching a vertical structure on the silicon wafer and smoothing the sidewalls of the vertical structure to form a vertical micromirror; 3D-2D patterning step: using two-photon printing to perform 3D patterning on the sidewalls of the vertical micromirror, and using spraying or layered coating of multiple layers of photoresist and exposure and development to achieve 2D patterning of areas outside the sidewalls, thereby achieving patterning of the entire wafer; Thin film growth step: growing optical thin films and electrical thin films on the sidewalls of the wafer and the vertical micromirrors, wherein the optical thin films include anti-reflection films, anti-reflection films, filter films, polarizing films, and spectroscopic films, and the electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0006] Furthermore, the manufacturing process of active optical devices includes: Deep etching and sidewall smoothing step: deep etching a vertical structure on the silicon wafer and smoothing the sidewalls of the vertical structure to form a vertical micromirror; 3D-2D patterning step: using two-photon printing to perform 3D patterning on the sidewalls of the vertical micromirror, and using spraying or layered coating of multiple layers of photoresist and exposure and development to achieve 2D patterning of areas outside the sidewalls, thereby achieving patterning of the entire wafer; Doping and activation step: performing ion implantation and heat treatment on the sidewalls of the vertical micromirror to achieve sidewall doping activation, ohmic contact formation, and metal electrode alloying; Thin film growth step: growing optical thin films and electrical thin films on the sidewalls of the wafer and the vertical micromirrors, wherein the optical thin films include anti-reflection films, anti-reflection films, filter films, polarizing films, and spectroscopic films, and the electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0007] Furthermore, in the deep etching and sidewall smoothing steps, the sidewall smoothing methods include but are not limited to high temperature annealing, low flow dry etching, low concentration wet chemical etching, reducing the alternating cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection of the front side.

[0008] Furthermore, in the three-dimensional-two-dimensional patterning step, exposure and development methods include but are not limited to contact exposure, deep ultraviolet lithography, and extreme ultraviolet lithography.

[0009] Furthermore, in the doping and activation steps, sidewall doping methods include, but are not limited to, tilted angle rotation ion implantation and plasma doping.

[0010] Furthermore, the bonding method for forming the microchannel is selected from at least one of transient liquid phase bonding, eutectic bonding, thermal compression bonding, hybrid bonding, and anodic bonding.

[0011] Furthermore, concave-convex three-dimensional integrated circuits are made on the upper and lower surfaces of the silicon wafer through a double-sided process, and the circuits on the upper and lower surfaces are connected through silicon vias; three double-sided concave-convex three-dimensional integrated circuits are bonded through micro-bumps and bonding rings to form microchannels, and the coolant flows horizontally through the microchannels formed by bonding and flows vertically between layers through the silicon vias.

[0012] Furthermore, several of the on-chip systems are installed in a cabinet, and a power supply for the entire cabinet and a coolant circulation system integrated with a circulation pump and a heat exchanger are installed at the bottom of the cabinet; the cabinets are connected by electrical cables or optical cables.

[0013] According to a second aspect of an embodiment of the present application, a digital manufacturing method for an on-wafer system including a photocurrent chip based on vertical micromirrors is provided, comprising: Digital twin modeling steps: By building a multi-physics field coupling model, a data-driven model library, and a real-time simulation engine, the on-chip system is digitally modeled at the system level; Virtual design and digital simulation steps: Based on the established digital model, artificial neural networks and large models are used to automatically layout the on-chip network interconnection topology, forming a simulator for on-chip system topology algorithms and performance simulation. This generates the on-chip system layout, dynamically adjusts the positions of power-consuming units, and configures microchannel cooling. Digital manufacturing process control step: controlling the micro-nano processing equipment to be manufactured using the method described in the first aspect, collecting error data in the micro-nano processing process in real time during the manufacturing process, predicting the optimal process parameters and feeding them back to the equipment control terminal; Automated test feedback steps: Several measurement steps are set up in the lithography, etching, thin film, and thermal treatment processes. After the node process and its measurement steps are completed, the measurement data is automatically extracted. The simulation results are compared with the measurement data to infer the overall processing quality of the wafer-level system. The results are fed back to the simulator to optimize process conditions. Dynamic correction mechanism steps: According to the measurement data, the simulator is dynamically corrected, the weight of the influence of the process parameters on the final performance is analyzed by quantifying the process parameters, and the highly sensitive parameters are corrected first. The adaptive simulation model is established and corrected by combining physical equations, artificial intelligence networks and large models, and measured parameters to improve the generalization ability of process window prediction, and further synchronously update the model in the simulator based on the measured data.

[0014] The technical solutions provided by the embodiments of the present application may have the following beneficial effects: As can be seen from the above embodiments, the present application utilizes key technologies such as sidewall smoothing, three-dimensional to two-dimensional patterning, sidewall doping, and sidewall thin film growth in vertically deep-etched silicon structures. By smoothing the sidewalls of the deep-etched silicon using high-temperature, dry, or wet methods, a vertical micromirror structure with a roughness of less than 1 nanometer can be formed. Furthermore, a three-dimensional to two-dimensional patterning method is used to load various passive optical devices and active optical devices onto a micro-electromechanical structure, forming an on-chip optical system with adjustable parameters and functions such as computing, sensing, and communication in the horizontal direction. Furthermore, transistor elements such as PN junctions, CMOS, FinFETs (Fin Field-Effect Transistors), and GAAFETs (Gate-All-Around Field-Effect Transistors) can be manufactured on the top, bottom, and sidewalls of the silicon wafer to realize a concave-convex three-dimensional integrated circuit, thereby achieving sidewall integration of major optoelectronic components. Compared to traditional methods of fabricating micromirrors, silicon photonic devices, or CMOS (Complementary Metal Oxide Semiconductor) integrated circuits on the surface of silicon wafers, this method not only fully utilizes the three-dimensional space of the silicon wafer to increase integration density, but also, for the optical computing component, the vertical micromirrors can form a fully functional on-chip optical system in the horizontal direction. Light propagation loss in air is extremely low, with loss occurring only at the component interfaces. This loss can be significantly reduced by growing optically transparent films, making it suitable for large-scale integration. Furthermore, integrated microfluidics can effectively dissipate heat from the high-density integrated system. Based on this, to address the large scale, complex physical field functions, and lengthy manufacturing processes of wafer-level integrated systems, a digital fabrication method for optoelectronic on-wafer integrated systems based on on-wafer system model building technology has been proposed, comprehensively improving the design and manufacturing efficiency of wafer-level systems.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] Figure 1 Schematic diagram of a method for manufacturing a PN junction diode based on a vertical micromirror according to the present invention, wherein (a-1)-(g-1) are front views of the wafer in each process, and (a-2)-(g-2) are top views of the wafer in each process; Figure 2 Schematic diagram of a method for manufacturing a PMOS field-effect transistor based on vertical deep sidewall etching according to the present invention, wherein (a-1)-(h-1) are front views of the wafer in each process, (a-2)-(h-2) are top views of the wafer in each process, and (a-3)-(h-3) are cross-sectional views of the wafer in each process; Figure 3 Schematic cross-sectional views of the on-wafer integrated structure of the three-dimensional integrated circuit chip and the microfluidic unit of the present invention are shown, wherein (a)-(c) are schematic views of the wafer in each process; Figure 4 Schematic diagram of a method for manufacturing a PIN photodetector based on vertically deep-etched sidewalls according to the present invention, wherein (a-1)-(f-1) are front views of the wafer in each process, and (a-2)-(f-2) are cross-sectional views of the wafer in each process; Figure 5 Shown is a schematic diagram of a three-dimensional optoelectronic on-wafer integration system based on vertical micromirrors, where (a) is a front view and (b) is a top view.

[0018] Figure 6 The figure shows a schematic diagram of the high-density integration of light, electricity, and flow to form a large-scale computing cluster.

[0019] Figure 7 Shown is a logic diagram of wafer-level chip model building technology and digital manufacturing methods.

[0020] Figure numerals: 1, vertical structure; 2, photosensitive resin; 3, N-type semiconductor region; 4, P-type semiconductor region; 5, PN junction; 6, P+-type semiconductor region; 7, P+-type semiconductor region; 8, ohmic contact electrode; 9, silicon dioxide layer; 10, polysilicon layer; 11, gate pattern photosensitive resin; 12, gate polysilicon; 13, first photoresist; 14, gate oxide layer; 15, source and drain; 16, metal silicide; 17, dielectric layer; 18, interconnect layer; 19, top integrated circuit; 20, bottom integrated circuit; 21, sidewall integrated circuit; 22, first concave-convex three-dimensional integrated circuit; 23, second concave-convex three-dimensional integrated circuit; 24, bonding ring; 25, microchannel; 26, through-silicon via; 28 , first double-sided concave-convex three-dimensional integrated circuit; 29, second double-sided concave-convex three-dimensional integrated circuit; 30, third double-sided concave-convex three-dimensional integrated circuit; 31, gate pattern photosensitive resin; 32, second photoresist; 33, N+ layer; 34, silicon dioxide layer; 35, intrinsic layer; 36, P+ layer; 37, N+ layer electrode; 38, P+ layer electrode; 39, laser; 40, spherical lens; 41, optical computing unit; 42, photodetector; 43, three-dimensional integrated circuit unit; 44, three-dimensional optoelectronic on-chip integrated system; 45, integrated circuit chip; 46, circuit board; 47, power supply board; 48, cooling fin; 49, cooling fan; 50, cabinet; 51, power supply; 52, cooling liquid circulation system; 53, optical cable; DETAILED DESCRIPTION

[0021] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0022] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0024] The present application provides an on-wafer integration method for a photocurrent chip based on a vertical micromirror, comprising: (1) Based on the structure of a drivable micro-electromechanical system, based on deep etching, sidewall smoothing and 3D-2D patterning methods, passive optical devices and active optical devices based on vertical micromirrors are manufactured to form optical chips; The passive optical devices include: reflectors, cylindrical mirrors, beam splitters, prisms, gratings, interferometers, etc. manufactured based on vertical deep etching and sidewall smoothing technology; spherical lenses, apertures, polarizers, wave plates, super lenses, optical waveguides, etc. manufactured based on sidewall additive and subtractive technology using sidewall two-photon printing and focused ion beam grayscale milling; optical thin films manufactured based on physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The active optical devices include: lasers, amplifiers, modulators, detectors, etc. manufactured based on three-dimensional-two-dimensional patterning technology and sidewall doping and epitaxial technology; Passive optical devices and active optical devices based on vertical micromirrors are manufactured on micro-electromechanical system structures such as comb teeth, cantilever beams, and springs that can be driven by electrostatics, piezoelectricity, thermal forces, and magnetism, so as to achieve on-chip adjustment of optical parameters such as focal length, optical path, and phase; passive optical devices and active optical devices based on vertical micromirrors are loaded on the micro-electromechanical system structure to form an on-chip optical system with adjustable parameters in the horizontal direction and functions such as computing, sensing, and communication.

[0025] In a specific implementation, the manufacturing process of the passive optical device may include: Deep etching and sidewall smoothing step: deep etching vertical structures on the silicon wafer, smoothing the sidewalls of the vertical structures to form vertical micromirrors, wherein sidewall smoothing methods include but are not limited to high temperature annealing, low flow dry etching, low concentration wet chemical etching, reducing the alternating cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection of the front side; A three-dimensional-two-dimensional patterning step: performing three-dimensional patterning on the sidewalls of the vertical micromirror using two-photon printing, and performing two-dimensional patterning on the area outside the sidewalls using spraying or layered coating of multiple layers of photoresist and exposure and development to achieve patterning of the entire wafer, wherein the exposure and development methods include but are not limited to contact exposure, deep ultraviolet lithography, and extreme ultraviolet lithography; Thin film growth step: growing optical thin films and electrical thin films on the sidewalls of the wafer and the vertical micromirrors, wherein the optical thin films include anti-reflection films, anti-reflection films, filter films, polarizing films, and spectroscopic films, and the electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0026] For active optical devices, the manufacturing process may include: Deep etching and sidewall smoothing step: deep etching a vertical structure on the silicon wafer and smoothing the sidewalls of the vertical structure to form a vertical micromirror; 3D-2D patterning step: using two-photon printing to perform 3D patterning on the sidewalls of the vertical micromirrors, and using spraying or layered coating of multiple layers of photoresist followed by exposure and development to perform 2D patterning on areas outside the sidewalls, thereby achieving patterning of the entire wafer; Doping and activation step: performing ion implantation and heat treatment on the sidewalls of the vertical micromirror to achieve sidewall doping activation, ohmic contact formation, and metal electrode alloying, wherein the sidewall doping method includes but is not limited to tilted angle rotation ion implantation and plasma doping; Thin film growth step: growing optical thin films and electrical thin films on the sidewalls of the wafer and the vertical micromirrors, wherein the optical thin films include anti-reflection films, anti-reflection films, filter films, polarizing films, and spectroscopic films, and the electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

[0027] It should be noted that, for passive optical devices and active optical devices, the manufacturing process is not just a matter of executing each step sequentially once, but rather some steps are selected to be executed multiple times according to actual manufacturing requirements.

[0028] (2) Manufacturing an integrated circuit on at least one of the top, bottom, and sidewall surfaces of a silicon wafer using a three-dimensional-two-dimensional patterning method to obtain a concave-convex three-dimensional integrated circuit, i.e., an electrical chip; Specifically, the combined use of a 3D-2D patterning method can pattern the top, bottom, and sidewall surfaces of a silicon wafer, thereby enabling the fabrication of PN junction, CMOS, FinFET, GAAFET, and other transistor components on the top, bottom, and sidewalls of the silicon wafer, thereby realizing concave-convex 3D integrated circuits. It should be noted that the 3D-2D patterning method used here is equivalent to the aforementioned 3D-2D patterning steps and will not be further described here.

[0029] In a specific implementation, a concave-convex three-dimensional integrated circuit can be made on one surface of a silicon wafer, or on both the upper and lower surfaces of the silicon wafer through a double-sided process, with the circuits on the upper and lower surfaces connected through silicon vias.

[0030] (3) Bonding several concave-convex three-dimensional integrated circuits through micro-bumps and bonding rings to form microchannels, and connecting the microchannels of multiple concave-convex three-dimensional integrated circuits through through holes to form a microfluidic unit; Multiple concave-convex three-dimensional integrated circuits are bonded together through micro-bumps and bonding rings to form microchannels. The microchannels of the multiple concave-convex three-dimensional integrated circuits are connected through through holes to form a complete microfluidic unit. Cooling liquid passes through the microfluidic unit to dissipate heat inside the optoelectronic integrated system. The method of bonding to form the microchannel is selected from at least one of transient liquid phase bonding, eutectic bonding, hot pressing bonding, hybrid bonding, and anodic bonding.

[0031] For double-sided concave-convex three-dimensional integrated circuits, three double-sided concave-convex three-dimensional integrated circuits can be bonded through micro-bumps and bonding rings to form microchannels. The coolant flows horizontally through the microchannels formed by bonding and flows vertically between layers through silicon vias.

[0032] (4) performing on-chip integration of the optical chip and the electrical chip, i.e., the microfluidic unit, to form an on-chip system; Optical units, electrical chips, and microfluidic units are densely integrated on the wafer to realize an on-chip system capable of processing complex functions such as computing, sensing, communication, signal processing, and data storage. Multiple on-chip systems are connected by cables or optical cables to form a large-scale computing cluster.

[0033] In a specific implementation, several of the on-chip systems are installed in a cabinet, and a power supply for the entire cabinet and a coolant circulation system integrated with a circulation pump and a heat exchanger are installed at the bottom of the cabinet; the cabinets are connected by electrical cables or optical cables.

[0034] Vertical micromirrors are fabricated by deep etching a single-crystal silicon wafer into a three-dimensional structure perpendicular to the wafer. Smoothing the vertical sidewalls reduces the roughness of the vertical sidewalls to 1 nanometer or less, meeting the requirements for optical-grade interfaces. Compared to conventional horizontal micromirrors in Micro-Opto-Electro-Mechanical Systems (MOEMS), vertical micromirrors eliminate the need for additional alignment and microassembly steps, enabling the direct fabrication of vertical optical components on the silicon wafer and forming a complete on-chip optical path in the horizontal direction. Furthermore, the vertical micromirror structure, with a roughness of less than 1 nanometer, also provides a good electrical interface. Through the key technologies proposed in this invention, such as the 3D-2D patterning step and sidewall doping step, 3D integrated circuits can be fabricated. Furthermore, the deep vertical trench structures also serve as excellent heat dissipation microchannels embedded within the silicon wafer, enabling heat dissipation in high-density integrated optoelectronic systems.

[0035] The following examples further illustrate the aforementioned on-wafer integration method. Examples 1 and 2, respectively, illustrate the fabrication methods for a PN junction diode and a PMOS field-effect transistor, the most basic units of a vertically structured three-dimensional integrated circuit. Example 3 illustrates the on-wafer integration method of the present invention's three-dimensional integrated circuit chip and microfluidic unit. Example 4 uses a PIN photodetector as an example to illustrate the fabrication method of an on-chip optical element based on a vertical micromirror. The PIN photodetector is both an important active optical element and the link between photoelectric conversion and integration. Furthermore, Example 5 provides a schematic diagram of a three-dimensional optoelectronic on-wafer integration system based on a vertical micromirror. Examples 6 and 7 illustrate the structure, design methods, and digital manufacturing methods for the high-density integration of light, electricity, and fluidics to form a large-scale computing cluster. This complete innovative methodological system has been formed, encompassing the underlying component structure, system integration, large-scale clusters, design methods, and digital manufacturing.

[0036] Example 1

[0037] The PN junction is a semiconductor device structure formed by the combination of a P-type semiconductor and an N-type semiconductor. It is not only the most basic unit in integrated circuits, but also the fundamental structural unit of many active optical devices. This embodiment uses the PN junction, the most basic unit in integrated circuits, as an example to provide an integrated circuit chip manufacturing method based on vertical micromirrors. However, the application scenarios of the present invention are not limited to this example and can also be applied to the manufacturing of integrated circuit devices with other structures on vertical sidewalls.

[0038] As shown in FIG1 , the manufacturing method of the PN junction based on the vertical micromirror includes the following steps: S11: Deeply etch the vertical structure 1 on the single crystal silicon wafer and smooth the sidewalls to produce a good optical plane and electrical vertical plane, namely a vertical micromirror.

[0039] In single crystal silicon wafers ( Figure 1 The upper surfaces of (a-1) and (a-2) are etched through a deep etching process to form a vertical structure 1 with a depth greater than 100 microns, a verticality better than 90°±0.3°, and an initial sidewall roughness better than 50 nanometers.

[0040] The sidewalls of the vertical structures are smoothed using methods including, but not limited to, high-temperature annealing, low-flow dry etching, low-concentration wet chemical etching, reducing the alternating etching and protection process cycles, gas cluster ion beam etching, focused ion beam milling, ion beam etching, and chemical mechanical polishing of the sidewalls with hard mask metal protection on the front side. In one embodiment of the present invention, the deep-etched through-silicon vias are preferably etched using a solution comprising less than 5 wt.% of potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH), 10 wt.% to 30 wt.% of isopropyl alcohol, and deionized water. This can produce vertical structures 1 with sidewall roughness less than 1 nanometer, serving as optically and electrically flat vertical surfaces, i.e., vertical micromirrors. In another embodiment of the present invention, the vertical structures are preferably post-etched using one or more low-flow steps of sulfur hexafluoride (SF6), argon plasma, oxygen plasma, or xenon difluoride (XeF2), with the gas flow rate typically being less than 30 sccm.

[0041] S12: Depositing a thin silicon dioxide layer on the vertical micromirror as a protective layer for ion implantation; using a two-photon printer (two-photon grayscale lithography) to photolithographically form an N-type semiconductor region 3 on the surface of the vertical micromirror using a photosensitive resin 2 as a mask; and performing N-type ion implantation into the N-type semiconductor region 3 ( Figure 1 (b-1), (b-2)).

[0042] S13: Using a two-photon printer, photolithography is performed on the surface of the vertical micromirror using the photosensitive resin 2 as a mask to form a P-type semiconductor region 4; P-type ion implantation is performed on the P-type semiconductor region 4; the photosensitive resin 2 is removed, and annealing is performed to activate the implantation to form a PN junction 5. Sidewall doping methods include, but are not limited to, tilted angle rotational ion implantation, plasma doping (PLAD), etc. ( Figure 1 (c-1), (c-2)).

[0043] S14: First, a two-photon printer is used to photoetch a P+ type semiconductor region 6 on the surface of the vertical micromirror using the photosensitive resin 2 as a mask; then, P+ type ion implantation is performed on the P+ type semiconductor region 6 ( Figure 1 (d-1), (d-2)).

[0044] S15: First, a two-photon printer is used to photoetch an N+ type semiconductor region 7 on the surface of the vertical micromirror using a photosensitive resin 2 as a mask; then, N+ type ion implantation is performed on the N+ type semiconductor region 7; finally, the photosensitive resin 2 is removed, and annealing and implantation activation are performed to form heavily doped regions N+ and P+ as ohmic contacts ( Figure 1 (e-1), (e-2)).

[0045] S16: Use a two-photon printer to perform photolithography on the surface of the vertical micromirror using the photosensitive resin 2 as a mask, and simultaneously expose the P+ type semiconductor region 6 and the N+ type semiconductor region 7 ( Figure 1 (f-1), (f-2)).

[0046] S17: First, a metal electrode layer is deposited on the surface of the vertical micromirror; then, excess metal is removed by a lift-off process, leaving only the metal electrode layer of the P+ type semiconductor region 6 and the N+ type semiconductor region 7; finally, the metal electrode layer is alloyed to form an ohmic contact electrode 8 ( Figure 1 (g-1), (g-2)).

[0047] Example 2

[0048] Field-effect transistors (MOSFETs) are the fundamental building blocks of modern integrated circuit chips. MOSFETs are also known as metal oxide semiconductor field effect transistors (MOS). MOS transistors can be categorized as NMOS and PMOS. NMOS refers to an N-channel transistor, with N+ source and drain regions formed on a P-type substrate. It conducts when a positive voltage is applied to the gate. PMOS refers to a P-channel transistor, with P+ source and drain regions formed on an N-type substrate. It conducts when a negative voltage is applied to the gate. NMOS and PMOS transistors can form complementary metal oxide semiconductors (CMOS), the fundamental building blocks of digital integrated circuits. This example uses PMOS as an example to illustrate how to fabricate integrated circuit chips with vertical sidewalls. The present invention provides a method for manufacturing an integrated circuit chip based on a vertical micromirror. However, the application scenario of the present invention is not limited to the PMOS example cited. It can also be applied to the manufacturing scenarios of integrated circuit devices with other structures such as NMOS, Fin Field-Effect Transistor (FinFET), Gate-all-around Field-effect Transistor (GAAFET) on vertical sidewalls.

[0049] like Figure 2 As shown, the manufacturing method of the PMOS based on the vertical micromirror includes the following steps: S21: Deeply etch the vertical structure 1 on the single crystal silicon wafer of the N-type substrate and smooth the sidewalls to produce a good optical plane and an electrical vertical plane, namely a vertical micromirror.

[0050] First, on a single crystal silicon wafer with an N-type substrate ( Figure 2A deep etching process was used to create vertical structures on the top surfaces of (a-1) and (a-2) in Figures 1 and 2, with a depth greater than 100 microns, a perpendicularity better than 90° ± 0.3°, and an initial sidewall roughness better than 50 nanometers. The sidewalls of these vertical structures were then smoothed to obtain a vertical structure 1 with a sidewall roughness less than 1 nm, which served as a good optical and electrical vertical surface.

[0051] S22: First, a silicon dioxide layer 9 is deposited on the vertical micromirror ( Figure 2 (b-1), (b-2)), methods include but are not limited to chemical vapor deposition (CVD), dry oxygen oxidation, wet oxygen oxidation, atomic layer deposition (ALD), etc.; then, the polysilicon layer 10 is preferably deposited using a low-pressure chemical vapor deposition (LPCVD) method.

[0052] S23: Use a two-photon printer (two-photon grayscale lithography) to photolithograph the shape of the gate on the surface of the silicon dioxide layer 9 and the polysilicon layer 10 of the vertical micromirror, that is, the gate pattern is protected by the photosensitive resin 11 printed by two-photon. Figure 2 (c-1), (c-2)).

[0053] S24: First, using the gate pattern photosensitive resin 11 as a mask, remove the polysilicon layer outside the gate pattern to form a gate polysilicon 12; then, using a spraying method, apply a first photoresist 13 on the wafer where the vertical micromirror is located, so that only the process surface of the vertical micromirror is exposed, and the other surfaces are protected by the first photoresist 13 ( Figure 2 (d-1), (d-2)).

[0054] It should be noted that the photosensitive resin used in two-photon printing is typically a negative resist, meaning the exposed pattern remains after development. This is used for patterning the sidewalls of vertical structures hundreds of microns deep, a form of three-dimensional patterning. The photoresist used in spray-coating can be either positive or negative, and is used for patterning beyond vertical structures. Because spray-coating is typically thicker, this method is suitable for applications where linewidth precision is less critical. Alternatively, a layered multilayer photoresist approach can be used to pattern beyond vertical structures: a low-viscosity negative photoresist is applied to cover the step areas to form a protective layer (approximately 1-2 microns thick), followed by a positive photoresist for submicron patterning of the bulk areas. Exposure methods include, but are not limited to, contact exposure, deep ultraviolet (DUV), and extreme ultraviolet (EUV) lithography. This method is suitable for applications requiring higher linewidth precision. However, both spray-coating and multilayer photoresist methods are two-dimensional patterning methods. In this way, two-photon printing realizes a three-dimensional patterning method for patterning the sidewall, and spraying or layered coating of multiple layers of photoresist realizes a two-dimensional patterning method for patterning structures other than the sidewall. The two cooperate with each other to realize the patterning of the entire wafer.

[0055] S25: First, preferably, buffered hydrofluoric acid (BHF) is used as an etching solution to remove the silicon dioxide layer 9 outside the gate pattern; then, the first photoresist 13 and the gate pattern photosensitive resin 11 are removed to obtain the gate oxide layer 14 ( Figure 2 (e-1), (e-2)).

[0056] S26: First, the source and drain regions are patterned using the three-dimensional and two-dimensional patterning methods; then, P+ doping is performed to form source and drain regions 15 ( Figure 2 (f-1) and (f-2) in the figure). Sidewall doping methods include, but are not limited to, tilted-angle rotary ion implantation and plasma doping (PLAD). Finally, after stripping, annealing is performed to activate the implant. S27: First, the ohmic contact region is patterned using the three-dimensional and two-dimensional patterning methods; then, titanium, nickel, cobalt, platinum and other metals are physically vapor deposited (PVD); finally, annealing is performed to form a metal silicide ohmic contact 16 ( Figure 2 (g-1), (g-2)).

[0057] S28: First, deposit a silicon dioxide dielectric layer 17; then, pattern the dielectric layer 17 using the three-dimensional-two-dimensional patterning method, and etch the dielectric layer 17 to expose the contact holes; then, PVD seed layer, electroplating copper to fill the contact holes; finally, preferably using ion beam etching (IBE) to etch the electroplated layer to form an interconnection line layer 18 and alloy ( Figure 2 (h-1), (h-2)).

[0058] Example 3

[0059] By using the combined three-dimensional and two-dimensional patterning method described in Example 2, the top, bottom, and sidewall surfaces of the silicon wafer can be patterned, thereby manufacturing integrated circuits 19 on the top of the silicon wafer, manufacturing integrated circuits 20 on the bottom, and manufacturing integrated circuits 21 on the sidewalls, forming concave-convex three-dimensional integrated circuits ( Figure 3 Compared to the traditional method of manufacturing integrated circuits only on the surface of the wafer, the method described in the present invention greatly increases the process area, thereby integrating more MOS tubes and achieving stronger performance.

[0060] Furthermore, the two concave-convex three-dimensional integrated circuits 22 and 23 can be bonded together through micro-bumps and bonding rings 24 to form a micro-channel 25, so that the coolant can dissipate heat inside the system composed of 22 and 23 ( Figure 3 (b) in the figure).

[0061] Furthermore, a double-sided process can be used to fabricate concave-convex three-dimensional integrated circuits on both the upper and lower surfaces of a silicon wafer, with the circuits on the upper and lower surfaces connected via through-silicon vias 26 (TSVs). Three double-sided concave-convex three-dimensional integrated circuits 28, 29, and 30 are bonded together via microbumps and bonding rings 24 to form microchannels 25. Cooling fluid can flow vertically between layers through vertical microchannel holes 27 fabricated (deeply etched) on the wafer, and horizontally through the microchannels 25 formed by bonding, thereby dissipating heat for the entire system ( Figure 3 (c) in the figure).

[0062] Example 4

[0063] Example 1 describes a method for fabricating a PN junction diode on the sidewalls of a vertically deeply etched silicon structure. PN junction diodes are not only the most fundamental unit in integrated circuits but also exhibit a photoelectric effect, making them suitable for use as photodetectors. To achieve photoelectric conversion and integration in the near-infrared band, Example 4 describes a method for fabricating a PIN detector on the sidewalls of a vertically deeply etched silicon structure. However, the application of this invention is not limited to this example and can also be applied to the fabrication of optical devices with other structures on vertical sidewalls.

[0064] S41: Deeply etching the vertical structure 1 on the single crystal silicon wafer and smoothing the sidewalls to produce a good optical plane and an electrical vertical plane, namely a vertical micromirror.

[0065] First, on a single crystal silicon wafer ( Figure 4 A deep etching process was used to create vertical structures on the top surfaces of (a-1) and (a-2) in Figures 1 and 2, with a depth greater than 100 microns, a perpendicularity better than 90° ± 0.3°, and an initial sidewall roughness better than 50 nanometers. These vertical structures were then smoothed to produce vertical micromirrors with a sidewall roughness less than 1 nm, serving as excellent optical and electrical vertical surfaces.

[0066] S42: Use a two-photon printer (two-photon grayscale lithography) to photolithographically pattern the N+ region on the sidewall surface of the vertical micromirror. That is, the gate pattern is protected by the photosensitive resin 31 printed by two-photon printing. Then, use the spray method to apply the second photoresist 32 on the wafer where the vertical micromirror is located, and expose and develop the vertical structure. Finally, N+ doping is performed to form an N+ layer 33, and the second photoresist 32 is removed ( Figure 4 (b-1), (b-2)).

[0067] S43: First, preferably, a PECVD method is used to deposit a silicon dioxide layer 34. Then, a three-dimensional-two-dimensional patterning method is used in combination to pattern the P+ region. Finally, hydrofluoric acid is used to remove the silicon dioxide layer on the surface of the P+ region, and then the photoresist is removed ( Figure 4 (c-1), (c-2)).

[0068] S44: First, an intrinsic layer 35 and a P+ layer 36 are sequentially grown on the surface of the N+ layer 33. The intrinsic layer 35 is preferably epitaxial silicon or germanium. Then, the silicon dioxide layer and the surface epitaxial residue are removed ( Figure 4 (d-1), (d-2)). S45: Combined 3D-2D patterning method to pattern the electrode area ( Figure 4 (e-1), (e-2)).

[0069] S46: First, the electrode area is patterned using a combined 3D-2D patterning method. Then, the N+ layer electrode 37 and the P+ layer electrode 38 are grown. The electrode layer material is preferably ITO (indium tin oxide). Finally, the PIN detector ( Figure 4 (f-1), (f-2)).

[0070] Example 5

[0071] In the aforementioned Examples 1-4, the present invention proposes methods for fabricating optoelectronic devices such as PN junctions, PIN detectors, and MOS transistors on vertical sidewalls. Because the present invention addresses key technologies for sidewall smoothing, sidewall patterning, sidewall doping, and sidewall thin-film growth in vertically deep-etched silicon structures, it can achieve sidewall integration of key optoelectronic components. This advantage lies in that, compared to methods for fabricating micromirrors, silicon optical devices, or CMOS integrated circuits on the surface of silicon wafers, it not only fully utilizes the three-dimensional space of the silicon wafer to increase integration density, but also, for the optical computing component, the vertical micromirrors can form a fully functional on-chip optical system in the horizontal direction. Light propagation loss in air is extremely low, with loss occurring only at the component interface. This loss can be significantly reduced by growing an optically transparent film, making it suitable for large-scale integration.

[0072] Figure 5 The figure shows a schematic diagram of a three-dimensional optoelectronic on-chip integration system based on vertical micromirrors. The horizontal laser light emitted by an edge-emitting laser 39 is collimated by a spherical lens 40, which is manufactured on the vertical sidewall using two-photon printing additive manufacturing or focused ion beam milling and has an optical anti-reflection film grown on it. The collimated light is then input into an optical computing unit 41 composed of a Mach-Zehnder interferometer based on a vertical micromirror. The output light after the optical computing is irradiated onto a photodetector 42 based on a vertical micromirror, converting the optical signal into an electrical signal, which is then input into a three-dimensional integrated circuit unit 43 for further signal processing and data calculation. To achieve higher integration density and better heat dissipation, the double-sided process and the technologies of through-silicon vias, microbumps, bonding rings, and bonding to form microchannels in Example 3 can be applied to a three-dimensional optoelectronic integrated system based on vertical micromirrors to meet the needs of more application scenarios.

[0073] Example 6

[0074] The three-dimensional optoelectronic on-chip integration system based on vertical micromirrors can form a computing cluster with complex functions under the support of power supply and heat dissipation systems, such as Figure 6 As shown. The three-dimensional optoelectronic on-wafer integrated system 44 based on vertical micromirrors is integrated and packaged with other integrated circuit chips 45 on a circuit board 46. The bottom of the circuit board 46 is connected to the power supply board 47 to provide working power to the on-wafer system 44. There are microfluidic cooling fins 48 on the top and bottom of the on-wafer system 44 and the inside and bottom of the power supply board 47 to dissipate heat from the high-density integrated system to ensure that the system can work stably. A cooling fan 49 is installed on the outside of the microfluidic cooling fin 48 to further enhance the heat dissipation capacity of the system. Multiple such on-wafer system units are installed in a cabinet 50. The bottom of the cabinet is equipped with a power supply 51 for supplying power to the entire cabinet and a coolant circulation system 52 integrated with a circulation pump and a heat exchanger. Multiple such cabinets 50 are connected to each other by cables or optical cables 53 to form a computing cluster with complex functions.

[0075] Example 7

[0076] The digital manufacturing method of the photocurrent on-wafer integrated system based on the on-wafer system simulator proposed in this invention is a digital tool covering the entire process of design, manufacturing, and testing. By building a wafer-level digital twin model, it can achieve closed-loop optimization and yield improvement for the entire life cycle of integrated circuit manufacturing. Figure 7 As shown in Figure 1, digital manufacturing methods mainly include digital twin modeling, virtual design and digital simulation, digital manufacturing process control, automated test feedback, and dynamic correction mechanisms. S71: Digital twin modeling steps: Perform system-level digital modeling of the on-wafer system by building a multi-physics coupling model, a data-driven model library, and a real-time simulation engine; The multi-physics field coupling model includes: an optical / electromagnetic model that simulates interconnect crosstalk and signal integrity through FDTD (finite-difference time-domain); and an electrical / thermodynamic model that predicts the thermal gradient, TSV stress distribution, parasitic parameters, and microchannel heat dissipation capacity of 3D stacked chips through finite element analysis.

[0077] The data-driven model library includes: a process parameter library for storing historical data of equipment such as lithography, etching, and deposition; a defect pattern library is a classification model trained based on a large artificial intelligence model, which is used to identify defects on the wafer surface during the manufacturing process, such as particle contamination, atlas features of overlay deviation, etc.

[0078] Real-time simulation engine: Real-time simulation is achieved through hardware acceleration and cloud collaboration. Hardware acceleration uses GPU clusters to achieve parallel simulation of wafer-level system functions and performance; cloud collaboration uses low-latency multi-tasking to synchronize multi-factory data through 5G networks to support production line linkage.

[0079] S72: Virtual Design and Digital Simulation Steps: Based on the mathematical model established in S71, use artificial neural networks and large models to automatically layout the on-chip network interconnection topology, form a simulator for on-chip system topology algorithms and performance simulation, generate the on-chip system layout, dynamically adjust the power unit position, and configure microchannel heat dissipation; (1) Simulator-driven intelligent layout: Use artificial neural networks and large models to automatically layout the on-chip network interconnection topology of the optoelectronic on-chip integrated system, and then perform automatic routing to generate the on-chip system layout.

[0080] (2) Optical-electrical-thermal-fluidic joint simulation: Dynamically adjust the position of the power consumption unit and configure microfluidic heat dissipation based on the simulation results.

[0081] S73: Digital manufacturing process control step: Based on the layout generated by the design and simulation results in S72, the micro-nano processing equipment is controlled to use the above-mentioned on-wafer integration method of the photocurrent chip based on the vertical micromirror to perform manufacturing. During the manufacturing process, the error data of the micro-nano processing is collected in real time, the optimal process parameters are predicted and fed back to the equipment control terminal; Real-time collection of error data in lithography, etching, thin film, and heat treatment processes in micro-nano processing, prediction of optimal process parameters, and feedback to the equipment control end.

[0082] S74: Automated Test Feedback Step: Multiple measurement steps are implemented during the lithography, etch, thin film, and thermal processes, including but not limited to film thickness, sheet resistance, etch depth, and structural topography. After the node process and its measurement steps are completed, measurement data is automatically extracted. Simulation results are compared with automated measurement data such as electron microscope images, sheet resistance, and film thickness to infer the overall processing quality of the wafer-level system. The results are then fed back to the simulator, allowing it to move from an ideal model to a closer approximation of the actual situation. An incremental learning framework is deployed to continuously train the defect classification model using production line data, assisting in analyzing and optimizing process conditions.

[0083] S75: Dynamic correction mechanism steps: According to the automated test results in S74, the simulator used for the on-wafer system topology algorithm and performance simulation in S72 is dynamically corrected. By quantifying the weight of the influence of process parameters on the final performance, the highly sensitive parameters are corrected first. The adaptive simulation model is established and corrected by combining physical equations, artificial neural networks and large models with measured parameters to improve the generalization ability of process window prediction. The model in the on-wafer system simulator is further updated synchronously based on the measured data.

[0084] (1) Error tracing and weight allocation: By quantifying the influence of process parameters (such as etching rate, deposition temperature, etching rate, etc.) on the final performance, the weight of the correction of highly sensitive parameters is analyzed, and the error transmission chain from the atomic level (ALD film growth) to the system level (power consumption delay product) is established to locate the bottleneck link.

[0085] (2) Adaptive simulation model: Combine physical equations, artificial intelligence networks, large models, and measured parameters to establish and modify adaptive simulation models to improve the generalization ability of process window prediction; (3) Digital twin image update: After each batch of production, the model in the simulator used for on-chip system topology algorithm and performance simulation is synchronously updated based on the measured data.

[0086] In summary, the present invention can form a vertical micromirror structure with a roughness of less than 1 nanometer by smoothing the sidewalls of deeply etched silicon through high temperature, dry method, or wet method. On this basis, a three-dimensional-two-dimensional patterning method is used to load various passive optical devices and active optical devices on the microelectromechanical structure, forming an on-chip optical system with adjustable parameters and functions such as computing, sensing, and communication in the horizontal direction. This on-chip optical system only has slight optical signal loss at the device interface, and the propagation loss in the air is extremely low, making it suitable for large-scale integration. At the same time, transistor elements such as PN junctions, CMOS, FinFET (Fin Field-Effect Transistor), GAAFET (Gate-All-Around Field-Effect Transistor) can be manufactured on the top, bottom, and sidewalls of the silicon wafer, realizing concave-convex three-dimensional integrated circuits and improving the integration density. By integrating optical units, electrical chips, and microfluidic units on the wafer with high density, we can realize on-wafer systems and large-scale computing clusters with complex functional processing capabilities such as computing, sensing, communication, signal processing, and data storage. We further proposed a wafer-level chip model construction technology and digital manufacturing method to comprehensively improve the design and manufacturing efficiency of wafer-level systems.

[0087] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed in this application.

[0088] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for on-wafer integration of a photocurrent chip based on vertical micromirrors, characterized in that: include: On a drivable micro-electromechanical system structure, based on deep etching, sidewall smoothing and 3D-2D patterning methods, passive and active optical devices based on vertical micromirrors are manufactured to form optical chips. On at least one of the top, bottom, and sidewall surfaces of a silicon wafer, a 3D-2D patterning method is used to manufacture an integrated circuit to obtain a concave-convex 3D integrated circuit, i.e., an electrical chip; Bonding a plurality of concave-convex three-dimensional integrated circuits through micro-bumps and bonding rings to form microchannels, and connecting the plurality of microchannels through through-holes to form a microfluidic unit; The optical chip, the electrical chip and the microfluidic unit are integrated on-wafer to form an on-wafer system including a photocurrent chip based on a vertical micromirror.

2. The method according to claim 1, characterized in that The manufacturing process of passive optical components includes: Deep etching and sidewall smoothing step: deep etching a vertical structure on the silicon wafer and smoothing the sidewalls of the vertical structure to form a vertical micromirror; 3D-2D patterning step: using two-photon printing to perform 3D patterning on the sidewalls of the vertical micromirror, and using spraying or layered coating of multiple layers of photoresist and exposure and development to achieve 2D patterning of areas outside the sidewalls, thereby achieving patterning of the entire wafer; Thin film growth step: growing optical thin films and electrical thin films on the sidewalls of the wafer and the vertical micromirrors, wherein the optical thin films include anti-reflection films, anti-reflection films, filter films, polarizing films, and spectroscopic films, and the electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

3. The method according to claim 1, characterized in that The manufacturing process of active optical devices includes: Deep etching and sidewall smoothing step: deep etching a vertical structure on the silicon wafer and smoothing the sidewalls of the vertical structure to form a vertical micromirror; 3D-2D patterning step: using two-photon printing to perform 3D patterning on the sidewalls of the vertical micromirror, and using spraying or layered coating of multiple layers of photoresist and exposure and development to achieve 2D patterning of areas outside the sidewalls, thereby achieving patterning of the entire wafer; Doping and activation step: performing ion implantation and heat treatment on the sidewalls of the vertical micromirror to achieve sidewall doping activation, ohmic contact formation, and metal electrode alloying; Thin film growth step: growing optical thin films and electrical thin films on the sidewalls of the wafer and the vertical micromirrors, wherein the optical thin films include anti-reflection films, anti-reflection films, filter films, polarizing films, and spectroscopic films, and the electrical thin films include insulating gate films, passivation layer films, and metal electrode films.

4. The method according to claim 2 or 3, characterized in that In the deep etching and sidewall smoothing steps, the sidewall smoothing methods include but are not limited to high temperature annealing, low flow dry etching, low concentration wet chemical etching, reducing the alternating cycle of etching and protection processes, gas cluster ion beam etching, focused ion beam etching milling, ion beam etching, and chemical mechanical polishing of the sidewalls based on hard mask metal protection of the front side.

5. The method according to claim 2 or 3, characterized in that In the three-dimensional-two-dimensional patterning step, exposure and development methods include but are not limited to contact exposure, deep ultraviolet lithography, and extreme ultraviolet lithography.

6. The method according to claim 2 or 3, characterized in that In the doping and activation steps, sidewall doping methods include, but are not limited to, tilted angle rotation ion implantation and plasma doping.

7. The method according to claim 1, characterized in that The bonding method for forming the microchannel is selected from at least one of transient liquid phase bonding, eutectic bonding, thermal compression bonding, hybrid bonding, and anodic bonding.

8. The method according to claim 1, characterized in that Through a double-sided process, concave-convex three-dimensional integrated circuits are made on the upper and lower surfaces of the silicon wafer, and the circuits on the upper and lower surfaces are connected through silicon vias; three double-sided concave-convex three-dimensional integrated circuits are bonded through micro-bumps and bonding rings to form microchannels, and the coolant flows horizontally through the microchannels formed by bonding and flows vertically between layers through silicon vias.

9. The method according to claim 1, characterized in that Several of the on-chip systems are installed in a cabinet. A power supply for the entire cabinet and a coolant circulation system integrated with a circulation pump and a heat exchanger are installed at the bottom of the cabinet; the cabinets are connected by electrical cables or optical cables.

10. A digital manufacturing method for an on-wafer system including a photocurrent chip based on vertical micromirrors, characterized in that: include: Digital twin modeling steps: By building a multi-physics field coupling model, a data-driven model library, and a real-time simulation engine, the on-chip system is digitally modeled at the system level; Virtual design and digital simulation steps: Based on the established digital model, artificial neural networks and large models are used to automatically layout the on-chip network interconnection topology, forming a simulator for on-chip system topology algorithms and performance simulation. This generates the on-chip system layout, dynamically adjusts the positions of power-consuming units, and configures microchannel cooling. Digital manufacturing process control step: controlling the micro-nano processing equipment to be manufactured using the method of claim 1, collecting error data in the micro-nano processing process in real time during the manufacturing process, predicting the optimal process parameters and feeding them back to the equipment control terminal; Automated test feedback steps: Several measurement steps are set up in the lithography, etching, thin film, and thermal treatment processes. After the node process and its measurement steps are completed, the measurement data is automatically extracted. The simulation results are compared with the measurement data to infer the overall processing quality of the wafer-level system. The results are fed back to the simulator to optimize process conditions. Dynamic correction mechanism steps: According to the measurement data, the simulator is dynamically corrected, the weight of the influence of the process parameters on the final performance is analyzed by quantifying the process parameters, and the highly sensitive parameters are corrected first. The adaptive simulation model is established and corrected by combining physical equations, artificial intelligence networks and large models, and measured parameters to improve the generalization ability of process window prediction, and further synchronously update the model in the simulator based on the measured data.

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