Method and device for splicing multiple photomasks of system on chip

Abstract

The embodiment of the invention discloses a method and a device for splicing multiple photomasks of a system on chip. A specific embodiment of the method comprises the following steps: determining a layout area corresponding to each functional unit required to be spliced on a wafer; determining a target number of photomasks required by each functional unit according to the layout area; according to the layout area corresponding to each functional unit, controlling an operation device, and equally dividing each functional unit into areas of the corresponding multiple photomasks; identifying the interconnection direction between the functional units, and obtaining the number of external interconnection signals corresponding to each interconnection unit and a corresponding outgoing line direction identification group; and controlling the operation equipment to splice the multiple photomasks to obtain the on-chip system layout. According to the embodiment, splicing of multiple photomasks can be achieved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of on-wafer systems, and more particularly to a method and device for splicing multiple masks between on-wafer systems. Background Art

[0002] System on Wafer (SoW) is a wafer-level very large-scale integration technology. Currently, the fifth-generation CoWos-S packaging technology is commonly used, supporting splicing with up to 4X mask widths. It can integrate more logic dies and HBM (High Bandwidth Memory), but only two types of chips are integrated: System on Chip (SOC) and HBM, making the chip variety relatively simple. Interconnections on the silicon-based interposer primarily involve interconnection between SOC chips and multiple data channels between the SOC and its corresponding HBM. Interconnections on the silicon substrate are relatively simple and are all completed within the 4X mask, with no interconnection between 4X masks.

[0003] However, because the system-on-wafer system can integrate multiple heterogeneous cores (such as storage, computing, and switching), the interconnect network it forms is necessarily more complex than that of traditional CoWoS-S. This means that the splicing within the 4x mask of the system-on-wafer system is more difficult. Here, after the CoWoS-S package is implemented using 4x mask splicing, the wafer is diced, the individual cores are then packaged and used. In other words, although the functional units require 4x mask splicing to implement, since there is no interconnection between the functional units, CoWoS-S does not need to consider the splicing between the 4x masks.

[0004] Furthermore, the wafer-level silicon substrate for a system-on-wafer (SWS) is implemented using a whole wafer (8-inch or 12-inch). This wafer substrate carries multiple functional units with identical functions, and the entire wafer constitutes a complete physical layout of the SWS wafer-level silicon substrate. For example, a 12-inch SWS wafer-level silicon substrate can have a layout area of ​​up to tens of thousands of square millimeters. High-density interconnections exist both within individual functional units and between them, and the density and complexity of these interconnections within functional units are higher than those found in CoWoS-S. Because these interconnections exist between functional units, even if the area of ​​a single SWS functional unit can be constrained within a 4x mask, conventional CoWoS-S intra-4x mask stitching technology still cannot solve the splicing challenges faced by SWS across multiple masks.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the inventive concept and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0006] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0007] Some embodiments of the present disclosure provide a method and apparatus for splicing multiple masks on a wafer system to solve the technical problems mentioned in the above background technology section.

[0008] In a first aspect, some embodiments of the present disclosure provide a method for realizing splicing between multiple masks of an on-wafer system, the method comprising: determining the layout area corresponding to each functional unit to be spliced ​​on the wafer according to the size of the mounted core particles and the process constraints of the core particle bonding; determining the target number of masks required for each functional unit according to the above layout area; controlling the operating equipment to place each functional unit in equal parts in the area of ​​the corresponding multiple masks according to the layout area corresponding to each functional unit; identifying the interconnection direction between each functional unit, and obtaining the number of externally interconnected signals and the corresponding output direction identification group corresponding to each interconnected unit, wherein the output direction identification is used to characterize the output direction of the interconnected unit; controlling the operating equipment to splice the multiple masks according to the number of externally interconnected signals and the output direction identification group corresponding to each interconnected unit to obtain the on-wafer system layout.

[0009] In a second aspect, some embodiments of the present disclosure provide an on-wafer system multi-mask splicing implementation device, the device comprising: a first determination unit, configured to determine the layout area corresponding to each functional unit to be spliced ​​on the wafer according to the size of the mounted core particles and the process constraints of the core particle bonding; a second determination unit, configured to determine the target number of masks required for each functional unit based on the above-mentioned layout area; a first control unit, configured to control the operating equipment according to the layout area corresponding to each functional unit, and place each functional unit equally in the area of ​​the corresponding multi-mask; an identification unit, configured to identify the interconnection direction between each functional unit, and obtain the number of external interconnected signals and the corresponding output direction identification group corresponding to each interconnected unit, wherein the output direction identification is used to characterize the output direction of the interconnected unit; a second control unit, configured to control the operating equipment to splice the multi-masks according to the number of external interconnected signals and the output direction identification group corresponding to each interconnected unit, to obtain the on-wafer system layout.

[0010] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0011] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation of the first aspect is implemented.

[0012] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the on-wafer system multiple mask splicing implementation method of some embodiments of the present disclosure, multiple mask internal splicing can be realized. Based on this, the on-wafer system multiple mask splicing implementation method of some embodiments of the present disclosure, first, by determining the layout area corresponding to each functional unit that needs to be spliced ​​on the wafer, thereby determining the number of required masks to combine into a multiple mask. Then, by identifying the interconnection direction between each functional unit, it can be used to determine the splicing position between the multiple masks. Thus, the multiple masks can be uniformly spliced ​​internally according to the number of externally interconnected signals and the line direction identification group corresponding to the interconnection unit. Thereby, the complexity of directly splicing between multiple masks is reduced, and then, the splicing between multiple masks (such as 4x masks) is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0014] Figure 1 is a flow chart of some embodiments of a method for implementing multiple mask stitching on a wafer system according to the present disclosure; Figure 2 It is a schematic diagram of the interconnection of functional units; Figure 3 This is a schematic diagram of the signal division of the switching chip; Figure 4 It is a schematic diagram of the splicing design of a single functional unit; Figure 5 It is a schematic diagram of splicing multiple masks of multiple functional units; Figure 6 1 is a schematic structural diagram of some embodiments of an apparatus for realizing multi-mask inter-splicing on a wafer system according to the present disclosure; Figure 7 It is a structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0016] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0017] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0018] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0019] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0020] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0021] Figure 1 The flowchart 100 of some embodiments of the on-wafer system multi-mask stitching implementation method according to the present disclosure is shown. The on-wafer system multi-mask stitching implementation method includes the following steps: Step 101 : determining the layout area corresponding to each functional unit to be spliced ​​on the wafer according to the size of the mounted die and the process constraints of the die bonding.

[0022] In some embodiments, the execution entity (e.g., a computing device) of the on-wafer system multi-mask stitching implementation method can determine the corresponding layout area on the wafer for each functional unit to be stitched based on the size of the mounted die and the process constraints of die bonding. The process constraints of die bonding can be the mounting spacing between the functional units.

[0023] It should be noted that the computing device described above can be either hardware or software. When the computing device is hardware, it can be implemented as a distributed cluster consisting of multiple servers or terminal devices, or as a single server or a single terminal device. When the computing device is software, it can be installed in the hardware devices listed above. It can be implemented as multiple software or software modules, for example, to provide distributed services, or as a single software or software module. No specific limitations are given here.

[0024] In some optional implementations of some embodiments, the execution entity determines the layout area corresponding to each functional unit to be spliced ​​on the wafer based on the size of the mounted chip and the process constraints of the chip bonding, including: In the first step, the size of a single functional unit and the layout data between each functional unit are determined using the size of the mounted core particles and the constraints of the core particle bonding. The size of the functional unit corresponding to the size of the mounted core particles can be found by looking up the table. Then, the layout data can be determined according to the preset arrangement method. Here, the layout size of the functional unit corresponding to the size of the mounted core particles can be selected from the constraints of the core particle bonding. For example, the constraints can include constraint sub-conditions corresponding to different models of mounted core particles. Each constraint sub-condition includes the size of the functional unit layout, including horizontal spacing and vertical spacing. Thus, the horizontal spacing and vertical spacing between each functional unit can be selected as the layout data.

[0025] The second step is to generate the layout area according to the size of each functional unit and the layout data between the functional units. The layout area can be determined according to a preset arrangement method.

[0026] For example, consider a 3×3 array arrangement for arranging nine functional units. The horizontal dimension of each functional unit can be determined by adding the length of the three functional units to the horizontal spacing between them, and the vertical dimension of each functional unit can be determined by adding the width of the three functional units to the vertical spacing between them. The product of the horizontal and vertical dimensions is then used to determine the layout area.

[0027] Step 102 : Determine the target number of masks required for each functional unit based on the layout area.

[0028] In some embodiments, the execution entity may determine a target number of multiplier masks required for each functional unit based on the layout area. Each functional unit may be assigned a corresponding number of masks (i.e., a target number, e.g., 4) based on a preset mask multiplier (e.g., 4). Thus, each functional unit may correspond to a multiplier mask composed of four masks. The size and multiplier of the multiplier masks may be set based on the layout area and the size of the functional unit.

[0029] Step 103 : According to the layout area corresponding to each functional unit, control the operating device to equally place each functional unit in the corresponding multiple mask area.

[0030] In some embodiments, the execution entity can control the operating device according to the layout area corresponding to each functional unit, and place each functional unit equally within the corresponding multi-fold mask area. Here, the operating device can be a robotic arm. Thus, the robotic arm can be controlled to place the functional units within the area covered by the multi-fold mask.

[0031] Step 104 : Identify the interconnection directions between the functional units, and obtain the number of externally interconnected signals and the corresponding outgoing line direction identification group corresponding to each interconnection unit.

[0032] In some embodiments, the execution entity can identify the interconnection direction between each functional unit, and obtain the number of externally interconnected signals corresponding to each interconnection unit and the corresponding outgoing line direction identification group, wherein the outgoing line direction identification is used to indicate the outgoing line direction of the interconnection unit.

[0033] In some optional implementations of some embodiments, the execution subject identifies the interconnection direction between the functional units and obtains the number of externally interconnected signals and the outgoing line direction identification group corresponding to each interconnection unit, including: The first step is to determine the interconnection signal group and the corresponding outgoing direction identification group for the external interconnection of the above-mentioned functional units based on the preset functional unit interconnection logic information. The external interconnection is the communication connection between adjacent functional units. Here, the functional unit interconnection logic information can represent the interconnection design between logical units. For example, the functional unit interconnection logic information can include a switching chip signal transmission pin identification group. Thus, the switching chip signal transmission pin identification representing the outgoing direction in the switching chip signal transmission pin identification group can be determined as the outgoing direction identification to obtain the outgoing direction identification group. The switching chip signal transmission pin identification representing the external signal transmission pin is determined as the interconnection signal to obtain the interconnection signal group. Here, each interconnection signal corresponds to an outgoing direction identification to represent the outgoing direction of the interconnection signal.

[0034] For example, see Figure 2The switching chip between a single functional unit is provided with four external interconnection directions, which can be used to interconnect with the four adjacent functional units above, below, left and right.

[0035] In the second step, based on the outgoing line direction identification group, each interconnection signal in the interconnection signal group is divided into signals to obtain a plurality of signal clusters.

[0036] In addition, the number of a plurality of signal clusters may be determined as the number of signals.

[0037] Optionally, based on the outgoing line direction identification group, each interconnection signal in the interconnection signal group is divided into multiple signal clusters, including: The first step is to split the interconnect signals in the aforementioned interconnect signal groups that correspond to the same outgoing direction identifier into a transmit signal group and a receive signal group. Signal splitting can be done by dividing the TX / RX signals from the same outgoing direction (e.g., outgoing from the right side of a functional unit) into two signal clusters: TX (Transmit) and RX (Receive) signals, which are then output through different masks.

[0038] In the second step, each transmitted signal in the transmitted signal group and each received signal in the received signal group are respectively determined as a signal cluster to obtain a plurality of signal clusters.

[0039] In practice, the P (Positive) and N (Negative) lines of the TX or RX differential signals are placed in a single signal cluster. Different signal clusters are routed from different masks to their corresponding scribe lines, avoiding the splicing area within the mask. When routing the lines, the length of the differential lines within and between pairs within and between signal clusters must be kept constant. Alignment markers are placed within the scribe lines for splicing between multiple masks. The width of the scribe lines is half the distance between two functional units, completing the layout design of the functional units. Since the switch chip is typically located in the middle of a single functional unit in an on-wafer system, that is, in the middle of a 4x mask, to reduce the risk of pattern shift during splicing between masks, the signals required for routing the switch chip up, down, left, and right are divided into two signal clusters and routed from two masks. Furthermore, the routing locations avoid the splicing area between two masks within the 4x mask.

[0040] For example, see Figure 3 The signal division diagram of the switching chip is shown. Figure 3The functional units in the switch are equally divided into four regions, each corresponding to a mask (i.e., mask Msk1, mask Msk2, mask Msk3, and mask Msk4), which together form a 4x mask. The external interconnection of the switch chip is generally high-speed interconnection. To meet signal quality requirements, the differential line pairs must have equal length constraints both within and between pairs. Figure 3 As shown, signal clusters can be S1, S2, S3, S4, S5, S6, S7, and S8. Here, S1 and S2 are differential signals that interconnect the switch chip of a functional unit with the adjacent functional unit above. S3 and S4 are differential signals that interconnect the switch chip of a functional unit with the adjacent functional unit to the right. S5 and S6 are differential signals that interconnect the switch chip of a functional unit with the adjacent functional unit below. S7 and S8 are differential signals that interconnect the switch chip of a functional unit with the adjacent functional unit to the left. Taking S1 and S2 as an example, when classifying signal clusters, the same pair of differential lines is grouped into the same signal cluster, for example, S1 (TX1 P / N, TX2 P / N, etc.) and S2 (RX1 P / N, RX2 P / N, etc.). When routing signals within a signal cluster, ensure that the differential lines within a pair within S1 and S2 are of equal length, as well as the lengths between pairs within S1 and S2.

[0041] Step 105 : According to the number of externally interconnected signals and the line direction identification group corresponding to each interconnection unit, the operating device is controlled to splice the multiple masks to obtain an on-wafer system layout.

[0042] In some embodiments, the execution subject may control the operating device to splice multiple masks according to the number of externally interconnected signals and the line direction identification group corresponding to each interconnection unit to obtain an on-wafer system layout.

[0043] First, see Figure 4 The schematic diagram of the splicing design of a single functional unit is shown. Figure 4 B1 in the Figure 3 In the figure, line cluster S1 represents line cluster S2, and B2 represents line cluster S2, and so on. The interconnected traces that need to be spliced ​​between quadruple masks run from the functional unit to the Scribe Line. The Scribe Line contains the alignment markers required for splicing, and the width of the Scribe Line is half the distance between the two functional units. When splicing between quadruple masks, the machine (operating equipment) splices A1 and A2, A3 and A4, B1 and B3, and B2 and B4 to complete the splicing between multiple masks. This splicing method completes the layout design of a single functional unit of the on-wafer system. Here, SL (Spacing) in the figure represents the distance between the functional unit and the splicing gap.

[0044] Then, see Figure 5The schematic diagram of multiple mask splicing of multiple functional units shown in FIG. Figure 4 The splicing design of a single functional unit is completed. When preparing the wafer substrate, the splicing between the 4x masks is completed by aligning the alignment mark (i.e. the line direction mark) in the Scribe Line, thereby completing the preparation of the entire on-wafer system (layout).

[0045] In practice, the above embodiments of the present application include the following three inventive points: 1. Design division within multiple masks: The single functional unit of the on-wafer system is equally divided and placed within multiple masks.

[0046] 2. The routing method of interconnection lines between multiple masks. External interconnection lines are divided into signal clusters, avoiding the splicing area within the multiple masks, and are led out through different masks respectively, while ensuring the same length between and within differential pairs.

[0047] 3. Implementation of splicing multiple masks. A single functional unit is divided equally and placed across multiple masks. The signal for splicing between masks is extended from the mask to the Scribe Line, completing the layout design of a single functional unit. Alignment marks are also placed in the Scribe Line to support wafer-level silicon substrate fabrication. This solves the challenge of splicing multiple masks during on-wafer system layout design and fabrication.

[0048] The above-mentioned various embodiments of the present disclosure have the following beneficial effects: through the on-wafer system multiple mask splicing implementation method of some embodiments of the present disclosure, multiple mask internal splicing can be realized. Based on this, the on-wafer system multiple mask splicing implementation method of some embodiments of the present disclosure, first, by determining the layout area corresponding to each functional unit that needs to be spliced ​​on the wafer, thereby determining the number of required masks to combine into a multiple mask. Then, by identifying the interconnection direction between each functional unit, it can be used to determine the splicing position between the multiple masks. Thus, the multiple masks can be uniformly spliced ​​internally according to the number of externally interconnected signals and the line direction identification group corresponding to the interconnection unit. Thereby, the complexity of directly splicing between multiple masks is reduced, and then, the splicing between multiple masks (such as 4x masks) is realized.

[0049] Further references Figure 6 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a device for realizing multi-mask splicing on a wafer system. These device embodiments are similar to Figure 1 Corresponding to the method embodiments shown, the on-wafer system multiple mask inter-splicing implementation device can be specifically applied to various electronic devices.

[0050] like Figure 6As shown, in some embodiments, an apparatus 600 for realizing multi-mask stitching on a wafer system includes: a first determining unit 601 , a second determining unit 602 , a first control unit 603 , an identifying unit 604 and a second control unit 605 . Among them, the first determination unit 601 is configured to determine the layout area corresponding to each functional unit to be spliced ​​on the wafer based on the size of the mounted core and the process constraints of the core bonding; the second determination unit 602 is configured to determine the target number of masks required for each functional unit based on the above layout area; the first control unit 603 is configured to control the operating equipment according to the layout area corresponding to each functional unit, and place each functional unit in an equal proportion in the area of ​​the corresponding multiple masks; the identification unit 604 is configured to identify the interconnection direction between each functional unit, and obtain the number of external interconnection signals and the corresponding output direction identification group corresponding to each interconnection unit, wherein the output direction identification is used to characterize the output direction of the interconnection unit; the second control unit 605 is configured to control the operating equipment to splice the multiple masks according to the number of external interconnection signals and the output direction identification group corresponding to each interconnection unit to obtain the on-wafer system layout.

[0051] It is understandable that the units described in the on-wafer system multiple mask splicing implementation device 600 are similar to those described in the reference Figure 1 Therefore, the operations, features and beneficial effects described above for the method are also applicable to the on-wafer system multiple mask stitching implementation device 600 and the units included therein, and will not be described in detail here.

[0052] Reference below Figure 7 , which shows a schematic structural diagram of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 7 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 7 As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium may store an operating system and a computer program. The computer program includes program instructions, which, when executed, may enable the processor to execute any of the above methods. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, may enable the processor to execute any of the above methods. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 7The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0053] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0054] In one embodiment, the processor is used to run a computer program stored in a memory to implement the following steps: determining the layout area corresponding to each functional unit to be spliced ​​on the wafer based on the size of the mounted core particles and the process constraints of the core particle bonding; determining the target number of masks required for each functional unit based on the above layout area; controlling the operating equipment to place each functional unit in equal parts in the area of ​​the corresponding multiple masks according to the layout area corresponding to each functional unit; identifying the interconnection direction between each functional unit, and obtaining the number of external interconnection signals and the corresponding output direction identification group corresponding to each interconnection unit, wherein the output direction identification is used to characterize the output direction of the interconnection unit; controlling the operating equipment to splice the multiple masks based on the number of external interconnection signals and the output direction identification group corresponding to each interconnection unit to obtain the on-wafer system layout.

[0055] An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the various embodiments of the method described above in the present disclosure.

[0056] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.

[0057] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0058] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A method for splicing multiple masks on a wafer system, characterized in that: include: Determine the layout area on the wafer for each functional unit to be spliced ​​based on the size of the mounted core and the process constraints of the core bonding; Determining a target number of masks required for each functional unit based on the layout area; According to the layout area corresponding to each functional unit, control the operating equipment to place each functional unit equally in the area of ​​the corresponding multiple mask; Identify the interconnection direction between each functional unit, and obtain the number of externally interconnected signals corresponding to each interconnection unit and the corresponding outgoing line direction identification group, wherein the outgoing line direction identification is used to characterize the outgoing line direction of the interconnection unit; According to the number of external interconnected signals and the line direction identification group corresponding to each interconnection unit, the control operation equipment is used to splice the multiple masks to obtain the on-wafer system layout.

2. The method according to claim 1, characterized in that in, The process of determining the layout area corresponding to each functional unit to be spliced ​​on the wafer based on the size of the mounted core particles and the process constraints of the core particle bonding includes: Using the size of the mounted core particles and the constraints of the core particle bonding, the size of a single functional unit and the layout data between each functional unit are determined; The layout area is generated according to the size of each functional unit and the layout data between the functional units.

3. The method according to claim 1, characterized in that The identifying of the interconnection direction between the functional units to obtain the number of externally interconnected signals corresponding to each interconnection unit and the corresponding outgoing line direction identification group includes: Determining, based on preset functional unit interconnection logic information, an interconnection signal group and a corresponding outgoing line direction identification group for external interconnection of the functional units, wherein the external interconnection is a communication connection between adjacent functional units; According to the outgoing line direction identification group, signal division is performed on each interconnection signal in the interconnection signal group to obtain a plurality of signal clusters.

4. The method according to claim 3, characterized in that The signal division of each interconnection signal in the interconnection signal group according to the outgoing line direction identification group to obtain multiple signal clusters includes: Splitting interconnection signals corresponding to the same outgoing line direction identifier in the interconnection signal group to obtain a transmission signal group and a reception signal group; Each transmitted signal in the transmitted signal group and each received signal in the received signal group are respectively determined as a signal cluster to obtain a plurality of signal clusters.

5. A multi-mask splicing device for an on-wafer system, characterized in that: include: The first determining unit is configured to determine the layout area corresponding to each functional unit to be spliced ​​on the wafer according to the size of the mounted chip and the process constraints of the chip bonding; a second determining unit configured to determine a target number of masks required for each functional unit according to the layout area; The first control unit is configured to control the operating device to place each functional unit equally within the corresponding multiple mask area according to the layout area corresponding to each functional unit; an identification unit configured to identify the interconnection direction between each functional unit, and obtain the number of externally interconnected signals corresponding to each interconnection unit and a corresponding outgoing line direction identification group, wherein the outgoing line direction identification is used to represent the outgoing line direction of the interconnection unit; The second control unit is configured to control the operating device to splice the multiple masks according to the number of external interconnected signals and the line direction identification group corresponding to each interconnection unit to obtain the on-wafer system layout.

6. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 4.

7. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

Images