Voltage regulator and semiconductor device

Abstract

The invention provides a voltage regulator and a semiconductor device, which can restrain response characteristics and phase margin deterioration depending on temperature when a load and a power supply of the voltage regulator change. The voltage regulator includes a differential amplifier circuit that controls an output transistor, and a phase compensation circuit that includes: a first transistor having a drain connected to an output terminal of the differential amplifier circuit, a current between the drain and the source having a negative temperature characteristic; the drain electrode of the second transistor is connected to the grid electrode of the first transistor, the grid electrode of the second transistor is connected to the grid electrode of the first transistor through a resistor, and current between the drain electrode and the source electrode has negative temperature characteristics; and a current mirror circuit that includes a voltage detection transistor that detects a voltage input to the gate of the output transistor, and that supplies a current having a positive temperature characteristic in accordance with a current flowing through the voltage detection transistor.

Description

Technical Field

[0001] The present invention relates to a voltage regulator and a semiconductor device. Background Art

[0002] Voltage regulators, which can output a constant voltage lower than the input voltage, have been widely used as integrated circuits (ICs) for power supplies of electronic devices. These voltage regulators have a phase compensation function that can suppress oscillation. Patent Document 1, for example, discloses voltage regulators with a phase compensation function.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2020-71681 Summary of the Invention

[0006] [Problems to be solved by the invention]

[0007] According to the conventional technology described above, the response characteristics and phase margin of a voltage regulator exhibit negative temperature characteristics when the load and power supply fluctuate. Specifically, in conventional voltage regulators, the response characteristics and phase margin may deteriorate when the load and power supply fluctuate, depending on the temperature characteristics of the phase compensation circuit and the temperature characteristics of the bias circuit relative to the phase compensation circuit.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a voltage regulator and a semiconductor device capable of suppressing temperature-dependent degradation of the response characteristics and phase margin of the voltage regulator when the load and power supply of the voltage regulator fluctuate.

[0009] [Technical means to solve the problem]

[0010] A voltage regulator according to one embodiment of the present invention includes: a differential amplifier circuit that amplifies and outputs a difference between a reference voltage and a voltage divided by a voltage output by an output transistor, and controls the gate of the output transistor; and a phase compensation circuit. In the voltage regulator, the phase compensation circuit includes: a first transistor having a drain connected to an output terminal of the differential amplifier circuit, and a drain-source current having a negative temperature characteristic due to a temperature characteristic of carrier mobility; a second transistor having a drain connected to the gate of the first transistor and a gate connected to the gate of the first transistor via a resistor, and a drain-source current having a negative temperature characteristic due to the temperature characteristic of carrier mobility; and a voltage detection transistor that detects a voltage input to the gate of the output transistor. The phase compensation circuit includes a current mirror circuit that supplies a current having a positive temperature characteristic to the drains of the first and second transistors based on a current flowing through the voltage detection transistor.

[0011] [Effects of the Invention]

[0012] According to the present invention, a voltage regulator and a semiconductor device can be provided that can suppress temperature-dependent degradation of the response characteristics and phase margin of the voltage regulator when a load or power supply of the voltage regulator fluctuates. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a circuit diagram showing the voltage regulator according to the first embodiment.

[0014] Figure 2 This is a graph showing the temperature characteristics of mobility in the first embodiment.

[0015] Figure 3 This is a graph for explaining the gain-frequency characteristics of each current in the transistor according to the first embodiment.

[0016] Figure 4 1 is a circuit diagram showing a voltage regulator according to a second embodiment.

[0017] Figure 5 1 is a circuit diagram showing a voltage regulator according to a third embodiment.

[0018] Figure 6 1 is a circuit diagram showing a voltage regulator according to a fourth embodiment.

[0019] Figure 7 1 is a circuit diagram showing a voltage regulator according to a fifth embodiment.

[0020] Figure 8 1 is a circuit diagram showing a voltage regulator according to a sixth embodiment.

[0021] [Explanation of Symbols]

[0022] 1, 1B, 1C, 1D, 1E: Voltage regulator

[0023] 61, 62: Bias current source

[0024] 100: Ground terminal

[0025] 101: Reference Voltage Circuit

[0026] 102: Differential amplifier circuit

[0027] 106: Output transistor / PMOS transistor

[0028] 108, 109, 113, 505: resistors

[0029] 110, 110A, 110D: Current mirror circuits

[0030] 112: First transistor / NMOS transistor

[0031] 114: Second transistor / NMOS transistor

[0032] 115: Capacitor

[0033] 121: Output terminal

[0034] 130, 131: Node

[0035] 150: Power terminal

[0036] 160: Phase compensation circuit

[0037] 170: Inverting amplifier

[0038] 171: Output terminal

[0039] 201: Voltage detection transistor / PMOS transistor

[0040] 202, 203, 204, 501, 502: PMOS transistors

[0041] 206, 503, 504: NMOS transistors

[0042] 506: Constant current source circuit

[0043] A0: Gain

[0044] L0: Gain-frequency characteristics at room temperature

[0045] L1: Gain-frequency characteristics when drain current is difficult to flow at high temperature

[0046] L2: Gain-frequency characteristics when drain current easily flows at low temperatures

[0047] MP1: PMOS transistor

[0048] μ: mobility DETAILED DESCRIPTION

[0049] [Implementation Method]

[0050] Hereinafter, preferred embodiments will be listed and a voltage regulator according to aspects of the present invention will be described in detail with reference to the accompanying drawings.

[0051] [First embodiment]

[0052] Figure 1 This is a circuit diagram showing a voltage regulator according to a first embodiment. First, the voltage regulator 1 will be described with reference to this diagram. The voltage regulator 1 includes a reference voltage circuit 101, a differential amplifier circuit 102, a phase compensation circuit 160, a P-type metal-oxide-semiconductor (PMOS) transistor 106, resistors 108 and 109, a ground terminal 100, an output terminal 121, and a power supply terminal 150.

[0053] Furthermore, all components included in the voltage regulator 1 do not need to be included in a single integrated circuit, and some components (eg, the resistor 108 and the resistor 109 ) may exist outside the IC.

[0054] In addition, although the reference numerals of the ground terminal 100 and the power terminal 150 are omitted, as long as the symbols representing the terminals are the same, they are respectively referred to as the ground terminal 100 and the power terminal 150 .

[0055] Furthermore, in the following description, the PMOS transistor 106 may be described as an output transistor.

[0056] Based on the input voltage applied between ground terminal 100 and power supply terminal 150, voltage regulator 1 generates a constant voltage lower than the input voltage and outputs it to output terminal 121. A predetermined load resistor and load capacitor (not shown) are connected to output terminal 121. Voltage regulator 1 has a phase compensation function to cope with variations in input voltage and output current. The following describes an example in which a load resistor is connected to output terminal 121.

[0057] The differential amplifier circuit 102 includes an inverting input terminal, a non-inverting input terminal, and an output terminal. Furthermore, the differential amplifier circuit 102 includes a positive power supply terminal and a negative power supply terminal (not shown). The inverting input terminal is connected to the reference voltage circuit 101. The non-inverting input terminal is connected to the connection point 120 between the resistors 108 and 109. The output terminal is connected to the gate terminal of the PMOS transistor 106. The differential amplifier circuit 102 amplifies and outputs the difference between the divided voltage (i.e., the voltage at the connection point 120 between the resistors 108 and 109) output by the PMOS transistor 106 and the output voltage VREF of the reference voltage circuit 101, thereby controlling the gate of the PMOS transistor 106.

[0058] Phase compensation circuit 160 provides phase compensation. Phase compensation circuit 160 includes a current mirror circuit 110, an N-type metal-oxide-semiconductor (NMOS) transistor 112, a resistor 113, an NMOS transistor 114, and a capacitor 115. The drain of NMOS transistor 112 is connected to the output terminal of differential amplifier circuit 102, its source is connected to ground terminal 100, and its gate is connected to one end of resistor 113 and the drain of NMOS transistor 114. The drain of NMOS transistor 114 is connected to current mirror circuit 110, its source is connected to ground terminal 100, and its gate is connected to the other end of resistor 113 and one end of capacitor 115. The other end of capacitor 115 is connected to output terminal 121 and the drain of PMOS transistor 106.

[0059] In the following description, the NMOS transistor 112 may be referred to as a first transistor, and the NMOS transistor 114 may be referred to as a second transistor.

[0060] Current mirror circuit 110 is connected between power supply terminal 150, the output terminal of differential amplifier circuit 102 (ie, node 130), and node 131. Current mirror circuit 110 outputs a predetermined current to nodes 130 and 131 according to the output voltage of differential amplifier circuit 102.

[0061] Figure 2 This is a graph showing the temperature characteristics of the mobility of the first embodiment. The horizontal axis of the graph represents temperature [°C], and the vertical axis represents mobility μ [cm] in logarithmic terms. 2 / V·sec]. In the figure, the solid line represents the temperature characteristics of electrons, and the dotted line represents the temperature characteristics of holes. In addition, the figure shows that the concentration Na of the P-type impurity is 10 14 to 10 19 Similarly, the figure shows that the concentration Nd of N-type impurities is 10 14to 10 19 Multiple examples of situations.

[0062] In the following description, the mobility-temperature characteristics of electrons and holes (ie, carriers) are sometimes not distinguished, and are referred to as carrier mobility-temperature characteristics.

[0063] As shown in the figure, carrier mobility μ increases as temperature decreases. This indicates that at low impurity concentrations, lattice scattering is particularly significant, so the change in mobility μ is largely dependent on temperature. Furthermore, at high impurity concentrations, impurity scattering is significant, so the change in mobility μ is less dependent on temperature. Thus, since carrier mobility μ increases as temperature decreases, the carrier mobility temperature characteristic can generally be said to have a negative temperature characteristic.

[0064] Therefore, since the drain current flowing between the drain and the source in the transistor is proportional to the mobility μ, it can be said that the current flowing between the drain and the source has a negative temperature characteristic.

[0065] Figure 3 This is a graph illustrating the gain-frequency characteristics of various currents in the transistor according to the first embodiment. Referring to this graph, the gain-frequency characteristics of various currents in the transistor are described, along with the case where the drain current decreases. The horizontal axis of the graph represents frequency logarithmically, and the vertical axis represents gain. In this graph, the gain-frequency characteristics at room temperature are represented by a solid line as L0, the gain-frequency characteristics at high temperatures, when drain current is difficult to flow, are represented by a dashed line (thin line) as L1, and the gain-frequency characteristics at low temperatures, when drain current easily flows, are represented by a dashed line (thick line) as L2.

[0066] like Figure 2 As shown in FIG, the current flowing between the drain and the source has a negative temperature characteristic, so when the current becomes smaller at a high temperature, as shown in FIG. Figure 3 This degrades the gain-frequency characteristics in the high-frequency region, while increasing the gain A0 in the low-frequency region. Furthermore, when the current increases at low temperatures, the gain-frequency characteristics in the high-frequency region improve, while decreasing the gain A0 in the low-frequency region. In other words, when the drain current decreases, the frequency characteristics generally deteriorate.

[0067] Therefore, at high temperatures, the gain-frequency characteristics of the transistor deteriorate, and thus the gain-frequency characteristics of the phase compensation circuit 160 also deteriorate, and the response characteristics and phase margin when the load and power supply fluctuate deteriorate depending on the temperature.

[0068] Back to Figure 1According to this embodiment, current mirror circuit 110 supplies a current with a positive temperature characteristic to the drains of NMOS transistor 112 and NMOS transistor 114. By supplying a current with a positive temperature characteristic, current mirror circuit 110 can increase the current flowing into the drains of NMOS transistor 112 and NMOS transistor 114 at high temperatures. Therefore, while the currents of the transistors in voltage regulator 1 have negative temperature characteristics, according to this embodiment, current mirror circuit 110 supplies a current with a positive temperature characteristic. This prevents temperature-dependent degradation of the response characteristics and phase margin of voltage regulator 1 when the load and power supply fluctuate.

[0069] Next, refer to Figures 4 to 8 A specific method for supplying a current having a positive temperature characteristic, an application example of the voltage regulator 1 according to the present embodiment, and the like will be described in detail.

[0070] [Second embodiment]

[0071] Figure 4 This is a circuit diagram showing a voltage regulator according to a second embodiment. With reference to this diagram, a current mirror circuit 110A, which is a specific form of the current mirror circuit 110 according to the first embodiment and is included in the voltage regulator 1A according to the second embodiment, will be described. The current mirror circuit 110A includes a PMOS transistor 201, a PMOS transistor 202, a PMOS transistor 203, a PMOS transistor 204, a constant current source circuit 506, and an NMOS transistor 206.

[0072] The source of the PMOS transistor 201 is connected to the power supply terminal 150, and the gate is connected to the Figure 1 The output node 130 of the differential amplifier circuit 102 is shown, and its drain is connected to a constant current source circuit 506. One end of the constant current source circuit 506 is connected to the drain of the PMOS transistor 201, and the other end is connected to the ground terminal 100. The source of the NMOS transistor 206 is connected to the ground terminal 100, and its drain is connected to the drain of the PMOS transistor 202. The source of the PMOS transistor 202 is connected to the power supply terminal 150, and its gate is connected to the drain of the PMOS transistor 202, the gate of the PMOS transistor 203, and the gate of the PMOS transistor 204. The source of the PMOS transistor 203 is connected to the power supply terminal 150, and its drain is connected to the node 130 (i.e., the drain of the NMOS transistor 112 of the phase compensation circuit 160). The source of the PMOS transistor 204 is connected to the power supply terminal 150, and its drain is connected to the node 131 (i.e., the drain of the NMOS transistor 114 of the phase compensation circuit 160).

[0073] The constant current source circuit 506 includes a PMOS transistor 501, a PMOS transistor 502, an NMOS transistor 503, an NMOS transistor 504, and a resistor 505. In the following description, the PMOS transistor 501 is sometimes referred to as a third transistor, the PMOS transistor 502 is sometimes referred to as a fourth transistor, the NMOS transistor 504 is sometimes referred to as a fifth transistor, the NMOS transistor 503 is sometimes referred to as a sixth transistor, and the resistor 505 is sometimes referred to as a first resistor.

[0074] The source of the PMOS transistor 501 is connected to the drain of the PMOS transistor 201, the gate is connected to the drain of the PMOS transistor 501, and the drain is connected to the drain of the NMOS transistor 503. The source of the PMOS transistor 502 is connected to the drain of the PMOS transistor 201, the gate is connected to the drain of the PMOS transistor 501, and the drain is connected to the drain of the NMOS transistor 504. The gate of the NMOS transistor 503 is connected to the drain of the NMOS transistor 504, and the source is connected to one end of the resistor 505. The gate of the NMOS transistor 504 is connected to the drain of the NMOS transistor 504, and the source is connected to the ground terminal 100. The other end of the resistor 505 is connected to the ground terminal 100.

[0075] The current mirror circuit 110A will act as Figure 1 The gate voltage of PMOS transistor 106, the output of differential amplifier circuit 102, is input to the gate of PMOS transistor 201. The drain current of PMOS transistor 201 changes depending on the value of the current flowing through the load resistor from PMOS transistor 106. The drain current of PMOS transistor 201 is mirrored (copied) to PMOS transistor 202. Furthermore, the drain current of PMOS transistor 201 is mirrored to phase compensation circuit 160 via PMOS transistor 202, PMOS transistor 203, and PMOS transistor 204. In other words, a current corresponding to the value of the current flowing through the load resistor from PMOS transistor 106 flows through nodes 130 and 131.

[0076] Here, PMOS transistor 501 and PMOS transistor 502 form a current mirror circuit. NMOS transistor 503 and NMOS transistor 504 form a current mirror circuit with their gates connected to each other, but the source of NMOS transistor 503 is connected to ground terminal 100 via a resistor. Therefore, a voltage drop occurs in resistor 505 due to the drain current of NMOS transistor 503, and the gate-source voltage of NMOS transistor 503 decreases accordingly. The voltage drop in resistor 505 is determined by the difference in K values ​​between NMOS transistor 503 and NMOS transistor 504, or the difference in K values ​​between PMOS transistor 501 and PMOS transistor 502, and the value of resistor 505. Therefore, constant current source circuit 506 operates as a constant current source circuit that is independent of the power supply voltage.

[0077] When the load current flowing through PMOS transistor 106, referenced by PMOS transistor 201, exceeds a certain fixed value, constant current source circuit 506 operates as a constant current circuit to limit the drive current value of phase compensation circuit 160. By limiting the drive current value of phase compensation circuit 160, offset is prevented from occurring in the transistors at the input stage of differential amplifier circuit 102. Variation in the output voltage caused by offset is eliminated, allowing accurate output voltage setting. Furthermore, the current consumption of phase compensation circuit 160 can be kept low according to the magnitude of the current flowing through the load resistor from PMOS transistor 106. Furthermore, even when the current flowing through the load resistor from PMOS transistor 106 is high, the drive current of phase compensation circuit 160 can be limited to prevent it from becoming excessively high.

[0078] Here, resistor 505 has a negative temperature characteristic. Due to the negative temperature characteristic of resistor 505, current mirror circuit 110A can supply a current with a positive temperature characteristic to nodes 130 and 131. By supplying a current with a positive temperature characteristic, current mirror circuit 110A can increase the current flowing into the drain of NMOS transistor 112 and the current flowing into the drain of NMOS transistor 114 at high temperatures. Therefore, according to this embodiment, the response characteristics and phase margin of voltage regulator 1 can be suppressed from deteriorating with temperature when the load and power supply of the voltage regulator fluctuate.

[0079] [Third embodiment]

[0080] Figure 5This is a circuit diagram of a voltage regulator according to a third embodiment. An example of a voltage regulator 1B according to the third embodiment will be described with reference to this diagram. The voltage regulator 1B differs from the first embodiment in that it further includes a bias current source 61 with positive temperature characteristics. The bias current source 61 is used in the differential amplifier circuit 102. In the illustrated example, the differential amplifier circuit 102 includes a grounded negative power supply terminal that allows a current with a positive temperature characteristic to flow to the ground point. The specific form of the bias current source 61 can be made using known techniques. By further employing the bias current source 61 with positive temperature characteristics in the differential amplifier circuit 102, temperature degradation of the load response characteristics can be further suppressed. Therefore, according to this embodiment, temperature-dependent degradation of the response characteristics and phase margin of the voltage regulator 1 when the load and power supply fluctuate can be suppressed.

[0081] [Fourth embodiment]

[0082] Figure 6 This is a circuit diagram showing a voltage regulator according to a fourth embodiment. With reference to this diagram, an example of a voltage regulator 1C according to the fourth embodiment will be described. The voltage regulator 1C differs from the first embodiment in that it further includes an inverting amplifier 170. In the description of the voltage regulator 1C, previously described components may be assigned the same reference numerals as those in the voltage regulator 1, and their description may be omitted.

[0083] The inverting amplifier 170 is connected between the differential amplifier circuit 102 and the PMOS transistor 106 . The output terminal 171 of the inverting amplifier 170 is connected to the drain of the NMOS transistor 112 and the gate of the PMOS transistor 106 .

[0084] Inverting amplifier 170 includes a PMOS transistor MP1 and an NMOS transistor MN1. The source of PMOS transistor MP1 is connected to power supply terminal 150, and the drain and gate are connected to each other. The drain and gate of PMOS transistor MP1 are connected to output terminal 171. The drain of NMOS transistor MN1 is connected to the drain and gate of PMOS transistor MP1, the gate is connected to the output terminal of differential amplifier circuit 102, and the source is connected to ground terminal 100.

[0085] As described above, according to this embodiment, even the voltage regulator 1C including the inverting amplifier 170 can be applied, and the temperature-dependent degradation of the response characteristics and phase margin of the voltage regulator 1C when the load and power supply of the voltage regulator 1C fluctuate can be suppressed.

[0086] [Fifth embodiment]

[0087] Figure 7This is a circuit diagram showing a voltage regulator according to the fifth embodiment. With reference to this diagram, an example of a voltage regulator 1D according to the fourth embodiment will be described. The voltage regulator 1D includes a current mirror circuit 110D in place of the current mirror circuit 110. Furthermore, the current mirror circuit 110D according to the fifth embodiment can also be applied to the voltage regulator 1 described in the first embodiment, and can also be applied to the voltage regulator 1C including the inverting amplifier 170 described in the fourth embodiment. The example shown in this diagram is an example of application to the voltage regulator 1C including the inverting amplifier 170 described in the fourth embodiment.

[0088] As shown in the figure, in the current mirror circuit 110D, the source of the PMOS transistor 203 is connected to the power supply terminal, and the gate and drain are connected to the gate of the PMOS transistor 106 and the drain of the NMOS transistor 112. That is, the PMOS transistor 203 is connected as a diode.

[0089] Since the PMOS transistor 203 is connected as a diode, even when the voltage at the gate terminal of the PMOS transistor 106 is close to the threshold voltage of the PMOS transistor 106, a current can be drawn from the power supply terminal 150 via the current mirror circuit 110D. Therefore, the gain at the gate terminal of the PMOS transistor 106 can be reduced.

[0090] Here, according to the conventional technology, when the electrostatic capacitance of the output capacitor is reduced, phase compensation may become difficult. Specifically, when the electrostatic capacitance of the output capacitor is reduced, the frequency F of the first pole generated by the output capacitor is P1 The frequency F of the second peak generated at the gate terminal of the PMOS transistor 106 is shifted to the wide area side and approaches the second peak frequency F P2 , zero-crossing frequency F zc Offset to the wide area side, zero cross frequency F zc The phase at θ approaches 0°. As a result, when the electrostatic capacitance of the output capacitor is reduced, phase compensation becomes difficult.

[0091] According to this embodiment, the gain at the gate terminal of the PMOS transistor 106 can be reduced, so that the frequency F of the second stage can be made P2 Shifted to the wide area side. The frequency F of the second pole P2 As a result of shifting to the wide area side, the frequency F of the first pole can be P1 With the frequency F of the second pole P2 Therefore, according to this embodiment, even when the electrostatic capacitance of the output capacitor is reduced, phase compensation can be performed without significantly increasing the circuit area.

[0092] [Sixth embodiment]

[0093] Figure 8 This is a circuit diagram showing a voltage regulator according to a sixth embodiment. With reference to this diagram, an example of a voltage regulator 1E according to the sixth embodiment will be described. The voltage regulator 1E according to the sixth embodiment is based on the structure of the voltage regulator 1C according to the fourth embodiment and further includes a bias current source 62 with positive temperature characteristics, as included in the voltage regulator 1B according to the third embodiment. The bias current source 62 is used in the differential amplifier circuit 102. In the example shown, the differential amplifier circuit 102 includes a grounded negative power supply terminal that allows a current with a positive temperature characteristic to flow to the ground point. The specific form of the bias current source 62 can be implemented using known techniques. By further applying the bias current source 62 with positive temperature characteristics to the differential amplifier circuit 102, the voltage regulator 1E including the inverting amplifier 170 can suppress temperature-dependent degradation of the response characteristics and phase margin, even when the load and power supply of the voltage regulator 1C fluctuate.

[0094] Furthermore, the voltage regulator 1, 1A, 1B, 1C, 1D, or 1E of this embodiment can be implemented as a predetermined semiconductor device. A semiconductor device need only include at least the voltage regulator 1, 1A, 1B, 1C, 1D, or 1E. In addition to the voltage regulator 1, 1A, 1B, 1C, 1D, or 1E, the semiconductor device may further include predetermined control circuits, peripheral circuits, and the like.

[0095] While the embodiments have been used to describe the modes for implementing the present invention, the specific aspects of the present invention are not limited to the embodiments, and various modifications, substitutions, and design changes can be made without departing from the spirit of the present invention.

[0096] Furthermore, the above-described embodiments and the configurations described in the embodiments can be combined and implemented.

Claims

1. A voltage regulator comprising: a differential amplifier circuit that outputs a voltage obtained by amplifying a difference between a reference voltage and a voltage divided by the voltage output by the output transistor to a gate of the output transistor; as well as Phase compensation circuit, In the voltage regulator, the phase compensation circuit includes: a first transistor, wherein the drain is connected to the output terminal of the differential amplifier circuit, and the current between the drain and the source has a negative temperature characteristic according to the temperature characteristic of the carrier mobility; a second transistor having a drain connected to the gate of the first transistor and a gate connected to the gate of the first transistor via a resistor, wherein a current between the drain and the source has a negative temperature characteristic according to the temperature characteristic of the carrier mobility; and A current mirror circuit includes a voltage detection transistor, which detects the voltage input to the gate of the output transistor, and the current mirror circuit supplies a current with a positive temperature characteristic to the drain of the first transistor and the drain of the second transistor according to the current flowing in the voltage detection transistor.

2. The voltage regulator according to claim 1, wherein The current mirror circuit includes a constant current source circuit for limiting the driving current value of the phase compensation circuit. The constant current source circuit comprises: a third transistor having a source connected to the drain of the voltage detection transistor and a gate connected to its own drain; a fourth transistor having a source connected to the drain of the voltage detection transistor and a gate connected to the gate of the third transistor; a fifth transistor, having a drain connected to the drain of the fourth transistor, a gate connected to its own drain, and a source grounded; a sixth transistor, having a drain connected to the drain of the third transistor and a gate connected to the gate of the fifth transistor; as well as A first resistor has one end connected to the source of the sixth transistor and the other end grounded.

3. The voltage regulator according to claim 2, wherein The first resistor has a negative temperature characteristic.

4. The voltage regulator according to claim 1, wherein The differential amplifier circuit includes a grounded negative power supply terminal. The negative-side power supply terminal allows a current having a positive temperature characteristic to flow toward a ground point.

5. A voltage regulator comprising: a differential amplifier circuit that outputs a voltage obtained by amplifying a difference between a reference voltage and a voltage divided by the voltage output by the output transistor to a gate of the output transistor; an inverting amplifier connected between the differential amplifier circuit and the output transistor; as well as Phase compensation circuit, In the voltage regulator, the phase compensation circuit includes: a first transistor, a drain of which is connected to the output terminal of the inverting amplifier, and a current between the drain and the source of which has a negative temperature characteristic according to the temperature characteristic of carrier mobility; a second transistor having a drain connected to the gate of the first transistor and a gate connected to the gate of the first transistor via a resistor, wherein a current between the drain and the source has a negative temperature characteristic according to the temperature characteristic of the carrier mobility; and A current mirror circuit includes a voltage detection transistor, which detects the voltage input to the gate of the output transistor, and the current mirror circuit supplies a current with a positive temperature characteristic to the drain of the first transistor and the drain of the second transistor according to the current flowing in the voltage detection transistor.

6. The voltage regulator according to claim 5, wherein The current mirror circuit includes a seventh transistor, The source of the seventh transistor is connected to the power supply terminal, and the gate and drain are connected to the gate of the first transistor and the drain of the second transistor. 7 . A semiconductor device comprising the voltage regulator according to claim 1 .

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