Electronic equipment and data processing method of electronic equipment

Abstract

The present application provides an electronic device comprising: memory banks including a first memory bank and a second memory bank, the number of bit lines of the first memory bank and the number of bit lines of the second memory bank being the same as the number of bit lines of the memory banks; and the sensing unit is arranged between the first memory bank and the second memory bank, the sensing unit is respectively and dynamically coupled with the first memory bank and the second memory bank, and the sensing unit is used for accessing data from the first memory bank or the second memory bank.

Description

Technical Field

[0001] The present application relates to an electronic device and a data processing method for the electronic device. Background Art

[0002] With the rapid development of artificial intelligence (AI), data demand has surged, and memory processing speed has become a key bottleneck. Under current memory process conditions, high bandwidth is often accompanied by high energy consumption. Read operations consume approximately 1.25 pJ / bit. For memory bandwidths of up to 1TB / s (or several times this), the power consumption for data transfer alone can reach 20W. This high energy consumption makes it difficult to meet the energy-efficient demands of independent neural processing units, necessitating innovation in memory architecture. Summary of the Invention

[0003] In view of the above problems, the present application provides an electronic device and a data processing method of the electronic device that reduce power consumption when processing data through a storage body.

[0004] According to a first aspect of the present application, an electronic device is provided, comprising: a storage body, comprising a first storage body and a second storage body, the number of bit lines of the first storage body and the number of bit lines of the second storage body being the same as the number of bit lines of the storage body; a sensing unit, arranged between the first storage body and the second storage body, the sensing unit being dynamically coupled to the first storage body and the second storage body respectively, and the sensing unit being used to access data from the first storage body or the second storage body.

[0005] According to an embodiment of the present application, the electronic device also includes: a first switch, which is arranged between the sensing unit and the first storage body, and the sensing unit is coupled to the bit line of the first storage body through the first switch; a second switch, which is arranged between the sensing unit and the second storage body, and the sensing unit is coupled to the bit line of the second storage body through the second switch.

[0006] According to an embodiment of the present application, the electronic device is used to: in response to an access to a first storage body, the first switch closes to couple the sensing unit to the first storage body, and the second switch opens to cut off the coupling between the sensing unit and the second storage body; in response to an access to the second storage body, the second switch closes to couple the sensing unit to the second storage body, and the first switch opens to cut off the coupling between the sensing unit and the first storage body.

[0007] According to an embodiment of the present application, the sensing unit is disposed in the middle of the memory bank, and the number of word lines of the first memory bank is the same as the number of word lines of the second memory bank.

[0008] According to an embodiment of the present application, the electronic device also includes: a third switch, arranged on the word line of the first storage body, dividing the first storage body into a third storage body and a fourth storage body; a fourth switch, arranged on the word line of the second storage body, dividing the second storage body into a fifth storage body and a sixth storage body.

[0009] According to an embodiment of the present application, the electronic device is used to: in response to access to a third storage body or a fourth storage body, the first switch corresponding to the third storage body or the fourth storage body is closed and the third switch is opened to couple the sensing unit to the third storage body or the fourth storage body, and the second switch is opened to cut off the coupling of the sensing unit to the second storage body.

[0010] According to an embodiment of the present application, the electronic device is used to: in response to access to the fifth storage body or the sixth storage body, the second switch corresponding to the fifth storage body or the sixth storage body is closed and the fourth switch is opened to couple the sensing unit to the fifth storage body or the sixth storage body, and the first switch is opened to cut off the coupling between the sensing unit and the first storage body.

[0011] According to an embodiment of the present application, the electronic device further includes: an address decoder, which decodes the input binary address to obtain a row address signal and a column address signal, and the electronic device controls the opening and closing of the first switch and the second switch according to the row address signal; a row address decoder, which activates the word line in the first storage body or the second storage body based on the row address signal; and a column address decoder, which selects the target bit line in the first storage body or the second storage body based on the column address signal; wherein, the electronic device controls the opening and closing of the first switch and the second switch according to the row address signal, including: the electronic device is used to close the first switch and disconnect the second switch in response to the row address signal being located in the first storage body; or to disconnect the first switch and close the second switch in response to the row address signal being located in the second storage body; wherein, selecting the target bit line in the first storage body or the second storage body based on the column address signal includes: the electronic device is used to select the target bit line in the first storage body to process data in response to the word line being located in the first storage body; or to select the target bit line in the second storage body to process data in response to the word line being located in the second storage body.

[0012] A second aspect of the present application provides a data processing method for an electronic device, comprising: obtaining a control signal input into the electronic device; and selecting a first storage body or a second storage body for data processing in response to the control signal; wherein the electronic device comprises a storage body and a sensing unit, the storage body comprises a first storage body and a second storage body, the number of bit lines of the first storage body and the number of bit lines of the second storage body are both the same as the number of bit lines of the storage body; the sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body respectively, and the sensing unit is used to access data from the first storage body or the second storage body.

[0013] A third aspect of the present application provides a computer program product, comprising a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implements a data processing method for an electronic device, the data processing method for an electronic device comprising: obtaining a control signal input into the electronic device; and selecting a first storage body or a second storage body for data processing in response to the control signal; wherein the electronic device comprises a storage body and a sensing unit, the storage body comprises a first storage body and a second storage body, the number of bit lines of the first storage body and the number of bit lines of the second storage body are both the same as the number of bit lines of the storage body; the sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body, respectively, and the sensing unit is used to access data from the first storage body or the second storage body. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0015] Figure 1 The structure of a conventional electronic device is schematically shown;

[0016] Figure 2 The internal structure of a conventional electronic device is schematically shown;

[0017] Figure 3 The structure of an electronic device according to an embodiment of the present application is schematically shown;

[0018] Figure 4 Schematically shows the internal structure of an electronic device according to an embodiment of the present application;

[0019] Figure 5 Schematically shows the internal structure of an electronic device according to another embodiment of the present application;

[0020] Figure 6 Schematically shows the internal structure of an electronic device according to another embodiment of the present application;

[0021] Figure 7 Schematically shows the internal structure of an electronic device according to another embodiment of the present application;

[0022] Figure 8 A diagram schematically illustrates the internal structure of an electronic device according to another embodiment of the present application; and

[0023] Figure 9 The flowchart of the data processing method of the electronic device according to the embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0025] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0026] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0027] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0028] Figure 1 The structure of a conventional electronic device 100 is schematically shown. Figure 2 The internal structure of a conventional electronic device 100 is schematically shown.

[0029] like Figure 1 As shown, in the conventional electronic device 100, the sensing unit 120 is located outside the entire memory bank 110 and is coupled to the bit line 140 of the memory bank 110. Figure 2 When reading data from memory bank 110, a row address decoder activates word line 130 corresponding to the row address signal. The voltage signal of memory cell 101 on word line 130 may need to pass through all memory cells 101 on bit line 140 before reaching sensing unit 120 for amplification. In electronic device 100, the capacitors of memory cells 101 are connected to their corresponding bit lines 140 via transistors. When the voltage signal is transmitted through memory cells 101, RC losses occur. The longer the bit line length, the greater the loss.

[0030] To reduce memory loss, an embodiment of the present application provides an electronic device, the electronic device comprising: a memory body, comprising a first memory body and a second memory body, the number of bit lines of the first memory body and the number of bit lines of the second memory body being the same as the number of bit lines of the memory body; a sensing unit, disposed between the first memory body and the second memory body, the sensing unit being dynamically coupled to the first memory body and the second memory body, respectively, and being used to access data from the first memory body or the second memory body. This embodiment provides a customized memory architecture, placing the sensing unit inside the memory body, and the first memory body and the second memory body being dynamically coupled to the sensing unit. When accessing data, power consumption is reduced by accessing the first memory body or the second memory body.

[0031] The following will be passed Figures 3 to 8 An electronic device according to an embodiment of the present application is described in detail.

[0032] Figure 3 The structure of an electronic device according to an embodiment of the present application is schematically shown.

[0033] like Figure 3 As shown, the electronic device 300 includes: a storage body 310, including a first storage body 311 and a second storage body 312, the number of bit lines of the first storage body 311 and the number of bit lines of the second storage body 312 are the same as the number of bit lines of the storage body 310; a sensing unit 320, arranged between the first storage body 311 and the second storage body 312, the sensing unit 320 is dynamically coupled to the first storage body 311 and the second storage body 312 respectively, and the sensing unit 320 is used to access data from the first storage body 311 or the second storage body 312.

[0034] According to an embodiment of the present application, the memory bank 310 is arranged along its word line 330 direction (eg Figure 3 310 is split into a first memory bank 311 and a second memory bank 312. The bit lines 340 of memory bank 310 are also split into two parts: a first sub-bit line 341 and a second sub-bit line 342. That is, each bit line 340 of memory bank 310 is split into a first sub-bit line 341 and a corresponding second sub-bit line 342, with a one-to-one correspondence between first sub-bit lines 341 and second sub-bit lines 342. The first sub-bit line 341 is located in the first memory bank 311, and the second sub-bit line 342 is located in the second memory bank 312. The number of bit lines in the first memory bank 311 and the number of bit lines in the second memory bank 312 are the same as the number of bit lines in the memory bank 310.

[0035] The sensing unit 320 is disposed between the first memory bank 311 and the second memory bank 312. Specifically, the sensing unit 320 is positioned inside the memory bank 310, rather than outside it. Specifically, it is positioned between the first sub-bit line 341 and the second sub-bit line 342 of the memory bank 310. The number of sensing units 320 is the same as the number of bit lines 340 in the memory bank 310. Specifically, a sensing unit 320 is disposed between each first sub-bit line 341 and the corresponding second sub-bit line 342. The sensing units 320 are dynamically coupled to the first memory bank 311 and the second memory bank 312, respectively. Specifically, the sensing units 320 are dynamically coupled to the first sub-bit line 341 of the first memory bank 311 and the second sub-bit line 342 of the second memory bank 312. For example, a switch can be used to dynamically couple the sensing units 320 to the first sub-bit line 341 and the second sub-bit line 342. The following describes that switches are provided between the sensing unit 320 and the first memory bank 311 and the second memory bank 312 to achieve dynamic coupling.

[0036] The sensing unit 320 is used to access data from the first memory bank 311 or the second memory bank 312. In practice, the sensing unit 320 accesses data via the first sub-bit line 341 of the first memory bank 311 or the second sub-bit line 342 of the second memory bank 312. For example, the sensing unit 320 can read data from the first memory bank 311, specifically, from the first sub-bit line 341. The specific process of accessing data will be described below in conjunction with the address decoder.

[0037] According to an embodiment of the present application, a customized electronic device is provided, and the sensing unit is provided inside the storage body and between the first storage body and the second storage body, and is dynamically coupled with the first storage body and the second storage body. When accessing data, the length of the bit line through which the voltage signal passes can be reduced, the RC loss can be reduced, and the memory power consumption can be reduced.

[0038] According to an embodiment of the present application, the electronic device 300 further includes: a first switch 350, which is provided between the sensing unit 320 and the first memory bank 311, and the sensing unit 320 is coupled to the bit line of the first memory bank 311 through the first switch 350; a second switch 360, which is provided between the sensing unit 320 and the second memory bank 312, and the sensing unit 320 is coupled to the bit line of the second memory bank 312 through the second switch 360. Figure 4 The settings of the first switch 350 and the second switch 360 and the states when accessing the memory bank are described.

[0039] Figure 4 The figure schematically shows the internal structure of an electronic device according to an embodiment of the present application. Figure 4 The internal structure diagram shown is Figure 3 Enlarged view of the area marked by the dashed line.

[0040] like Figure 4 As shown, first switches 350 are disposed between sensing cells 320 and first sub-bit lines 341 of first memory bank 311. A first switch 350 is disposed between each first sub-bit line 341 and its corresponding sensing cell 320. The number of first switches 350 is the same as the number of first sub-bit lines 341 and sensing cells 320. Sensing cells 320 are coupled to first sub-bit lines 341 of first memory bank 311 via first switches 350.

[0041] The second switches 360 are disposed between the sensing cells 320 and the second sub-bit lines 342 of the second memory bank 312. A second switch 360 is disposed between each second sub-bit line 342 and the corresponding sensing cell 320. The number of second switches 360 is the same as the number of second sub-bit lines 342 and the number of sensing cells 320. The sensing cells 320 are coupled to the second sub-bit lines 342 of the second memory bank 312 via the second switches 360.

[0042] According to an embodiment of the present application, the electronic device 300 is used to: in response to an access to the first storage body 311, the first switch 350 is closed to couple the sensing unit 320 with the first storage body 311, and the second switch 360 is opened to cut off the coupling between the sensing unit 320 and the second storage body 312; in response to an access to the second storage body 312, the second switch 360 is closed to couple the sensing unit 320 with the second storage body 312, and the first switch 350 is opened to cut off the coupling between the sensing unit 320 and the first storage body 312.

[0043] Switches are used to separate the first and second storage banks 311, 312, and the sensing unit 320, enabling dynamic coupling of the sensing unit 320 with the first and second storage banks 312. When the first switch 350 is closed and the second switch 360 is open, the sensing unit 320 is coupled to the first storage bank 311; conversely, the sensing unit 320 is coupled to the second storage bank 312. This configuration allows for dynamic control of access areas and increases data access flexibility.

[0044] In response to access to the first memory bank 311 or the second memory bank 312, part of the memory bank 310 (for example, the first memory bank 311 or the second memory bank 312) is connected to the circuit by controlling the opening and closing of the switch. Therefore, the signal only needs to pass through part of the memory bank to realize data reading and writing, thereby shortening the bit line length through which the signal passes and reducing RC loss.

[0045] For example, when accessing data, the electronic device closes the first switch 350 and opens the second switch 360, or closes the second switch 360 and opens the first switch 350, based on the row address signal generated by the decoder. This allows only the first memory bank 311 or the second memory bank 312 to be connected to the circuit, enabling data access from the connected first memory bank 311 or the second memory bank 312. The method of controlling the opening and closing of the first switch 350 and the second switch 360 based on the generated address signal will be described below and will not be elaborated on in detail here.

[0046] For example, the first switch 350 and the second switch 360 can be replaced by a single-pole double-throw switch, the moving contact of the single-pole double-throw switch is located at the sensing unit 320, and the two static contacts are located at the first sub-bit line 341 and the second sub-bit line 342 respectively. By controlling the connection state of the moving contact, the sensing unit 320 is coupled to the first sub-bit line 341 or the second sub-bit line 342.

[0047] According to an embodiment of the present application, the sensing unit 320 is disposed in the middle of the memory bank 310 , and the number of word lines of the first memory bank 312 is the same as the number of word lines of the second memory bank 312 .

[0048] like Figure 3 The figure shows a case where the sensing unit 320 is disposed in the middle of the memory bank 310. This is equivalent to the sensing unit 320 dividing the memory bank 310 into two equal parts along direction A. In this case, the first memory bank 311 and the second memory bank 312 have the same number of word lines and bit lines, and the first memory bank 311 and the second memory bank 312 include the same number of memory cells 301. Because the bit line lengths of the first memory bank 311 and the second memory bank 312 are half the bit line length of the memory bank 310, the average bit line length that the voltage signal travels through when data is accessed in the first memory bank 311 or the second memory bank 312 is half the average bit line length that the voltage signal travels through when data is accessed in the memory bank 310. Therefore, compared to conventional electronic devices, the electronic device of the embodiment can save 50% of power consumption.

[0049] In practice, the sensing unit 320 does not necessarily need to be located in the middle of the memory bank 310, nor does it need to divide the word lines of the memory bank 310 evenly into two parts. The sensing unit 320 can be located at any position along the word line direction A of the memory bank 310, as long as the memory bank 310 is split into multiple sub-memory banks, which constitute the memory bank 310. For example, the sensing unit 320 can be located above the middle of the memory bank 310, or the sensing unit 320 can be located below the middle of the memory bank 310.

[0050] Figure 5 The internal structure of an electronic device 300 according to another embodiment of the present application is schematically shown.

[0051] like Figure 5 As shown, the sensing unit 320 is arranged at the lower part of the middle position of the memory bank 310, and is dynamically coupled to the first memory bank 311 through the first switch 350, and is dynamically coupled to the second memory bank 312 through the second switch 360. The number of word lines of the first memory bank 311 is greater than the number of word lines of the second memory bank 312. In the case where the sensing unit 320 is arranged at the lower part of the middle position of the memory bank 310, since the bit line length of the second memory bank 312 is smaller than the bit line length of the first memory bank 311, the average bit line length of the signal passing when accessing data to the second memory bank 312 is smaller than the average bit line length of the signal passing when accessing data to the first memory bank 311. Therefore, when processing data with a smaller amount of data, data can be read and / or written through the second memory bank 312 to reduce memory power consumption. When reading and / or writing data with a smaller amount of data, Figure 5 The average bit line length of the signal when accessing data in the second memory bank 312 is less than Figure 3 When the sensing unit 320 is disposed in the middle of the memory bank 310 , the average bit line length of the signal passing through the second memory bank 312 during data access can further reduce RC loss because the average bit line length of the voltage signal passing through is shorter.

[0052] For example, two or more rows of sensing units 320 may be arranged inside and / or outside the memory bank 310 along the word line direction A, so as to split the memory bank 310 into at least three sub-memory banks. That is, at least two sensing units 320 are arranged on each bit line 340 of the memory bank 310, and each sensing unit 320 is dynamically coupled to the bit lines around it. Figure 6 and Figure 7 An embodiment in which multiple rows of sensing units 320 are provided is described.

[0053] Figure 6 The internal structure of an electronic device 300 according to another embodiment of the present application is schematically shown.

[0054] like Figure 6 As shown, two rows of sensing units 320 are arranged within memory bank 310 along wordline direction A, dividing memory bank 310 into four sub-memory banks. Sub-memory banks 3101 and 3102 are separated by sensing units 320 and switches, sub-memory banks 3103 and 3104 are separated by sensing units 320 and switches, and sub-memory banks 3102 and 3103 are separated by switches. Access to any sub-memory bank is achieved by controlling the opening and closing of the switches. For example, opening switches 3501 and 3503 and closing switch 3502 enables access to sub-memory bank 3102.

[0055] Exemplarily, at least two of the sub-storage body 3101, sub-storage body 3102, sub-storage body 3103 and sub-storage body 3104 of the storage body 310 can be accessed simultaneously, for example, by closing switches 3501 and 3504, and opening switches 3502, 3503 and 3505, and reading data from or writing data to sub-storage body 3101 and sub-storage body 3103.

[0056] For example, a dual-port memory can be used from Figure 6 The dual-port memory accesses different storage addresses based on two independent ports and performs data reading and / or writing operations in parallel, for example, referring to Figure 6 , close switches 3501 and 3504, and open switches 3502, 3503, and 3505. One port of the dual-port memory reads data from sub-bank 3101, and the other port writes data to sub-bank 3103. The dual-port memory has an integrated hardware conflict detection circuit. When the access addresses of the two ports conflict, this circuit detects the conflict. After detecting a conflict, internal arbitration logic intervenes, and the arbitration result determines which port performs the access operation.

[0057] Figure 7 The internal structure of an electronic device 300 according to another embodiment of the present application is schematically shown.

[0058] like Figure 7 As shown, sensing units 320 are provided inside and outside memory bank 310 along wordline direction A, dividing memory bank 310 into three sub-memory banks. Sub-memory bank 3105 is separated from sub-memory bank 3106 by sensing units 320 and switches, while sub-memory bank 3106 is separated from sub-memory bank 3107 by a switch. Access to any sub-memory bank is achieved by controlling the opening and closing of the switches. For example, opening switch 3508 and closing switch 3509 enables access to sub-memory bank 3107.

[0059] For example, at least two of the sub-memory banks 3105, 3106, and 3107 of the memory bank 310 can be accessed simultaneously, for example, by closing switches 3506 and 3509 and opening switches 3507 and 3508, reading data from the sub-memory bank 3105 and writing data to the sub-memory bank 3107. Figure 7 Multiple sub-banks are shown accessing data.

[0060] The specific steps of reading and writing data through the electronic device 300 will be described in detail below in conjunction with the address decoder.

[0061] According to an embodiment of the present application, the electronic device 300 further includes: an address decoder 370, which decodes the input binary address to obtain a row address signal and a column address signal, and the electronic device 300 controls the opening and closing of the first switch 350 and the second switch 360 according to the row address signal; a row address decoder 371, which activates the word line 330 in the first storage body 311 or the second storage body 312 based on the row address signal; and a column address decoder 372, which selects the target bit line in the first storage body 311 or the second storage body 312 based on the column address signal; wherein the electronic device 300 controls the opening and closing of the first switch 350 and the second switch 360 according to the row address signal. It includes: the electronic device 300 is located in the first storage body 311 in response to the row address signal, the first switch 350 is closed, and the second switch 360 is opened; or the electronic device 300 is located in the second storage body 312 in response to the row address signal, the first switch 350 is opened, and the second switch 360 is closed; wherein, selecting the target bit line in the first storage body 311 or the second storage body 312 based on the column address signal includes: the electronic device 300 is located in the first storage body 311 in response to the word line 330 being located in the first storage body 311, selecting the target bit line in the first storage body 311 to process data; or selecting the target bit line in the second storage body 312 to process data in response to the word line 330 being located in the second storage body 312.

[0062] Taking the case where the word line 330 corresponding to the address of the data to be read is located in the first memory bank 311 as an example, the data reading operation is as follows.

[0063] Before the operation begins, the first sub-bit line 341 and the second sub-bit line 342 (usually there are two complementary bit lines BL and / BL for differential detection) are usually precharged to a precise intermediate reference voltage (usually VDD / 2), which puts the first sub-bit line 341 and the second sub-bit line 342 in a balanced state that is sensitive to small voltage changes.

[0064] The CPU / memory controller sends the address for data to be read. The address decoder 370 interprets the address and, based on the row address signal, closes the first switch 350 and opens the second switch 360. The row address decoder 371 outputs an activation signal to the corresponding word line 330 (located in the first memory bank 311). This increases the voltage of this word line 330, turning on the transistor switches of all memory cells 301 in that row. The memory cell capacitor is connected to its corresponding first sub-bit line 341 (BL or / BL) through the turned-on transistor. The first sub-bit line 341 has its own capacitance, much greater than that of the memory cell capacitor. When these two are connected, charge is redistributed between the memory cell capacitor and the first sub-bit line capacitor. If the memory cell capacitor stores a logic "1" (charged, with a voltage close to VDD), it injects a small amount of charge into the first sub-bit line 341, which is precharged to VDD / 2, causing the voltage on this first sub-bit line 341 to rise slightly. If the memory cell capacitor stores a logic "0" (low charge, voltage close to 0V), the charge on the first sub-bitline 341 flows into the memory cell capacitor, causing the voltage on the first sub-bitline 341 to drop slightly. The complementary bitline / BL is typically connected to a reference cell (storing a fixed value such as VDD / 2) or maintained in a precharged state, with its voltage changing very little or in the opposite direction (for differential comparison). At this point, a very small voltage difference ΔV (positive or negative) is generated between BL and / BL.

[0065] When the sensing unit 320 is enabled, it detects the tiny voltage difference ΔV between BL and / BL. Using a positive feedback mechanism, the sensing unit 320 rapidly amplifies this voltage difference. Ultimately, it pulls the bit line with the higher voltage up to the full power supply voltage VDD (representing logic "1") and pulls the bit line with the lower voltage down to ground GND (representing logic "0"). This process is called latching.

[0066] The column address decoder 372 selects which column (or columns) of the sensing unit 320 in the first memory bank 311 is connected to the data output bus according to the address. The stable logic level (VDD or GND) output by the selected sensing unit 320 is read out to the data output buffer, which drives the signal to the output pin of the memory chip and finally transmits it back to the CPU / memory controller.

[0067] After amplifying the voltage to a logic level, the sensing unit 320 also writes that logic level back to the corresponding storage cell capacitor. When the sensing unit 320 pulls BL to VDD, this VDD voltage charges the storage cell capacitor through the turned-on transistor (writing a "1"); when it pulls BL to GND, the storage cell capacitor discharges (writing a "0"). In this way, the data of the cell being read is automatically restored after the read operation is completed.

[0068] After the read operation is completed, word line 330 is turned off (voltage drops, transistors are turned off), disconnecting memory cell 301 from first sub-bit line 341. First sub-bit line 341 (BL and / BL) is precharged to the reference voltage again, preparing for the next access (read or write).

[0069] Taking the case where the word line 330 corresponding to the address to be written data is located in the first memory bank 311 as an example, the data writing operation is as follows.

[0070] The first and second sub-bit lines 341 and 342 (BL and / BL) are precharged to VDD / 2.

[0071] The CPU / memory controller sends the address and data to be written. Address decoder 370 interprets the address and, based on the row address signal, closes first switch 350 and opens second switch 360. Row address decoder 371 outputs an activation signal to the corresponding word line 330 (located in first memory bank 311). This increases the voltage on word line 330, turning on the transistor switches in all memory cells 301 in that row.

[0072] The column address decoder 372 selects which column (or columns) of the first sub-bit line 341 on the first memory bank 311 is connected to the data input circuit (write driver) according to the address, and the data to be written (such as logic "1" or "0") is loaded into the data input buffer.

[0073] The write driver forcibly drives the selected first sub-bit line 341 (BL and / BL) based on the data value to be written. If a "1" is to be written, the write driver drives BL to VDD and / BL to GND (or maintains it at the reference voltage). If a "0" is to be written, the write driver drives BL to GND and / BL to VDD.

[0074] Since the word line 330 of this row is active (the transistor is on), the selected memory cell capacitor is connected to the first sub-bit line 341 driven by the write driver through the turned-on transistor. If the first sub-bit line 340 is driven to VDD, the memory cell capacitor is charged to VDD (writing a "1"). If the first sub-bit line 341 is driven to GND, the memory cell capacitor is discharged to GND (writing a "0").

[0075] After the write operation is complete, word line 330 is turned off (voltage drops, transistors are turned off), disconnecting memory cell 301 from first sub-bit line 341. First sub-bit line 341 (BL and / BL) is precharged to the reference voltage again, preparing for the next access (read or write).

[0076] When data is read and written, reading and writing can be achieved only through the first storage body 311 or the second storage body 312, saving memory power consumption.

[0077] Figure 8 The structure of an electronic device 300 according to another embodiment of the present application is schematically shown.

[0078] According to an embodiment of the present application, the electronic device 300 also includes: a third switch 380, which is arranged on the word line 330 of the first storage body 311, dividing the first storage body 311 into a third storage body 3111 and a fourth storage body 3112; a fourth switch 390, which is arranged on the word line 330 of the second storage body 312, dividing the second storage body 312 into a fifth storage body 3121 and a sixth storage body 3122.

[0079] like Figure 8 As shown, a third switch 380 is provided on each word line 330 of the first memory bank 311. For example, a third switch 380 is provided on each word line 330 of the first memory bank 311 along the bit line direction B of the first memory bank 311. The third switch 380 divides the first memory bank 311 into a third memory bank 3111 and a fourth memory bank 3112. A fourth switch 390 is provided on each word line 330 of the second memory bank 312. For example, a fourth switch 390 is provided on each word line 330 of the second memory bank 312 along the bit line direction B of the second memory bank 312. The fourth switch 390 divides the second memory bank 312 into a fifth memory bank 3121 and a sixth memory bank 3122.

[0080] Exemplarily, the number of bit lines of the third storage body 3111 and the fourth storage body 3112 can be the same or different. For example, the third switch 380 can be set in the middle position of each word line 330 of the first storage body 311, and the third storage body 3111 and the fourth storage body 3112 have the same number of storage cells 301.

[0081] Exemplarily, the number of bit lines of the fifth storage body 3121 and the sixth storage body 3122 can be the same or different. For example, the fourth switch 390 can be set to the left of the middle position of each word line 330 of the second storage body 312, and the number of storage cells 301 of the fifth storage body 3121 is smaller than the number of storage cells 301 of the sixth storage body 3122 (the number of bit lines of the fifth storage body 3121 is smaller than the number of bit lines of the sixth storage body 3122).

[0082] For example, the positions of the sensing unit 320, the third switch 380, and the fourth switch 390 can be set so that the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121, and the sixth storage body 3122 have the same size, and the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121, and the sixth storage body 3122 include the same number of storage cells 301. For example, the sensing unit 320 is set in the middle position of the bit line 340, and the third switch 380 and the fourth switch 390 are set in the middle position of the word line 330.

[0083] When reading and writing data, data can be read from the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121 or the sixth storage body 3122, or data can be written to the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121 or the sixth storage body 3122 through switch control.

[0084] Exemplarily, the electronic device 300 is configured to: in response to access to the third storage bank 3111 or the fourth storage bank 3112, close the first switch 350 corresponding to the third storage bank 3111 or the fourth storage bank 3112 and open the third switch 380 to couple the sensing unit 320 to the third storage bank 3111 or the fourth storage bank 3112, and open the second switch 360 to disconnect the sensing unit 320 from the second storage bank 312. Alternatively, the electronic device 300 is configured to: in response to access to the fifth storage bank 3121 or the sixth storage bank 3122, close the second switch 360 corresponding to the fifth storage bank 3121 or the sixth storage bank 3122 and open the fourth switch 390 to couple the sensing unit 320 to the fifth storage bank 3121 or the sixth storage bank 3122, and open the first switch 350 to disconnect the sensing unit 320 from the first storage bank 311.

[0085] Reference Figure 8 For example, the first switch 350 corresponding to the fourth storage body 3112 may be closed, the third switch 380 may be opened, and the second switch 360 may be opened, and data may be read from and / or written to the fourth storage body 3112 .

[0086] Exemplarily, when data is processed using the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121 or the sixth storage body 3122, the row address decoder outputs an activation signal to the corresponding word line, and the word line length of the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121 and the sixth storage body 3122 is reduced relative to the word line length of the storage body 310, the first storage body 311 and the second storage body 312. When the word line is activated (high level), the transistor switches of all storage cells 301 corresponding to the word line rows of the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121 and the sixth storage body 3122 (the length of the word line row is less than the word line length of the storage body 310) are turned on, so that their storage capacitors are connected to the corresponding bit lines.

[0087] By setting a switch on the word line 330 of the memory bank 310, the first memory bank 311 and the second memory bank 312 are split again, and finally four small sub-memory banks are formed, which shortens the word line length activated by the row address signal, thereby saving memory power consumption and improving access speed.

[0088] The data reading or writing operation on the third storage body 3111, the fourth storage body 3112, the fifth storage body 3121 or the sixth storage body 3122 is similar to the data reading or writing operation on the first storage body 311 or the second storage body 312, and will not be elaborated here.

[0089] Based on the above electronic device, this application also provides a data processing method for an electronic device. Figure 9 The method is described in detail.

[0090] Figure 9 The flowchart of the data processing method of the electronic device according to the embodiment of the present application is schematically shown.

[0091] like Figure 9 As shown, the data processing method 900 of the electronic device of this embodiment includes operations S910 to S920.

[0092] In operation S910, a control signal input to an electronic device is acquired.

[0093] In operation S920, in response to a control signal, the first storage body or the second storage body is selected for data processing; wherein, the electronic device includes a storage body and a sensing unit, the storage body includes a first storage body and a second storage body, the number of bit lines of the first storage body and the number of bit lines of the second storage body are both the same as the number of bit lines of the storage body; the sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body respectively, and the sensing unit is used to access data from the first storage body or the second storage body.

[0094] Exemplarily, the control signal input to the electronic device may be a signal for reading data and / or writing data to the electronic device. For example, the control signal may include write data and a write address.

[0095] Exemplarily, in response to the control signal, the first memory bank or the second memory bank is selected for data processing, that is, the first memory bank or the second memory bank is selected for data processing according to the binary address included in the control signal.

[0096] The specific process of selecting the first memory bank or the second memory bank in combination with the address decoder has been described above and will not be elaborated on in detail here.

[0097] For example, you can also use Figure 8 The electronic device shown includes a third memory bank, a fourth memory bank, a fifth memory bank, and a sixth memory bank, and performs data processing. For example, in response to a control signal input to the electronic device, the third memory bank, the fourth memory bank, the fifth memory bank, or the sixth memory bank is selected for data processing. The process of selecting the third memory bank, the fourth memory bank, the fifth memory bank, or the sixth memory bank for reading or writing data in conjunction with the address decoder is similar to the process of selecting the first memory bank or the second memory bank for reading or writing data in conjunction with the address decoder, and is not further described herein.

[0098] According to an embodiment of the present application, a computer program product is also provided, including a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implement a data processing method of an electronic device, and the data processing method of the electronic device includes: obtaining a control signal input into the electronic device; and in response to the control signal, selecting a first storage body or a second storage body for data processing; wherein the electronic device includes a storage body and a sensing unit, the storage body includes a first storage body and a second storage body, and the number of bit lines of the first storage body and the number of bit lines of the second storage body are both the same as the number of bit lines of the storage body; the sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body, respectively, and the sensing unit is used to access data from the first storage body or the second storage body.

[0099] When the computer program or instruction is executed by the processor, the above functions defined in the electronic device of the embodiment of the present application are performed. According to the embodiment of the present application, the systems, devices, modules, units, etc. described above can be implemented by computer program modules.

[0100] According to an embodiment of the present application, the program code for executing the computer program provided by the embodiment of the present application can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0101] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0102] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

Claims

1. An electronic device, wherein: The electronic device comprises: A memory bank, comprising a first memory bank and a second memory bank, wherein the number of bit lines of the first memory bank and the number of bit lines of the second memory bank are both the same as the number of bit lines of the memory bank; The sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body respectively, and the sensing unit is used to access data from the first storage body or the second storage body.

2. The electronic device according to claim 1, wherein The electronic device further comprises: a first switch, disposed between the sensing unit and the first memory bank, wherein the sensing unit is coupled to a bit line of the first memory bank through the first switch; The second switch is provided between the sensing unit and the second memory bank, and the sensing unit is coupled to the bit line of the second memory bank through the second switch.

3. The electronic device according to claim 2, wherein The electronic device is used for: In response to access to the first memory bank, the first switch is closed to couple the sensing unit to the first memory bank, and the second switch is opened to disconnect the sensing unit from the second memory bank. In response to access to the second memory bank, the second switch is closed to couple the sensing unit to the second memory bank, and the first switch is opened to disconnect the sensing unit from the first memory bank.

4. The electronic device according to claim 1, wherein The sensing unit is disposed in the middle of the memory bank, and the number of word lines of the first memory bank is the same as the number of word lines of the second memory bank.

5. The electronic device according to claim 2, wherein The electronic device further comprises: a third switch, provided on a word line of the first memory bank, dividing the first memory bank into a third memory bank and a fourth memory bank; The fourth switch is provided on the word line of the second memory bank, and divides the second memory bank into a fifth memory bank and a sixth memory bank. The electronic device according to claim 5 , wherein: The electronic device is used to: in response to access to the third storage body or the fourth storage body, close the first switch corresponding to the third storage body or the fourth storage body and open the third switch to couple the sensing unit with the third storage body or the fourth storage body, and open the second switch to cut off the coupling between the sensing unit and the second storage body.

7. The electronic device according to claim 5, wherein: The electronic device is used to: in response to access to the fifth storage body or the sixth storage body, the second switch corresponding to the fifth storage body or the sixth storage body is closed and the fourth switch is opened to couple the sensing unit with the fifth storage body or the sixth storage body, and the first switch is opened to cut off the coupling of the sensing unit with the first storage body.

8. The electronic device according to claim 2, wherein: The electronic device further comprises: an address decoder, decoding an input binary address to obtain a row address signal and a column address signal, wherein the electronic device controls the opening and closing of the first switch and the second switch according to the row address signal; a row address decoder, configured to activate a word line in the first memory bank or the second memory bank based on the row address signal; a column address decoder for selecting a target bit line in the first memory bank or the second memory bank based on the column address signal; The electronic device controlling the opening and closing of the first switch and the second switch according to the row address signal includes: The electronic device is configured to close the first switch and open the second switch in response to the row address signal being located in the first memory bank; or to open the first switch and close the second switch in response to the row address signal being located in the second memory bank; The selecting a target bit line in the first memory bank or the second memory bank based on the column address signal includes: The electronic device is configured to select a target bit line in the first memory bank to process data in response to the word line being located in the first memory bank; or to select a target bit line in the second memory bank to process data in response to the word line being located in the second memory bank.

9. A data processing method for an electronic device, wherein: The method comprises: Acquiring a control signal input to the electronic device; and In response to the control signal, selecting the first memory bank or the second memory bank for data processing; In which, the electronic device includes a storage body and a sensing unit, the storage body includes the first storage body and the second storage body, the number of bit lines of the first storage body and the number of bit lines of the second storage body are both the same as the number of bit lines of the storage body; the sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body respectively, and the sensing unit is used to access data from the first storage body or the second storage body.

10. A computer program product comprising a computer program or instructions, wherein: When the computer program or instruction is executed by the processor, a data processing method of an electronic device is implemented. The data processing method of the electronic device includes: Acquiring a control signal input to the electronic device; and In response to the control signal, selecting the first memory bank or the second memory bank for data processing; In which, the electronic device includes a storage body and a sensing unit, the storage body includes the first storage body and the second storage body, the number of bit lines of the first storage body and the number of bit lines of the second storage body are both the same as the number of bit lines of the storage body; the sensing unit is arranged between the first storage body and the second storage body, the sensing unit is dynamically coupled to the first storage body and the second storage body respectively, and the sensing unit is used to access data from the first storage body or the second storage body.

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