Serial data transmission method, device and system, electronic equipment and storage medium

Abstract

The embodiment of the invention relates to a serial data transmission method, device and system, electronic equipment and a storage medium, and the method comprises the steps: responding to a triggering data transmission operation, determining an address of a corresponding target storage area, and determining a data transmission direction; determining a target slave device where the target storage area is located from the at least two slave devices based on the address; selecting a target chip selection signal output port connected with the target slave device from at least two preset chip selection signal output ports; setting the level of the target chip selection signal output port as a first preset level; generating a data transmission instruction based on the address and the data transmission direction; and sending the data transmission instruction to the target slave device by using a serial data transmission port connected with the target slave device, and performing data communication with the target slave device. According to the embodiment of the invention, the conflict of data read-write addresses when the types of the slave devices are the same and the address spaces of the memories are the same can be avoided, and the accuracy of data read-write is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a serial data transmission method, device, system, electronic device and storage medium. Background Art

[0002] Many current communication device applications involve a single master device connected to multiple slave devices, with the master device writing data to or reading data from the slave device's memory. For example, a master device might include a CPU and an FPGA (Field Programmable Gate Array), both connected via a local bus (local data bus). The CPU must configure cross-device data, requiring communication with the slave devices via the FPGA. To save costs, the local bus is typically converted to a bus format that uses fewer ports. Furthermore, when multiple slave devices have the same functionality, they often use identical circuitry. This requires that the converted local bus format be able to distinguish and identify each slave device.

[0003] When the types of slave devices are the same, the memory address spaces inside the respective slave devices are the same. The existing technology cannot effectively distinguish these slave devices of the same type, which easily leads to memory space access conflicts and affects the normal operation of the devices. Summary of the Invention

[0004] In view of this, in order to solve some or all of the above technical problems, the embodiments of the present application provide a serial data transmission method, device, system, electronic device and storage medium.

[0005] In a first aspect, an embodiment of the present application provides a serial data transmission method applied to a master device, the method comprising: in response to triggering a data transmission operation, determining the address of a target storage area corresponding to a data read and write operation to be performed, and determining a data transmission direction; based on the address, determining a target slave device where the target storage area is located from at least two preset slave devices; selecting a target chip select signal output port connected to the target slave device from at least two preset chip select signal output ports; setting the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; based on the address and data transmission direction, generating a data transmission instruction in accordance with a preset data transmission format; using the serial data transmission port connected to the target slave device, sending the data transmission instruction to the target slave device, and using the serial data transmission port to communicate data with the target slave device.

[0006] In one possible implementation, based on the address, the target slave device where the target storage area is located is determined from at least two preset slave devices, including: extracting data on preset data bits from the address as chip select data; and determining the slave device corresponding to the chip select data as the target slave device from at least two slave devices.

[0007] In one possible embodiment, based on the address and data transmission direction, a data transmission instruction is generated in accordance with a preset data transmission format, including: if the data transmission direction is a write data direction, obtaining the data to be written; based on the address, generating a write data instruction in a first preset format; using a serial data transmission port connected to the target slave device, sending the data transmission instruction to the target slave device, and using the serial data transmission port to communicate data with the target slave device, including: using the serial data transmission port, sending the write data instruction and the data to be written to the target slave device.

[0008] In one possible embodiment, based on the address and data transmission direction, a data transmission instruction is generated in accordance with a preset data transmission format, including: if the data transmission direction is a read data direction, based on the address, a read data instruction in a second preset format is generated; using a serial data transmission port connected to the target slave device, the data transmission instruction is sent to the target slave device, and data communication with the target slave device is performed using the serial data transmission port, including: using the serial data transmission port, sending a read data instruction to the target slave device; in response to receiving a response signal sent by the target slave device, receiving read data from the serial data transmission port.

[0009] In one possible embodiment, after sending a data transmission instruction to the target slave device using a serial data transmission port connected to the target slave device and communicating data with the target slave device using the serial data transmission port, the method further includes: in response to completion of the data transmission, setting the level of the target chip select signal output port to a second level.

[0010] In a second aspect, an embodiment of the present application provides a serial data transmission method applied to a slave device, the method comprising: in response to detecting that the level of a chip select signal input terminal is a first preset level, receiving a data transmission instruction sent by a master device from a serial data transmission port; based on the data transmission instruction, determining the address of a target storage area corresponding to a data read and write operation to be performed, and determining a data transmission direction; based on the address and data transmission direction, performing data read and write operations on the target storage area.

[0011] In one possible implementation, data read and write operations are performed on a target storage area based on an address and a data transmission direction, including: if the data transmission direction is a write data direction, receiving data to be written sent by a master device from a serial data transmission port; and writing the data to be written into the target storage area according to the address.

[0012] In one possible implementation, data read and write operations are performed on a target storage area based on an address and a data transmission direction, including: if the data transmission direction is a read data direction, reading data from the target storage area according to the address; sending a response signal to a master device, and sending the read data to the master device.

[0013] In a third aspect, an embodiment of the present application provides a serial data transmission system, which includes a master device and at least two slave devices, the master device includes a main processor and a data transceiver, and the main processor and the data transceiver are connected through a local data bus; the data transceiver includes a serial data transmission port, a clock signal output port and at least two chip select signal output ports, and each of the at least two slave devices is respectively connected to the corresponding chip select signal output port, and are both connected to the serial data transmission port and the clock signal output port; the main processor sends data to be written to at least two slave devices to the data transceiver through the local data bus, and receives data read from at least two slave devices from the data transceiver; the data receiver is used to execute the method described in any embodiment of the first aspect above; and the at least two slave devices are respectively used to execute the method described in any embodiment of the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides a serial data transmission device applied to a master device, the device comprising: a first determination module for determining, in response to triggering a data transmission operation, the address of a target storage area corresponding to a data read and write operation to be performed, and determining the data transmission direction; a second determination module for determining, based on the address, a target slave device where the target storage area is located from at least two preset slave devices; a selection module for selecting a target chip select signal output port connected to the target slave device from at least two preset chip select signal output ports; a first setting module for setting the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; a generation module for generating a data transmission instruction in accordance with a preset data transmission format based on the address and data transmission direction; a communication module for sending the data transmission instruction to the target slave device using the serial data transmission port connected to the target slave device, and communicating data with the target slave device using the serial data transmission port.

[0015] In a fifth aspect, an embodiment of the present application provides a serial data transmission device applied to a slave device, the device comprising: a receiving module for receiving a data transmission instruction sent by a master device from a serial data transmission port in response to detecting that the level of a chip select signal input terminal is a first preset level; a third determination module for determining, based on the data transmission instruction, the address of a target storage area corresponding to a data read and write operation to be performed, and determining the data transmission direction; a read and write module for performing data read and write operations on the target storage area based on the address and data transmission direction.

[0016] In a sixth aspect, an embodiment of the present application provides an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the method of any embodiment of the first or second aspect of the present application is implemented.

[0017] In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method of any embodiment of the first or second aspect described above is implemented.

[0018] In an eighth aspect, an embodiment of the present application provides a computer program, which includes a computer-readable code. When the computer-readable code runs on a device, the processor in the device implements a method as in any embodiment of the first aspect or the second aspect of the first aspect mentioned above.

[0019] The serial data transmission method, apparatus, system, electronic device and storage medium provided by the embodiments of the present application are as follows: a master device determines the target slave device to be used for data communication based on the address of the target storage area on the slave device and the data transmission direction, sets the level of the chip select signal output port connected to the target slave device to a first preset level, and then sends a data transmission instruction to the target slave device. In accordance with a serial data communication mode, the data transmission instruction is sent to the target slave device using the serial data transmission port connected to the target slave device, and data communication is performed with the target slave device through the serial data transmission port, thereby associating the address space of the memory of each slave device with the identifier of the slave device. The master device can select the target slave device based on the address of the target storage area to be operated, and other slave devices will not be selected, thereby avoiding conflicts in data read and write addresses when multiple slave devices are of the same type and have the same address space of the memory, thereby improving the accuracy of data reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0023] Figure 1 A flowchart of a serial data transmission method applied to a master device provided in an embodiment of the present application;

[0024] Figure 2 A flowchart of another serial data transmission method applied to a master device provided in an embodiment of the present application;

[0025] Figure 3 A flowchart of another serial data transmission method applied to a master device provided in an embodiment of the present application;

[0026] Figure 4A A timing diagram showing a master device writing data to a slave device according to an embodiment of the present application;

[0027] Figure 4B A timing diagram showing a master device reading data from a slave device according to an embodiment of the present application;

[0028] Figure 5 A flowchart of another serial data transmission method applied to a master device provided in an embodiment of the present application;

[0029] Figure 6 A flowchart of a serial data transmission method applied to a slave device provided in an embodiment of the present application;

[0030] Figure 7 A flowchart of another serial data transmission method applied to a slave device provided in an embodiment of the present application;

[0031] Figure 8 A structural diagram of a serial data transmission system provided in an embodiment of the present application;

[0032] Figure 9 A schematic diagram of a state machine of a data transceiver provided in an embodiment of the present application;

[0033] Figure 10 A schematic diagram of a state machine of a slave device provided in an embodiment of the present application;

[0034] Figure 11 A schematic structural diagram of a serial data transmission device applied to a master device provided in an embodiment of the present application;

[0035] Figure 12 A schematic structural diagram of a serial data transmission device applied to a slave device provided in an embodiment of the present application;

[0036] Figure 13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It is apparent that the described embodiments are only a portion of the embodiments of the present application, rather than all of the embodiments. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions, and numerical values ​​described in these embodiments do not limit the scope of the present application.

[0038] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish between different steps, devices, modules and other objects, and neither represent any specific technical meaning nor indicate the logical order between them.

[0039] It should also be understood that in this embodiment, “a plurality of” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0040] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0041] In addition, the term "and / or" in this application is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the related objects are in an "or" relationship.

[0042] It should also be understood that the description of each embodiment in this application focuses on the differences between the embodiments, and the same or similar aspects can be referenced with each other. For the sake of brevity, they will not be described one by one.

[0043] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0044] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the above-mentioned technologies, methods, and equipment should be considered part of the specification.

[0045] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0046] It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other. To facilitate understanding of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0047] In order to solve the technical problem in the prior art that memory address conflicts are prone to occur when multiple identical slave devices communicate with a master device, the present application provides a serial data transmission method that can avoid memory access conflicts of slave devices and improve the accuracy of data reading and writing.

[0048] Figure 1 A flow chart of a serial data transmission method applied to a master device provided in an embodiment of the present application. The master device in this method is connected to at least two slave devices for communication. The master device can be various types of electronic devices, including but not limited to chips that can perform data processing functions (such as microprocessors, microcontrollers, field programmable gate arrays, digital signal processors, SOC (system on chip, system on chip), etc.), circuit boards and one or more electronic devices. In addition, the execution subject of this method can be hardware or software. When the above-mentioned execution subject is hardware, the execution subject can be one or more of the above-mentioned electronic devices. For example, a single electronic device can execute this method, or a plurality of electronic devices can cooperate with each other to execute this method. When the above-mentioned execution subject is software, this method can be implemented as multiple software or software modules, or as a single software or software module. It is not specifically limited here.

[0049] like Figure 1 As shown, the method specifically includes:

[0050] Step 101 : In response to triggering a data transmission operation, determining the address of a target storage area corresponding to a data read / write operation to be performed, and determining a data transmission direction.

[0051] In this embodiment, the data transfer operation can be performed automatically or manually by the user. When the data transfer operation is triggered, the master device needs to read or write data to the slave device. When reading or writing, the master device can automatically generate a data transfer instruction or receive an externally input data transfer instruction. The data transfer instruction can include the address of the target storage area, and the master device can obtain the address of the target storage area from the data transfer instruction. The target storage area is a storage area included in the memory on one of the at least two slave devices. The data transfer direction can be read or write, and the data transfer direction is determined by the data transfer instruction, that is, the data transfer instruction includes an identifier indicating the data transfer direction.

[0052] In one example, when data needs to be written to a target storage area, the user can manually input the address of the target storage area, or the master device can automatically determine the address of the target storage area corresponding to the data to be written based on the data writing order, and then generate a data transfer instruction containing the address of the target storage area and indicating the execution of the data write operation. When data needs to be read from the target storage area, the user can manually input the address of the target storage area, or the master device can determine the address of the target storage area where the data to be read is located based on the attributes of the data to be read (such as name, type, etc.), and then generate a data transfer instruction containing the address of the target storage area and indicating the execution of the data read operation.

[0053] Step 102 : Based on the address, determine the target slave device where the target storage area is located from at least two preset slave devices.

[0054] In this embodiment, the address may include an identifier of the slave device, and the target slave device where the target storage area is located may be determined based on the identifier. As an example, a designated data bit of the address may be the identifier of the slave device.

[0055] Step 103 : Selecting a target chip select signal output port connected to a target slave device from at least two preset chip select signal output ports.

[0056] In this embodiment, each of the at least two chip select signal output ports is connected to a slave device respectively, and the master device can determine the target chip select signal output port corresponding to the target slave device based on the preset correspondence between the chip select signal output port and the slave device.

[0057] Step 104 : setting the level of the target chip select signal output port to a first preset level, so that the target slave device is in a communication state.

[0058] In this embodiment, the first preset level is a level that enables the slave device to activate a data read and write function. For example, the first preset level is a low level.

[0059] Step 105 : Generate a data transmission instruction based on the address and the data transmission direction in accordance with a preset data transmission format.

[0060] In this embodiment, the data transmission format is a predefined format that the master device and the slave device need to follow when communicating. For example, the data transmission instruction includes a frame header, a read / write address, a read / write indication signal, and the like.

[0061] Step 106 : Sending a data transmission instruction to the target slave device by using the serial data transmission port connected to the target slave device, and performing data communication with the target slave device by using the serial data transmission port.

[0062] In this embodiment, the master device can convert the data transmission instruction and the data to be sent into a serial communication signal and send it from the serial data transmission port to the target slave device, or receive the serial signal sent by the target slave device from the serial data transmission port and convert it into read data.

[0063] The embodiment of the present application provides a serial data transmission method applied to a master device, in which the master device determines the target slave device to be used for data communication based on the address of the target storage area on the slave device and the data transmission direction, sets the level of the chip select signal output port connected to the target slave device to a first preset level, and then sends a data transmission instruction to the target slave device. In accordance with a serial data communication mode, the data transmission instruction is sent to the target slave device using the serial data transmission port connected to the target slave device, and data communication is performed with the target slave device through the serial data transmission port, thereby associating the address space of the memory of each slave device with the identifier of the slave device. The master device can select the target slave device based on the address of the target storage area to be operated, and other slave devices will not be selected, thereby avoiding conflicts in data read and write addresses when multiple slave devices are of the same type and have the same address space of the memory, thereby improving the accuracy of data reading and writing.

[0064] In some optional implementations of this embodiment, such as Figure 2 As shown, step 102 includes:

[0065] Step 1021: extract the data at the preset data bit from the address as chip selection data.

[0066] The preset data bits are usually the data on the highest N bits of the address. For example, if the storage space address of the slave device is 12 bits and the address bus of the master device is 16 bits, the highest 4 bits are the preset data bits and the lowest 12 bits are the storage address of the data on the slave device.

[0067] Step 1022: Determine, from at least two slave devices, a slave device corresponding to the chip select data as a target slave device.

[0068] If the number of slave devices is 8, and the address is represented by hexadecimal data addr[15:0], for the master device, the address space of slave device 1 is 16'h0000~16'h0FFF, the address space of slave device 2 is 16'h1000~16'h1FFF, and so on. The address space of slave device 8 is 16'h7000~16'h7FFF. Then the master device will decode addr[15:12]. When addr[15:12] = 4'h0, slave device 1 is the target slave device to be communicated. When addr[15:12] = 4'h1, slave device 2 is the target slave device to be communicated. And so on. When addr[15:12] = 4'h7, slave device 7 is the target slave device to be communicated.

[0069] This embodiment combines the data storage address and device identification of the slave device by setting some data bits in the address of the target storage area as chip select data and the remaining data bits as the actual address. For the master device, the target storage area in the target slave device can be directly accessed according to the address on the address bus, thereby improving the accuracy and efficiency of data reading and writing with multiple slave devices.

[0070] In some optional implementations of this embodiment, such as Figure 3 As shown, step 105 includes:

[0071] Step 1051: If the data transmission direction is a data writing direction, obtain the data to be written.

[0072] Specifically, the master device may obtain the data to be written from the data bus.

[0073] Step 1052: Generate a write data instruction in a first preset format based on the address.

[0074] Specifically, the write data instruction may include a frame header, a write address, a write instruction, and other components. Figure 4A As shown, it shows a timing diagram of the master device writing data to the slave device. Figure 4A In the example, clk is the clock signal between the master device and the slave device. cs_n is the chip select signal output from the chip select signal output port, and the low level (first preset level) is valid. signal is the signal transmitted on the serial data transmission port. Figure 4A As shown, the frame header of the write data instruction is binary data "01", and includes a read / write address (a write address in this embodiment) and a write indication, and the write indication is a low level.

[0075] like Figure 3 As shown, step 106 includes:

[0076] Step 1061: Send a write data instruction and data to be written to the target slave device using the serial data transmission port.

[0077] like Figure 4A As shown in the signal, the master device first sends a frame header to the target slave device, then sends the read / write address and write indication, and then sends the binary "00" by default, and then sends the write data.

[0078] This embodiment sets a write data instruction in a first preset format. When the data transmission direction is write data, the write data instruction and the data to be written are sent to the target slave device based on the first preset format in a serial data transmission mode. This achieves accurate determination of the data transmission direction and accurate writing of data to the target slave device when writing data to the target slave device, thereby improving the accuracy of data reading and writing.

[0079] In some optional implementations of this embodiment, such as Figure 5 As shown, step 105 includes:

[0080] Step 1053 : If the data transmission direction is a data read direction, a read data instruction in a second preset format is generated based on the address.

[0081] Specifically, the read data instruction may include a frame header, a read address, a read instruction, and other components. Figure 4B As shown, it shows a timing diagram of a master device reading data from a slave device. Figure 4B In the example, clk is the clock signal between the master device and the slave device. cs_n is the chip select signal output from the chip select signal output port, and the low level (first preset level) is valid. signal is the signal transmitted on the serial data transmission port. Figure 4B As shown, the frame header of the read data instruction is binary data "01", and includes a read / write address (a write address in this embodiment) and a read indication, and the read indication is a high level.

[0082] Step 106 includes:

[0083] Step 1062: Send a read data instruction to the target slave device using the serial data transmission port.

[0084] like Figure 4B As shown in the signal, the master device first sends a frame header to the target slave device, then sends the read and write address and read indication, and then waits for the response signal sent by the target slave device.

[0085] Step 1063 : In response to receiving the response signal sent by the target slave device, receive the read data from the serial data transmission port.

[0086] like Figure 4B As shown in the signal, after the target slave device receives the read data instruction, it sends a response signal to the master device to notify the master device to receive the data, and then sends the data read from the target storage area to the master device.

[0087] This embodiment sets a read data instruction of a second preset format. When the data transmission direction is read data, based on the second preset format, a write data instruction is sent to the target slave device in a serial data transmission mode, and then the read data is received. This achieves accurate determination of the data transmission direction when reading data from the target slave device, and accurate reading of data from the target slave device, thereby improving the accuracy of data reading and writing.

[0088] In some optional implementations of this embodiment, after step 106, the method further includes:

[0089] In response to the completion of data transmission, the level of the target chip select signal output port is set to a second level.

[0090] As an example, the first preset level is a low level, and the second preset level is a high level.

[0091] This embodiment sets the level of the target chip select signal output port to the second level when data transmission is completed, so that the target slave device can no longer communicate with the master device, and waits for the next data communication to be performed and executes the method of the embodiment of the present application again, thereby avoiding data conflicts between multiple slave devices and improving the accuracy of data communication.

[0092] Figure 6 A flow chart of a serial data transmission method applied to a slave device provided in an embodiment of the present application. The slave device in this method is connected to the master device for communication, and the slave device can be various types of electronic devices, including but not limited to chips (such as microprocessors, microcontrollers, field programmable gate arrays, digital signal processors, SOCs, etc.) that can perform data processing functions, circuit boards, and one or more electronic devices. In addition, the execution subject of this method can be hardware or software. When the above-mentioned execution subject is hardware, the execution subject can be one or more of the above-mentioned electronic devices. For example, a single electronic device can execute this method, or a plurality of electronic devices can cooperate with each other to execute this method. When the above-mentioned execution subject is software, this method can be implemented as multiple software or software modules, or as a single software or software module. It is not specifically limited here.

[0093] like Figure 6 As shown, the method specifically includes:

[0094] Step 601: In response to detecting that the level of a chip select signal input terminal is a first preset level, receiving a data transmission instruction sent by a master device from a serial data transmission port.

[0095] In this embodiment, a chip select signal input terminal of the slave device is connected to a chip select signal output terminal of the master device, and a serial data transmission port of the slave device is connected to a serial data transmission port of the master device. When the level at the chip select signal input terminal is a first preset level (e.g., a low level), the data read and write function of the slave device is activated, and the slave device can receive a data transmission instruction from the serial data transmission port. For a description of the data transmission instruction, reference can be made to the above-mentioned embodiment corresponding to the master device, and no further details are given here.

[0096] Step 602 : Based on the data transmission instruction, determine the address of the target storage area corresponding to the data read / write operation to be performed, and determine the data transmission direction.

[0097] In this embodiment, the data transmission instruction may include the address of the target storage area. The slave device may parse the data transmission instruction to obtain the address and determine the data transmission direction according to the read / write indication signal included in the data transmission instruction.

[0098] Step 603: Perform data read and write operations on the target storage area based on the address and data transmission direction.

[0099] In this embodiment, the read and write operations may include receiving data to be written from the serial data transmission port and writing the data into the target storage area, or may include reading data from the target storage area according to the address of the target storage area and sending the data to the master device.

[0100] The embodiment of the present application provides a serial data transmission method applied to a slave device. When the slave device detects that the level of the chip select signal input terminal is a first preset level, it receives a data transmission instruction sent by the master device from the serial data transmission port. Based on the data transmission instruction, the address of the target storage area corresponding to the data read and write operation to be performed is determined, as well as the data transmission direction. Based on the address and the data transmission direction, the data read and write operation is performed on the target storage area. This enables the master device to accurately control the read and write enable of the slave device and accurately determine the storage area targeted by the data read and write operation. Therefore, when the master device communicates with multiple slave devices, the slave devices can be accurately controlled to avoid conflicts caused by data reading and writing between each other, thereby improving the accuracy of data reading and writing.

[0101] In some optional implementations of this embodiment, such as Figure 7 As shown, step 603 includes:

[0102] Step 6031: If the data transmission direction is a write data direction, the data to be written sent by the master device is received from the serial data transmission port.

[0103] Step 6032: Write the data to be written into the target storage area according to the address.

[0104] like Figure 4AAs shown, after the master device sends the data transmission instruction, the slave device enters the receiving state according to the write instruction included in the data transmission instruction, and parses the address of the target storage area from the data transmission instruction, and then receives the above-mentioned data to be written and stores the received data into the target storage area.

[0105] This embodiment parses the data transmission instruction. When the master device writes data to the slave device, the data to be written is stored in the target storage area according to the parsed address, thereby enabling the slave device to accurately determine the data transmission direction and accurately write data to the target storage area, thereby improving the accuracy of data reading and writing.

[0106] In some optional implementations of this embodiment, such as Figure 7 As shown, step 603 includes:

[0107] Step 6033: If the data transmission direction is the data read direction, data is read from the target storage area according to the address.

[0108] Step 6034: Send a response signal to the master device and send the read data to the master device.

[0109] like Figure 4B As shown, after the master device sends the data transmission instruction, the slave device enters the sending state according to the read instruction included in the data transmission instruction, and then sends a response signal to the master device. The response signal is a high-level pulse signal, and then the address of the target storage area is parsed from the data transmission instruction. The stored data can then be read and sent to the master device.

[0110] This embodiment parses the data transmission instruction. When the master device reads data from the slave device, the data is read from the target storage area according to the parsed address and sent to the master device, thereby enabling the slave device to accurately determine the data transmission direction and accurately read data from the target storage area, thereby improving the accuracy of data reading and writing.

[0111] Figure 8 This is a structural diagram of a serial data transmission system provided in an embodiment of the present application. Figure 8 As shown, the system includes a master device 801 and at least two slave devices 802. The master device 801 includes a main processor 8011 and a data transceiver 8012. The main processor 8011 and the data transceiver 8012 are connected via a local data bus.

[0112] Among them, the main processor 8011 (CPU) is used to perform various data processing operations using data read from the slave device, or write generated data to the slave device. The data transceiver 8012 can be implemented based on various devices, such as FPGAs, single-chip microcomputers, etc. The main processor 8011 and the data transceiver 8012 are connected via a local data bus (Localbus). The local data bus may include address lines and data lines. The address line width is generally greater than the data width of the storage address space of the slave device, so that the identifier of the slave device can be set in a specific data bit in the address line. For example, if the address line width is 16 bits and the storage space width of the slave device is 12 bits, the upper 4 bits of the address line can be set as the identifier of the slave device. Therefore, when communicating with the slave device, the target slave device and the target storage area on the target slave device can be determined based on an address.

[0113] In this embodiment, the data transceiver 8012 includes a serial data transmission port, a clock signal output port and at least two chip select signal output ports. Each of the at least two slave devices 802 is connected to the corresponding chip select signal output port, and is also connected to the serial data transmission port and the clock signal output port.

[0114] like Figure 8 As shown in the figure, signal represents the serial data transmission port. The line connected to it is the serial data bus, and each of the K slave devices is connected to the serial data bus. clk represents the clock signal output port, and each of the K slave devices is connected to the clock signal output port. cs_n[K-1:0] represents the K chip select signal output ports, each of which is connected to a slave device.

[0115] In this embodiment, the main processor 8011 sends data to be written into at least two slave devices 802 to the data transceiver 8012 via the local data bus, and receives data read from at least two slave devices 802 from the data transceiver 8012 .

[0116] In this embodiment, the data receiver is used to execute the serial data transmission method applied to the master device 801, that is, to receive the address sent by the master processor 8011 from the local data bus and to communicate data with the slave device according to the address.

[0117] In this embodiment, at least two slave devices 802 are respectively used to execute the above serial data transmission method applied to slave devices, that is, receive the data transmission instruction sent by the above data transceiver 8012 and perform data communication with the master device 801 according to the data transmission instruction.

[0118] Optionally, for the data transceiver, five states can be defined: idle, fixed format transmission, data transmission, response detection and data recovery, such as Figure 9As shown in FIG, it shows a schematic diagram of a state machine formed according to the above states. The transition process between each state is as follows:

[0119] 1. Idle state: This state is entered after power-on initialization is completed or a read / write operation is completed. In this state, cs_n and signal send all 1s, and clk sends the clock normally. When the data read / write address on the local bus is detected, the fixed format state is entered.

[0120] 2. Fixed format transmission state: In this state, cs_n pulls the corresponding chip select signal output port low according to the address decoding results. Simultaneously, signal transmits the frame header, read / write address, and read / write instruction data in the corresponding format. When the transmission is completed, if it is a write operation, it enters the data transmission state; if it is a read operation, it enters the response detection state.

[0121] 3. Data transmission state: In this state, the signal sends read and write data in the corresponding format. When the read and write data are sent, it waits for the local bus chip select to end, that is, when cs_n = 1, and enters the idle state.

[0122] 4. Response detection state: In this state, the signal port is set to receive, and the signal data is parsed to determine whether it is a valid response. When a valid response is detected, it enters the data recovery state.

[0123] 5. Data recovery state: In this state, the signal data is parsed and sent back to the main processor in the localbus format. When the localbus chip select ends, that is, when cs_n=1, it enters the idle state.

[0124] For slave devices, five states can be defined: idle, frame header detection, address recovery, read / write, data recovery, and data reply. Figure 10 As shown, it shows a schematic diagram of a state machine formed according to the above states.

[0125] The transition process between states is as follows:

[0126] 1. Idle state: This state is entered after power-on initialization is completed or a read / write operation is completed. In this state, the signal port is set to receive. When cs_n = 0 is detected, the frame header detection state is entered.

[0127] 2. Frame header detection state: In this state, the signal data is parsed to determine whether it is a valid frame header. When a valid frame header is detected, the address recovery and read / write state are entered.

[0128] 3. Restore address and read / write state: In this state, the read / write address and read / write indication in the signal are parsed, the read / write address is stored in the addr_reg register (e.g., the address register defined by the slave device FPGA), and the read / write indication is stored in the rw_reg register (e.g., the read / write indication register defined by the slave device FPGA). When the parsing is complete, if it is a write operation, the data recovery state is entered; if it is a read operation, the data reply state is entered.

[0129] 4. Data recovery state: In this state, the write data in the signal is parsed and stored in wdata_reg (for example, the write data register defined by the slave FPGA). Then, the write operation is completed according to the addr_reg and rw_reg information. When the write data parsing is completed, the idle state is entered after waiting for cs_n = 1.

[0130] 5. Reply data state: In this state, the signal port is set to send and sends T clk cycles of 0 (T>=0, determined by the delay of the slave device preparing stable read data). When the read data is ready, the response signal and read data are sent in the corresponding format of the signal. When the response indication and read data are sent, wait for cs_n=1 and then enter the idle state.

[0131] The serial data transmission system provided by the embodiment of the present application sets a serial data transmission port, a clock signal output port and multiple chip select signal output ports between a master device and multiple slave devices. The master device and the slave device respectively execute the above-mentioned serial data transmission method applied to the master device and the above-mentioned serial data transmission method applied to the slave device, thereby associating the address space of the memory of each slave device with the identifier of the slave device. The master device can select the target slave device according to the address of the target storage area to be operated, and other slave devices will not be selected, thereby avoiding conflicts in data read and write addresses when multiple slave devices are of the same type and have the same address space of the memory, thereby improving the accuracy of data reading and writing.

[0132] Figure 11A schematic structural diagram of a serial data transmission device for a master device provided in an embodiment of the present application. Specifically, the device comprises: a first determination module 1101 for determining, in response to triggering a data transmission operation, the address of a target storage area corresponding to a data read / write operation to be performed, and determining the data transmission direction; a second determination module 1102 for determining, based on the address, a target slave device where the target storage area is located from at least two preset slave devices; a selection module 1103 for selecting, from at least two preset chip select signal output ports, a target chip select signal output port connected to the target slave device; a first setting module 1104 for setting the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; a generation module 1105 for generating a data transmission instruction in accordance with a preset data transmission format based on the address and the data transmission direction; and a communication module 1106 for sending the data transmission instruction to the target slave device using the serial data transmission port connected to the target slave device, and performing data communication with the target slave device using the serial data transmission port.

[0133] In one possible implementation, the second determination module includes: an extraction unit for extracting data on a preset data bit from the address as chip select data; a determination unit for determining a slave device corresponding to the chip select data as a target slave device from at least two slave devices.

[0134] In one possible embodiment, the generation module includes: an acquisition unit, used to acquire the data to be written if the data transmission direction is a write data direction; a first generation unit, used to generate a write data instruction in a first preset format based on the address; the communication module is further used for: a first sending unit, used to use the serial data transmission port to send the write data instruction and the data to be written to the target slave device.

[0135] In one possible embodiment, the generation module includes: a second generation unit, which is used to generate a read data instruction in a second preset format based on the address if the data transmission direction is a read data direction; the communication module includes: a second sending unit, which is used to send a read data instruction to the target slave device using a serial data transmission port; and a first receiving unit, which is used to receive read data from the serial data transmission port in response to receiving a response signal sent by the target slave device.

[0136] In a possible implementation, the device further includes: a second setting module, configured to set the level of the target chip select signal output port to a second level in response to completion of data transmission.

[0137] The serial data transmission device provided in this embodiment and applied to the master device may be as follows: Figure 11The serial data transmission device applied to the master device shown in the figure can execute all the steps of the above serial data transmission methods applied to the master device, thereby achieving the technical effects of the above serial data transmission methods applied to the master device. Please refer to the above related description for details. For the sake of brevity, it will not be repeated here.

[0138] Figure 12 This is a schematic diagram of the structure of a serial data transmission device for a slave device provided in an embodiment of the present application. The device specifically comprises: a receiving module 1201 for receiving a data transmission instruction sent by a master device from a serial data transmission port in response to detecting that the level of a chip select signal input terminal is a first preset level; a third determination module 1202 for determining, based on the data transmission instruction, the address of a target storage area corresponding to a data read / write operation to be performed, and determining the data transmission direction; and a read / write module 1203 for performing data read / write operations on the target storage area based on the address and data transmission direction.

[0139] In one possible embodiment, the read / write module includes: a second receiving unit, used to receive the data to be written sent by the master device from the serial data transmission port if the data transmission direction is the write data direction; and a writing unit, used to write the data to be written into the target storage area according to the address.

[0140] In one possible embodiment, the read / write module includes: a reading unit, which is used to read data from the target storage area according to the address if the data transmission direction is the read data direction; and a third sending unit, which is used to send a response signal to the master device and send the read data to the master device.

[0141] The serial data transmission device provided in this embodiment and applied to the slave device may be as follows: Figure 12 The serial data transmission device applied to the slave device shown in the figure can execute all the steps of the above serial data transmission methods applied to the slave device, thereby achieving the technical effects of the above serial data transmission methods applied to the slave device. Please refer to the above related description for details. For the sake of brevity, it will not be repeated here.

[0142] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 13 The electronic device 1300 shown includes: at least one processor 1301, a memory 1302, at least one network interface 1304 and another user interface 1303. The various components in the electronic device 1300 are coupled together via a bus system 1305. It is understood that the bus system 1305 is used to achieve connection and communication between these components. In addition to including a data bus, the bus system 1305 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 1305 is not shown in FIG. Figure 13Various buses are labeled as bus system 1305.

[0143] The user interface 1303 may include a display, a keyboard, or a pointing device (eg, a mouse, a trackball, a touchpad, or a touch screen).

[0144] It is understood that the memory 1302 in the embodiment of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDRSDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus random access memory (DRRAM). The memory 1302 described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0145] In some embodiments, the memory 1302 stores the following elements, executable units, or data structures, or a subset thereof, or an extended set thereof: an operating system 13021 and application programs 13022 .

[0146] Among them, the operating system 13021 includes various system programs, such as the framework layer, core library layer, and driver layer, which are used to implement various basic services and handle hardware-based tasks. Application programs 13022 include various application programs, such as media players and browsers, which are used to implement various application services. Programs that implement the methods of the embodiments of the present application can be included in application programs 13022.

[0147] In this embodiment, by calling a program or instruction stored in the memory 1302, specifically, a program or instruction stored in the application 13022, the processor 1301 is configured to execute the method steps provided in each embodiment of the serial data transmission method applied to the master device, for example, including:

[0148] In response to triggering a data transmission operation, determining the address of a target storage area corresponding to a data read / write operation to be performed, and determining the data transmission direction; based on the address, determining a target slave device where the target storage area is located from at least two preset slave devices; selecting a target chip select signal output port connected to the target slave device from at least two preset chip select signal output ports; setting the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; based on the address and the data transmission direction, generating a data transmission instruction in accordance with a preset data transmission format; using a serial data transmission port connected to the target slave device, sending the data transmission instruction to the target slave device, and using the serial data transmission port to communicate data with the target slave device.

[0149] In addition, the processor 1301 is also used to execute the method steps provided by each embodiment of the serial data transmission method applied to the master device, for example, including: in response to detecting that the level of the chip select signal input terminal is a first preset level, receiving a data transmission instruction sent by the master device from the serial data transmission port; based on the data transmission instruction, determining the address of the target storage area corresponding to the data read and write operation to be performed, and determining the data transmission direction; based on the address and data transmission direction, performing data read and write operations on the target storage area.

[0150] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 1301. Processor 1301 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 1301 or by software instructions. The above processor 1301 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software units in the decoding processor. The software units can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 1302 , and the processor 1301 reads the information in the memory 1302 and completes the steps of the above method in combination with its hardware.

[0151] It is understood that the embodiments described herein may be implemented using hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, or other electronic units or combinations thereof for performing the above-mentioned functions of the present application.

[0152] For software implementation, the techniques described above can be implemented by a unit that performs the functions described above. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0153] The electronic device provided in this embodiment may be Figure 13 The electronic device shown in can execute all the steps of the above-mentioned serial data transmission method applied to the master device or the serial data transmission method applied to the slave device, thereby achieving the technical effects of the above-mentioned serial data transmission method applied to the master device or the serial data transmission method applied to the slave device. Please refer to the above related description for details. For the sake of brevity, it is not repeated here.

[0154] The present application also provides a storage medium (computer-readable storage medium). The storage medium stores one or more programs. The storage medium may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, hard disk, or solid-state drive; and the memory may also include a combination of the aforementioned types of memory.

[0155] When one or more programs in the storage medium can be executed by one or more processors, the serial data transmission method applied to the master device or the serial data transmission method applied to the slave device is implemented on the electronic device side.

[0156] The processor is configured to execute a program stored in the memory to implement the following steps of a serial data transmission method applied to a master device and executed on the electronic device side:

[0157] In response to triggering a data transmission operation, determining the address of a target storage area corresponding to a data read / write operation to be performed, and determining the data transmission direction; based on the address, determining a target slave device where the target storage area is located from at least two preset slave devices; selecting a target chip select signal output port connected to the target slave device from at least two preset chip select signal output ports; setting the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; based on the address and the data transmission direction, generating a data transmission instruction in accordance with a preset data transmission format; using a serial data transmission port connected to the target slave device, sending the data transmission instruction to the target slave device, and using the serial data transmission port to communicate data with the target slave device.

[0158] In addition, the processor is further configured to execute a program stored in the memory to implement the following steps of a serial data transmission method applied to a slave device and executed on the electronic device side:

[0159] In response to detecting that the level of the chip select signal input terminal is a first preset level, a data transmission instruction sent by a master device is received from the serial data transmission port; based on the data transmission instruction, an address of a target storage area corresponding to the data read and write operation to be performed is determined, and a data transmission direction is determined; based on the address and the data transmission direction, a data read and write operation is performed on the target storage area.

[0160] Professionals should also be further aware that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0161] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0162] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of stated features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0163] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A serial data transmission method applied to a master device, characterized in that: The method comprises: In response to triggering a data transmission operation, determining an address of a target storage area corresponding to a data read or write operation to be performed, and determining a data transmission direction; Based on the address, determining a target slave device where the target storage area is located from at least two preset slave devices; Selecting a target chip select signal output port connected to the target slave device from at least two preset chip select signal output ports; Setting the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; Based on the address and the data transmission direction, generating a data transmission instruction according to a preset data transmission format; The data transmission instruction is sent to the target slave device by using a serial data transmission port connected to the target slave device, and data communication is performed with the target slave device by using the serial data transmission port.

2. The method according to claim 1, characterized in that The step of determining, based on the address, a target slave device where the target storage area is located from at least two preset slave devices includes: Extracting data on a preset data bit from the address as chip selection data; From the at least two slave devices, a slave device corresponding to the chip select data is determined as a target slave device.

3. The method according to claim 1, characterized in that The step of generating a data transmission instruction based on the address and the data transmission direction and in accordance with a preset data transmission format includes: If the data transmission direction is a data writing direction, obtaining data to be written; Based on the address, generating a write data instruction in a first preset format; The method of sending the data transmission instruction to the target slave device by using a serial data transmission port connected to the target slave device, and performing data communication with the target slave device by using the serial data transmission port, comprises: The serial data transmission port is used to send the write data instruction and the data to be written to the target slave device.

4. The method according to claim 1, wherein The step of generating a data transmission instruction based on the address and the data transmission direction and in accordance with a preset data transmission format includes: If the data transmission direction is a data read direction, generating a data read instruction in a second preset format based on the address; The method of sending the data transmission instruction to the target slave device by using a serial data transmission port connected to the target slave device, and performing data communication with the target slave device by using the serial data transmission port, comprises: Using the serial data transmission port, sending the read data instruction to the target slave device; In response to receiving the response signal sent by the target slave device, read-in data is received from the serial data transmission port.

5. The method according to claim 1, wherein After sending the data transmission instruction to the target slave device by using the serial data transmission port connected to the target slave device, and performing data communication with the target slave device by using the serial data transmission port, the method further includes: In response to the completion of data transmission, the level of the target chip select signal output port is set to a second level.

6. A serial data transmission method applied to a slave device, characterized in that: The method comprises: In response to detecting that the level of the chip select signal input terminal is a first preset level, receiving a data transmission instruction sent by the master device from the serial data transmission port; Based on the data transmission instruction, determining the address of the target storage area corresponding to the data read and write operation to be performed, and determining the data transmission direction; Based on the address and the data transmission direction, data reading and writing operations are performed on the target storage area.

7. The method according to claim 6, characterized in that The performing data reading and writing operations on the target storage area based on the address and the data transmission direction includes: If the data transmission direction is a data write direction, receiving the data to be written sent by the master device from the serial data transmission port; The data to be written is written into the target storage area according to the address.

8. The method according to claim 6, characterized in that The performing data reading and writing operations on the target storage area based on the address and the data transmission direction includes: If the data transmission direction is a data reading direction, reading data from the target storage area according to the address; A response signal is sent to the master device, and the read data is sent to the master device.

9. A serial data transmission system, characterized in that: The system includes a master device and at least two slave devices, the master device includes a main processor and a data transceiver, and the main processor and the data transceiver are connected via a local data bus; The data transceiver includes a serial data transmission port, a clock signal output port and at least two chip select signal output ports, each of the at least two slave devices is connected to the corresponding chip select signal output port, and both are connected to the serial data transmission port and the clock signal output port; The main processor sends data to be written to the at least two slave devices to the data transceiver through the local data bus, and receives data read from the at least two slave devices from the data transceiver; The data receiver is used to perform the method according to any one of claims 1 to 5; The at least two slave devices are respectively used to execute the method according to any one of claims 6 to 8.

10. A serial data transmission device applied to a master device, characterized in that: The device comprises: A first determining module is configured to determine, in response to triggering a data transmission operation, an address of a target storage area corresponding to a data read or write operation to be performed, and a data transmission direction; a second determining module, configured to determine, based on the address, a target slave device where the target storage area is located from at least two preset slave devices; A selection module, configured to select a target chip select signal output port connected to the target slave device from at least two preset chip select signal output ports; a first setting module, configured to set the level of the target chip select signal output port to a first preset level so that the target slave device is in a communication state; A generating module, configured to generate a data transmission instruction based on the address and the data transmission direction and in accordance with a preset data transmission format; The communication module is used to send the data transmission instruction to the target slave device by using the serial data transmission port connected to the target slave device, and to perform data communication with the target slave device by using the serial data transmission port.

11. A serial data transmission device for a slave device, characterized in that: The device includes: a receiving module, configured to receive a data transmission instruction sent by a master device from a serial data transmission port in response to detecting that the level of the chip select signal input terminal is a first preset level; A third determining module is configured to determine, based on the data transmission instruction, an address of a target storage area corresponding to a data read / write operation to be performed, and a data transmission direction; A read / write module is configured to perform data read / write operations on the target storage area based on the address and the data transmission direction.

12. An electronic device, characterized in that: include: memory for storing computer programs; A processor is configured to execute a computer program stored in the memory, and when the computer program is executed, the serial data transmission method according to any one of claims 1 to 8 is implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the serial data transmission method according to any one of claims 1 to 8 is implemented.

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