Instruction recognition method and device, electronic equipment and readable storage medium

Abstract

Embodiments of the present application provide an instruction identification method and device, electronic equipment and readable storage medium, the method comprising: inserting a target instruction at a target position in a first source code to obtain a second source code; using a first compiler and a second compiler to compile the second source code to obtain a first compilation result and a second compilation result; obtaining a first instruction sequence recorded by the first compilation result and a second instruction sequence recorded by the second compilation result; the first instruction sequence contains a plurality of first instruction segments, and the second instruction sequence contains a plurality of second instruction segments; performing instruction matching calculation on the first instruction segment in the first instruction sequence and the second instruction segment in the second instruction sequence to obtain a matching result and determine redundant instructions. Embodiments of the present application can identify redundant instructions generated by the compiler, optimize the compilation process of the compiler, and make the compiler generate more efficient compilation results.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to an instruction identification method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] A compiler, also known as a compiling program, is a translation program that translates a source program written in a high-level programming language into an equivalent machine language format target program. The compiler belongs to a translation program implemented by a generative implementation approach. It takes a source program written in a high-level programming language as input and outputs a target program represented in assembly language or machine language. The compiled target program usually needs to go through a running phase to run under the support of a running program, process initial data, and calculate the required calculation results.

[0003] A compiler can not only complete basic translation work, but also can improve program performance through complex analysis and optimization techniques. However, due to the complexity of computer architecture, programming language characteristics and optimization techniques, the code generated by the compiler may still have redundant instructions, resulting in suboptimal program running efficiency. SUMMARY

[0004] In view of the above problems, the present application is proposed to provide an instruction identification method which can automatically identify redundant instructions generated by a compiler, thereby optimizing the compilation process of the compiler, correcting the compilation result of the compiler, generating more refined and efficient compilation results, improving the quality of the compilation result of the compiler, and further improving the program running efficiency.

[0005] Correspondingly, the present application also provides an instruction identification device, electronic equipment and a computer program product to ensure the implementation and application of the above method.

[0006] In a first aspect, the present application discloses an instruction identification method, which comprises:

[0007] inserting a target instruction at a target position in a first source code to obtain a second source code;

[0008] compiling the second source code using a first compiler to obtain a first compilation result, and compiling the second source code using a second compiler to obtain a second compilation result;

[0009] obtain a first instruction sequence for executing the first compilation result record, and a second instruction sequence for executing the second compilation result record; the first instruction sequence comprises a first instruction segment obtained by dividing the position of the target instruction, and the second instruction sequence comprises a second instruction segment obtained by dividing the position of the target instruction;

[0010] perform instruction matching calculation on the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence to obtain a matching result;

[0011] determine redundant instructions in the first instruction sequence or the second instruction sequence according to the matching result.

[0012] In a second aspect, an embodiment of the present application discloses an instruction recognition device, and the device comprises:

[0013] a stubbing module, configured to insert a target instruction at a target position in a first source code to obtain a second source code;

[0014] a compiling module, configured to compile the second source code using a first compiler to obtain a first compilation result, and compile the second source code using a second compiler to obtain a second compilation result;

[0015] an execution record module, configured to obtain a first instruction sequence for executing the first compilation result record, and a second instruction sequence for executing the second compilation result record; the first instruction sequence comprises a first instruction segment obtained by dividing the position of the target instruction, and the second instruction sequence comprises a second instruction segment obtained by dividing the position of the target instruction;

[0016] a matching calculation module, configured to perform instruction matching calculation on the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence to obtain a matching result;

[0017] an instruction recognition module, configured to determine redundant instructions in the first instruction sequence or the second instruction sequence according to the matching result.

[0018] In a third aspect, an embodiment of the present application discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction makes the processor execute the steps of the instruction recognition method in any one of the preceding descriptions.

[0019] In a fourth aspect, an embodiment of the present application discloses a readable storage medium, wherein the readable storage medium stores a program or instructions, and the program or instructions are executed by a processor to implement the instruction identification method according to any one of the preceding aspects.

[0020] In a fifth aspect, an embodiment of the present application discloses a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of the instruction identification method according to any one of the preceding aspects.

[0021] Embodiments of the present application have the following advantages:

[0022] Embodiments of the present application insert target instructions at target positions in the first source code to obtain second source code, and realize the instrumenting of the first source code. The second source code is compiled by using a first compiler and a second compiler respectively to obtain a first compilation result and a second compilation result. A first instruction sequence recorded by executing the first compilation result and a second instruction sequence recorded by executing the second compilation result are acquired respectively. Since the optimization capabilities of different compilers are different, the redundant instructions can be identified by comparing the differences between the first instruction sequence and the second instruction sequence. Further, since the second source code contains the pre-inserted target instructions, the complete instruction sequence can be divided into smaller instruction segments according to the instrumenting points (i.e. the positions of the target instructions) during the running process after the second source code is compiled. Therefore, the identification of whether there are redundant instructions in the instruction segments can be based on the instruction segments, and the accuracy of identifying the redundant instructions can be improved.

[0023] The instruction identification method provided by the embodiments of the present application can be used to identify the redundant instructions generated by the compiler, so that the compilation process of the compiler can be optimized, the compilation result of the compiler can be corrected, the compiler can generate more refined and efficient compilation results, the quality of the compilation result of the compiler can be improved, and the program running efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a step flowchart of an embodiment of the instruction identification method of the present application;

[0025] Figure 2 is a schematic diagram of an overall flow of an embodiment of the present application;

[0026] Figure 3 is a structural block diagram of an embodiment of the instruction identification device of the present application;

[0027] Figure 4 shows exemplary alignment and hint effects of a compilation optimization tool;

[0028] Figure 5 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0030] The terms "first", "second", and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class and do not limit the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects. The term "a plurality of" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0031] Reference Figure 1 , a step flowchart of an instruction recognition method embodiment of the present application is shown, which can include the following steps:

[0032] Step 101, inserting a target instruction at a target position in a first source code to obtain a second source code;

[0033] Step 102, using a first compiler to compile the second source code to obtain a first compilation result, and using a second compiler to compile the second source code to obtain a second compilation result;

[0034] Step 103, respectively acquiring a first instruction sequence for executing the first compilation result record, and a second instruction sequence for executing the second compilation result record; the first instruction sequence contains a first instruction segment obtained by dividing the position of the target instruction, and the second instruction sequence contains a second instruction segment obtained by dividing the position of the target instruction;

[0035] Step 104, performing instruction matching calculation on the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence to obtain a matching result;

[0036] Step 105, determining redundant instructions in the first instruction sequence or the second instruction sequence according to the matching result.

[0037] The instruction identification method provided by the embodiment of the present application can be used to identify the redundant instructions generated by the compiler, thereby optimizing the compiling process of the compiler, correcting the compiling result of the compiler, making the compiler generate more refined and efficient compiling result, improving the quality of the compiling result of the compiler, and further improving the program running efficiency.

[0038] The redundant instruction refers to an instruction which does not provide additional effective calculation in the program execution process, but can complete the same function with fewer instructions.

[0039] In example one, it is assumed that the first instruction segment is as follows:

[0040] ld.w $a1, $a0, 0

[0041] bstrpick.d $a2, $a1, 31, 0

[0042] The first instruction segment includes two instructions. The first instruction "ld.w $a1, $a0, 0" is a signed load instruction, which is used to load the 4-byte data at the address of the register $a0 into the register $a1, and perform signed extension to 64 bits. The second instruction "bstrpick.d $a2, $a1, 31, 0" is a bit extraction instruction, which is used to take out the low 32 bits (from the 0th bit to the 31st bit, 4 bytes) of the data in the register $a1, and perform unsigned extension to 64 bits, and store it in the register $a2.

[0043] It is assumed that the second instruction segment is as follows:

[0044] ld.wu $a2, $a0, 0

[0045] The second instruction segment includes only one instruction. The second instruction segment and the first instruction segment implement the same function. The one instruction in the second instruction segment is an unsigned load instruction, which is used to load the 4-byte data at the address of the register $a0 into the register $a2, and perform unsigned extension to 64 bits.

[0046] In example one, the first instruction segment and the second instruction segment are two different instruction segments executed by different compiling results of the same source code obtained by different compilers. In this example, the function that can be completed by one instruction is implemented by two instructions by the compiler, which increases the number of instructions and the execution period, so the instruction "bstrpick.d $a2, $a1, 31, 0" can be called a redundant instruction, or it is considered that there is a redundant instruction in the first instruction segment.

[0047] In order to identify the redundant instructions generated by the compiler, the embodiment of the present application first inserts a target instruction at a target position in the first source code to obtain a second source code.

[0048] The first source code refers to the source code of a target program. Embodiments of the present application do not limit the type of the target program. The target program can be a program written in various programming languages, such as C, C++, Java, Python, JavaScript, etc. The target program can be a program for different application fields, including but not limited to an operating system kernel program, a graphics rendering program, a data processing and analysis program, a network communication program, a game program, a hardware test program, etc. The target program can be a program running on different platforms, such as a desktop operating system (Windows, Mac OS, Linux, etc.), a mobile operating system (Android, iOS, etc.), an embedded system, and a cloud computing platform, etc. No matter whether the target program is for scientific computing, business application, artificial intelligence, or any other field, the present instruction identification method can be applied.

[0049] The purpose of inserting the target instruction at the target position in the first source code in the embodiments of the present application is to instrument the first source code to obtain the second source code, so that after the second source code is compiled, the instruction sequence executed in the running process can be divided into a plurality of instruction segments according to the instrumentation points (i.e. the positions of the target instructions). Thus, based on the instruction segments, it can be determined whether there is a redundant instruction in each instruction segment, and the accuracy of identifying the redundant instruction can be improved.

[0050] Optionally, the target instruction can be an instruction already existing in an existing instruction set and will not cause changes to the architecture visible state. For example, the target instruction can include a No-Operation (NOP) instruction. The NOP instruction will not change the state of any register, memory, or flag bit after execution.

[0051] The embodiments of the present application do not limit the position (target position) of inserting the target instruction in the first source code. The target position can be any position in the first source code. Further, the embodiments of the present application also do not limit the number of target instructions inserted. For example, the number of target instructions inserted can be determined according to the number of target positions determined.

[0052] In an optional embodiment of the present application, inserting the target instruction at the target position in the first source code to obtain the second source code can include:

[0053] Step S11, converting the first source code into an abstract syntax tree;

[0054] Step S12, traversing each node of the abstract syntax tree, and determining a target position in the node;

[0055] Step S13, inserting a target instruction at each target position to obtain a processed abstract syntax tree;

[0056] Step S14, converting the processed abstract syntax tree into a second source code.

[0057] To facilitate determining the target positions suitable for inserting the target instructions in the first source code, the first source code can be converted into an abstract syntax tree (AST) using a syntax analysis tool.

[0058] The abstract syntax tree is a tree structure representation of the source code, abstracting away specific syntax details (such as parentheses, semicolons, etc.), and only retaining the structure and semantic information of the program. Each node of the abstract syntax tree represents a syntax structure (such as an expression, a statement, a declaration, etc.).

[0059] The nodes of the abstract syntax tree are traversed, and the target positions are determined in the nodes. A target instruction is inserted at each target position to obtain a processed abstract syntax tree. Finally, the processed abstract syntax tree is converted into a source code (a second source code).

[0060] In an optional embodiment of the present application, the traversing of the nodes of the abstract syntax tree and the determination of the target positions in the nodes can include:

[0061] The nodes of the abstract syntax tree are traversed, and a target node whose node type is a statement block is identified. The starting position of the target node is determined as a target position.

[0062] The statement block (block) or code block or composite statement refers to a sequence of statements enclosed by a pair of explicit or implicit boundary symbols (such as {}), which are executed in sequence. The block is a basic structured unit of the program, which is used to combine multiple statements and can introduce a new scope.

[0063] The variables declared in the statement block (block) usually have a local scope. For example, the following statement block in C / C++ language: { int x;}, the variable x is only valid within the statement block. The statements in the statement block are executed in sequence, and the whole block is regarded as a logical unit.

[0064] Illustratively, the statement block (block) can include a function body, a loop body, or a conditional branch, etc. The insertion point (target position) can be located at the starting position of each statement block (Block), such as the starting position of the loop body.

[0065] In an example, the first source code includes the following code segment:

[0066] int sum(int arr, int n) {

[0067] int s = 0;

[0068] for (int i=0; i<n; i++) {

[0069] s += arr[i];

[0070] }

[0071] return s;

[0072] }

[0073] The first source code contains two loop bodies, and a target instruction can be inserted at the start of each loop body, such as a target instruction denoted as __MARK(i), and the second source code includes the following code segment:

[0074] int sum(int arr, int n) {

[0075] __MARK(1);

[0076] int s = 0;

[0077] for (int i=0; i<n; i++) {

[0078] __MARK(2);

[0079] s += arr[i];

[0080] }

[0081] return s;

[0082] }

[0083] In the example, a target instruction “__MARK(1)” is inserted at the start of the first loop body, and a target instruction “__MARK(2)” is inserted at the start of the second loop body.

[0084] In an embodiment of the present application, the target position for inserting a target instruction is not limited to the start of a statement block (such as a loop body), and can be any position. In an optional embodiment of the present application, the step of determining a target position in a node of the abstract syntax tree can include:

[0085] Traverse each node of the abstract syntax tree, identify a target sequence point in the node, determine the position of the target sequence point as a target position; the target sequence point satisfies the following conditions: all expressions before the target sequence point have been evaluated, and all side effects have been generated, and all side effects after the target sequence point have not been generated; the side effects include modification operations on the environment state.

[0086] Wherein, the side effect is an additional impact generated during program execution (not only the return value), for example, the side effect includes modification operations on the environment state. Illustratively, the side effect can include but is not limited to any one of the following: modifying the value of a variable; modifying a global / static variable; performing an I / O (input / output) operation; calling a side-effect function; modifying the data pointed to by a pointer.

[0087] The target sequence point is a specific position in program execution, which can guarantee that all side effects have been generated before, and all side effects have not been generated after, thereby guaranteeing that the program can generate consistent side effects after being compiled and running to the insertion point, and further guaranteeing the correctness of identifying redundant instructions.

[0088] Illustratively, the target sequence point satisfying the above conditions can include but is not limited to any one of the following: the end of a statement (such as encountering ";"); after the first operand of a logical operator (such as &&, ||); at a function call (after parameter evaluation and before entering the function body).

[0089] The embodiment of the application inserts a target instruction at the position of the target sequence point, which can guarantee that the side effects (such as variable modification, I / O operation, etc.) of all expressions before the insertion point have taken effect, can provide consistent snapshots (such as before and after a function call, when a statement is executed), will not introduce additional undefined behaviors, and provides a basis for correctly identifying redundant instructions subsequently.

[0090] Next, the second source code is compiled using two different compilers respectively to obtain different compilation results. For example, the second source code is compiled using a first compiler to obtain a first compilation result; and the second source code is compiled using a second compiler to obtain a second compilation result.

[0091] The compilation result refers to a binary executable file, which contains instructions (machine code) that can be executed by a CPU.

[0092] Since different compilers may have different optimization capabilities, register allocation strategies, and instruction selection modes, different compilers may generate different compilation results when compiling the same source code (second source code). The first compilation result compiled by the first compiler and the second compilation result compiled by the second compiler are compared in the embodiment of the present application, and redundant instructions generated by the first compiler or the second compiler can be identified.

[0093] Further, to obtain more accurate comparison analysis results, the same target architecture (that is, the platform on which the code generated by compilation runs) can be selected when the second source code is compiled by the first compiler and the second compiler.

[0094] In Example Two, for the same second source code, the first compiler (such as compiler A, which is assumed to be a GCC compiler) is used for compilation to obtain the first compilation result (such as binary file A); the second compiler (such as compiler B, which is assumed to be a Clang compiler) is used for compilation to obtain the second compilation result (such as binary file B); and the target architecture is ensured to be the same (assumed to be x86-64); that is, binary file A and binary file B can both run on a platform with a target architecture of x86-64.

[0095] In one example, it is assumed that the Clang compiler generates two instructions (such as the two instructions in the first instruction segment shown in Example One) to implement a certain function, and the GCC compiler generates one instruction (such as the one instruction in the second instruction segment shown in Example One) to implement the same function. By comparing the instruction segments generated by the two compilers for the same function, it can be identified that the "bstrpick.d" instruction in the first instruction segment generated by the Clang compiler is a redundant instruction, and the mode of generating instructions for implementing the function during the compilation of the Clang compiler can be optimized to improve the quality of the compilation result of the Clang compiler.

[0096] Further, since the compiler can only be based on static code analysis during compilation and cannot obtain runtime data (such as input values, real tendencies of branch prediction, memory access patterns, etc.), comparison analysis based on static compilation results cannot completely predict the runtime behavior of the program, which may result in inaccurate identification of redundant instructions.

[0097] Based on the defects of the static analysis method, the embodiment of the present application identifies the redundant instructions that may exist in the program by dynamically recording the instruction sequence executed during the program runtime to improve the identification accuracy.

[0098] Specifically, after compiling the second source code using a first compiler to obtain a first compilation result and compiling the second source code using a second compiler to obtain a second compilation result, the first compilation result and the second compilation result are executed respectively. In the process of executing the first compilation result, a first instruction sequence of execution is recorded, and in the process of executing the second compilation result, a second instruction sequence of execution is recorded. The first instruction sequence comprises first instruction segments obtained by dividing the first instruction sequence at positions of the target instructions, and the second instruction sequence comprises second instruction segments obtained by dividing the second instruction sequence at positions of the target instructions. By comparing the first instruction segments in the first instruction sequence with the second instruction segments in the second instruction sequence, redundant instructions in the first instruction segments or the second instruction segments can be identified.

[0099] In an optional embodiment of the present application, the first instruction sequence of execution of the first compilation result record and the second instruction sequence of execution of the second compilation result record are obtained respectively, which can include:

[0100] The first compilation result and the second compilation result are executed respectively on a host computer of the same architecture using a binary translator, which records the first instruction sequence of execution in the process of executing the first compilation result and records the second instruction sequence of execution in the process of executing the second compilation result.

[0101] The embodiments of the present application identify redundant instructions generated by the compiler by recording the instruction sequences of execution of the dynamically running programs (the first compilation result and the second compilation result), and the analysis result is more intuitive and accurate compared with the static analysis method.

[0102] The embodiments of the present application do not limit the way of running the first compilation result and the second compilation result to obtain the first instruction sequence of execution and the second instruction sequence of execution. The embodiments of the present application preferably use a binary translator to run the first compilation result and the second compilation result respectively. It should be noted that the embodiments of the present application use a binary translator to execute the first compilation result and the second compilation result respectively on a host computer of the same architecture. For example, the same binary translator can be used to execute the first compilation result and the second compilation result respectively on a host computer.

[0103] In specific implementation, a binary translator or other tools can be used to run the first compilation result and the second compilation result respectively, so as to record the first instruction sequence of execution and the second instruction sequence of execution, and divide the instruction sequences of execution into smaller instruction segments according to positions of the insertion points.

[0104] A binary translator can convert binary code of one Instruction Set Architecture (ISA) to binary code of another ISA. Through the binary translator, an application of one ISA can run on another ISA.

[0105] Taking the second example above as an example, assuming that the binary translator used is QEMU, the guest platform is an x86 architecture, and the host platform is an ARM architecture, the process of obtaining the first instruction sequence is as follows:

[0106] Second source code → compiler A → binary file A (such as instructions of an x86 architecture) → executing binary file A on a host (such as an ARM architecture) through a binary translator (such as QEMU) → converting to instructions of an ARM architecture to execute → recording the first instruction sequence executed.

[0107] The process of obtaining the second instruction sequence is as follows:

[0108] Second source code → compiler B → binary file B (such as instructions of an x86 architecture) → executing binary file B on a host (such as an ARM architecture) through a binary translator (such as QEMU) → converting to instructions of an ARM architecture to execute → recording the second instruction sequence executed.

[0109] It can be understood that the target architecture corresponding to the first and second compilation results obtained by compiling the second source code is the source platform architecture (the guest architecture), and the target platform architecture running the first and second compilation results is the host architecture. The embodiment of the present application does not limit the target architecture corresponding to the compilation result, nor does it limit the host architecture. The target architecture corresponding to the compilation result and the host architecture can be the same architecture or different architectures.

[0110] In the embodiment of the present application, the binary translator is used as a tool for executing the first and second compilation results and recording the instruction sequence executed during the execution process. Only the functions of executing the compilation result and recording the instruction sequence executed are required, and the function of cross-ISA translation of the binary translator can not be used. Therefore, the target architecture corresponding to the compilation result and the host architecture can be the same architecture. The binary translator is used as a tool for viewing, rewriting, and modifying binary code, for dynamic instruction sequence collection, for identifying and marking the position of a probe instruction, and for dividing instruction sequence segments.

[0111] The embodiment of the present application can use the same binary translator to execute the first compilation result and the second compilation result in sequence, the binary translator records the first instruction sequence executed in the process of executing the first compilation result, and records the second instruction sequence executed in the process of executing the second compilation result, and records the positions of the inserted target instructions in the first instruction sequence and the second instruction sequence respectively. Thus, the first instruction sequence recorded by executing the first compilation result is divided into several first instruction segments by the inserted target instructions, and the second instruction sequence recorded by executing the second compilation result is divided into several second instruction segments by the inserted target instructions.

[0112] When the binary translator translates (the first compilation result or the second compilation result), it decodes each machine code to obtain the corresponding assembly instruction, and compares the assembly code of the preset target instruction with the assembly code, and if they are consistent, it is determined that the target instruction is recognized, and the position of the target instruction is recorded. The binary translator can record each instruction executed, such as recording in a dedicated buffer, and write into a log file after the buffer is full, to obtain the recorded first instruction sequence and second instruction sequence.

[0113] Next, the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence are subjected to instruction matching calculation, and a matching result can be obtained; according to the matching result, redundant instructions in the first instruction sequence or the second instruction sequence are determined.

[0114] Among them, the first instruction segment and the corresponding second instruction segment realize the same function. The instructions in the instruction segments with the same function are compared one by one, and if there is no matching instruction for a certain instruction, the instruction is a redundant instruction.

[0115] Taking example one as an example, the first instruction segment includes two instructions, and the second instruction segment includes one instruction. The first instruction segment and the second instruction segment are subjected to instruction matching calculation, and a matching result is obtained. Through instruction matching calculation, it can be determined that the "ld.w $a1, $a0, 0" instruction in the first instruction segment matches the "ld.wu $a2, $a0, 0" instruction in the second instruction segment, and it is determined that the "bstrpick.d $a2, $a1, 31, 0" instruction in the first instruction segment does not have a matching instruction in the second instruction segment, and thus it can be determined that the "bstrpick.d $a2, $a1, 31, 0" instruction in the first instruction segment is a redundant instruction.

[0116] Referring to Figure 2 , a whole flowchart of an embodiment of the present application is shown. As Figure 2As shown, first, the first source code is instrumented, and target instructions are inserted at target positions in the first source code to obtain second source code. Then, the second source code is compiled using a first compiler (compiler A) and a second compiler (compiler B) respectively to obtain a first compilation result (binary file A) and a second compilation result (binary file B), and the same target architecture (such as x86 architecture) is compiled. Next, the first compilation result (binary file A) and the second compilation result (binary file B) are executed on a host platform of the same architecture (such as arm architecture) using a binary translator, and a first instruction sequence and a second instruction sequence are recorded respectively. Finally, a first instruction segment in the first instruction sequence and a corresponding second instruction segment in the second instruction sequence are calculated for instruction matching to obtain a matching result; according to the matching result, differences between instructions output by compiler A and compiler B for compiling the same source code can be compared, and then redundant instructions in the first instruction sequence or the second instruction sequence can be determined, and an identification result is output.

[0117] It should be noted that the binary translator can be a dynamic binary translator or a static binary translator, and the embodiments of the present application do not limit this. The functions of recording the instruction sequence and recording the target instruction position can be implemented using the dynamic binary translator and the static binary translator.

[0118] In an optional embodiment of the present application, the instruction matching calculation of the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence to obtain a matching result can include:

[0119] In step S21, for each first instruction segment in the first instruction sequence, a corresponding second instruction segment in the second instruction sequence is determined; the first instruction segment and the corresponding second instruction segment have the same function;

[0120] In step S22, for each first instruction in the first instruction segment, a matching degree is calculated with each second instruction in the corresponding second instruction segment respectively to obtain the matching degree between the each first instruction and the each second instruction.

[0121] The embodiments of the present application do not limit the method of instruction matching calculation of the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence. For example, the sequence alignment method can be used. Sequence alignment is to find the similarity or difference between two or more sequences by arranging them.

[0122] The embodiment of the present application aligns the first instruction sequence and the second instruction sequence by using a sequence alignment method, finds out instruction segments with the same function, and establishes a one-to-one correspondence. That is, for each first instruction segment in the first instruction sequence, a second instruction segment with the same function is found out in the second instruction sequence, and a correspondence between each first instruction segment and second instruction segment is established.

[0123] For the first instruction segment and the second instruction segment with the correspondence, a matching degree is calculated respectively for each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment, and a matching degree between each first instruction and each second instruction can be obtained.

[0124] Taking example one as an example, the first instruction segment in example one is a certain instruction segment in the first instruction sequence. The second instruction segment in example one is a certain instruction segment in the second instruction sequence. The first instruction segment and the second instruction segment in example one implement the same function and have a correspondence. Therefore, a matching degree is calculated respectively for each first instruction in the first instruction segment and each second instruction in the second instruction segment. Specifically, a matching degree is calculated for the first instruction "ld.w $a1, $a0, 0" in the first instruction segment and the instruction "ld.wu $a2, $a0, 0" in the second instruction segment, and a matching degree is calculated for the second instruction "bstrpick.d $a2, $a1, 31, 0" in the first instruction segment and the instruction "ld.wu $a2, $a0, 0" in the second instruction segment.

[0125] It should be noted that in example one, the first instruction segment contains two instructions, and the second instruction segment contains one instruction. Therefore, the matching degrees are calculated respectively for the two instructions in the first instruction segment and the one instruction in the second instruction segment. It can be understood that in specific implementation, the number of instructions contained in the first instruction segment and the second instruction segment can be one or more.

[0126] In an optional embodiment of the present application, the determining of the redundant instruction in the first instruction sequence or the second instruction sequence according to the matching result can include:

[0127] In step S31, for each first instruction segment and the corresponding second instruction segment in the first instruction sequence, a matching first instruction and a matching second instruction in the first instruction segment and the second instruction segment are determined according to the matching degree between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment.

[0128] Step S32, if a certain first instruction in the first instruction segment, there is no second instruction matching the first instruction in the corresponding second instruction segment, it is determined that the first instruction is a redundant instruction; or

[0129] Step S33, if a certain second instruction in the second instruction segment, there is no first instruction matching the second instruction in the corresponding first instruction segment, it is determined that the second instruction is a redundant instruction.

[0130] According to the matching degree between the calculated first instruction and the second instruction, the matching first instruction and the second instruction in the first instruction segment and the second instruction segment can be determined. For example, if the matching degree between a certain first instruction and a certain second instruction exceeds a preset value, it is considered that the first instruction and the second instruction match. The preset value can be set according to actual conditions.

[0131] For example, in Example 1, the matching degree between the first instruction "ld.w $a1, $a0, 0" in the first instruction segment and the second instruction "ld.wu $a2, $a0, 0" in the second instruction segment exceeds the preset value, and it is determined that the first instruction "ld.w $a1, $a0, 0" and the second instruction "ld.wu $a2, $a0, 0" match. Since the first instruction "bstrpick.d $a2, $a1, 31, 0" in the first instruction segment does not have a matching second instruction in the second instruction segment, it is determined that the first instruction "bstrpick.d $a2, $a1, 31, 0" is a redundant instruction.

[0132] In an optional embodiment of the present application, the matching degree between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment can include:

[0133] Step S41, the operation code similarity between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment is calculated; the operation code similarity is calculated according to whether the operation code field is the same and whether the operation code type is the same;

[0134] Step S42, the matching degree between the first instruction and the second instruction is calculated according to the operation code similarity of the first instruction and the second instruction.

[0135] The embodiment of the present application calculates the matching degree between two instructions based on the operation code similarity of the two instructions.

[0136] The operation code (Opcode) of an instruction is a binary coded field in a machine instruction that identifies the type of operation, indicating what operation (such as addition, load, jump, etc.) the processor is to perform.

[0137] The Opcode similarity can be calculated according to whether the Opcode fields are the same and whether the Opcode types are the same. For example, for a certain first instruction and a certain second instruction to be compared, first determine whether the Opcode fields of the two are the same. If the Opcode fields of the two are the same, assuming that the Opcode fields are both add (addition), determine the Opcode similarity to be a first value (such as 0.9), and further determine the matching degree of the first instruction and the second instruction to be the first value (such as 0.9).

[0138] If the Opcode fields of the two are different, further determine whether the Opcode types of the two are the same. If the Opcode types of the two are the same, assuming that the Opcode field of the first instruction is add and the Opcode field of the second instruction is sub (subtraction). Although the Opcode fields are different, the Opcode types are the same, both belonging to arithmetic operation instructions, determine the Opcode similarity to be a second value (such as 0.5), and further determine the matching degree of the first instruction and the second instruction to be the second value (such as 0.5).

[0139] If the Opcode fields of the two are different and the Opcode types are also different, determine the Opcode similarity to be a third value (such as 0.1), and further determine the matching degree of the first instruction and the second instruction to be the third value (such as 0.1).

[0140] When the matching degree of the first instruction and the second instruction exceeds a preset value (such as 0.5), it is considered that the first instruction and the second instruction match; otherwise, it is considered that the first instruction and the second instruction do not match.

[0141] It should be noted that the present embodiment does not limit the first value, the second value, the third value, and the preset value, and does not limit the method of calculating the matching degree between instructions. For example, for two instructions, the matching degree of the two instructions can be calculated based on the Opcode similarity of the two instructions. For another example, the matching degree of the two instructions can also be calculated by weighting the Opcode similarity of the two instructions and the operand similarity of the two instructions.

[0142] Exemplarily, for a certain first instruction and a certain second instruction to be compared, the Opcode similarity can be calculated according to the Opcode fields and the Opcode types of the two instructions; the operand similarity can be calculated according to the operand values, the operand types, and the storage positions of the two instructions; and the matching degree of the first instruction and the second instruction can be calculated by weighting the Opcode similarity and the operand similarity.

[0143] The embodiment of the present application can identify the redundant instructions generated by the compiler using sequence alignment technology. The specific scheme can include three stages: source code instrumentation, instruction sequence collection, and instruction segment alignment. In the source code instrumentation stage, steps 101 and 102 are performed, and the goal is to divide the complete instruction sequence of program execution into smaller granularity instruction segments. In the instruction sequence collection stage, step 103 is performed, and the goal is to detect the redundant instructions in the program by dynamically recording the instruction sequence executed by the program at runtime. In the instruction segment alignment stage, steps 104 and 105 are performed, and the goal is to align the instruction sequences by sequence alignment technology and analyze and identify the possible redundant instructions therein.

[0144] In a specific implementation, the first instruction sequence and the second instruction sequence can be input into a preset tool, and the input first instruction sequence and the second instruction sequence are marked with the positions of the target instructions, so as to divide the first instruction sequence into a plurality of first instruction segments and divide the second instruction sequence into a plurality of second instruction segments. The preset tool automatically performs sequence alignment calculation on the first instruction sequence and the second instruction sequence. For each first instruction segment in the first instruction sequence, a functionally identical second instruction segment is automatically found in the second instruction sequence, a corresponding relationship between each first instruction segment and the second instruction segment is established, and instruction matching calculation is performed on each first instruction segment and the corresponding second instruction segment, and the redundant instructions therein are automatically identified and marked.

[0145] The embodiment of the present application does not limit the type of the preset tool, and the preset tool can be a debugging library or tool set provided by various programming languages; or can be a customized script or tool developed for a specific programming language or application scenario.

[0146] After identifying the redundant instructions in the first instruction sequence or the second instruction sequence, report information can be output to report the relevant information of the redundant instructions, such as the content of the redundant instructions, the position of the redundant instructions, etc. Thus, the instruction selection mode in the compiler can be optimized according to the report information, the compilation result of the compiler can be corrected, the compiler can generate more refined and efficient compilation results, the quality of the compilation result of the compiler can be improved, and the program running efficiency can be improved. In addition, the embodiment of the present application can identify the redundant instructions generated by the compiler by an automated method, which can improve the efficiency of the compiler developer in analyzing the performance defects of the compiler and improve the quality of the code generated by the compiler.

[0147] It should be noted that, for the method embodiments, the series of acts complement each other to achieve the purpose of this embodiment, therefore, the sequence of the method should not be construed as limiting the application. Optionally, the sequence of the acts can be changed or two or more acts can be combined, however, the disclosure should not be construed as limited to the sequence provided by the description.

[0148] Referring to Figure 3 , a structural block diagram of an instruction recognition device embodiment of the present application is shown, which can include:

[0149] The insertion module 301 is configured to insert a target instruction at a target position in a first source code to obtain a second source code.

[0150] The compiling module 302 is configured to compile the second source code using a first compiler to obtain a first compilation result, and compile the second source code using a second compiler to obtain a second compilation result.

[0151] The execution record module 303 is configured to obtain a first instruction sequence for executing the first compilation result record and a second instruction sequence for executing the second compilation result record, respectively; the first instruction sequence includes a first instruction segment obtained by dividing the position of the target instruction, and the second instruction sequence includes a second instruction segment obtained by dividing the position of the target instruction.

[0152] The matching calculation module 304 is configured to perform instruction matching calculation on the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence to obtain a matching result.

[0153] The instruction recognition module 305 is configured to determine redundant instructions in the first instruction sequence or the second instruction sequence according to the matching result.

[0154] Optionally, the insertion module includes:

[0155] The first conversion submodule is configured to convert the first source code into an abstract syntax tree.

[0156] The target determination submodule is configured to traverse each node of the abstract syntax tree and determine a target position in the node.

[0157] The instruction insertion submodule is configured to insert a target instruction at each target position to obtain a processed abstract syntax tree.

[0158] The second conversion submodule is configured to convert the processed abstract syntax tree into a second source code.

[0159] Optionally, the target determining submodule is specifically configured to:

[0160] traverse each node of the abstract syntax tree, identify a target node of which a node type is a statement block, and determine a starting position of the target node as the target position.

[0161] Optionally, the target determining submodule is specifically configured to:

[0162] traverse each node of the abstract syntax tree, identify a target sequence point in the node, and determine a position of the target sequence point as the target position; the target sequence point satisfies the following conditions: all expressions before the target sequence point have been evaluated, and all side effects have been generated, and all side effects after the target sequence point have not been generated; the side effects include modification operations on an environment state.

[0163] Optionally, the execution recording module is specifically configured to:

[0164] execute the first compiled result and the second compiled result respectively on a host machine of the same architecture using a binary translator, the binary translator records a first instruction sequence executed in a process of executing the first compiled result, and records a second instruction sequence executed in a process of executing the second compiled result.

[0165] Optionally, the matching calculating module comprises:

[0166] a segment corresponding submodule, configured to, for each first instruction segment in the first instruction sequence, determine a corresponding second instruction segment in the second instruction sequence; the first instruction segment and the corresponding second instruction segment have the same function;

[0167] a matching calculating submodule, configured to, for each first instruction in the first instruction segment, calculate a matching degree between the first instruction and each second instruction in the corresponding second instruction segment respectively, to obtain the matching degree between the first instruction and the second instruction;

[0168] the instruction identifying module comprises:

[0169] an instruction matching submodule, configured to, for each first instruction segment and the corresponding second instruction segment in the first instruction sequence, determine matched first instructions and second instructions in the first instruction segment and the second instruction segment according to the matching degree between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment;

[0170] The first determining sub-module is configured to determine a first instruction in the first instruction segment as a redundant instruction if there is no second instruction matching the first instruction in the corresponding second instruction segment.

[0171] The second determining sub-module is configured to determine a second instruction in the second instruction segment as a redundant instruction if there is no first instruction matching the second instruction in the corresponding first instruction segment.

[0172] Optionally, the matching calculating sub-module comprises:

[0173] The first calculating unit is configured to calculate an operation code similarity between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment respectively, wherein the operation code similarity is calculated according to whether the operation code fields are the same and whether the operation code types are the same.

[0174] The second calculating unit is configured to calculate a matching degree between the first instruction and the second instruction according to the operation code similarity between the first instruction and the second instruction.

[0175] Optionally, the target instruction comprises a no-operation instruction.

[0176] The instruction recognition device provided by the embodiment of the present application inserts a target instruction at a target position in the first source code to obtain a second source code, and realizes the instrumenting of the first source code. The first source code is compiled by using a first compiler and a second compiler respectively to obtain a first compilation result and a second compilation result. A first instruction sequence recorded by the first compilation result and a second instruction sequence recorded by the second compilation result are obtained respectively. Since the optimization capabilities of different compilers are different, the redundant instructions can be identified by comparing the differences between the first instruction sequence and the second instruction sequence. Further, since the second source code comprises the target instruction inserted in advance, the complete instruction sequence during the execution can be divided into smaller instruction segments according to the instrumenting point (i.e. the position of the target instruction) after the second source code is compiled. Therefore, the redundant instructions in the instruction segments can be identified based on the instruction segments, and the accuracy of identifying the redundant instructions can be improved.

[0177] The instruction recognition device provided by the embodiment of the present application can be used to identify the redundant instructions generated by the compiler, so that the compilation process of the compiler can be optimized, the compilation result of the compiler can be corrected, the compiler can generate more refined and efficient compilation results, the quality of the compilation result of the compiler can be improved, and the program running efficiency can be improved.

[0178] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts are described in the method embodiment.

[0179] The instruction recognition method described in the above embodiments can be implemented as a compiler optimization tool for compiler development. The compiler optimization tool can include: a compiler interface configured to receive a first compilation result of a first compiler (e.g., LLVM) on a patched source code and a second compilation result of a second compiler (e.g., GCC) on the patched source code; an instruction executor configured to execute the first compilation result and the second compilation result to obtain a first instruction sequence and a second instruction sequence, the first and second instruction sequences including a plurality of first instruction segments and a plurality of second instruction segments divided by a patching point, respectively; and an instruction alignment tool configured to align the first instruction sequence and the second instruction sequence based on the plurality of first instruction segments and the plurality of second instruction segments, and prompt an alignment result. Redundancy can exist in the instruction segments that cannot be aligned.

[0180] Figure 4 The alignment and prompting effects in the LLVM-based compiler optimization process are shown. The left side is the GCC generated code, and the right side is the LLVM generated code. It can be seen that there is a large piece of assembly code generated by LLVM that cannot be found in the left side, which prompts that LLVM may generate inefficient assembly code.

[0181] Reference Figure 5 is a structural schematic diagram of an electronic device provided by an embodiment of the present application. As shown in Figure 5 The electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store at least one executable instruction. The executable instruction causes the processor to execute the steps of the instruction recognition method of the foregoing embodiments.

[0182] The embodiments of the present application provide a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a program or a processor of a terminal, the terminal can execute the steps of the instruction recognition method of the foregoing embodiments.

[0183] Each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0184] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer program instructions.

[0185] Embodiments of the present application are described herein with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing device or other programmable data processing terminal devices to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal devices, create means for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0186] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing terminal device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device to cause a series of operational steps to be performed on the computer or other programmable terminal device to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal device provide steps for implementing the functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams. Figure 1 one or more functions specified in the flowchart illustrations and / or block diagrams.

[0188] Finally, it needs to be pointed out that, in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "comprising" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal device including a series of elements does not only include those elements, but can also include other elements not explicitly listed, or further include elements inherent in such a process, method, article, or terminal device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or terminal device including the element.

[0189] The principles and implementation of the application are described herein by applying specific examples, and the above description of the examples is only for the purpose of helping to understand the method of the application and its core idea; at the same time, for those skilled in the art, according to the idea of the application, there will be changes in specific implementation and application scope, and the above description of the content of the specification should not be understood as a limitation of the application.

Claims

1. A method for recognizing instructions, characterized in that, The method includes: Insert the target instruction at the target location in the first source code to obtain the second source code; The second source code is compiled using a first compiler to obtain a first compilation result; and the second source code is compiled using a second compiler to obtain a second compilation result. A first instruction sequence for executing the first compilation result record and a second instruction sequence for executing the second compilation result record are obtained respectively; the first instruction sequence includes a first instruction fragment segmented by the location of the target instruction, and the second instruction sequence includes a second instruction fragment segmented by the location of the target instruction. The first instruction segment in the first instruction sequence is matched with the corresponding second instruction segment in the second instruction sequence to obtain the matching result; Based on the matching result, redundant instructions in the first instruction sequence or the second instruction sequence are determined.

2. The method according to claim 1, characterized in that, The step of inserting the target instruction at the target location in the first source code to obtain the second source code includes: Convert the first source code into an abstract syntax tree; Traverse each node of the abstract syntax tree and determine the target position within each node; Insert a target instruction at each target location to obtain the processed abstract syntax tree; The processed abstract syntax tree is converted into second source code.

3. The method according to claim 2, characterized in that, The step of traversing each node of the abstract syntax tree and determining the target position within the node includes: Traverse each node of the abstract syntax tree, identify the target node whose node type is a statement block, and determine the starting position of the target node as the target position.

4. The method according to claim 2, characterized in that, The step of traversing each node of the abstract syntax tree and determining the target position within the node includes: Traverse each node of the abstract syntax tree, identify the target sequence point in the node, and determine the position of the target sequence point as the target position; the target sequence point satisfies the following conditions: all expressions before the target sequence point have been evaluated and all side effects have occurred, and all side effects after the target sequence point have not occurred; the side effects include modifications to the environment state.

5. The method according to claim 1, characterized in that, The step of obtaining the first instruction sequence for executing the first compilation result record and the second instruction sequence for executing the second compilation result record respectively includes: The first compilation result and the second compilation result are executed using a binary translator. The binary translator records the first instruction sequence executed during the execution of the first compilation result and the second instruction sequence executed during the execution of the second compilation result.

6. The method according to claim 1, characterized in that, The step of matching the first instruction fragment in the first instruction sequence with the corresponding second instruction fragment in the second instruction sequence to obtain a matching result includes: For each first instruction segment in the first instruction sequence, a corresponding second instruction segment is determined in the second instruction sequence; the first instruction segment and its corresponding second instruction segment have the same function. For each first instruction in the first instruction segment, a matching degree is calculated with each second instruction in the corresponding second instruction segment to obtain the matching degree between each first instruction and each second instruction; The step of determining redundant instructions in the first instruction sequence or the second instruction sequence based on the matching result includes: For each first instruction segment and its corresponding second instruction segment in the first instruction sequence, the matching first instruction and second instruction in the first instruction segment and the corresponding second instruction segment are determined according to the matching degree between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment; If a first instruction in the first instruction segment does not have a matching second instruction in the corresponding second instruction segment, then the first instruction is determined to be a redundant instruction; or... If a second instruction in the second instruction segment does not have a matching first instruction in the corresponding first instruction segment, then the second instruction is determined to be a redundant instruction.

7. The method according to claim 6, characterized in that, The step of calculating the matching degree between each first instruction in the first instruction segment and each second instruction in the corresponding second instruction segment to obtain the matching degree between each first instruction and each second instruction includes: For each first instruction in the first instruction segment, an opcode similarity is calculated with each second instruction in the corresponding second instruction segment; the opcode similarity is calculated based on whether the opcode fields are the same and whether the opcode types are the same. The matching degree between the first instruction and the second instruction is calculated based on the similarity of their opcodes.

8. The method according to claim 1, characterized in that, The target instruction includes no operation instruction.

9. An instruction recognition device, characterized in that, The device includes: An instrumentation module is used to insert target instructions at target locations in the first source code to obtain the second source code. A compilation module is used to compile the second source code using a first compiler to obtain a first compilation result; and to compile the second source code using a second compiler to obtain a second compilation result; An execution record module is used to obtain a first instruction sequence for executing the first compilation result record and a second instruction sequence for executing the second compilation result record, respectively; the first instruction sequence includes a first instruction fragment segmented by the location of the target instruction, and the second instruction sequence includes a second instruction fragment segmented by the location of the target instruction; The matching calculation module is used to perform instruction matching calculation on the first instruction segment in the first instruction sequence and the corresponding second instruction segment in the second instruction sequence to obtain the matching result; The instruction recognition module is used to determine redundant instructions in the first instruction sequence or the second instruction sequence based on the matching result.

10. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the steps of the instruction recognition method as described in any one of claims 1 to 8.

11. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the instruction identification method as described in any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the instruction recognition method as described in any one of claims 1 to 8.

13. A compiler optimization apparatus, comprising: A compiler interface is used to receive the first compilation result of the instrumented source code from a first compiler and the second compilation result of the instrumented source code from a second compiler. An instruction executor executes the first compilation result and the second compilation result to obtain a first instruction sequence and a second instruction sequence, wherein the first and second instruction sequences respectively include a plurality of first instruction fragments and a plurality of second instruction fragments segmented by instrumentation points; as well as An alignment tool aligns the first instruction sequence and the second instruction sequence based on the plurality of first instruction fragments and second instruction fragments, and displays the alignment result.

14. The compiler optimization apparatus according to claim 13, wherein, The instruction executor is a binary translator.

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