Compiling method, electronic device, and storage medium

Abstract

Embodiments of the present disclosure provide a compiling method, an electronic device and a storage medium. The method comprises: obtaining an object operator; dividing the object operator into a plurality of logical basic blocks according to implementation of the object operator, wherein the plurality of logical basic blocks comprise a first logical basic block and a second logical basic block; determining a first instruction position in the first logical basic block according to hardware attributes of a processor used to execute the object operator; inserting at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block according to an instruction dependency relationship between the plurality of logical basic blocks; and fusing the inserted at least one instruction into a control instruction stream corresponding to the first logical basic block, and generating an assembly code according to the fused control instruction stream. The method can schedule instructions across modules and adapt to different hardware architectures when compiling instructions, thereby improving instruction parallelism, processor hardware resource utilization and compiling efficiency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of compilation, and in particular, to a compilation method, an electronic device, and a storage medium. BACKGROUND

[0002] In the field of high-performance operator development for artificial intelligence chips, developers usually generate underlying assembly code (such as various underlying virtual machine instruction sets corresponding to artificial intelligence chips) suitable for execution by artificial intelligence chips using high-level programming languages (such as C++ or Python) to achieve efficient use of computing resources. To improve development efficiency and code maintainability, a modular design method is generally used to divide a complete computing process into multiple modules, where each module is implemented in the form of an independent function or code segment, and in the compilation phase, the instruction sequences generated by each functional module are arranged in a predetermined order. The current modular design method has the problems of limited instruction scheduling range and increased code complexity when performing cross-module scheduling, which leads to increased maintenance costs, poor hardware adaptability, and other problems. SUMMARY

[0003] At least one embodiment of the present disclosure provides a compilation method, including: obtaining an object operator; dividing the object operator into a plurality of logical basic blocks according to implementation of the object operator, wherein the plurality of logical basic blocks include a first logical basic block and a second logical basic block; determining a first instruction position in the first logical basic block according to a hardware attribute of a processor used to execute the object operator; inserting at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block according to an instruction dependency relationship between the plurality of logical basic blocks; and merging the inserted at least one instruction into a control instruction stream corresponding to the first logical basic block, and generating assembly code according to the merged control instruction stream.

[0004] For example, in the compilation method provided by at least one embodiment of the present disclosure, the first logical basic block includes a storage instruction for processing a first data block, and the second logical basic block includes a prefetch instruction for processing at least part of data of a second data block, the second data block being a next data block to be processed of the first data block.

[0005] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, the first logical basic block is included in the first region, and the at least one instruction corresponding to the second logical basic block is inserted into the first instruction position in the first logical basic block according to the instruction dependency relationship among the plurality of logical basic blocks, including: in response to the second logical basic block being independent of the first logical basic block, splitting the first region into a first sub-region and a second sub-region according to the first instruction position, and inserting the at least one instruction corresponding to the second logical basic block in the form of the second region between the first sub-region and the second sub-region, wherein the execution order is the first sub-region, the second region, and the second sub-region.

[0006] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, before the at least one instruction corresponding to the second logical basic block is inserted into the first instruction position in the first logical basic block, the method further includes: marking the at least one instruction corresponding to the second logical basic block as a pluggable instruction sequence, so that the at least one instruction is inserted into the first instruction position in the first logical basic block.

[0007] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, the at least one instruction inserted is integrated into a control instruction stream corresponding to the first logical basic block, and the assembly code is generated according to the integrated control instruction stream, including: after the at least one instruction corresponding to the second logical basic block is inserted into the first instruction position, the integrated control instruction stream is generated according to the execution order of the regions corresponding to the plurality of logical basic blocks.

[0008] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, the hardware attribute includes at least one of the number of cache regions, the bandwidth for storing instructions, and the computing capability.

[0009] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, the first instruction position in the first logical basic block is determined according to the hardware attribute of the processor for executing the object operator, including: determining the first instruction position in the first logical basic block based on the execution time of the instruction in the first logical basic block and the execution time of the instruction in the second logical basic block.

[0010] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, the first logical basic block further includes a function post-processing instruction, and before the storage instruction in the first logical basic block is executed, the processor for executing the object operator executes the function post-processing instruction to perform optimization processing on the calculation result of the first data block.

[0011] For example, in the compiling method provided in at least one of the embodiments of the present disclosure, the plurality of logical basic blocks further include a third logical basic block, the first logical basic block depends on the third logical basic block, and the third logical basic block includes a loading instruction and a calculation instruction for processing the first data block.

[0012] The disclosure provides a compiling device in at least one embodiment. The compiling device comprises an obtaining module, a dividing module and an inserting module. The obtaining module is configured to obtain an object operator. The dividing module is configured to divide the object operator into a plurality of logical basic blocks according to implementation of the object operator, wherein the plurality of logical basic blocks comprise a first logical basic block and a second logical basic block. The inserting module is configured to insert at least one instruction corresponding to the second logical basic block into a first instruction position in the first logical basic block according to an instruction dependency relationship between the plurality of logical basic blocks.

[0013] The disclosure provides an electronic device in at least one embodiment. The electronic device comprises at least one processor and at least one memory. The at least one memory has program code stored therein. The program code, when executed by the at least one processor, causes the at least one processor to perform the compiling method provided in any one of the embodiments of the disclosure.

[0014] The disclosure provides a non-transitory computer-readable storage medium having computer-readable instructions stored thereon. The computer-readable instructions, when executed by at least one processor, cause the processor to perform the compiling method provided in any one of the embodiments of the disclosure.

[0015] In order to solve the problems that the modular design method has limited instruction scheduling range, and when cross-module scheduling is performed, the code complexity is increased, the maintenance cost is increased, the hardware adaptability is poor, and the like, the disclosure provides a compiling method, device, electronic device and storage medium in at least one embodiment. In at least one embodiment of the disclosure, by inserting at least one instruction corresponding to the second logical basic block into a first instruction position in the first logical basic block, cross-module instruction scheduling can be implemented when compiling instructions and adapted to different hardware architectures. According to the hardware attribute of the processor, the insertion position of the instruction can be determined, the parallel degree of the instruction can be improved, the pipeline stall can be reduced, and the utilization rate of the hardware resources of the processor can be improved. The instructions (or instruction sequences) are transmitted between the logical basic blocks instead of the data dependency relationship, which can avoid strong coupling between the logical basic blocks due to the data dependency relationship (for example, the data dependency relationship makes the logical basic blocks have to pay attention to the underlying implementation details of each other, such as details of how data is generated, stored and transmitted, so that when one logical basic block is modified, other associated logical basic blocks need to be adjusted synchronously), thereby decoupling the code logic and reducing the complexity of the code. Moreover, the developer no longer needs to manually write the insertion logic of the instruction, thereby realizing the automation of instruction insertion (or instruction injection), reducing the cost of manual optimization, and improving the compiling efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced in the following. Obviously, the drawings described below only relate to some embodiments of the present disclosure and not limit the present disclosure.

[0017] Figure 1 A flowchart of a compiling method provided by at least one embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram of cross-module scheduling instructions provided by at least one embodiment of the present disclosure;

[0019] Figure 3 A schematic block diagram of a compiling apparatus provided by at least one embodiment of the present disclosure;

[0020] Figure 4 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0021] Figure 5 A schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure;

[0022] Figure 6 A schematic block diagram of a non-transitory computer readable storage medium provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present disclosure.

[0024] Flowcharts are used in the present disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in sequence. On the contrary, various steps can be processed in reverse order or simultaneously as needed. Meanwhile, other operations can be added to these processes, or one or more steps of operations can be removed from these processes.

[0025] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity of particular mentioned items, but indicate the existence of at least one of the particular mentioned items. The terms "comprises", "comprising", "includes", "including" and the like can mean the presence of a stated element or item but do not preclude the presence or addition of other elements or items. The terms "connected", "coupled", and the like can not be limited to a physical or mechanical connection or coupling, but can also include an electrical connection or coupling, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions can also be changed accordingly.

[0026] As described above, in the field of high-performance operator development for artificial intelligence chips, developers usually use high-level programming languages (such as C++ or Python) to generate underlying assembly code (such as various types of artificial intelligence chip corresponding underlying virtual machine instruction sets) suitable for artificial intelligence chip execution, in order to achieve efficient use of computing resources. The artificial intelligence chips here include but are not limited to graphics processing units (GPU), general-purpose graphics processing units (GPGPU), tensor processing units (TPU), neural network processing units (NPU), deep learning processing units (DPU), accelerated processing units (APU), field programmable gate arrays (FPGA), and multi-core processors with artificial intelligence computing capabilities, etc.

[0027] To improve development efficiency and code maintainability, a modular design method is generally used to divide a complete calculation process into multiple modules, each of which is implemented in the form of an independent function or code segment, and in the compilation stage, the instruction sequences generated by the functional modules are arranged in a predetermined order. For example, a matrix multiplication calculation can be divided into a main loop (mainLoop) module and an epilogue module. The mainLoop module is used to generate a data block loading (Load) instruction and a matrix multiply-accumulate (MMA) calculation instruction, and the epilogue module is used to generate a data block storage (Store) instruction and a post-processing instruction (such as an instruction for performing a normalization operation, etc.). The loading instruction is, for example, an instruction for reading data from the memory to the internal register or cache of the processor, and the storage instruction is, for example, an instruction for writing data from the internal register or cache of the processor back to the memory. This modular design method relies on function calls or code splicing. In the compilation stage, the instruction sequences generated by the modules are arranged in a predetermined order, for example, in a loop order of mainLoop module→epilogue module→mainLoop module→epilogue module, so as to generate the assembly code of the matrix multiplication calculation.

[0028] However, this modular design method based on function calls and code segment splicing has certain limitations. First, the scope of instruction scheduling is limited. In the compilation instruction, modular design causes the instruction sequences generated by the modules to be constrained in a single code segment, thereby lacking the ability to interleave instructions across modules. For example, it is not possible to insert the Load instruction generated by the mainLoop module of the next data block into the code segment corresponding to the epilogue module of the current data block. Second, in modular design, the inter-module instruction dependency relationship can be passed through function parameters or global variables to implement cross-module instruction scheduling, which increases code complexity and maintenance costs. Alternatively, the developer can manually write instruction insertion logic to implement cross-module instruction scheduling, which can easily destroy the original code structure, is difficult to adapt to scheduling strategies under different hardware architectures, and can also lead to a significant increase in development costs, low efficiency of manual optimization, and lack of universality.

[0029] At least one embodiment of the present disclosure provides a compilation method and device, an electronic device, and a storage medium.

[0030] The compiling method of at least one embodiment of the present disclosure includes: obtaining an object operator; dividing the object operator into a plurality of logical basic blocks according to implementation of the object operator, wherein the plurality of logical basic blocks include a first logical basic block and a second logical basic block; determining a first instruction position in the first logical basic block according to a hardware attribute of a processor used to execute the object operator; inserting at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block according to an instruction dependency relationship between the plurality of logical basic blocks; and fusing the inserted at least one instruction into a control instruction stream corresponding to the first logical basic block, and generating assembly code according to the fused control instruction stream.

[0031] In the compiling method provided by at least one embodiment of the present disclosure, by inserting at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block, cross-module instruction scheduling can be implemented when compiling instructions and adapted to different hardware architectures; the insertion position of the instruction can be determined according to the hardware attribute of the processor, which can improve the parallel degree of the instruction, reduce pipeline stalls, and improve the utilization rate of the hardware resources of the processor; the instructions (or instruction sequences) are transmitted between the logical basic blocks instead of data dependencies, which can avoid strong coupling between the logical basic blocks due to data dependency relationships (for example, the data dependency relationship makes the logical basic blocks have to pay attention to the underlying implementation details of each other, such as details of how data is generated, stored, and transmitted, which leads to the need to adjust other associated logical basic blocks when modifying one logical basic block), thereby decoupling the code logic and reducing the complexity of the code, and the developer no longer needs to manually write the insertion logic of the instruction, thereby realizing the automation of instruction insertion (or instruction injection), reducing the cost of manual optimization, and improving the compiling efficiency.

[0032] Further, the compiling method provided by at least one embodiment of the present disclosure determines the insertion position of the instruction according to the hardware attribute of the processor, and implements the instruction insertion based on a hardware-independent compiler intermediate representation, and after the order rearrangement of the instruction is completed, the control instruction stream based on the intermediate representation is converted into machine instructions (assembly code) of a target hardware architecture. Therefore, this method can shield the underlying hardware details, so that the upper layer logic does not need to care about the target hardware architecture, and thus can be applied to different target hardware architectures.

[0033] In the computing process of artificial intelligence, various computations or operations can be implemented in the form of an "operator", and each operator can be understood as a code segment or a function that performs a specific computation or operation.

[0034] For example, the compiling method provided by at least one embodiment of the present disclosure can be applied to the fields of general computing, artificial intelligence and machine learning, embedded systems, etc.

[0035] For example, in the field of general computing, the object operator can be various operation units used, defined, and executed in scientific computing (such as matrix operation, numerical simulation), general program logic operation (conditional judgment, loop iteration), and the like, such as a matrix multiplication operator, a loop count operator, and the like. The compiling method of the present disclosure can optimize the operation process, adapt to different CPU hardware architectures, and improve the computing efficiency.

[0036] For example, in the field of artificial intelligence and machine learning, the object operator covers operation modules in model training (such as gradient calculation, weight update, etc.), inference prediction (such as feature mapping, classification judgment, etc.), and the like, as well as neural network layer calculation operators (such as convolution operators, fully connected operators, etc.), loss function calculation operators, and the like. Through the compiling method of the present disclosure, cross-module instruction scheduling can be realized, and GPUs, NPUs, and the like can be adapted to accelerate model training and inference.

[0037] For example, in the field of embedded systems, the object operator involves functional modules of hardware control (such as sensor data acquisition, peripheral device instruction interaction, etc.), low-power task scheduling (such as sleep-wake control, operation resource allocation, etc.), real-time logic processing (such as event response, state machine operation), and the like, such as a sensor data analysis operator, a power management control operator, a real-time event processing operator, and the like. The compiling method of the present disclosure can adapt to embedded hardware resources, optimize instruction execution, and ensure efficient and stable operation of the system.

[0038] Of course, the present disclosure is not limited thereto. For other application scenarios or fields, as long as the needs of operator compiling optimization, adaptation to hardware, and pursuit of instruction execution efficiency improvement are involved, the compiling method described in at least one embodiment of the present disclosure can be applied, and detailed description will not be repeated here.

[0039] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of known functions and known components can be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is denoted by the same or similar reference numeral in each figure.

[0040] Some embodiments of the present disclosure and examples thereof will be described in detail below with reference to the accompanying drawings.

[0041] Figure 1 A flowchart of a compiling method provided by at least one embodiment of the present disclosure.

[0042] For example, as shown in Figure 1 The compiling method provided by at least one embodiment of the present disclosure can include the following steps S110-S150.

[0043] Step S110: Obtain an object operator.

[0044] Step S120: According to the implementation of the object operator, the object operator is divided into a plurality of logical basic blocks, wherein the plurality of logical basic blocks include a first logical basic block and a second logical basic block.

[0045] Step S130: According to the hardware properties of the processor used to execute the object operator, a first instruction position in the first logical basic block is determined.

[0046] Step S140: According to the instruction dependency relationship between the plurality of logical basic blocks, at least one instruction corresponding to the second logical basic block is inserted into the first instruction position in the first logical basic block.

[0047] Step S150: The inserted at least one instruction is integrated into a control instruction stream corresponding to the first logical basic block, and an assembly code is generated according to the integrated control instruction stream.

[0048] For step S110, the object operator may, for example, be an operator for artificial intelligence (AI) (hereinafter referred to as an AI operator), such as a high-performance operator implemented based on a general-purpose graphics processing unit (GPGPU) (hereinafter referred to as a GPU high-performance operator), etc. The embodiments of the present disclosure do not limit the calculation function to be implemented for the operator.

[0049] For example, the AI operator can refer to various tensor calculation operations performed in an AI framework, such as a convolution operator, a pooling operator, a normalization operator, a matrix multiplication operator, an element-wise operation operator, etc.; the GPU high-performance operator (or GPU acceleration operator) can refer to an operation that can efficiently utilize the parallel architecture of the GPU to accelerate the calculation, and can include an accelerated implementation of various AI operators. The "object operator" here is used to refer to an operator that describes an object.

[0050] In the compiler front-end processing stage, the compiler can perform front-end processing operations such as lexical analysis, syntax analysis, and semantic analysis on the source program, thereby identifying the object operator in the source program. Through graph construction, these operators can be encapsulated as nodes (Node) in the computation graph, forming a kind of general intermediate representation (Intermediate Representation, IR), and the edges in the computation graph represent the data dependency relationship.

[0051] An intermediate representation is a structured, platform-independent abstract form used by a compiler to represent a program internally, enabling decoupling between various language front-ends and target back-ends. An example is the Low-Level Virtual Machine (LLVM) IR. LLVM is an open-source compiler framework designed as a collection of modular, reusable compiler and toolchain technologies.

[0052] For step S120, according to the implementation process (i.e., the calculation process or the operation process) of the object operator, the compiler can divide the object operator into a plurality of logic basic blocks (LBBs). A logic basic block is a discrete structural unit that constitutes a program, each logic basic block including a sequence of instructions that are executed sequentially and not containing any starting point or ending point of a jump or branch (except that the last instruction can be a control transfer instruction). Each logic basic block has only one entry point and one exit point. The logic basic block is a basic unit in the control flow analysis, optimization, and compilation process, which helps to understand and operate the control structure of the program. For example, in the intermediate representation, the object operator can be divided into a plurality of logic basic blocks, and the logic basic blocks are connected according to control transfer instructions (branch, jump, function call / return) to form a control flow graph (CFG) for subsequent optimization, analysis, and target code generation. The control flow graph is a directed graph that describes the execution path of a program, with nodes being logic basic blocks and edges being jump logic.

[0053] For example, the plurality of logic basic blocks corresponding to the object operator can include a first logic basic block and a second logic basic block. The first logic basic block can include a store instruction for processing a first data block, and the second logic basic block can include a prefetch instruction for processing at least part of data of a second data block, the second data block being a next data block to be processed of the first data block. That is, the object operator can be divided into the first logic basic block and the second logic basic block. The prefetch instruction is a pre-load instruction, and the "prefetch instruction for processing at least part of data of a second data block" refers to an instruction for pre-loading at least part of data of the second data block in the process of processing the first data block.

[0054] In some examples, the plurality of logical basic blocks can further include a third logical basic block, the third logical basic block can include a load instruction and a compute instruction for processing the first data block, in the instruction sequence included in the third logical basic block, the load instruction is located before the compute instruction, that is, in the instruction execution stage, the processor executes the load instruction first to load the first data block, and then executes the compute instruction to perform corresponding computation on the first data block. The first logical basic block depends on the third logical basic block (in other words, the instructions in the first logical basic block depend on the instructions in the third logical basic block), that is, the processor executes the instruction sequence in the first logical basic block after executing the instruction sequence in the third logical basic block. That is, the object operator can be divided into the first logical basic block, the second logical basic block and the third logical basic block.

[0055] In some examples, the first logical basic block can further include a functional post-processing instruction. In the instruction sequence included in the first logical basic block, the functional post-processing instruction can be located before the store instruction. In the instruction execution stage, before the processor executing the store instruction for the first data block, the functional post-processing instruction can be executed to perform optimization processing on the computation result of the first data block, and then the optimized computation result is stored in the corresponding memory (such as memory or cache, etc.).

[0056] It should be noted that the compute instruction and the functional post-processing instruction can be determined according to the type of the object operator. For example, when the object operator is a matrix multiplication operator, the compute instruction can include a matrix multiplication accumulation instruction (MMA instruction), or can include a multiplication instruction and an addition instruction to perform multiplication and addition operation on the first data block, and the functional post-processing instruction can include instructions for activation function (such as ReLU, Sigmoid), normalization processing and the like. The functional post-processing instruction is used to perform subsequent processing on the multiplication and addition operation result of the first data block, such as performing nonlinear activation (such as ReLU), normalization processing and the like on the multiplication and addition operation result.

[0057] For step S130, the hardware attribute can include at least one of the number of cache regions, the bandwidth for storing instructions and the computing capability, which is not limited by the present disclosure.

[0058] For example, the number of cache regions can be embodied as the pipeline depth (number of stages) of the processor; the bandwidth for storing instructions can be embodied as the memory throughput capacity available for storing instructions per unit time; and the computing capability can be embodied as the amount of operations that can be completed by the processor per unit time. During the execution of the instructions, the number of cache regions, the bandwidth for storing instructions and the computing capability of the processor can all determine the execution time of the instructions.

[0059] For step S140, the instruction dependency relationship between the plurality of logical basic blocks can be managed through a Control Flow Graph (CFG), and then at least one instruction (e.g., a prefetch instruction used to process at least part of the data of the second data block) corresponding to the second logical basic block can be dynamically inserted into a first instruction position in the first logical basic block, so as to implement cross-module scheduling of the instruction. The first instruction position can be determined according to the instruction dependency relationship between the logical basic blocks, and the specific determination manner will be described in detail below.

[0060] For example, the instruction dependency relationship refers to a constraint relationship between two instructions, which cannot be randomly exchanged in execution order, otherwise the program semantics or result correctness will be affected. The instruction dependency relationship can include a data dependency relationship and a control dependency relationship. For example, if an instruction uses data generated or modified by another instruction, there is a data dependency between the two instructions; if the execution of an instruction depends on the result of a previous branch instruction, it is said that the instruction has a control dependency on the branch instruction. Therefore, when selecting the insertion point (the first instruction position) in the first logical basic block, the inserted instruction should not have an instruction dependency relationship with the instructions after the first instruction position in the first logical basic block. Based on this rule, the position meeting the above condition can be determined as the first instruction position.

[0061] For example, a region is a control flow subgraph abstraction built on an intermediate representation, which can support a nested structure and is used to describe how a set of related logical basic blocks are organized together. For example, a region can be a subgraph of a control flow graph, which has a single entry basic block and a single exit basic block. All control flow edges entering the subgraph point to the single entry basic block, and all control flow edges leaving the subgraph point to the single exit basic block. For example, a region can include one or more logical basic blocks, and which logical basic blocks correspond to the region can be determined based on a control flow graph.

[0062] For example, the instructions in each logical basic block can be organized and managed through an intermediate representation or a region representing a code segment in a compiler, so that the logical relationship between the instructions is more clear, and the dynamically inserted instruction (e.g., the instruction dynamically inserted into the first instruction position in the first logical basic block) can be fused with the original instruction into a unified control flow. This is conducive to compilation optimization, and is also more conducive to converting the instruction into assembly code in the subsequent step, which will be described in detail below.

[0063] For example, the first logical basic block described above can be included in a first region, that is, the instructions corresponding to the first logical basic block are included in the first region. Correspondingly, the example of step S140 can include the following step S240.

[0064] Step S240: in response to the second logical basic block being independent of the first logical basic block, splitting the first region into a first sub-region and a second sub-region according to the first instruction position, and inserting the at least one instruction corresponding to the second logical basic block in the form of a second region between the first sub-region and the second sub-region, wherein the instruction execution order is the first sub-region, the second region, and the second sub-region.

[0065] It should be noted that the "second logical basic block being independent of the first logical basic block" means that there is no instruction dependency relationship between the second logical basic block and the first logical basic block, that is, the execution of the instructions corresponding to the second logical basic block does not depend on the execution result of the instructions in the first logical basic block, and the two can be executed in parallel or out of order without affecting the correctness of the program.

[0066] For example, in step S240, the second region can include at least one instruction (for example, a prefetch instruction of part of the data of the second data block) corresponding to the second logical basic block, and in some examples, the second region can also include all instructions (for example, a prefetch instruction of all data of the second data block) corresponding to the second logical basic block. Under the premise that there is no instruction dependency relationship between the second logical basic block and the first logical basic block, the first region can be split into two sub-regions (the first sub-region and the second sub-region) at the first instruction position, and the second region is inserted between the first sub-region and the second sub-region. The above operation makes it possible to execute the instructions corresponding to the logical basic blocks in the first sub-region first, then execute the instructions corresponding to the logical basic blocks in the second region, and finally execute the instructions corresponding to the logical basic blocks in the second sub-region in the instruction execution phase.

[0067] The compiling method provided by at least one embodiment of the present disclosure organizes and manages the instructions in each logical basic block by region, and uniformly manages the insertion logic of the instructions by region, which simplifies the coupling degree between each logical basic block, avoids manual modification of multiple function interfaces or manual writing of the insertion logic of the instructions, and supports dynamic adjustment of the scheduling strategy without destroying the original structure of the logical basic block. Further, the region can be used as an abstract layer to implement cross-module insertion of instructions, which can shield the differences of the underlying hardware and be more easily adapted to different instruction sets, cache configurations, thread models, etc.

[0068] For example, the at least one instruction corresponding to the second logical basic block can include a prefetch instruction (i.e., a load instruction for the next data block to be processed), and before inserting the at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block, the compiling method provided by at least one embodiment of the present disclosure can further include the following step: marking the at least one instruction corresponding to the second logical basic block as a Pluggable Instruction Sequence, so that the at least one instruction is inserted into the first instruction position in the first logical basic block. For example, the "Pluggable Instruction Sequence" here means a group of instructions that can be flexibly inserted or connected into other logical basic blocks, and also means a group of instructions that will be scheduled across modules.

[0069] For example, in some examples, the second logical basic block can include instructions for coordinate calculation. Correspondingly, in addition to scheduling the prefetch instruction across modules, part of the instructions for coordinate calculation located in the second logical basic block can also be scheduled across modules. According to actual needs, other types of instructions can also be scheduled across modules, which are not limited by the embodiments of the present disclosure.

[0070] For example, one specific example of the above step S130 can include: determining the first instruction position in the first logical basic block based on the execution time of the instruction in the first logical basic block and the execution time of the instruction in the second logical basic block.

[0071] In one example, the first logical basic block includes 4 store instructions (denoted as Store_Instruction_0~Store_Instruction_3) for storing the computation result of the first data block, each store instruction takes 1000 cycles to execute, the instruction (e.g., a prefetch instruction for the second data block) in the second logical basic block that is marked as the pluggable instruction sequence takes 3000 cycles to execute, therefore, to avoid the delay caused by loading the second data block, the first instruction position to insert the prefetch instruction can be the position between Store_Instruction_0 and Store_Instruction_1. The processor transmits the prefetch instruction to the hardware device immediately after executing Store_Instruction_0, and then executes Store_Instruction_1, Store_Instruction_2 and Store_Instruction_3 in sequence. That is, the processor executes Store_Instruction_1, Store_Instruction_2 and Store_Instruction_3 simultaneously with the hardware device loading the second data block, and after the processor finishes executing Store_Instruction_3, part or all of the data required for the computation operation on the second data block has been loaded.

[0072] In another example, the first logical basic block includes 2 functional post-processing instructions (denoted as Func_Post_Instruction_0 and Func_Post_Instruction_1) and 4 store instructions (denoted as Store_Instruction_0~Store_Instruction_3), each functional post-processing instruction takes 2000 cycles to execute, each store instruction takes 1000 cycles to execute, the instruction (e.g., a prefetch instruction for the second data block) in the second logical basic block that is marked as the pluggable instruction sequence takes 4000 cycles to execute, therefore, the first instruction position to insert the prefetch instruction can be the position between Func_Post_Instruction_1 and Store_Instruction_0, or the position between Func_Post_Instruction_0 and Func_Post_Instruction_1.

[0073] For step S150, the control instruction flow describes the order in which the instructions are executed in sequence according to the path described by the control flow graph (CFG) during the execution of the program. That is, the control instruction flow reflects the actual execution logic of the program at runtime, and determines which instructions are executed, when they are executed, and the order of execution. For example, based on the machine basic block reorganization technology of the LLVM region, control flow fusion can be implemented by cross-basic block instruction migration and CFG topology reconstruction, so as to integrate the instructions inserted at the first instruction position (i.e., the instructions migrated across the logical basic block) into the instruction flow corresponding to the first logical basic block (i.e., the control instruction flow corresponding to the first data block), and generate the assembly code according to the fused control instruction flow.

[0074] An exemplary implementation of "integrating the inserted at least one instruction into the control instruction flow corresponding to the first logical basic block" in step S150 is as follows: after inserting the at least one instruction corresponding to the second logical basic block at the first instruction position, generating the fused control instruction flow according to the execution order of the regions corresponding to the plurality of logical basic blocks.

[0075] For example, assuming that the execution order of the regions is: the first sub-region, the second region, and the second sub-region, the assembly code generated according to the fused control instruction flow will execute the instructions in the above order at runtime, that is, first execute the instructions corresponding to the basic blocks in the first sub-region, then execute the instructions corresponding to the basic blocks in the second region, and finally execute the instructions corresponding to the basic blocks in the second sub-region.

[0076] Figure 2 A schematic diagram of scheduling instructions across modules is shown according to at least one embodiment of the present disclosure, wherein, Figure 2 The left side of the schematic diagram shows the control instruction flow before the instructions are scheduled across modules, Figure 2 The right side of the schematic diagram shows the control instruction flow after the instructions are scheduled across modules.

[0077] In Figure 2In the illustrated example, the object operator is a matrix multiplication operator, which is divided into a logical basic block LBB1 included in a region Region1(i) and a logical basic block LBB2 included in a region Region2(i) according to an implementation of the matrix multiplication operator (e.g., which can include loading of input data, execution of multiply-accumulate operations, post-processing of operation results, and write-back storage of final data), where the logical basic block LBB1 includes a Load instruction and a matrix multiply-accumulate (MMA) instruction, the logical basic block LBB2 includes a functional post-processing instruction and a Store instruction, and i is a natural number. The "i" in Region1(i) and Region2(i) indicates that the instructions in the region are used for data block i. For example, the instructions in Region1(0) and Region2(0) are used for processing data block 0, the instructions in Region1(1) and Region2(1) are used for processing data block 1 (i.e., the next data block to be processed after data block 0), and so on. It is noted that the logical basic block LBB1 in Region1(0) and the logical basic block LBB1 in Region1(1) are not the same logical basic block, and so on.

[0078] Before scheduling the instructions across the modules, as shown on the left side of Figure 2 , the instructions in each logical basic block are arranged in a loop in the order of Region1→Region2 at compile time. Specifically, for data block 0, according to the Load instruction in Region1(0), data block 0 is loaded from memory, for example. Then, according to the MMA instruction in Region1(0), a matrix multiply-accumulate operation is performed on the loaded data block 0 to obtain a multiply-accumulate operation result for data block 0. Finally, according to the functional post-processing instruction in Region2(0), the multiply-accumulate operation result is processed, and according to the Store instruction in Region2(0), the processed multiply-accumulate operation result is stored to a corresponding memory (e.g., a buffer). After data block 0 is processed, data block 1 is processed in a similar manner, which is not described again here.

[0079] As shown on the left side of Figure 2 , since the instructions in Region1(1) for processing data block 1 are independent of the instructions in Region2(0) for processing data block 0, i.e., there is no instruction dependency between the two, the instructions for processing data block 1 can be scheduled across the modules into the region for processing data block 0.

[0080] For example, in the case of Figure 2When the Load instruction in Region1(1) on the left, which is used to process data block 1, is scheduled across modules to Region2(0), the Load instruction in Region1(1) can be marked as a pluggable instruction sequence. For example... Figure 2 As shown on the right, Region2(0) can be split into Sub-region2_0(0) and Sub-region2_1(0) according to the first instruction position, and at least some of the Load instructions in Region1(1) can be inserted between Sub-region2_0(0) and Sub-region2_1(0) in the form of a region (e.g., represented as Region3(1)). At this time, the instructions in these regions are executed in the order of Region1(0), Sub-region2_0(0), Region3(1) and Sub-region2_1(0). Region1(1) now includes the remaining Load instructions and MMA instructions.

[0081] Since the Load instruction for data block 1 is inserted into the instruction for processing data block 0 in the form of Region 3(1), it is equivalent to preloading the data block 1 to be processed during the processing of data block 0. The Load instruction for data block 1 is also referred to as the "prefetch instruction" below.

[0082] For example, suppose Region2(0) includes 2 post-processing instructions and 4 Store instructions. If the position of the first instruction is between the second and third Store instructions, then the resulting Sub-region2_0(0) includes 2 post-processing instructions and the first 2 Store instructions, and Sub-region2_1(0) includes the last 2 Store instructions. The Prefetch instruction for data block 1 is inserted between the second and third Store instructions in the form of Region3(1).

[0083] When the processor executes the instructions in the regions in the order of Region1(0), Sub-region2_0(0), Region3(1) and Sub-region2_1(0), the Prefetch instruction in Region3(1) is transmitted to the background (i.e., the hardware device) to start the loading operation of the data block 1 in advance immediately after the processor finishes executing the instructions in Sub-region2_0(0). When the processor executes the instructions in Sub-region2_1(0) (i.e., during the remaining storage operation of the processed multiply-accumulate operation result corresponding to the data block 0), the hardware device is performing the asynchronous loading operation of the data block 1. When the processor finishes executing the instructions in Sub-region2_1(0) and starts executing the instructions in Region1(1), part or all of the data required for the multiply-accumulate operation on the data block 1 has been loaded on the hardware device. Therefore, the processor can start the calculation operation on the data block 1 (i.e., execute the MMA instruction for processing the data block 1) immediately after finishing Sub-region2_1(0), thereby avoiding the delay caused by waiting for the loading of the data block 1 (or the calculation unit for executing the MMA instruction is in an idle state), and further improving the calculation efficiency.

[0084] In addition, Figure 2 Only the cross-module scheduling operation on the instructions for processing the data block 0 and the data block 1 is shown in the above embodiment, but the embodiments of the present disclosure are not limited thereto. Figure 2 The "..." in the above embodiment indicates that the cross-module scheduling operation can also be performed on the instructions for processing other data blocks (e.g., the data block 2, the data block 3, etc.). For example, the instructions for the data block 2 are cross-module scheduled (or inserted) into the instructions for processing the data block 1 in the form of Region3(2), and the specific operation is similar to the cross-module scheduling (or insertion) of the instructions in Region1(1) for processing the data block 1 into the instructions for processing the data block 0 in the form of Region3(1), which will not be described herein again.

[0085] The compiling method provided by at least one embodiment of the present disclosure can cross-module interleave the instructions, so that the operations in different stages (e.g., the storage instructions for processing the first data block and the prefetch instructions for processing the second data block) can be executed in parallel, the delay caused by accessing the memory can be hidden, and the idle period can be reduced by using the idle threads, registers, etc. in the processor to perform the preloading operation, thereby improving the instruction throughput and shortening the overall execution time.

[0086] In some embodiments of the present disclosure, the process of cross-module scheduling the instructions includes a basic block generation stage, an instruction injection stage and a control flow reconstruction stage.

[0087] During the basic block generation stage, based on the implementation of the object operator, the object operator is divided into multiple logical basic blocks, and instructions corresponding to each logical basic block of the object operator are generated in the form of functions or code segments. Among them, the multiple logical basic blocks include a first logical basic block for processing the first data block and a second logical basic block for processing the second data block. The second data block is the next data block to be processed after the first data block.

[0088] During the instruction injection phase, based on the instruction dependencies between multiple logic basic blocks, at least one instruction corresponding to the second logic basic block (e.g., a prefetch instruction for processing at least a portion of the data in the second data block) is inserted as a pluggable instruction sequence into the first instruction position in the first logic basic block.

[0089] During the control flow reconfiguration phase, based on the LLVM Region or intermediate representation layer basic block reorganization technology, the instruction inserted at the first instruction position is integrated into the control instruction stream corresponding to the first logical basic block (i.e., the control instruction stream corresponding to the first data block), and assembly code is generated according to the fused control instruction stream.

[0090] For example, such as Figure 2 As shown on the right, after inserting at least one instruction corresponding to the second logical basic block (e.g., the Prefetch instruction for data block 1 in region 3(1)) at the first instruction position in the logical basic block LBB2 (e.g., between region Sub-region2_0(0) and region Sub-region2_1(0)), the fused control instruction flow is generated according to the execution order of the regions corresponding to the multiple logical basic blocks, i.e., Region1(0)→Sub-region2_0(0)→Region3(1)→Sub-region2_1(0)→Region1(1)→Sub-region2_0(1)→Region3(2)→Sub-region2_1(0)→…. Then, assembly code is generated based on the fused control instruction flow.

[0091] For example, since the instructions in the merged control instruction stream have a one-to-one mapping relationship with the assembly language, the instructions in the merged control instruction stream can be directly printed as assembly code, for example, using the Print() function, for execution.

[0092] For example, the generated assembly code can first be used by an assembler to generate machine code, and the generated file can be saved as an object file; then the object file can be linked into an executable file by a linker so that it can run on an electronic device.

[0093] It should be further noted that in various embodiments of the present disclosure, the execution order of various steps of the compiling method is not limited, although the execution process of various steps is described in a specific order above, which does not constitute a limitation on the embodiments of the present disclosure. Various steps in the compiling method can be executed in series or in parallel, which can be determined according to actual needs.

[0094] For example, compared with the above description, the compiling method provided by at least one embodiment of the present disclosure can further include more or fewer steps, and the embodiments of the present disclosure are not limited thereto.

[0095] Figure 3 A schematic block diagram of a compiling device provided by at least one embodiment of the present disclosure is shown. The compiling device may, for example, be a compiler and can be located at a host end.

[0096] For example, as shown in Figure 3 The compiling device 300 provided by at least one embodiment of the present disclosure includes an acquisition module 301, a division module 302, a determination module 303, an insertion module 304, and a fusion module 305.

[0097] For example, the acquisition module 301 is configured to acquire an object operator.

[0098] For example, the division module 302 is configured to divide the object operator into a plurality of logical basic blocks according to implementation of the object operator, wherein the plurality of logical basic blocks include a first logical basic block and a second logical basic block.

[0099] For example, the determination module 303 is configured to determine a first instruction position in the first logical basic block according to a hardware attribute of a processor used to execute the object operator.

[0100] For example, the insertion module 304 is configured to insert at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block according to an instruction dependency relationship between the plurality of logical basic blocks.

[0101] For example, the fusion module 305 is configured to integrate the inserted at least one instruction into a control instruction stream corresponding to the first logical basic block, and generate assembly code according to the integrated control instruction stream.

[0102] For example, in at least one embodiment of the present disclosure, the first logical basic block includes a storage instruction for processing a first data block, and the second logical basic block includes a prefetch instruction for processing at least part of a second data block, and the second data block is a next data block to be processed after the first data block.

[0103] For example, in at least one embodiment of the present disclosure, the first logical basic block is included in the first region, and the inserting module 304 is further configured to: in response to the second logical basic block being independent of the first logical basic block, split the first region into a first sub-region and a second sub-region according to the first instruction position, and insert the at least one instruction corresponding to the second logical basic block in the form of the second region between the first sub-region and the second sub-region, wherein the execution order is the first sub-region, the second region, and the second sub-region.

[0104] For example, in at least one embodiment of the present disclosure, the compiling device 300 further includes a marking module configured to mark the at least one instruction corresponding to the second logical basic block as a pluggable instruction sequence before inserting the at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block, so that the at least one instruction is inserted into the first instruction position in the first logical basic block.

[0105] For example, in at least one embodiment of the present disclosure, the fusing module is further configured to generate the fused control instruction stream according to the execution order of the regions corresponding to the plurality of logical basic blocks after inserting the at least one instruction corresponding to the second logical basic block at the first instruction position.

[0106] For example, in at least one embodiment of the present disclosure, the hardware attribute includes at least one of a number of cache regions, a bandwidth for storing instructions, and a computing capability.

[0107] For example, in at least one embodiment of the present disclosure, the determining module is further configured to determine the first instruction position in the first logical basic block based on an execution time of the instruction in the first logical basic block and an execution time of the instruction in the second logical basic block.

[0108] For example, in at least one embodiment of the present disclosure, the first logical basic block further includes a function post-processing instruction, and before executing the storage instruction in the first logical basic block, the processor executes the function post-processing instruction to perform optimization processing on the calculation result of the first data block.

[0109] For example, in at least one embodiment of the present disclosure, the plurality of logical basic blocks further include a third logical basic block, and the first logical basic block depends on the third logical basic block, and the third logical basic block includes a loading instruction and a calculation instruction for processing the first data block.

[0110] It should be noted that the above various modules and units can be implemented by software, hardware, firmware, or any combination thereof, for example, the obtaining module, the dividing module, and the inserting module can be respectively implemented as an obtaining circuit, a dividing circuit, and an inserting circuit, and embodiments of the present disclosure do not limit the specific implementation thereof.

[0111] It should be noted that the compiling apparatus 300 provided in at least one embodiment of the present disclosure can be used to implement the foregoing compiling method, and can also achieve similar technical effects to the foregoing compiling method, which will not be described herein.

[0112] It should be noted that in the embodiments of the present disclosure, the compiling apparatus 300 can include more or fewer modules or units, and the connection relationship between the modules or units is not limited and can be determined according to actual needs. The specific implementation manner of each module or unit is not limited and can be constituted by an analog device according to the circuit principle, or can be constituted by a digital chip, or constituted in other applicable manners.

[0113] For example, some embodiments of the present disclosure also provide an electronic device.

[0114] Figure 4 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown. As shown in the figure, the electronic device 400 can include at least one processor 401 and at least one memory 402. The at least one memory 402 stores program code, which when executed by the at least one processor 401, causes the at least one processor 401 to perform the steps of the compiling method according to the embodiments of the present disclosure. Figure 4

[0115] For example, the processor 401 can be any one of a graphics processor, a tensor processor, a neural network processor, a deep learning processor, an acceleration processor, a general-purpose graphics processor, and a multi-core processor with artificial intelligence computing capability, in addition to any conventional processor. For example, the processor here can refer to a processor chip capable of parallel computing.

[0116] For example, the memory 402 stores computer readable code which, when executed by the processor 401, can cause the processor 401 to implement the steps of the compiling method according to the embodiments of the present disclosure. The memory 402 can be any suitable type of memory. For example, by executing the computer readable code in the memory 402, the processor 401 can implement the steps of the compiling method described above in conjunction with the accompanying drawings.

[0117] ​It can be understood that the electronic device according to the embodiments of the present disclosure can implement cross-module instruction scheduling by inserting the at least one instruction corresponding to the second logical basic block into the first instruction position in the first logical basic block according to the compiling method as described above. The passing of instructions (or instruction sequences) between the logical basic blocks instead of the passing of data dependencies can avoid the strong coupling between the logical basic blocks due to the data dependencies (for example, the data dependencies make the logical basic blocks have to pay attention to the underlying implementation details of each other, such as details of how data is generated, stored, and passed, which leads to the need to adjust other associated logical basic blocks when modifying one logical basic block), thereby decoupling the code logic and reducing the complexity of the code, and the developer can no longer need to manually write the insertion logic of the instructions, thereby implementing the automation of instruction insertion (or instruction injection) and reducing the cost of manual optimization. The specific steps performed by the electronic device according to the embodiments of the present disclosure can refer to the description of the compiling method according to the present disclosure above, which will not be repeated here.

[0118] Figure 5 An architecture schematic of another electronic device according to at least one embodiment of the present disclosure is shown. Figure 5 The electronic device shown is merely an example and should not impose any limitation on the functions and use range of the embodiments of the present disclosure.

[0119] The electronic device in the at least one embodiment of the present disclosure can include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a Personal Digital Assistant (PDA), a tablet computer (PAD), a Portable Multimedia Player (PMP), a vehicle terminal (for example, a car navigation terminal), a wearable electronic device, and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like. Figure 5 The electronic device shown is merely an example and should not impose any limitation on the functions and use range of the embodiments of the present disclosure.

[0120] The electronic device includes at least one processor and a memory. The processor here can be referred to as the processing apparatus 501 described below, and the memory can include at least one of a Read-Only Memory (ROM), a Random Access Memory (RAM), and a storage device 508. The memory is used to store a program for executing the methods described in the various method embodiments above; and the processor is configured to execute the program stored in the memory. The processor can be a Central Processing Unit (CPU) or other forms of processing units having data processing and / or instruction execution capabilities, and can control other components in the electronic device to perform desired functions.

[0121] For example, as Figure 5As shown, in some examples, the electronic device 500 includes a processing device 501 (e.g., a central processor, a graphics processor, etc.) that can perform various appropriate actions and processes according to programs stored in a Read-Only Memory (ROM) or loaded into a Random Access Memory (RAM) from the storage device 508. In the RAM 503, various programs and data required for the operation of the computer system are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other by a bus 504. An Input / Output (I / O) interface is also connected to the bus 504.

[0122] For example, the following components can be connected to the I / O interface 505: input devices 506 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 507 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, etc.; storage devices 508 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 509 including, for example, a LAN card, a modem, etc. The communication devices 509 can allow the electronic device 500 to perform communication with other devices to exchange data, perform communication processing via a network such as the Internet, wirelessly or by wire. Although Figure 5 The electronic device 500 is shown to include various devices, but it should be understood that not all of the shown devices are required to be implemented or included. More or fewer devices can alternatively be implemented or included.

[0123] For example, the electronic device 500 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, for example, a USB interface, a lighting interface, etc. The communication devices 509 can communicate with networks and other devices by wireless communication.

[0124] For example, according to at least one embodiment of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, at least one embodiment of the present disclosure includes a computer program product including a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network by the communication devices 509, or installed from the storage devices 508, or installed from the ROM 502. When the computer program is executed by the processing devices 501, the above-mentioned functions defined in the methods of at least one embodiment of the present disclosure are performed.

[0125] It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium may, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In at least one embodiment of the present disclosure, the computer readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus or device. In at least one embodiment of the present disclosure, the computer readable signal medium can include a data signal carried in a baseband or as a part of a carrier wave, which carries computer readable program code. Such a propagated data signal can take various forms, including but not limited to an electromagnetic signal, an optical signal or any suitable combination of the above. The computer readable signal medium can also be any computer readable medium other than the computer readable storage medium, which can send, transmit or propagate the program for use by or in connection with an instruction execution system, apparatus or device. The program code contained in the computer readable medium can be transmitted by any suitable medium, including but not limited to a wire, a cable, a radio frequency (RF) or the like, or any suitable combination of the above.

[0126] The computer readable medium described above can be included in the electronic device 500 described above; or can exist separately and not be assembled into the electronic device 500.

[0127] Embodiments of the present disclosure also provide a non-transitory computer readable storage medium having computer readable instructions stored thereon, which, when executed by a processor, cause the processor to perform the steps of the compiling method according to the present disclosure.

[0128] Figure 6 A schematic block diagram of a non-transitory computer readable storage medium provided for at least one embodiment of the present disclosure is shown.

[0129] For example, as shown in Figure 6 The non-transitory computer readable storage medium 600 stores computer readable instructions 601, which, when executed by at least one processor, perform one or more steps of the compiling method described above.

[0130] For example, the storage medium can include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage medium. For example, the readable storage medium can also be the memory 402 in the computer 400 in FIG. 1, and the relevant description can refer to the foregoing, which will not be repeated here. Figure 4 The memory 402 in the computer 400 in FIG. 1 can also be the readable storage medium, and the relevant description can refer to the foregoing, which will not be repeated here.

[0131] Embodiments of the present disclosure provide a compiling method and device, an electronic device, and a storage medium. By using the compiling method and device, the electronic device, and the storage medium provided by the present disclosure, cross-module instruction scheduling can be achieved. By passing instructions (or instruction sequences) between logical basic blocks instead of passing data dependency relationships, strong coupling between the logical basic blocks due to data dependency relationships (for example, the data dependency relationship makes the logical basic blocks have to pay attention to the underlying implementation details of each other, such as details of how data is generated, stored, and transmitted, so that when one logical basic block is modified, other associated logical basic blocks need to be adjusted synchronously) can be avoided, thereby decoupling code logic and reducing the complexity of the code. Moreover, the developer no longer needs to manually write insertion logic of instructions, thereby achieving automation of instruction insertion (or instruction injection) and reducing the cost of manual optimization.

[0132] Although the present disclosure has been described in detail in the foregoing general description and specific embodiments, modifications and improvements can be made to the present disclosure on the basis of the embodiments of the present disclosure, which will be apparent to those skilled in the art. Therefore, these modifications or improvements made on the basis of the spirit of the present disclosure are within the scope of protection of the present disclosure.

[0133] For the present disclosure, the following points need to be explained:

[0134] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0135] (2) For the sake of clarity, the thickness of a layer or region is exaggerated or reduced in the drawings used to describe the embodiments of the present disclosure, that is, the drawings are not drawn according to the actual proportions.

[0136] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0137] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A compilation method, characterized in that, The compilation method includes: Get the object operator; Based on the implementation of the object operator, the object operator is divided into multiple logical basic blocks, wherein the multiple logical basic blocks include a first logical basic block and a second logical basic block; The location of the first instruction in the first logical basic block is determined based on the hardware attributes of the processor used to execute the object operator; Based on the instruction dependencies between the plurality of logical basic blocks, at least one instruction from the second logical basic block is inserted into the first instruction position in the first logical basic block; The inserted at least one instruction is incorporated into the control instruction stream corresponding to the first logic basic block, and assembly code is generated based on the fused control instruction stream.

2. The compilation method according to claim 1, characterized in that, The first logical basic block includes storage instructions for processing the first data block. The second logic block includes a prefetch instruction for processing at least a portion of the data of a second data block, which is the next data block to be processed after the first data block.

3. The compilation method according to claim 1 or 2, characterized in that, The first logical basic block is included in the first region. The step of inserting at least one instruction from the second logical basic block into the first instruction position in the first logical basic block according to the instruction dependency relationship between the plurality of logical basic blocks includes: In response to the second logic block being independent of the first logic block, the first region is split into a first sub-region and a second sub-region according to the first instruction position, and at least one instruction from the second logic block is inserted between the first sub-region and the second sub-region in the form of a second region, wherein the instruction execution order is the first sub-region, the second region, and the second sub-region.

4. The compilation method according to claim 1 or 2, characterized in that, Before inserting at least one instruction from the second logic block into the first instruction position in the first logic block, the method further includes: At least one instruction in the second logic block is marked as a pluggable instruction sequence so that the at least one instruction is inserted into a first instruction position in the first logic block.

5. The compilation method according to claim 1 or 2, characterized in that, The step of integrating the inserted at least one instruction into the control instruction stream corresponding to the first logic basic block includes: After inserting at least one instruction corresponding to the second logic block at the first instruction position, the fused control instruction stream is generated according to the execution order of the regions corresponding to the plurality of logic blocks.

6. The compilation method according to claim 1 or 2, characterized in that, The hardware attributes include at least one of the following: the number of cache regions, the bandwidth used to store instructions, and computing power.

7. The compilation method according to claim 6, characterized in that, Determining the first instruction location in the first logical basic block based on the hardware attributes of the processor used to execute the object operator includes: The location of the first instruction in the first logical block is determined based on the execution time of the instructions in the first logical block and the execution time of the instructions in the second logical block.

8. The compilation method according to claim 2, characterized in that, The first basic logic block also includes post-processing instructions. Before executing the storage instructions in the first logical basic block, the processor for executing the object operator executes the post-processing instructions to optimize the calculation results of the first data block.

9. The compilation method according to claim 2, characterized in that, The plurality of logical basic blocks further includes a third logical basic block, the first logical basic block depends on the third logical basic block, and the third logical basic block includes loading instructions and calculation instructions for processing the first data block.

10. An electronic device, characterized in that, The electronic device includes: At least one processor; and At least one memory, The at least one memory stores program code, which, when executed by the at least one processor, causes the at least one processor to perform the compilation method according to any one of claims 1-9.

11. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer-readable instructions, which, when executed by at least one processor, cause the processor to perform the compilation method according to any one of claims 1-9.

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