Chip debugging apparatus and chip

Abstract

The chip debugging device provided by the embodiment of the present disclosure comprises a multi-input bridge, a master control module, a plurality of relay modules and a plurality of adaptation modules; the multi-input bridge is connected with the master control module, the master control module is connected with the plurality of relay modules; different relay modules are connected with different adaptation modules; different adaptation modules are connected with different debugging objects in the chip; the multi-input bridge is used for sending the received debugging instruction to the master control module; the master control module is used for sending the debugging instruction to the corresponding relay module, so that the relay module sends the debugging instruction to the connected adaptation module, the debugging instruction is sent to the connected debugging object by the adaptation module, and the debugging object is debugged; the adaptation module is used for receiving the response information sent by the debugging object, and sending the response information to the master control module through the relay module, and the master control module outputs the response information through the multi-input bridge. The present scheme can improve the reliability of debugging the chip.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more particularly to a chip debugging device and a chip. Background Technology

[0002] Chip debugging is mainly used to diagnose and repair various anomalies or defects in the chip design, manufacturing and application process. When debugging a System on Chip (SoC), the peripherals of the Central Processing Unit (CPU) are the debugging objects. Debugging of the debugging objects can be achieved by accessing the register resources of the peripherals.

[0003] Currently, when debugging a chip, the CPU in the chip relays the debugging commands to the target object via the chip's internal peripheral bus to achieve debugging of the target object.

[0004] However, if some areas of the chip fail or some paths of the peripheral bus fail, debugging commands cannot be sent to the target being debugged, making it impossible to debug at least some of the target being debugged. Therefore, the reliability of debugging the chip is low. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a chip debugging apparatus and a chip to solve or at least alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a chip debugging apparatus is provided, comprising: a multi-input bridge, a main control module, multiple relay modules, and multiple adapter modules; the multi-input bridge is connected to the main control module, and the main control module is connected to the multiple relay modules; the relay modules are connected to the adapter modules, and different relay modules are connected to different adapter modules; the adapter modules are connected to a debugging object included in the chip, and different adapter modules are connected to different debugging objects; the multi-input bridge is used to send received debugging instructions to the main control module; the main control module is used to send the debugging instructions to the corresponding relay module, so that the relay module sends the debugging instructions to the connected adapter module, and the adapter module sends the debugging instructions to the connected debugging object for debugging the debugging object; the adapter module is used to receive response information issued by the connected debugging object based on the debugging instructions, and send the response information to the connected relay module, so that the relay module sends the response information to the main control module, and the main control module outputs the response information through the multi-input bridge.

[0007] According to a second aspect of the present disclosure, a chip is provided, including the chip debugging apparatus described in the first aspect above.

[0008] The above technical solution constructs a transmission path for debugging commands and response information through a multi-input bridge, a main control module, a relay module, and an adapter module. Debugging commands are sequentially transmitted to the target object via these modules. Response information from the target object is output sequentially via the adapter module, relay module, main control module, and multi-input bridge. Debugging is achieved by sending debugging commands to the target object, and the debugging result and status are determined by outputting response information. This transmission path, constructed by the multi-input bridge, main control module, relay module, and adapter module, is independent of the chip's peripheral bus. Debugging commands do not require CPU relay. Failure of certain areas within the chip or partial failure of peripheral bus pathways does not affect chip debugging, allowing for more comprehensive chip debugging and improving its reliability. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0010] Figure 1 This is a schematic diagram of a chip according to an embodiment of the present disclosure;

[0011] Figure 2 This is a schematic diagram of a chip debugging apparatus according to an embodiment of the present disclosure;

[0012] Figure 3 This is a schematic diagram of a chip debugging apparatus according to another embodiment of the present disclosure;

[0013] Figure 4 This is a schematic diagram of a chip debugging apparatus according to yet another embodiment of the present disclosure;

[0014] Figure 5 This is a schematic diagram of the main control module according to an embodiment of this disclosure;

[0015] Figure 6 This is a schematic diagram of the main control module according to another embodiment of this disclosure;

[0016] Figure 7 This is a schematic diagram of a transmitting unit according to an embodiment of the present disclosure;

[0017] Figure 8 This is a schematic diagram of a receiving unit according to an embodiment of the present disclosure;

[0018] Figure 9This is a schematic diagram of the parallel port timing used by the transmitting unit and the receiving unit according to an embodiment of this disclosure;

[0019] Figure 10 This is a schematic diagram of an adapter module according to an embodiment of this disclosure;

[0020] Figure 11 This is a schematic diagram of a relay module according to an embodiment of this disclosure;

[0021] Figure 12 This is a schematic diagram of a routing module according to an embodiment of this disclosure;

[0022] Figure 13 This is a schematic diagram of an endpoint module according to an embodiment of the present disclosure;

[0023] Figure 14 This is a schematic diagram of the transmission timing used by the protocol layer of a chip debugging apparatus according to an embodiment of the present disclosure;

[0024] Figure 15 This is a schematic diagram of the protocol layer data organization of a chip debugging apparatus according to an embodiment of the present disclosure. Detailed Implementation

[0025] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0026] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0027] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0028] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0029] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0030] First, some nouns or terms that appear in the description of the embodiments of this disclosure shall be interpreted as follows:

[0031] Chip: Also known as an integrated circuit (IC), a chip is a miniature electronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) onto a small semiconductor material. Based on their function and application, chips can be classified into various types, such as central processing units (CPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0032] System-on-a-Chip (SoC): A SoC is a highly integrated chip that integrates a processor (CPU), memory (such as RAM and ROM), input / output interfaces, communication modules, analog signal processing modules, and many other functions onto a single chip, forming a complete system. Its core idea is to condense a complex electronic system into a single chip, thereby achieving design goals such as high performance, low power consumption, small size, and low cost.

[0033] Peripheral Bus: A peripheral bus is a communication bus used to connect the processor and other peripheral devices (such as input / output devices, storage devices, etc.), enabling data transmission and control signal exchange between the processor and peripheral devices.

[0034] Multiplexer: A multiplexer (MUX) is an important digital logic circuit used to select one signal from multiple input signals for output. It is widely used in digital systems for data selection, signal switching, bus control and other scenarios.

[0035] The chip debugging apparatus and chip provided in the embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0036] chip

[0037] Figure 1 A schematic diagram of a chip according to an embodiment of this disclosure is shown. (As follows) Figure 1 As shown, chip 100 includes a chip debugging device 10 and multiple debugging objects 20. The chip debugging device 10 and the debugging objects 20 are connected. The chip debugging device 10 is a circuit used to debug the debugging objects 20. The debugging objects 20 can be peripheral devices of the CPU in the chip, such as memory (e.g., random access memory, read-only memory, and cache), input / output interfaces, communication modules, analog signal processing modules, power management modules, clock systems, memory controllers, and security modules. The chip debugging device 10 and the debugging objects 20 are packaged in the same chip, for example, the chip debugging device 10 and the debugging objects 20 are packaged in the same SoC.

[0038] In one embodiment, the chip debugging device 10 can be connected to an external debugging device via an interface. The debugging device sends debugging commands to the chip debugging device 10, which then sends these commands to one or more corresponding debugging objects 20 to perform debugging on the debugging objects 20. After completing the debugging action based on the received debugging commands, the debugging object 20 can send response information to the chip debugging device 10. The chip debugging device 10 then sends the response information back to the debugging device, enabling the debugging device to determine the debugging status and result of the debugging object 20. The debugging device can be any device suitable for sending debugging commands and receiving response information, such as a portable computer, server, handheld device, or chip.

[0039] In another embodiment, the chip debugging device 10 is connected to a processing unit (such as a CPU) in the chip 100. The processing unit can send debugging commands to the chip debugging device 10, and the chip debugging device 10 sends the debugging commands to one or more corresponding debugging objects 20 to debug the debugging objects 20. After the debugging object 20 completes the debugging action based on the received debugging commands, it can send response information to the chip debugging device 10. The chip debugging device 10 sends the response information to the processing unit so that the processing unit can determine the debugging status and debugging result of the debugging object 20.

[0040] Multiple chips 100, each including a chip debugging device 10, can be interconnected. One chip 100 serves as the master chip, and the remaining chips 100 serve as slave chips. The master chip can send debugging commands to the chip debugging devices 10 included in each slave chip through its chip debugging device 10, so as to debug the debugging object 20 included in each slave chip.

[0041] Chip debugging device

[0042] Figure 2 A schematic diagram of a chip debugging apparatus according to an embodiment of this disclosure is shown. Figure 2 As shown, the chip debugging device 10 includes a multi-input bridge 11, a main control module 12, multiple relay modules 13 and multiple adapter modules 14.

[0043] The multi-input bridge 11 is connected to the main control module 12, and the main control module 12 is connected to multiple relay modules 13. Each relay module 13 is connected to an adapter module 14, and different relay modules 13 are connected to different adapter modules 14. Each adapter module 14 is connected to a debugging object 20, and different adapter modules 14 are connected to different debugging objects 20.

[0044] The multi-input bridge 11 can receive debugging commands sent by external debugging devices to the chip 100. After receiving the debugging command, the multi-input bridge 11 can send the debugging command to the main control module 12. After receiving the debugging command, the main control module 12 can send the debugging command to the corresponding relay module 13. After receiving the debugging command, the relay module 13 can send the debugging command to the connected adapter module 14. The adapter module 14 can then send the received debugging command to the connected debugging object 20 for debugging of the debugging object 20.

[0045] The main control module 12 sends debugging commands to the corresponding relay module 13. The adapter module 14 connected to the relay module 13 is the destination adapter module for the debugging commands, and the debugging object 20 connected to the destination adapter module is the target of the debugging commands. When the main control module 12 sends debugging commands to the corresponding relay module 13, if the relay module 13 connected to the destination adapter module is directly connected to the main control module 12, then the main control module 12 directly sends the debugging commands to the corresponding relay module 13. If the relay module 13 connected to the destination adapter module is connected to the main control module 12 through at least one other relay module 13, then the main control module 12 forwards the debugging commands to the corresponding relay module 13 through the forwarding of at least one relay module 13.

[0046] After the adapter module 14 sends the debugging command to the connected debugging object 20, the debugging object 20 will send response information to the connected adapter module 14 based on the debugging command. Upon receiving the response information, the adapter module 14 can send it to the connected relay module 13. Upon receiving the response information, the relay module 13 can send it to the main control module 12. Upon receiving the response information, the main control module 12 can output it through the multi-input bridge 11, for example, by sending the response information to a debugging device outside the chip 100 via the multi-input bridge 11.

[0047] Between the main control module 12 and the adapter module 14, the transmission paths for debugging commands and response information are the same, but the transmission directions are opposite. Debugging commands are transmitted from the main control module 12 to the adapter module 14, and response information is transmitted from the adapter module 14 to the main control module 12.

[0048] In this embodiment, a transmission path for debugging commands and response information is constructed using a multi-input bridge 11, a main control module 12, a relay module 13, and an adapter module 14. Debugging commands are transmitted sequentially to the debugging object 20 via the multi-input bridge 11, the main control module 12, the relay module 13, and the adapter module 14. Response information from the debugging object 20 is output sequentially via the adapter module 14, the relay module 13, the main control module 12, and the multi-input bridge 11. Debugging of the debugging object 20 is achieved by sending debugging commands to it, and the debugging result and status are determined by outputting response information. The transmission path constructed by the multi-input bridge 11, the main control module 12, the relay module 13, and the adapter module 14 is independent of the peripheral bus in the chip 100. Debugging commands do not need to be relayed through the CPU. Failure of some areas of the chip 100 or failure of some peripheral bus paths does not affect the debugging of the chip, thus allowing for more comprehensive debugging of the chip 100 and improving the reliability of debugging the chip 100.

[0049] In one possible implementation, such as Figure 3As shown, chip 100 includes a peripheral bus 30 and a processing unit 40, with the peripheral bus 30 connected to the processing unit 40. The processing unit 40 may be a CPU. In addition to being connected to the relay module 13, the adapter module 14 is also connected to the processing unit 40 via the peripheral bus 30. The adapter module 14 is connected to the debugging object 20 via the peripheral bus 30.

[0050] Within chip 100, processing unit 40 communicates with debugging object 20 via peripheral bus 30. Processing unit 40 sends access requests to debugging object 20 via peripheral bus 30 to perform data processing and logic control tasks. When debugging chip 100, adapter module 14 transmits debugging instructions and response information between relay module 13 and debugging object 20. To ensure that processing unit 40 and debugging object 20 can still communicate normally via peripheral bus 30, adapter module 14 is connected to debugging object 20 and processing unit 40 via peripheral bus 30. Processing unit 40 can send access requests to adapter module 14 via peripheral bus 30, and then adapter module 14 can send access requests to debugging object 20 via peripheral bus 30.

[0051] When debugging chip 100, relay module 13 sends debugging commands to adapter module 14. Adapter module 14 performs protocol conversion on the debugging commands to match the protocol of peripheral bus 30. Then, it sends the protocol-converted debugging commands to debugging object 20 via peripheral bus 30, which connects adapter module 14 and debugging object 20. Debugging object 20 generates response information based on the debugging commands and sends the response information to adapter module 14 via peripheral bus 30, which connects adapter module 14 and debugging object 20. Adapter module 14 performs protocol conversion on the response information to match the protocol of the bus used by chip debugging device 10, and then sends the protocol-converted response information to adapter module 14.

[0052] In one example, the peripheral bus 30 could be an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI) bus, or the like.

[0053] In this embodiment, the adapter module 14 is connected to the relay module 13 and also to the peripheral bus 30 in the chip 100. The adapter module 14 is connected to the debugging object 20 through the peripheral bus 30. The adapter module 14 can transmit debugging instructions and response information between the relay module 13 and the debugging object 20, and can also transmit access requests between the processing unit 40 and the debugging object 20. This ensures that the chip 100 works normally while the chip debugging device 10 can debug the chip 100.

[0054] In one possible implementation, such as Figure 4 As shown, the chip debugging device 10 also includes an internal bus 15 and at least one routing module 16. It should be noted that... Figure 4 The example chip debugging device 10 includes a routing module 16, while in other embodiments the chip debugging device 10 may include multiple routing modules 16.

[0055] The main control module 12, routing module 16, and multiple relay modules 13 are connected sequentially via an internal bus 15, forming a main-chain network. The routing module 16 is located between two relay modules 13 in the main-chain network, and the main control module 12 is located at the first end of the main-chain network. Figure 4 In the example chip debugging device 10, the main chain network includes a main control module 12, a routing module 16 and three relay modules 13. In other embodiments, the main chain network may include more routing modules 16 and more or fewer relay modules 13.

[0056] In addition to connecting to the two relay modules 13 in the main chain network, routing module 16 is also sequentially connected to at least one other relay module 13 via internal bus 15 to construct a slave chain network. Routing module 16 is located at the first end of the slave chain network. Each routing module 16 corresponds to one slave chain network, so the number of routing modules 16 is equal to the number of slave chain networks. Figure 4 In the chip debugging device 10 shown, the slave network includes a routing module 16 and two relay modules 13. In other embodiments, the slave network may include more or fewer relay modules 13.

[0057] The internal bus 15 can transmit communication data between the main control module 12 and the relay module 13, between the relay modules 13, between the relay module 13 and the routing module 16, and between the relay module 13 and the adapter module 14. The main control module 12 and the relay modules 13 can transmit debugging commands and response information via the interconnecting internal bus 15. Similarly, the relay modules 13, the routing module 16, and the adapter module 14 can all transmit debugging commands and response information via the interconnecting internal bus 15.

[0058] The debugging command includes the identification information of the target adapter module, and the debugging object 20 connected to the target adapter module is the debugging object targeted by the debugging command. After receiving the debugging command, the routing module 16 can determine whether the target adapter module is located in the main chain network or the slave chain network based on the identification information included in the debugging command. If the relay module 13 connected to the target adapter module is located in the main chain network, the routing module 16 sends the debugging command to the relay module 13 connected to it in the main chain network. If the relay module 13 connected to the target adapter module is located in the slave chain network, the routing module 16 sends the debugging command to the relay module 13 connected to it in the slave chain network.

[0059] In this embodiment, the main control module 12 and relay module 13, the relay modules 13 and each other, the relay module 13 and routing module 16, and the relay module 13 and adapter module 14 are connected via an internal bus 15. The internal bus 15 is used to transmit communication data related to chip debugging, such as debugging commands and response information. Debugging of the debugging object 20 is achieved through the internal bus 15, without using the external bus 30. This avoids the inability to debug at least some of the debugging objects 20 due to partial failure of parts of the chip 100 or partial failure of the external bus 30, thus improving the reliability of debugging the chip 100. A slave chain network can be extended through the routing module 16. Each slave chain network can connect one or more debugging objects 20. When there are many debugging objects 20 in the chip 100, it ensures that the chip debugging device 10 can connect to each debugging object 20, thereby ensuring the comprehensiveness of debugging the chip 100.

[0060] In one possible implementation, when the chip debugging device 10 includes a routing module 16, the chip debugging device 10 may also include multiple endpoint modules 17, with the second end of the main chain network and each slave chain network connected to an endpoint module 17. Figure 4 The example chip debugging device 10 has a master chain network and a slave chain network. The first end of the master chain network is the master control module 12, and the second end of the master chain network is the endpoint module 17. The first end of the slave chain network is the routing module 16, and the second end of the slave chain network is the endpoint module 17.

[0061] After the main control module 12 issues a debugging command, if the destination adapter module fails to issue a response due to a fault or other reason, that is, if the debugging command is not responded to by any adapter module 14, the endpoint module 17 can send a non-response message to the main control module 12 through the internal bus 15. Then, the main control module 12 can output the non-response message through the multi-input bridge 11. For example, the multi-input bridge 11 can send the non-response message to the debugging device.

[0062] If the relay module 13 to which the target adapter module is connected is located in the main chain network, the non-response message is sent by the endpoint module 17 connected to the second end of the main chain network. If the relay module 13 to which the target adapter module is connected is located in the slave chain network, the non-response message is sent by the endpoint module 17 connected to the second end of the slave chain network, where the relay module 13 to which the target adapter module is connected is located in the slave chain network.

[0063] If the non-response message is sent by endpoint module 17 located in the main chain network, the non-response message is transmitted to the master control module 12 through the main chain network. If the non-response message is sent by endpoint module 17 located in the slave chain network, the non-response message is first transmitted to the main chain network through the slave chain network, and then transmitted to the master control module 12 through the main chain network.

[0064] In this embodiment, after issuing the debugging command, the issuing end (debugging device) needs to send back the debugging result or debugging process information to ensure the integrity of the internal bus 15 transmission; otherwise, the issuing end cannot determine whether the debugging is complete. When an adapter module 14 responds to the debugging command, the chip debugging device 10 sends response information to the issuing end to ensure the integrity of the internal bus 15 transmission. By setting an endpoint module 17 at the second end of the master chain network and the slave chain network, when the debugging command is not responded to by any adapter module 14, the endpoint module 17 sends a non-response information to the issuing end to ensure the integrity of the internal bus 15 transmission.

[0065] In one possible implementation, such as Figure 4 As shown, the internal bus 15 includes a clock line CLK, an instruction data line CMD, an response data line RESP, and a select data line RESP_SEL.

[0066] The main control module 12 can send clock signals to the relay module 13, adapter module 14, routing module 16, and endpoint module 17 via the clock line CLK to drive these modules. The clock signal can be generated by the main control module 12 or sent to the main control module 12 by a debugging device; this embodiment of the present disclosure does not limit the specific method used.

[0067] The Command Data Line (CMD) is a downlink data line, allowing the main control module 12 to send debugging commands. Upon receiving a debugging command, the relay module 13 broadcasts the command via the Command Data Line (CMD) to the connected adapter module 14 and downstream relay modules 13 or routing modules 16. Upon receiving the debugging command, the routing module 16, if the target adapter module is connected to a relay module 13 in the main chain network, sends the debugging command to that relay module 13 in the main chain network via the Command Data Line (CMD). If the target adapter module is connected to a relay module 13 in the slave chain network, the routing module 16 sends the debugging command to that relay module 13 in the slave chain network via the Command Data Line (CMD).

[0068] The response data line RESP is an uplink data line, through which the adapter module 14 can send response information to the main control module 12. Upon receiving the response information, the adapter module 14 sends it to the connected relay module 13 via the response data line RESP. Upon receiving the response information, the relay module 13 sends it to the upstream main control module 12, relay module 13, or routing module 16 via the response data line RESP. Upon receiving the response information, the routing module 16 sends it to the upstream relay module 13 via the response data line RESP.

[0069] Endpoint module 17 can send a non-response message to the connected relay module 13 via the response data line RESP. Upon receiving the non-response message, relay module 13 sends the non-response message to the upstream master control module 12, relay module 13, or routing module 16 via the response data line RESP. Upon receiving the non-response message, routing module 16 sends the non-response message to the upstream relay module 13 via the response data line RESP.

[0070] By selecting the RESP_SEL data line as the downlink data line, the adapter module 14 can send a occupancy information to the endpoint module 17. This occupancy information indicates that the response data line RESP is occupied, preventing the endpoint module 17 from issuing a non-response message. After sending a response message to the connected relay module 13 via the response data line RESP, the adapter module 14 can send occupancy information to the connected relay module 13 via the RESP_SEL data line. Upon receiving the occupancy information, the relay module 13, through the RESP_SEL data line, sends the occupancy information to the connected endpoint module 17, the downstream relay module 13, or the downstream routing module 16. After receiving the occupancy information, if the relay module 13 connected to the target adapter module is located in the main chain network, the routing module 16 sends the occupancy information to the endpoint module 17 connected to the second end of the main chain network by selecting the data line RESP_SEL. If the relay module 13 connected to the target adapter module is located in the slave chain network, the routing module 16 sends the occupancy information to the endpoint module 17 connected to the second end of the slave chain network by selecting the data line RESP_SEL.

[0071] If endpoint module 17 receives a occupancy message, it means that adapter module 14 has responded to the debugging command and sent a response message through the response data line RESP. At this time, the response data line RESP is occupied, and endpoint module 17 no longer sends a non-response message to avoid bus conflict.

[0072] In this embodiment, the internal bus 15 includes a clock line CLK, an instruction data line CMD, a response data line RESP, and a select data line RESP_SEL. The clock line CLK is used to transmit clock signals, the instruction data line CMD is used to transmit debug instructions, the response data line RESP is used to transmit response information and non-response information, and the select data line RESP_SEL is used to transmit occupancy information. The internal bus 15, which includes four lines, meets the requirements for debugging the chip 100. Since the internal bus 15 includes a smaller number of signal lines, the area occupied by the chip debugging device 10 in the chip 100 can be reduced.

[0073] In one possible implementation, such as Figure 5 The schematic diagram of the main control module 12 shown includes a first receiving unit 121, a first transmitting unit 122, a control register 123, a parallel port controller 124, and a first multiplexer 125.

[0074] The first receiving unit 121 and the parallel port controller 124 are both connected to the multi-input bridge 11, and the first multiplexer 125 is connected to the first receiving unit 121, the first transmitting unit 122, the control register 123 and the parallel port controller 124.

[0075] The multi-input bridge 11 can be connected to a debugging device via an external bus 18. The debugging device connected to the external bus 18 can be another chip, including the chip debugging device 10. The external bus 18 and the internal bus 15 have the same protocol type. Figure 5 As shown, the external bus 18 includes a clock line CLK, an instruction data line CMD, and a response data line RESP. The clock line CLK is used for the debugging device to send a clock signal to the multi-input bridge 11. The instruction data line CMD is used for the debugging device to send debugging commands to the multi-input bridge 11. The response data line RESP is used for the multi-input bridge 11 to send response or non-response information to the debugging device. When the debugging device sends a debugging command to the multi-input bridge 11 through the external bus 18, the multi-input bridge 11 sends the received clock signal to the first receiving unit 121. The first transmitting unit 122 transmits this clock signal through the clock line CLK included in the internal bus 15. In the external bus 18, both the instruction data line CMD and the response data line RESP are synchronized with the clock line CLK. The first receiving unit 121 can send the received debugging command to the first multiplexer 125.

[0076] The multi-input bridge 11 can also connect to debugging devices via a Universal Asynchronous Receiver-Transmitter (UART) bus, a Serial Peripheral Interface (SPI) bus, etc. The debugging devices connected to the UART bus or SPI bus can be portable computers, servers, handheld devices, etc. The protocol supported by the internal bus 15 is different from the protocols supported by the UART bus and SPI bus. The multi-input bridge 11 includes a protocol conversion module. When the multi-input bridge 11 receives debugging commands via the UART bus or SPI bus, the protocol conversion module can convert the debugging commands to match the protocol of the internal bus 15, and then send the converted debugging commands to the parallel port controller 124. For example, the protocol conversion module can convert the debugging commands into parallel interface data and send it to the parallel port controller 124. The parallel port controller 124 can then send the received debugging commands to the first multiplexer 125.

[0077] When the first transmitting unit 122 sends a debugging command from the parallel port controller 124 or the control register 123, the main control module 12 transmits the clock signal based on the clock signal generated by the clock source inside the chip 100 through the clock line CLK included in the internal bus 15.

[0078] The control register 123 is connected to the peripheral bus 30, which can be an APB bus, an AXI bus, etc. The processing unit 40 included in the chip 100 is connected to the peripheral bus 30. The processing unit 40 can send debugging commands to the control register 123 through the peripheral bus 30. The control register 123 performs protocol conversion on the debugging commands and sends them to the first multiplexer 125.

[0079] The first multiplexer 125 can receive debugging commands from the first receiving unit 121, the control register 123, or the parallel port controller 124, and send the received debugging commands to the first sending unit 122. When multiple of the first receiving unit 121, the control register 123, and the parallel port controller 124 simultaneously send debugging commands to the first multiplexer 125, the first multiplexer 125 receives the debugging command sent by the one with the highest priority among the first receiving unit 121, the control register 123, and the parallel port controller 124 according to a preset priority.

[0080] After receiving the debugging command, the first sending unit 122 can send the received debugging command to the corresponding adapter module 14 through the internal bus 15. Specifically, the first sending unit 122 sends the debugging command to the connected relay module 13, and the relay module 13 sends the debugging command to the corresponding adapter module 14.

[0081] It should be noted that the above embodiments illustrate the processing procedure of the main control module 12 for debugging commands. The transmission paths of response and non-response information are the same as those of the debugging commands, but the transmission directions of response and non-response information are opposite to those of the debugging commands. After receiving the response or non-response information, the first sending unit 122 returns the response or non-response information along the original path according to the source of the debugging command. If the debugging command comes from the first receiving unit 121, the first sending unit 122 sends the response or non-response information to the first receiving unit 121 through the first multiplexer 125, and the first receiving unit 121 sends the response or non-response information to the debugging device through the multi-input bridge 11. If the debugging command comes from the parallel port controller 124, the first sending unit 122 sends the response or non-response information to the parallel port controller 124 through the first multiplexer 125, and the parallel port controller 124 sends the response or non-response information to the debugging device through the multi-input bridge 11. If the debugging instruction comes from the control register 123, the first sending unit 122 sends the response information or non-response information to the control register 123 through the first multiplexer 125, and the control register 123 sends the response information or non-response information to the processing unit 40 in the chip 100.

[0082] After receiving a response or non-response message, the control register 123 converts the response or non-response message to a protocol compatible with the peripheral bus 30, and then sends the protocol-converted response or non-response message to the processing unit 40 via the peripheral bus 30. After the parallel port controller 124 sends the response or non-response message to the multi-input bridge 11, the protocol conversion module in the multi-input bridge 11 converts the response or non-response message to a protocol compatible with the UART bus or SPI bus, and then sends the response or non-response message to the debugging device via the UART bus or SPI bus.

[0083] In this embodiment, the main control module 12 includes a first receiving unit 121, a control register 123, and a parallel port controller 124. The first receiving unit 121 can receive debugging commands input through the external bus 18, the control register 123 can receive debugging commands input through the peripheral bus 30, and the parallel port controller 124 can receive debugging commands input through the UART bus or SPI bus, etc. Thus, the chip debugging device 10 supports debugging commands from multiple sources, improving the applicability of the chip debugging device 10.

[0084] In one possible implementation, such as Figure 6 As shown, the main control module 12 also includes a second transmitting unit 126, which is connected to the multi-input bridge 11 and the control register 123.

[0085] The processing unit 40 can send off-chip debugging instructions to the control register 123 via the peripheral bus 30. These off-chip debugging instructions are used to debug another chip. After receiving the off-chip debugging instructions, the control register 123 can send them to the second sending unit 126. The second sending unit 126 can then send the off-chip debugging instructions to the multi-input bridge 11. In turn, the multi-input bridge 11 can send the off-chip debugging instructions to the chip debugging device 10 in another chip, thereby enabling debugging of the target chip in the other chip.

[0086] The second transmitting unit 126 is connected to the multi-input bridge 11 via a clock line CLK, an instruction data line CMD, and a response data line RESP. The multi-input bridge 11 is connected to another chip via an external bus 18. The second transmitting unit 126 sends a clock signal to the multi-input bridge 11 via the clock line CLK. The second transmitting unit 126 sends an external debugging command to the multi-input bridge 11 via the instruction data line CMD. The multi-input bridge 11 sends response or non-response information to the second transmitting unit 126 in response to the external debugging command via the response data line RESP. The multi-input bridge 11 sends a clock signal to the other chip via the clock line CLK included in the external bus 18. The multi-input bridge 11 sends an external debugging command to the other chip via the instruction data line CMD. The multi-input bridge 11 receives response or non-response information from the other chip in response to the external debugging command via the response data line RESP.

[0087] In this embodiment of the present disclosure, the control register 123 can receive off-chip debugging instructions sent by the processing unit 40 in the chip 100. After the control register 123 sends the off-chip debugging instructions to the second sending unit 126, the second sending unit 126 can send the off-chip debugging instructions to the chip debugging device 10 in another chip through the multi-input bridge 11, so as to realize the debugging of another chip through the current chip, which improves the convenience of debugging chips in a multi-chip system.

[0088] In one possible implementation, Figure 7 A schematic diagram of a transmitting unit according to an embodiment of this disclosure is shown. The structures of the first transmitting unit 122 and the second transmitting unit 126 can both be the same as the structure of this transmitting unit. Figure 7 As shown, the transmitting unit includes a transceiver state machine, a transceiver counter, a shift register, and an ID lookup table. The transmitting unit can accept parallel port input, translate it through the ID lookup table, load data conforming to the protocol layer specifications into the shift register, and transmit it bit by bit under the control of the transceiver counter.

[0089] In one possible implementation, Figure 8 A schematic diagram of a receiving unit according to an embodiment of this disclosure is shown. The structure of a first receiving unit 121 may be the same as that of this receiving unit. The receiving unit can receive instructions transmitted on the bus according to pre-configured parameters. Figure 8 As shown, the receiving unit includes a transceiver state machine, a transceiver counter, and multiple independent shift registers (ID shift register, control word shift register, address shift register, and data shift register). When the receiving unit hears a new transmission on the bus, it first uses the ID shift register to match the pre-configured ID. Only when the ID matches successfully will the other shift registers start working to obtain the complete transmission command. Subsequently, the receiving unit exchanges data completely with the subsequent stage through the parallel port.

[0090] In one possible implementation, the parallel port timing used by the transmitting and receiving units is as follows: Figure 9 As shown. In Figure 9 In the timing diagram shown, ckl is the clock signal, wr_en is the read / write enable signal (active high), wr_data_mode is the data length control signal, wr_flag is the read / write operation control signal, wr_data is the data being written, wr_add is the address being written, err_resp is the read / write operation error indicator signal (active high indicates a read / write operation error has occurred), wr_real_done_resp is the read / write operation completion indicator signal, rdata_vd is the read data valid indicator signal (active high indicates the read data is valid at the current moment), and rdata_dout is the read data complete indicator signal.

[0091] wr_en, wr_data_mode, wr_flag, wr_data, and wr_add are driven by the master side, while err_resp, wr_real_done_resp, rdata_vd, and rdata_dout are driven by the slave side. A transmission must be initiated by the master. The master uses a high level on the wr_en signal to indicate that wr_data_mode, wr_flag, wr_data, and wr_addr are valid. Subsequently, the slave can, after any time interval, indicate that a write operation is complete by using a high level on wr_read_done_resp or that a read operation is valid by using a high level on rdata_vd.

[0092] In one possible implementation, such as Figure 10 The schematic diagram of the adapter module 14 shown includes a second receiving unit 141, a protocol generator 142, and a second multiplexer 143. The protocol generator 142 is connected to the second receiving unit 141 and the second multiplexer 143. The second receiving unit 141 is connected to the relay module 13, and the second multiplexer 143 is connected to the debugging object 20 and the peripheral bus 30.

[0093] The second receiving unit 141 can receive debugging instructions from the relay module 13 and send the received debugging instructions to the protocol generator 142. The protocol generator 142 can perform protocol conversion on the received debugging instructions, converting them to a protocol compatible with the peripheral bus 30. For example, when the peripheral bus 30 is an APB bus, the debugging instructions are converted to a protocol compatible with the APB bus; when the peripheral bus 30 is an AXI bus, the debugging instructions are converted to a protocol compatible with the AXI bus. After performing protocol conversion, the protocol generator 142 sends the converted debugging instructions to the second multiplexer 143. The processing unit 40 in the chip 100 can send an access request to the second multiplexer 143 via the peripheral bus 30. The second multiplexer 143 can select either the debugging instructions from the protocol generator 142 or the access request from the processing unit 40 to send to the debugging object 20.

[0094] The protocol used by the second multiplexer 143 to transmit data with the protocol generator 142 and the debug object 20 is the same as the protocol used by the peripheral bus 30. For example, when the peripheral bus 30 is an APB bus, the second multiplexer 143 transmits data with the debug object 20 and the protocol generator 142 through the APB bus protocol; when the peripheral bus 30 is an AXI bus, the second multiplexer 143 transmits data with the debug object 20 and the protocol generator 142 through the AXI bus protocol.

[0095] The second multiplexer 143 can select data from the peripheral bus 30 or the protocol generator 142 according to a preset priority and send it to the debugging object 20.

[0096] In this embodiment, the protocol generator 142 included in the adapter module 14 can convert the debugging instructions from the relay module 13 to a protocol that matches the peripheral bus 30. Therefore, the debugging instructions transmitted by the protocol generator 142 to the second multiplexer 143 have the same protocol type as the access requests transmitted by the peripheral bus 30 to the second multiplexer 143. Thus, the adapter module 14 can be seamlessly integrated into the chip 100 without modifying the code of the debugging object 20 and the peripheral bus 30. The adapter module 14 can be directly inserted in front of the debugging object 20 to enable access to the debugging object 20. While enabling debugging through the internal bus 15, it ensures that the processing unit 40 can access the debugging object 20 normally.

[0097] In one possible implementation, such as Figure 11 The schematic diagram of the relay module 13 shown includes a first register 131, a second register 132, a third register 133, a first logic OR unit 134, and a third multiplexer 135.

[0098] If relay module 13 is connected to main control module 12, then first register 131 is connected to main control module 12, and first register 131 can receive debugging commands sent by main control module 12. If relay module 13 is connected to an upstream relay module 13, then first register 131 is connected to upstream relay module 13, and first register 131 can receive debugging commands sent by upstream relay module 13.

[0099] The first register 131 is also connected to the adapter module 14 and to either the downstream relay module 13 or the endpoint module 17. If the relay module 13 is connected to the downstream relay module 13, then the first register 131 is connected to the downstream relay module 13, and the first register 131 can send received debugging commands to both the connected adapter module 14 and the downstream relay module 13. If the relay module 13 is connected to the endpoint module 17, then the first register 131 is connected to the endpoint module 17, and the first register 131 can send received debugging commands to both the connected adapter module 14 and the endpoint module 17.

[0100] The first logic OR unit 134 is connected to the upstream relay module 13, the adapter module 14, and the third register 133. The upstream relay module 13 and the adapter module 14 can send occupancy information to the first logic OR unit 134. Upon receiving the occupancy information from the upstream relay module 13 or the adapter module 14, the first logic OR unit 134 sends occupancy information to the third register 133. After receiving the occupancy information, the third register 133 can send the occupancy information to the connected downstream relay module 13 or the endpoint module 17.

[0101] The third multiplexer 135 is connected to the adapter module 14 and the downstream relay module 13 or endpoint module 17, and is also connected to the second register 132, which is connected to the upstream relay module 13 or master control module 12. The third multiplexer 135 receives response information from the connected adapter module 14 or downstream relay module 13 and sends the received response information to the connected second register 132. The second register 132 can send the received response information to the connected upstream relay module 13 or master control module 12. If the relay module 13 is connected to the upstream relay module 13, the second register 132 included in that relay module 13 sends the response information to the upstream relay module 13; if the relay module 13 is connected to the master control module 12, the second register 132 included in that relay module 13 sends the response information to the master control module 12.

[0102] It should be noted that, for the current relay module 13, the upstream relay module 13 refers to the relay module 13 connected to the current relay module 13 and located between the current relay module 13 and the main control module 12, and the downstream relay module 13 refers to the relay module 13 connected to the current relay module 13 and located between the current relay module 13 and the endpoint module 17. The first register 131, the second register 132, and the third register 133 can all be first-level registers.

[0103] In this embodiment, the first register 131 broadcasts debug commands to the connected adapter module 14 and the downstream relay module 13 or endpoint module 17, ensuring that the debug commands can be sent to the target adapter module, thereby ensuring that the corresponding debug object 20 can be debugged. The third register 133 receives occupancy information sent from the adapter module 14 or the upstream relay module 13, and sends the received occupancy information to the downstream relay module 13 or endpoint module 17, so that the occupancy information can eventually be transmitted to the endpoint module 17. This ensures that the endpoint module 17 will not issue a non-response information when the adapter module 14 responds to the debug command, thus avoiding internal bus 15 conflicts.

[0104] In one possible implementation, such as Figure 12 The schematic diagram of the routing module 16 shown is provided. The routing module 16 receives a counter 161, a first shift register 162, a second shift register 163, a fourth register 164, a fourth multiplexer 165, a fifth multiplexer 166, and a second logic OR unit 167.

[0105] The first shift register 162 is connected to the upstream relay module 13, and is also connected to the receive counter 161 and the fourth multiplexer 165. The fourth multiplexer 165 is connected to the two downstream relay modules 13. One relay module 13 connected to the fourth multiplexer 165 is located in the main chain network, and the other relay module 13 connected to the fourth multiplexer 165 is located in the slave chain network.

[0106] The second shift register 163 is connected to the upstream relay module 13, and is also connected to the receive counter 161 and the fifth multiplexer 166. The fifth multiplexer 166 is connected to the two downstream relay modules 13. One relay module 13 connected to the fifth multiplexer 166 is located in the main chain network, and the other relay module 13 connected to the fifth multiplexer 166 is located in the slave chain network.

[0107] The fourth register 164 is connected to the second logic OR unit 167, and the fourth register 164 is connected to the upstream relay module 13. The second logic OR unit 167 is connected to two downstream relay modules 13. One relay module 13 connected to the second logic OR unit 167 is located in the main chain network, and the other relay module 13 connected to the fourth multiplexer 165 is located in the slave chain network.

[0108] After receiving the debug command CMD, the first shift register 162 sends it to the receive counter 161 and the fourth multiplexer 165. Upon receiving the debug command CMD, the receive counter 161 determines whether the destination adapter module for the debug command CMD is located in the main chain network or the slave chain network through ID matching. If the destination adapter module is located in the main chain network, the receive counter 161 sends a first strobe signal to the fourth multiplexer 165, causing the fourth multiplexer 165 to send the debug command CMD to the relay module 13 located in the main chain network and connected thereto. If the destination adapter module is located in the slave chain network, the receive counter 161 sends a second strobe signal to the fourth multiplexer 165, causing the fourth multiplexer 165 to send the debug command CMD to the relay module 13 located in the slave chain network and connected thereto.

[0109] After receiving the occupancy information RESP_SEL, the second shift register 163 sends the occupancy information RESP_SEL to the receive counter 161 and the fifth multiplexer 166. Upon receiving the occupancy information RESP_SEL, the receive counter 161 determines whether the target adapter module of the previous debug instruction CMD is located in the main chain network or the slave chain network through ID matching. The previous debug instruction CMD refers to the debug instruction targeted by the occupancy information RESP_SEL issued by a certain adapter module 14. If the target adapter module of the previous debug instruction CMD is located in the main chain network, the receive counter 161 sends a third strobe signal to the fifth multiplexer 166, causing the fifth multiplexer 166 to send the occupancy information RESP_SEL to the relay module 13 located in the main chain network and connected to it. If the target adapter module of the previous debugging instruction CMD is located in the slave chain network, the receive counter 161 sends the fourth strobe signal to the fifth multiplexer 166, causing the fifth multiplexer 166 to send the occupancy information RESP_SEL to the relay module 13 located in the slave chain network and connected to it.

[0110] After receiving a response message RESP sent by a relay module 13 located in the main chain network or connected in the chain network, the second logic OR unit 167 sends the received response message RESP to the fourth register 164, and the fourth register 164 sends the response message RESP to the upstream relay module 13.

[0111] It should be noted that, for the current routing module 16, its upstream relay module 13 refers to the relay module 13 connected to the current routing module 16 and between the current routing module 16 and the main control module 12, and its downstream relay module 13 refers to the relay module 13 connected to the current routing module 16 and between the current routing module 16 and the endpoint module 17. The fourth register 164 can be a first-level register.

[0112] In this embodiment, the receive counter 161 determines whether the target adapter module 14 is located in the main chain network or the slave chain network by ID matching. Based on the determination result, it sends a strobe signal to the fourth multiplexer 165 or the fifth multiplexer 166, so that the fourth multiplexer 165 can accurately send the debug command CMD to the chain network where the target adapter module 14 is located, ensuring that the corresponding debug object 20 can be debugged accurately. The fifth multiplexer 166 can accurately send the occupancy information RESP_SEL to the corresponding endpoint module 17, ensuring that the endpoint module 17 will not send a non-response information when the adapter module 14 responds to the debug command CMD, thus avoiding transmission conflicts on the internal bus 15.

[0113] In one possible implementation, such as Figure 13 The schematic diagram of endpoint module 17 shown includes a downlink listening unit 171, an uplink sending unit 172, a transceiver state machine 173, and a timeout counter 174.

[0114] The transceiver state machine 173 is connected to the downlink monitoring unit 171, the uplink transmitting unit 172, and the timeout counter 174. Both the downlink monitoring unit 171 and the uplink transmitting unit 172 are connected to the upstream relay module 13.

[0115] Downlink monitoring unit 171 can receive the debugging command CMD and the occupancy information RESP_SEL sent from the upstream relay module 13, and send the debugging command CMD and the occupancy information RESP_SEL to the transceiver state machine 173. Upon receiving the debugging command CMD, the transceiver state machine 173 controls the timeout counter 174 to start counting. If the transceiver state machine 173 does not receive the occupancy information RESP_SEL when the timeout counter 174 reaches its timeout period, the transceiver state machine 173 sends a non-response message to the upstream transmitting unit 172. The upstream transmitting unit 172 then sends the non-response message to the upstream relay module 13, which in turn sends it to the main control module 12. If the transceiver state machine 173 receives the occupancy information RESP_SEL before the timeout period reaches its timeout period, the transceiver state machine 173 does not send a non-response message.

[0116] In this embodiment, after receiving the debug command CMD, the transceiver state machine 173 controls the timeout counter 174 to start counting. If the timeout counter 174 reaches the timeout period, and the transceiver state machine 173 has not yet received the occupancy information RESP_SEL, it indicates that no adapter module 14 has responded to the debug command CMD. The transceiver state machine 173 issues a non-response information to notify the debugging device to complete the debugging of the corresponding debugging object 20, ensuring the integrity of the internal bus 15 transmission. If the transceiver state machine 173 receives the occupancy information RESP_SEL within the timeout counter 174, it indicates that the debug command CMD has been responded to by an adapter module 14. In this case, the transceiver state machine 173 will not issue a non-response information, ensuring the accuracy of the feedback information to the debugging device and avoiding conflicts on the internal bus 15.

[0117] In one possible implementation, the chip debugging device 10 may further include one or more signal recovery modules. The signal recovery modules are connected between relay modules 13 or between relay modules 13 and routing modules 16. The signal recovery modules can restore the integrity of received debugging commands, response information, occupancy information, non-response information and other signals, and send out the restored signals.

[0118] The signal recovery module can include multiple primary registers. For example, primary registers can be set for signal lines CLK, CMD, RESP, and RESP_SEL. The signals on the corresponding data lines can be latched through the primary registers to restore the integrity of the bus signals.

[0119] In this embodiment of the disclosure, since the signal will be lost during transmission, the amplitude, waveform and timing of the signal will change. By setting a signal recovery module in the chip debugging device 10, the amplitude, waveform and timing of the signal are restored and corrected, and the integrity of the signal is restored, thereby ensuring the accuracy of the signals received by each module in the chip debugging device 10, and thus ensuring the reliability of chip debugging.

[0120] In one possible implementation, Figure 14 The diagram shown illustrates the transmission timing used by the protocol layer of the chip debugging device 10. Figure 15 A schematic diagram of the protocol layer data organization of the chip debugging device 10 is shown. For example... Figure 14 and Figure 15As shown, an 8-bit ID is used to identify the maximum number of adapter modules 14 required. The ID is used to identify the adapter module 14, and different adapter modules 14 correspond to different IDs. A 40-bit address width is used based on the maximum bus address width. Three valid data length modes are selected based on common data lengths: 1 byte, 2 bytes, and 4 bytes. During data transmission, a position-first timing mode is used so that the adapter module 14 can identify the ID first.

[0121] During inter-chip transmission, the protocol layer of the chip debugging device 10 is the same as the aforementioned protocol layer, but special restrictions are placed on the IDs to avoid ID conflicts. In this embodiment, to simplify hardware circuit design and improve hardware circuit reusability, the ID restrictions for inter-chip transmission are also effective for intra-chip transmission.

[0122] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this disclosure can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this disclosure.

[0123] The methods described above according to embodiments of this disclosure can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded over a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0124] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments disclosed herein.

[0125] The above embodiments are only used to illustrate the embodiments of this disclosure, and are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this disclosure, and the patent protection scope of the embodiments of this disclosure should be defined by the claims.

Claims

1. A chip debugging device, comprising: Multiple input bridges, main control module, multiple relay modules and multiple adapter modules; The multi-input bridge is connected to the main control module, and the main control module is connected to the plurality of relay modules; The relay module is connected to the adapter module, and different relay modules are connected to different adapter modules; The adapter module is connected to the debugging object included in the chip, and different adapter modules are connected to different debugging objects; The multi-input bridge is used to send the received debugging commands to the main control module; The main control module is used to send the debugging command to the corresponding relay module, so that the relay module sends the debugging command to the connected adapter module, and the adapter module sends the debugging command to the connected debugging object to debug the debugging object; The adapter module is used to receive response information issued by the connected debugging object based on the debugging command, and send the response information to the connected relay module, so that the relay module sends the response information to the main control module, and the main control module outputs the response information through the multi-input bridge.

2. The apparatus according to claim 1, wherein, The adapter module is connected to the peripheral bus in the chip; The adapter module is used to receive an access request sent by the processing unit included in the chip through the peripheral bus, and send the access request to the connected debugging object.

3. The apparatus according to claim 2, further comprising: Internal bus and at least one routing module; The main control module, the at least one routing module, and the multiple relay modules are connected sequentially through the internal bus to form a main chain network. The routing module is located between two relay modules in the main chain network, and the main control module is located at the first end of the main chain network. The routing module and at least one of the relay modules are connected sequentially through the internal bus to form a chain network, with the routing module located at the first end of the chain network. The internal bus is used to transmit communication data between the main control module and the relay module, between the relay modules, between the relay module and the routing module, and between the relay module and the adapter module. The routing module is used to send the debugging instruction to the main chain network or the relay module connected to the routing module in the slave chain network, according to the debugging object corresponding to the debugging instruction.

4. The apparatus according to claim 3, further comprising: Multiple endpoint modules; The second end of both the main chain network and the slave chain network is connected to an endpoint module; The endpoint module is used to send a non-response information to the main control module through the internal bus when the debugging command issued by the main control module is not responded to by any of the adapter modules, so that the main control module outputs the non-response information through the multi-input bridge.

5. The apparatus according to claim 4, wherein, The internal bus includes clock lines, instruction data lines, response data lines, and select data lines; The clock line is used for the main control module to send clock signals to the relay module, the adapter module, the routing module and the endpoint module; The instruction data line is used to transmit the debugging instructions; The response data line is used to transmit the response information and the non-response information; The selected data line is used for the adapter module to send occupancy information to the endpoint module. The occupancy information is sent by the adapter module after sending the response information. If the endpoint module receives the occupancy information within the timeout period, it will not send the non-response information.

6. The apparatus according to claim 3, wherein, The main control module includes: a first receiving unit, a first transmitting unit, a control register, a parallel port controller, and a first multiplexer; The first receiving unit and the parallel port controller are both connected to the multi-input bridge; the first multiplexer is connected to the first receiving unit, the parallel port controller, the control register, and the first transmitting unit; The multi-input bridge is used to send the received debugging instructions that match the internal bus protocol to the first receiving unit, and to convert the received debugging instructions that do not match the internal bus protocol to a protocol that matches the internal bus, and then send the protocol-converted debugging instructions to the parallel port controller. The first receiving unit is used to send the received debugging command to the first multiplexer; The parallel port controller is used to send the received debugging command to the first multiplexer; The control register is used to receive debugging instructions sent by the processing unit through the peripheral bus, and to send the received debugging instructions to the first multiplexer. The first multiplexer is used to send debugging instructions from the first receiving unit, the parallel port controller, or the control register to the first transmitting unit; The first sending unit is used to send the received debugging instructions to the corresponding adapter module via the internal bus.

7. The apparatus according to claim 6, wherein, The main control module further includes: a second transmitting unit; The second transmitting unit is connected to the multi-input bridge and the control register, respectively; The control register is used to receive off-chip debugging instructions sent by the processing unit through the peripheral bus, and to send the off-chip debugging instructions to the second sending unit; The second sending unit is used to send the off-chip debugging command to the chip to be debugged through the multi-input bridge.

8. The apparatus according to claim 3, wherein, The adaptation module includes: a second receiving unit, a protocol generator, and a second multiplexer; The protocol generator is connected to the second receiving unit and the second multiplexer, the second receiving unit is connected to the relay module, and the second multiplexer is connected to the debugging object and the peripheral bus. The second receiving unit is configured to receive the debugging instruction from the relay module and send the debugging instruction to the protocol generator; The protocol generator is used to convert the received debugging instructions into a protocol that matches the peripheral bus, and send the protocol-converted debugging instructions to the second multiplexer; The second multiplexer is used to send the debugging instruction from the protocol generator or the access request sent by the processing unit through the peripheral bus to the connected debugging object.

9. The apparatus according to claim 5, wherein, The relay module includes: a first register, a second register, a third register, a first logic OR unit, and a third multiplexer; The first register is connected to the main control module or the upstream relay module, and the first register is also connected to the debugging object and the downstream relay module or the endpoint module. The second register is connected to the third multiplexer, and the second register is also connected to the upstream relay module or main control module; The third multiplexer is connected to the adapter module and the downstream relay module or the endpoint module; The first logic or unit is connected to the upstream relay module, and the first logic or unit is connected to the adapter module and the third register, the third register being connected to the downstream relay module or the endpoint module; The first register is used to receive the debugging command and send the debugging command to the adapter module and the downstream relay module or the endpoint module; The first logic unit is configured to receive the occupancy information from the adapter module or the upstream relay module, and send the occupancy information to the third register; The third register is used to send the received occupancy information to the downstream relay module or endpoint module; The third multiplexer is used to receive the response information from the adapter module or the downstream relay module, and send the response information to the main control module or the upstream relay module.

10. The apparatus according to claim 5, wherein, The routing module includes: a receive counter, a first shift register, a second shift register, a fourth multiplexer, a fifth multiplexer, a fourth register, and a second logic OR unit; The first shift register is connected to the upstream relay module, and the first shift register is connected to the receive counter and the fourth multiplexer, the fourth multiplexer being connected to the two downstream relay modules; The second shift register is connected to the upstream relay module, and the second shift register is connected to the receive counter and the fifth multiplexer, the fifth multiplexer being connected to the two downstream relay modules; The fourth register is connected to the second logic OR unit, the fourth register is connected to the upstream relay module, and the second logic OR unit is connected to the two downstream relay modules; The first shift register is used to send the received debugging instruction to the receive counter and the fourth multiplexer; The second shift register is used to send the received occupancy information to the receive counter and the fifth multiplexer; The receive counter is configured to, upon receiving the debug instruction, send a first strobe signal to the fourth multiplexer if the destination adapter module of the debug instruction is located in the main chain network, causing the fourth multiplexer to send the received debug instruction to a downstream relay module located in the main chain network and connected thereto; and send a second strobe signal to the fourth multiplexer if the destination adapter module of the debug instruction is located in the slave chain network, causing the fourth multiplexer to send the received debug instruction to a downstream relay module located in the slave chain network and connected thereto. The module; and upon receiving the occupancy information, if the target adaptation module of the previous debugging instruction is located in the main chain network, a third strobe signal is sent to the fifth multiplexer, causing the fifth multiplexer to send the received occupancy information to the downstream relay module located in the main chain network and connected thereto; if the target adaptation module of the previous debugging instruction is located in the slave chain network, a fourth strobe signal is sent to the fifth multiplexer, causing the fifth multiplexer to send the received occupancy information to the downstream relay module located in the slave chain network and connected thereto; The second logic OR unit is used to send the received response information to the fourth register, so that the fourth register sends the response information to the upstream relay module.

11. The apparatus according to claim 5, wherein, The endpoint module includes: a downlink listening unit, an uplink sending unit, a transceiver state machine, and a timeout counter; The transceiver state machine is connected to the downlink monitoring unit, the uplink transmitting unit, and the timeout counter; Both the downlink monitoring unit and the uplink transmitting unit are connected to the relay module; The downlink monitoring unit is used to receive the debugging command and the occupancy information, and send the received debugging command and the occupancy information to the transceiver state machine; The transceiver state machine is used to control the timeout counter to start counting after receiving the debugging command. If the occupancy information is not received when the timeout counter reaches the timeout period, the non-response information is sent to the uplink transmission unit. The uplink transmitting unit is used to send the non-response information to the upstream relay module via the internal bus.

12. The apparatus according to any one of claims 3-11, wherein the apparatus further comprises at least one signal recovery module; The signal recovery module is connected between the relay modules or between the relay module and the routing module; The signal recovery module is used to restore the integrity of the received signal and then send out the restored signal.

13. A chip, comprising the chip debugging apparatus according to any one of claims 1-12.

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