Memory time sequence parameter adjusting and optimizing method and device, computer equipment and storage medium

Abstract

The invention discloses a memory time sequence parameter tuning method and device, computer equipment and a storage medium, relates to the technical field of server memories, and dynamically relates to time sequence parameter combination and memory interface signal quality by establishing an automatic closed-loop process of parameter configuration, signal measurement, condition verification and parameter optimization. Parameter suitability is accurately judged based on an actual measurement result, and a parameter optimization mechanism is driven to automatically iterate to generate a new candidate parameter combination, so that dependence on artificial experience is eliminated, and the limitation that a traditional method is low in efficiency and difficult to deal with dynamic changes in a complex parameter space is overcome. Therefore, the technical problems that in the prior art, memory time sequence parameter tuning is low in efficiency, poor in adaptability and insufficient in stability are solved, and the technical effects of remarkably improving the integrity of memory signals, enhancing the running stability of a server and improving the energy efficiency ratio of a memory subsystem are achieved.

Description

Technical Field

[0001] The present application relates to the field of memory server technology, and in particular to a method, apparatus, computer equipment, and storage medium for tuning memory timing parameters. Background Art

[0002] In data centers, where computing power demands are rapidly increasing, memory signal integrity has become a core physical-layer constraint that determines overall server performance and stability. The accuracy of memory timing parameter selection directly impacts the signal quality margin, dynamic power efficiency, and system-level fault tolerance of memory channels. With the continuous increase in DDR bus speeds and the introduction of new memory architectures such as 3D stacked memory, the number and complexity of memory timing parameters have increased significantly, making traditional parameter selection methods increasingly inadequate.

[0003] Existing methods for selecting memory timing parameters have significant shortcomings. Coarse-grained tuning based on empirical rules relies on conservative timing, resulting in energy waste in high-frequency scenarios and failing to adapt to the dynamic balancing requirements under mixed loads. Brute-force searches lacking physical constraints are extremely inefficient in vast parameter spaces and are prone to falling into local optima. Static parameters struggle to cope with dynamic disturbances such as temperature drift, leading to decreased system stability over long periods of operation. These issues adversely impact the efficiency and accuracy of memory timing parameter tuning. Summary of the Invention

[0004] The present application provides a method, apparatus, computer equipment and storage medium for tuning memory timing parameters, in order to at least solve the problems in related technologies of coarse-grained tuning based on empirical rules, which wastes energy and has poor adaptability, has low search efficiency and is prone to local optimality, and static parameters are difficult to cope with dynamic interference, resulting in decreased stability and affecting the efficiency and accuracy of memory timing parameter tuning.

[0005] This application provides a method for tuning memory timing parameters, including: Configuring a candidate timing parameter combination for a memory controller in the server to be optimized, and obtaining candidate signal measurement results of a memory interface when the memory controller operates under the candidate timing parameter combination; Verify whether the candidate signal measurement results of the memory interface meet the preset tuning conditions; If the preset tuning conditions are not met, the parameter optimization mechanism is triggered to generate the next set of candidate timing parameter combinations to be verified, and the configuration and verification operations are repeated until the target signal measurement results that meet the preset tuning conditions are output, and the candidate timing parameter combination corresponding to the target signal measurement results is used as the target timing parameter combination.

[0006] The present application also provides a memory timing parameter tuning device, comprising: A configuration module is used to configure a candidate timing parameter combination to a memory controller in a server to be optimized, and obtain candidate signal measurement results of a memory interface when the memory controller operates under the candidate timing parameter combination; A verification module, used to verify whether the measurement results of the candidate signals of the memory interface meet the preset tuning conditions; The trigger module is used to trigger the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified if the preset tuning conditions are not met, and repeatedly perform the configuration and verification operations until the target signal measurement results that meet the preset tuning conditions are output, and the candidate timing parameter combination corresponding to the target signal measurement results is used as the target timing parameter combination.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned memory timing parameter tuning methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned memory timing parameter tuning methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned memory timing parameter tuning methods when the computer program is executed by a processor.

[0010] Through this application, a closed-loop tuning mechanism of complete parameter configuration, signal measurement, condition verification and parameter optimization is constructed. Under this mechanism, the parameter combination can be dynamically associated with the signal quality, and the adaptability of the parameters can be accurately judged based on the results obtained from actual measurements, and iterative optimization can be automatically performed. This method effectively avoids the tuning limitations caused by reliance on manual experience in traditional methods, solves the problem of low tuning efficiency due to insufficient manual experience, and also overcomes the defect that traditional methods cannot cope with dynamic changes. Therefore, the technical problems of low efficiency, poor adaptability and insufficient stability of memory timing parameter tuning in the prior art can be solved, and ultimately the technical effects of significantly improving memory signal quality, enhancing system operation stability and improving energy efficiency can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1A flowchart of a method for tuning memory timing parameters provided in an embodiment of the present application; Figure 2 A schematic diagram of another method for tuning memory timing parameters provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a memory timing parameter tuning system provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a device for tuning memory timing parameters provided in an embodiment of the present application; Figure 5 A schematic diagram of the hardware structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0014] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0015] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0016] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the memory timing parameter tuning method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0017] In this embodiment, a method for tuning memory timing parameters is provided. Figure 1 is a flow chart of a method for tuning memory timing parameters according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps: Step S101: configuring a candidate timing parameter combination to a memory controller in a server to be optimized, and obtaining candidate signal measurement results of a memory interface when the memory controller operates under the candidate timing parameter combination.

[0018] In an embodiment of the present application, first, a parameter optimization mechanism (such as a Bayesian optimization algorithm or a trained deep neural network) generates a candidate timing parameter combination (i.e., a set of memory timing parameters to be tested, including key parameters such as tCL, tRCD, and tRP, whose value range is determined based on the debugging range in the debugging instruction); then, the scheduling PC transmits the candidate timing parameter combination to the baseboard management controller (BMC) of the server to be optimized through an Intelligent Platform Management Interface (IPMI) command. When the server to be optimized is powered on, the basic input and output system (BIOS) obtains the candidate timing parameter combination from the BMC and writes it to the register of the memory controller (the hardware unit responsible for managing memory read and write operations) to complete the parameter configuration; finally, the scheduling subsystem starts the signal integrity (Signal Integrity) function. The Memory Integrity (SI) measurement tool measures the memory interface (the signal transmission interface between the memory and the memory controller, including signal lines such as data signals (DQ) and address signals (Addr)). It obtains data on whether each DQ / Addr signal can be effectively collected at different delays under the candidate timing parameter combination. After analysis, it obtains candidate signal measurement results reflecting signal quality (the core is the effective delay width of each signal, that is, the delay range within which the signal can stably collect data).

[0019] Step S102 , verifying whether the measurement results of the candidate signals of the memory interface meet the preset tuning conditions.

[0020] In an embodiment of the present application, multiple signals of the memory interface (such as DQ data signals, Addr address signals, etc.) are first extracted from the candidate signal measurement results; then, the effective delay width of each signal is calculated (i.e., the delay range within which the signal can stably collect data), and it is verified whether it meets the corresponding delay characteristics. Specifically, the type of signal (such as DQ signal or Addr signal) is first determined, and then, based on the association between the preset signal type and the preset delay threshold, the delay threshold corresponding to the signal of this type is found, and the delay threshold is detected to see whether it falls within the center area of ​​the effective delay width (the center area refers to the middle 50% range of the effective delay width), thereby obtaining a verification result of a single signal; finally, based on the verification results of all signals, it is determined whether the preset tuning conditions are met (the preset tuning conditions refer to the qualification standards set based on the minimum effective delay width requirements recommended by the memory controller designer or the actual scenario requirements): if the effective delay widths of all signals meet the corresponding delay characteristics (i.e., their respective delay thresholds all hit the center area), then it is determined that the candidate signal measurement results meet the preset tuning conditions; if any signal does not meet the conditions, then it is determined that it does not meet the conditions.

[0021] In step S103, if the preset tuning conditions are not met, the parameter optimization mechanism is triggered to generate the next set of candidate timing parameter combinations to be verified, and the configuration and verification operations are repeated until the target signal measurement results that meet the preset tuning conditions are output, and the candidate timing parameter combination corresponding to the target signal measurement results is used as the target timing parameter combination.

[0022] In an embodiment of the present application, if the verification result shows that the candidate signal measurement result does not meet the preset tuning conditions (i.e., there is at least one memory interface signal whose effective delay width does not meet the corresponding delay characteristics), the parameter optimization mechanism is triggered: first, the current candidate timing parameter combination and its corresponding candidate signal measurement result are added to the training data set to form an updated training data set; then, the target signal evaluation model (such as a deep neural network with a hybrid CNN-LSTM architecture) is retrained using the updated data set to obtain an optimized target signal evaluation model; and then, the next set of candidate timing parameter combinations to be verified is predicted and screened using the optimization model. Afterwards, the configuration of the new candidate timing parameter combination to the memory controller and the acquisition of the corresponding candidate signal measurement results and the verification of the new measurement results are repeated. The above process is repeated until a certain verification result meets the preset tuning conditions. At this time, the signal measurement result that meets the conditions is determined as the target signal measurement result, and its corresponding candidate timing parameter combination is the target timing parameter combination (referring to a set of memory timing parameters that can ultimately be directly used for memory controller configuration and can ensure signal integrity).

[0023] In the embodiment of the present application, before configuring the candidate timing parameter combination to the server to be optimized, such as Figure 2 As shown, the method further includes: Step S201: Detect debugging instructions for the server to be optimized.

[0024] In an embodiment of the present application, the scheduling subsystem monitors in real time whether there are debugging instructions for the server to be optimized (the server that needs to perform memory timing parameter tuning) through a preset interface (such as a network communication interface, a local command line interface, or a graphical operation interface). The debugging instruction is an instruction that triggers the memory timing parameter tuning process, and usually contains key information such as the tuning target (such as improving signal integrity and reducing power consumption), the debugging range of the timing parameters (such as the value range of parameters such as tCL and tRCD), and the tuning termination condition (such as the maximum number of iterations, the target signal quality threshold). After detecting the instruction, the scheduling subsystem verifies the legality of the instruction (such as whether the format is correct and whether it contains necessary parameters). After the verification is passed, the instruction content is recorded to provide a basis for the subsequent startup parameter optimization mechanism.

[0025] Step S202 : triggering a parameter optimization mechanism based on a debug instruction, and generating candidate timing parameter combinations according to a debug range of the timing parameter combination in the debug instruction.

[0026] In an embodiment of the present application, after detecting a debug instruction, a parameter optimization mechanism (a collaborative optimization mechanism integrating a Bayesian optimization algorithm and a deep learning model) is triggered based on the instruction. The specific process is as follows: first, the debugging range of the timing parameter combination in the debug instruction is parsed (i.e., the value range of timing parameters such as tCL, tRCD, and tRP, such as the ±50% safety margin of the JEDEC standard timing); then, based on the debug range, an initial first timing parameter combination is generated within the range through a Bayesian optimization algorithm (with a Gaussian process model as the core), and after being configured to the memory controller, the corresponding first signal measurement result is obtained. Then, the second timing parameter combination and the signal result are iteratively predicted and verified until a training data set containing a sufficient number of parameter-signal mapping relationships is formed; then, the training data set is used to train an initial signal evaluation model (an untrained 1DCNN and LSTM hybrid architecture model) to obtain a target signal evaluation model that can evaluate signal quality; finally, the target signal evaluation model is used to perform signal quality scoring on the parameter combinations in the training data set, and parameter combinations with higher scores are screened out as candidate timing parameter combinations.

[0027] By detecting debugging instructions, it is possible to accurately respond to the tuning requirements of the server to be optimized, ensuring that the tuning direction meets the actual debugging goals; generating candidate timing parameter combinations based on the debugging range in the debugging instructions can avoid blind parameter exploration and reduce invalid parameter configurations, thereby improving the targetedness and initial efficiency of memory timing parameter tuning.

[0028] In an embodiment of the present application, generating a candidate timing parameter combination according to a debugging range of the timing parameter combination in a debugging instruction includes the following steps A1-A3: Step A1: parsing the debugging range of the timing parameter combination in the debugging instruction.

[0029] Specifically, the instruction parsing module in the scheduling subsystem performs structured parsing on the acquired debug instructions, extracting the debugging range of the timing parameter combinations contained therein—that is, clarifying the allowable value ranges (such as minimum and maximum values) for various timing parameters such as tCL (CAS Latency), tRCD (RAS-to-CAS Delay), and tRP (RAS Precharge Time). During the parsing process, the legitimacy of each parameter range must be verified to ensure that it does not exceed the limit values ​​specified by the memory hardware specification (Spec) (for example, tCL must not be less than the minimum latency supported by the memory chip). The parsing results are then converted into boundary conditions of the parameter space (such as tCL∈[30T,50T], tRCD∈[35T,45T]), providing a constraint basis for the subsequent generation of timing parameter combinations within this range (such as selecting the first timing parameter combination in step A21).

[0030] Step A2: construct a training data set based on the debugging range, and use the training data set to train the initial signal evaluation model to obtain a target signal evaluation model.

[0031] Specifically, based on the debug range (timing parameter value range) obtained through analysis, a training dataset is first constructed: a first timing parameter combination is selected within the debug range using a Bayesian optimization algorithm, configured to the memory controller of the server to be optimized, and the corresponding first signal measurement result is obtained. A Gaussian process model is then constructed based on the first parameter combination and the first signal result to predict the next set of second timing parameter combinations. The iterative operations of configuration, measurement, and prediction are repeated until the preset sampling conditions are met, forming a training dataset (containing a mapping relationship between the timing parameter combination and the corresponding signal measurement results). This training dataset is then used to train the initial signal evaluation model (an untrained 1D convolutional neural network and long short-term memory network hybrid architecture used to evaluate signal quality): network parameters (such as CNN convolution kernel weights and LSTM hidden layer parameters) are adjusted through a backpropagation algorithm to minimize the loss function (such as mean squared error or weighted sum of quantile losses) between the signal quality score output by the model and the actual signal measurement result. Ultimately, a target signal evaluation model that can accurately evaluate signal quality is obtained.

[0032] In an embodiment of the present application, constructing a training data set based on a debugging range includes the following steps A21-A24: Step A21: Select a first timing parameter combination within the debugging range.

[0033] Specifically, within the debugging range (i.e., the allowable value range of each timing parameter, such as tCL∈[30T,50T] and tRCD∈[35T,45T]), the initial sampling module of the Bayesian optimization algorithm selects the first timing parameter combination (referring to the first set of memory timing parameters when constructing the training dataset, including key parameters such as tCL, tRCD, and tRP). This selection uses a random sampling strategy to randomly generate specific values ​​from the value range of each parameter, while simultaneously removing the minimum and maximum values ​​within the range (to avoid signal quality anomalies that may be caused by extreme values). If specific prior knowledge is preset (such as parameter values ​​that have performed well in historical tuning), values ​​close to this prior knowledge will be prioritized for selection to ensure that the first timing parameter combination is within the safe operating range of the hardware, providing a foundation for subsequent configuration and signal measurement.

[0034] Step A22: configure a first timing parameter combination to a memory controller in the server to be optimized, and obtain a first signal measurement result of a memory interface when the memory controller operates under the first timing parameter combination.

[0035] Specifically, the scheduling module first transmits the selected first timing parameter combination (the initial set of memory timing parameters) to the baseboard management controller of the server to be optimized via an intelligent platform management command. After the server to be optimized is powered on, the basic input / output system obtains the first timing parameter combination from the baseboard management controller via the in-band intelligent platform management interface and writes it to the memory controller, completing the parameter configuration. Subsequently, the scheduling subsystem activates the SI measurement tool to measure the memory interface signals: by detecting whether each memory interface signal can be effectively collected at different delays relative to the clock signal, recording the delay range within which the signal can be stably collected, and extracting it through the analysis program, obtaining the first signal measurement result corresponding to the first timing parameter combination (the core of which is the effective delay width of each signal, a quantitative indicator of signal quality).

[0036] Step A23: constructing a Gaussian process model based on the first timing parameter combination and the first signal measurement result, and predicting the next set of second timing parameter combinations to be debugged by using the Gaussian process model.

[0037] In an embodiment of the present application, a Gaussian process model is constructed based on the first timing parameter combination and the first signal measurement result, including: establishing an initial Gaussian process model based on the first timing parameter combination and the first signal measurement result; configuring the random dynamic characteristics between each timing parameter in the first timing parameter combination and the preset acquisition strategy of the timing parameters in the initial Gaussian process model to obtain a Gaussian process model.

[0038] An initial Gaussian process model is established based on the first time series parameter combination and results, providing a basic framework for parameter prediction. The random dynamic characteristics between the configuration parameters make the model more consistent with the dynamic changes of the memory runtime parameters. The preset acquisition strategy can guide the model to efficiently explore the parameter space. The resulting Gaussian process model has higher prediction accuracy and greater practicality.

[0039] Among them, an initial Gaussian process model is established based on the first timing parameter combination and the first signal measurement result, including: establishing a parameter space and a corresponding indicator space based on the debugging range in the debugging instruction; writing the first timing parameter combination into the parameter space, writing the first signal measurement result into the indicator space, and establishing a probabilistic mapping between the parameter space and the indicator space according to the mapping relationship between the first timing parameter combination and the first signal measurement result, to obtain an initial Gaussian process model.

[0040] Based on the debugging range, parameter space and indicator space are established to make the correspondence between parameters and signal results more structured and clear; data is written into the space and a probabilistic mapping is established to quantify the uncertainty relationship between parameters and signal results, so that the initial Gaussian process model has probabilistic prediction capabilities and provides a scientific mathematical basis for subsequent parameter prediction.

[0041] Specifically, a parameter space (a set of value intervals for each timing parameter) and a corresponding indicator space (a set of ranges for signal measurement results) are first established based on the debugging scope specified in the debugging instruction. The first timing parameter combination and the first signal measurement results (such as the effective delay width of each signal) are then written into the parameter space. Based on this mapping, a probabilistic mapping is established between the parameter space and the indicator space (i.e., describing the relationship between the parameter combination and signal quality through a probability distribution), resulting in an initial Gaussian process model. The initial model is then configured with the stochastic dynamics of each parameter in the first timing parameter combination (dynamic correlations between parameters that vary with the environment or the parameters themselves, such as the coupling relationship between tRCD and tWR) and a preset acquisition strategy (a strategy for balancing exploration and utilization of the parameter space, such as a hybrid strategy combining expected improvement in EI and probabilistic improvement in PI), forming a complete Gaussian process model. The preset acquisition strategy in the model is then invoked to select the parameter combination with the greatest potential for signal quality improvement from the parameter space, which serves as the next set of timing parameter combinations to be debugged.

[0042] In an embodiment of the present application, the next set of second timing parameter combinations to be debugged is predicted by a Gaussian process model, including: calling a preset acquisition strategy in the Gaussian process model; and using the preset acquisition strategy to filter out the next set of second timing parameter combinations to be debugged from the parameter space in the Gaussian process model.

[0043] Specifically, the pre-configured preset acquisition strategy in the Gaussian process model is first called (referring to the rules used to balance the "exploration" and "utilization" of the parameter space, such as a hybrid strategy that integrates expected improvement EI and probabilistic improvement PI, where EI is used to evaluate the potential benefits of parameter combinations in improving signal quality, and PI is used to evaluate the probability of their improvement of signal quality); then, the preset acquisition strategy is used to evaluate the parameter space of the Gaussian process model (the set of value intervals for each timing parameter) and calculate the comprehensive "exploration-utilization" score of each potential parameter combination - parameter combinations with great potential for improving signal quality (high EI value) and high uncertainty (unknown areas to be explored) are preferentially screened out, and they are determined as the next set of second timing parameter combinations to be debugged, so as to improve tuning efficiency while avoiding falling into local optimality.

[0044] Calling the preset acquisition strategy can give parameter screening a clear optimization goal and direction; using the strategy to screen the second time series parameter combination from the parameter space can give priority to the parameter combination with the most exploration value for testing, avoid invalid parameter attempts, improve parameter exploration efficiency, and speed up the construction of the training data set.

[0045] Step A24, configure a second timing parameter combination to the memory controller in the server to be optimized, obtain the second signal measurement result of the memory interface when the memory controller is running under the second timing parameter combination, iteratively perform parameter prediction and configuration operations until the preset sampling conditions are met, and use the mapping relationship between the timing parameter combination and the measurement results to generate a training data set.

[0046] Specifically, first, following the same configuration process as step A22, the second timing parameter combination predicted by the Gaussian process model in step A23 is written to the memory controller register of the server to be optimized via an IPMI command through the BMC and BIOS. Subsequently, the SI measurement tool is activated to measure the memory interface signals, and the SI analysis program extracts the second signal measurement results corresponding to this parameter combination (the core of which is the effective delay width of each DQ / Addr signal). Next, the Gaussian process model is iteratively executed to predict new timing parameter combinations, configure them to the memory controller, and obtain the corresponding signal measurement results until the preset sampling conditions are met (e.g., the number of mapping relationships between parameter combinations and measurement results reaches 100, or the improvement in the signal quality indicator is less than 1% for five consecutive times). Finally, the timing parameter combinations generated through all iterations and their corresponding signal measurement results are organized into a dataset containing the mapping relationships, thereby generating a training dataset.

[0047] The first timing parameter combination is selected within the debugging range and the corresponding signal results are obtained to provide initial data support for model construction; a Gaussian process model is constructed based on the initial data, which can effectively capture the nonlinear relationship between parameters and signals; the second timing parameter combination is predicted by the model and iterative sampling is performed, which can efficiently explore the parameter space within a limited range and avoid redundant testing. The training data set finally generated is more representative and comprehensive, laying a high-quality data foundation for subsequent model training.

[0048] Step A3: Determine candidate timing parameter combinations using the target signal evaluation model.

[0049] Analyzing the debugging range can clarify the boundaries of parameter exploration and provide precise direction for subsequent tuning; constructing a training data set based on the debugging range and training the target signal evaluation model can use a data-driven approach to learn the correlation between parameters and signals and improve the scientific nature of parameter evaluation; using the target signal evaluation model to determine candidate combinations can reduce reliance on manual experience, improve the quality and screening efficiency of candidate parameters, and accelerate the tuning process.

[0050] In the embodiment of the present application, determining a candidate timing parameter combination using a target signal evaluation model includes the following steps A31-A33: Step A31: Convert the mapping relationship in the training data set into a feature vector.

[0051] Specifically, the numerical features of key parameters such as tCL and tRCD are extracted from the timing parameter combination. From the signal measurement results, the time domain statistical features (such as eye height, eye width, and Q factor) and frequency domain features (such as noise power spectral density) of the signal eye diagram are extracted through sliding window sampling (window length 1000ns, step length 50ns), and the effective delay width (Margin) features of each DQ / Addr signal are also incorporated. These extracted features are integrated and standardized according to preset dimensions (such as 32 dimensions) to form feature vectors that can be input into deep neural networks, realizing the numerical expression of the mapping relationship.

[0052] Step A32: evaluate each eigenvector using the target signal evaluation model to obtain a signal quality score for each eigenvector.

[0053] In an embodiment of the present application, a target signal evaluation model is used to evaluate each feature vector to obtain a signal quality score for each mapping relationship, including: extracting the signal local features and timing-dependent features in the feature vector; analyzing the signal local features and timing-dependent features to obtain analysis results; and determining the signal quality score of the feature vector based on the analysis results.

[0054] Specifically, a target signal evaluation model composed of a 1D convolutional neural network (CNN) and a long short-term memory network (LSTM) is used to evaluate feature vectors. First, a CNN layer (using multi-scale convolution kernels, such as 3×1 and 5×1) extracts local signal features (such as impulse response spikes and noise spikes) from the feature vector. An LSTM layer (containing 256 hidden units) then captures temporal dependency features in the feature vector (such as the temporal correlation between parameters, such as the dynamic interaction effect of tCL and tRCD). The model then fuses and analyzes the extracted local signal features and temporal dependency features, combining them with mapping calculations in a fully connected layer to determine the signal quality score corresponding to the feature vector. This score, generated based on big data training, reflects the comprehensive signal quality of the mapping relationship between the timing parameter combination and the signal measurement results.

[0055] Extracting local signal features can capture the detailed characteristics of the signal, and extracting time-dependent features can reflect the correlation pattern of the signal over time. The combination of the two makes feature analysis more comprehensive; analyzing the features can deeply explore the mechanism of the influence of parameters on signal quality; determining the score based on the analysis results can make the score more in line with the actual signal performance and improve the accuracy and reliability of model evaluation.

[0056] Step A33: Screen candidate timing parameter combinations from the training data set based on the signal quality score.

[0057] Specifically, a signal quality score screening threshold is set (this threshold can be determined based on the margin range set by the memory controller and actual needs, such as no less than 80 points). Timing parameter combinations in the training dataset whose signal quality scores reach or exceed this threshold are screened out as candidate timing parameter combinations. The signal measurement results corresponding to these combinations (such as the effective delay width of each DQ / Addr signal) must meet the preset standards (at least the minimum recommended value set by the memory controller).

[0058] Converting the mapping relationship into a feature vector facilitates the model to quantify the relationship between parameters and signals; using the target signal evaluation model to obtain the signal quality score, the effect of the parameter combination can be objectively and quantitatively evaluated; screening candidate combinations based on the score can accurately retain high-quality parameter combinations, reduce the verification cost of low-quality parameters, and improve the accuracy and efficiency of tuning.

[0059] In the embodiment of the present application, verifying whether the candidate signal measurement result meets the preset tuning condition includes the following steps B1-B3: Step B1: extract multiple memory interface signals from the candidate signal measurement results.

[0060] Specifically, multiple memory interface signals are extracted from the candidate signal measurement results corresponding to the candidate timing parameter combinations. These signals are specifically the DQ signals (data signals) and Addr signals (address signals) specified in the memory specification standard (Spec). The extraction is based on quality characteristics such as the effective delay width (Margin) of each signal, obtained by processing the measurement records obtained by the SI measurement tool through the SI analysis program. By screening out the DQ / Addr signals that meet the signal quality requirements under the candidate combinations, a set of multiple memory interface signals is formed for subsequent analysis.

[0061] Step B2: Calculate the effective delay width of the memory interface signal, and verify whether the effective delay width of the memory interface signal satisfies the corresponding delay characteristic, to obtain a verification result.

[0062] Specifically, the effective delay width of the memory interface signal is first calculated. This width refers to the delay range within which the memory interface signal can stably acquire data under different delays relative to the clock signal. This is obtained by analyzing the measured data of the memory interface signal using an SI analysis program. Next, it is verified whether the effective delay width satisfies the corresponding delay characteristic, where the delay characteristic is the delay standard that the memory interface signal should meet, determined based on the association between a preset signal type and a preset delay threshold. During the specific verification, the signal type of the memory interface signal is first obtained, and then the corresponding delay threshold is found based on the association. The delay threshold is then tested to see if it hits the center area of ​​the effective delay width. If it does, the verification result is satisfied; otherwise, it is not satisfied.

[0063] In an embodiment of the present application, verifying whether the effective delay width of the memory interface signal satisfies the corresponding delay characteristics and obtaining a verification result includes the following steps B21-B23: Step B21: Obtain the signal type of the memory interface signal.

[0064] Specifically, the signal type of the memory interface signal is obtained. The signal type refers to the classification of memory interface signals based on their function and role, such as data signals (DQ signals) and address signals (Addr signals). The signal type of each memory interface signal is determined by parsing the classification definition of memory interface signals in the memory specification standard and combining it with the identification information of each signal (such as signal name and transmission content characteristics) in the candidate signal measurement results obtained by the SI measurement tool.

[0065] Step B22: Determine the delay threshold corresponding to the signal type based on the association between the preset signal type and the preset delay threshold.

[0066] Specifically, a preset signal type refers to a predefined memory interface signal category (such as a DQ signal, an Addr signal, etc.). A preset delay threshold is a benchmark value set for different signal types to measure whether the effective delay width meets the standard. It is usually determined based on the margin range pre-set by the memory controller and the actual application scenario requirements. An association relationship refers to a pre-established mapping relationship (which can be stored in a mapping table or database format) that maps each preset signal type to the corresponding preset delay threshold. After obtaining the signal type of the memory interface signal, querying this association relationship can obtain the preset delay threshold corresponding to that signal type.

[0067] Step B23: Verify the effective delay width based on the delay threshold to obtain a verification result.

[0068] Obtaining the signal type can clarify the characteristic differences between different signals; determining the corresponding delay threshold based on the correlation relationship makes the threshold setting more in line with the actual needs of different signals and avoids the irrationality of a unified threshold; verifying the effective delay width based on the threshold can improve the pertinence and accuracy of the verification and ensure that the signal evaluation meets its own characteristic requirements.

[0069] In an embodiment of the present application, the effective delay width is verified based on the delay threshold to obtain a verification result, including: detecting whether the delay threshold hits the central area of ​​the effective delay width; if it hits the central area of ​​the effective delay width, determining that the verification result is that the effective delay width meets the delay characteristics; or, if it does not hit the central area of ​​the effective delay width, determining that the verification result is that the effective delay width does not meet the delay characteristics.

[0070] Specifically, the effective delay width is verified based on the delay threshold, where the center region refers to the middle portion of the effective delay width's delay range (the center position can be determined by calculating the average of the effective delay width's starting and ending values, and the center region is typically a certain range based on this center position). During verification, the delay threshold is checked to see if it falls within the center region of the effective delay width. If so, the effective delay width is determined to meet the delay characteristics, and the verification result is passed. If not, the effective delay width is determined to not meet the delay characteristics, and the verification result is failed.

[0071] By detecting whether the delay threshold hits the center area of ​​the effective delay width, it can be determined whether the signal has sufficient timing margin; if it hits the center area, it is determined that the delay characteristics are met, which can ensure that the signal has strong anti-interference ability during operation, reduce errors caused by timing fluctuations, and improve the stability of memory operation; if it does not hit the center area, it is determined that the delay characteristics are not met, and signals with insufficient timing margin can be identified in time, avoiding the use of parameter combinations that may cause signal instability, thereby eliminating memory operation risks in advance and ensuring the reliability of the server memory system.

[0072] In step B3, if the verification result shows that the effective delay width of each memory interface signal satisfies the corresponding delay characteristics, it is determined that the candidate signal measurement result satisfies the preset tuning conditions; or, if the verification result shows that the effective delay width of any memory interface signal does not satisfy the corresponding delay characteristics, it is determined that the candidate signal measurement result does not satisfy the preset tuning conditions.

[0073] Extracting multiple memory interface signals allows for a comprehensive assessment of the memory's operating status, avoiding the one-sided nature of single-signal evaluation. Calculating the effective delay width quantifies the signal's timing margin, verifying whether it meets the delay characteristics and accurately determining whether the signal quality meets standards. Determining whether the tuning conditions are met based on the verification results makes tuning decisions more objective and accurate, ensuring the effectiveness of the tuning results.

[0074] Specifically, when all memory interface signals are verified, and the verification results obtained are that the effective delay width meets the corresponding delay characteristics (that is, the delay threshold of each signal hits the center area of ​​its effective delay width), then the candidate signal measurement result is determined to meet the preset tuning conditions. Among them, the preset tuning conditions refer to the standards pre-set by the system for judging whether the candidate signal measurement results meet the standards, and all memory interface signals must pass verification to be met. As long as the effective delay width of one or more signals in the verification results of all memory interface signals does not meet the corresponding delay characteristics (that is, the delay threshold of the signal does not hit the center area of ​​its effective delay width), it is determined that the candidate signal measurement result does not meet the preset tuning conditions and further parameter optimization is required.

[0075] When the effective delay widths of all memory interface signals meet the corresponding delay characteristics, the tuning conditions are determined to be met. This ensures that all key signals in the memory system are stable, prevents local signal issues from affecting overall memory performance, and ensures the comprehensive reliability of the tuning results. If any memory interface signal does not meet the delay characteristics, the tuning conditions are determined to be unmet. This ensures strict control of signal quality and timely elimination of parameter combinations with potential risks, preventing memory errors or performance degradation caused by individual signal anomalies and ensuring the rigor of the tuning process.

[0076] In the embodiment of the present application, triggering the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified includes the following steps C1-C3: Step C1: adding the candidate timing parameter combination and the candidate signal measurement result to the training data set to obtain an updated training data set.

[0077] Specifically, the candidate timing parameter combination (the set of memory timing parameters to be verified) and the corresponding candidate signal measurement results (the signal measurement data of the memory interface under this parameter combination) are added to the existing training dataset (the set of timing parameters and measurement results used to train the signal evaluation model), thereby forming an updated training dataset and providing richer training data for subsequent model optimization.

[0078] Step C2: training the target signal evaluation model based on the updated training data set to obtain an optimized target signal evaluation model.

[0079] Specifically, the target signal evaluation model (the model initially trained to evaluate signal quality) is retrained based on the updated training dataset. During training, the model parameters are adjusted using a backpropagation algorithm, enabling the model to more accurately learn the mapping relationship between timing parameters and signal measurement results. Ultimately, an optimized target signal evaluation model is obtained, improving its prediction accuracy.

[0080] Step C3: using the optimized target signal evaluation model to determine the next set of candidate timing parameter combinations to be verified.

[0081] Specifically, the optimized target signal evaluation model is used to evaluate the timing parameter combinations in the parameter space. The model outputs the signal quality-related prediction results of each combination based on the learned mapping relationship. Based on this, a group of timing parameter combinations with higher signal quality potential are screened out as the next group of candidate timing parameter combinations to be verified, thereby promoting the continuous optimization process.

[0082] Adding candidate combinations and signal results to the training dataset can enrich the diversity and timeliness of the dataset; optimizing the target signal evaluation model based on the updated dataset can enable the model to continuously learn new parameter and signal association patterns, thereby improving prediction accuracy; using the optimized model to determine the next set of candidate combinations can make parameter exploration more targeted, accelerate the search for the optimal timing parameter combination, and improve overall tuning efficiency.

[0083] The embodiment of the present application also provides a system for tuning memory timing parameters, such as Figure 3 As shown, including: servers to be optimized and tuning equipment; The server to be optimized receives the candidate timing parameter combination sent by the tuning device, loads the parameter combination through the memory controller and runs it, and simultaneously feeds back the signal measurement results of the memory interface to the tuning device. Finally, the memory configuration is completed based on the target timing parameter combination determined by the tuning device. The tuning device is used to generate candidate timing parameter combinations and send them to the server to be optimized, receive and analyze the signal measurement results fed back by the server to be optimized, and iteratively optimize the parameter combinations through the parameter optimization mechanism until the target timing parameter combination that meets the preset tuning conditions is determined.

[0084] The server to be optimized includes: baseboard management controller, basic input and output module; The baseboard management controller is used to receive candidate timing parameter combinations sent by the tuning device and configure them into the memory controller. It also monitors the operating status of the memory controller, collects raw signal data from the memory interface, and feeds it back to the tuning device. The basic input and output module is used to provide underlying hardware interface support for the parameter configuration of the memory controller, initialize the memory operating environment, and ensure that the candidate timing parameter combination can be correctly loaded and executed by the memory controller.

[0085] The tuning equipment includes: parameter generation module, signal measurement module, signal analysis module and target signal evaluation model; The parameter generation module is used to analyze the debugging range of timing parameters based on debugging instructions and trigger the parameter optimization mechanism. It uses the Gaussian process model to predict and generate candidate timing parameter combinations. In the iterative process, it combines the signal measurement results to update the training data set and generate the next set of parameter combinations to be verified. The signal measurement module is used to receive the original signal data fed back by the server to be optimized, pre-process it, and generate standardized candidate signal measurement results; The signal analysis module verifies whether the candidate signal measurement results meet the preset tuning conditions. It extracts the effective delay width of the memory interface signal, matches the corresponding delay threshold according to the signal type, verifies whether the effective delay width hits the center area of ​​the threshold, and determines whether the tuning conditions are met based on the verification result. The target signal evaluation model is used for training based on the training dataset. It converts the mapping relationship between the timing parameter combination and the signal measurement results into a feature vector, extracts and analyzes the local features and timing dependency features of the signal, and outputs a signal quality score. Based on the score, candidate timing parameter combinations are screened from the training dataset, and the model performance is optimized through the updated training dataset in iterations.

[0086] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0087] The embodiment of the present application also provides a device for tuning memory timing parameters, such as Figure 4 Shown, including: A configuration module 41 is configured to configure a candidate timing parameter combination to a memory controller in a server to be optimized, and obtain candidate signal measurement results of a memory interface when the memory controller operates under the candidate timing parameter combination; A verification module 42 is used to verify whether the measurement results of the candidate signals of the memory interface meet the preset tuning conditions; The trigger module 43 is used to trigger the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified if the preset tuning conditions are not met, and repeatedly perform the configuration and verification operations until the target signal measurement results that meet the preset tuning conditions are output, and the candidate timing parameter combination corresponding to the target signal measurement results is used as the target timing parameter combination.

[0088] Furthermore, the device also includes: A detection module, used to detect debugging instructions for the server to be optimized; The generation module is used to trigger the parameter optimization mechanism based on the debugging instruction and generate candidate timing parameter combinations according to the debugging range of the timing parameter combination in the debugging instruction.

[0089] Furthermore, the generation module includes: The parsing submodule is used to parse the debugging range of the timing parameter combination in the debugging instruction; The training submodule is used to construct a training data set based on the debugging range, and use the training data set to train the initial signal evaluation model to obtain the target signal evaluation model; The first determination submodule is configured to determine a candidate timing parameter combination using a target signal evaluation model.

[0090] Furthermore, the training submodule includes: A selection unit, configured to select a first timing parameter combination within a debugging range; A configuration unit, configured to configure a first timing parameter combination to a memory controller in the server to be optimized, and obtain a first signal measurement result of a memory interface when the memory controller runs under the first timing parameter combination; A construction unit, configured to construct a Gaussian process model based on the first timing parameter combination and the first signal measurement result, and predict a next set of second timing parameter combinations to be debugged through the Gaussian process model; A generation unit is used to configure a second timing parameter combination to the memory controller in the server to be optimized, obtain a second signal measurement result of the memory interface when the memory controller is running under the second timing parameter combination, iteratively perform parameter prediction and configuration operations until a preset sampling condition is met, and generate a training data set using a mapping relationship between the timing parameter combination and the measurement results.

[0091] Furthermore, a construction unit is used to establish an initial Gaussian process model based on the first timing parameter combination and the first signal measurement result; the random dynamic characteristics between the various timing parameters in the first timing parameter combination and the preset acquisition strategy of the timing parameters are configured in the initial Gaussian process model to obtain a Gaussian process model.

[0092] Furthermore, the construction unit is also used to establish a parameter space and a corresponding indicator space based on the debugging range in the debugging instruction; write the first timing parameter combination into the parameter space, write the first signal measurement result into the indicator space, and establish a probabilistic mapping between the parameter space and the indicator space according to the mapping relationship between the first timing parameter combination and the first signal measurement result to obtain an initial Gaussian process model.

[0093] Furthermore, submodules are determined, including: A conversion unit, used to convert the mapping relationship in the training data set into a feature vector; An evaluation unit, configured to evaluate each eigenvector using a target signal evaluation model to obtain a signal quality score for each eigenvector; The screening unit is used to screen candidate timing parameter combinations from the training data set based on the signal quality score.

[0094] Furthermore, the evaluation unit is used to extract the signal local features and timing-dependent features in the feature vector; analyze the signal local features and timing-dependent features to obtain analysis results; and determine the signal quality score of the feature vector based on the analysis results.

[0095] Furthermore, the verification module 42 includes: an extraction submodule, configured to extract a plurality of memory interface signals from the candidate signal measurement results; A calculation submodule is used to calculate the effective delay width of the memory interface signal and verify whether the effective delay width of the memory interface signal meets the corresponding delay characteristics to obtain a verification result; The second determination submodule is used to determine whether the candidate signal measurement results meet the preset tuning conditions based on the verification results; if the verification result is that the effective delay width of each memory interface signal meets the corresponding delay characteristics, then it is determined that the candidate signal measurement results meet the preset tuning conditions; or, if the verification result is that the effective delay width of any memory interface signal does not meet the corresponding delay characteristics, then it is determined that the candidate signal measurement results do not meet the preset tuning conditions.

[0096] Furthermore, the calculation submodule also includes: An acquisition unit, used for acquiring a signal type of a memory interface signal; a matching unit, configured to determine a delay threshold corresponding to a signal type based on an association between a preset signal type and a preset delay threshold; The verification unit is used to verify the effective delay width based on the delay threshold and obtain a verification result.

[0097] Furthermore, the verification unit is used to detect whether the delay threshold hits the central area of ​​the effective delay width; if it hits the central area of ​​the effective delay width, the verification result is determined to be that the effective delay width meets the delay characteristics; or, if it does not hit the central area of ​​the effective delay width, the verification result is determined to be that the effective delay width does not meet the delay characteristics.

[0098] Furthermore, the trigger module 43 is used to add the candidate timing parameter combination and the candidate signal measurement results to the training data set to obtain an updated training data set; train the target signal evaluation model based on the updated training data set to obtain an optimized target signal evaluation model; and use the optimized target signal evaluation model to determine the next set of candidate timing parameter combinations to be verified.

[0099] See also Figure 5 , Figure 5 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 5As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0100] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0101] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to execute the method shown in the above embodiment.

[0102] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created based on the use of a computer device for displaying a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0103] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0104] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0105] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0106] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for tuning memory timing parameters, characterized in that: include: Configuring a candidate timing parameter combination for a memory controller in a server to be optimized, and obtaining candidate signal measurement results of a memory interface when the memory controller operates under the candidate timing parameter combination; Verifying whether the candidate signal measurement results of the memory interface meet preset tuning conditions; If the preset tuning conditions are not met, the parameter optimization mechanism is triggered to generate the next set of candidate timing parameter combinations to be verified, and the configuration and verification operations are repeated until the target signal measurement results that meet the preset tuning conditions are output, and the candidate timing parameter combination corresponding to the target signal measurement results is used as the target timing parameter combination.

2. The method according to claim 1, characterized in that Before configuring the candidate timing parameter combination to the server to be optimized, the method further includes: Detecting debugging instructions for the server to be optimized; A parameter optimization mechanism is triggered based on the debug instruction, and candidate timing parameter combinations are generated according to the debug range of the timing parameter combination in the debug instruction.

3. The method according to claim 2, characterized in that Generating a candidate timing parameter combination according to the debugging range of the timing parameter combination in the debugging instruction includes: parsing the debugging range of the timing parameter combination in the debugging instruction; Constructing a training data set based on the debugging range, and using the training data set to train an initial signal evaluation model to obtain a target signal evaluation model; The target signal evaluation model is used to determine candidate timing parameter combinations.

4. The method according to claim 3, characterized in that The constructing of a training data set based on the debugging range includes: Selecting a first timing parameter combination within the debugging range; Configuring the first timing parameter combination to a memory controller in the server to be optimized, and obtaining a first signal measurement result of a memory interface when the memory controller operates under the first timing parameter combination; Building a Gaussian process model based on the first timing parameter combination and the first signal measurement result, and predicting a next set of second timing parameter combinations to be debugged by using the Gaussian process model; The second timing parameter combination is configured to the memory controller in the server to be optimized, and a second signal measurement result of the memory interface when the memory controller is running under the second timing parameter combination is obtained. The parameter prediction and configuration operations are iteratively performed until the preset sampling conditions are met, and a training data set is generated using the mapping relationship between the timing parameter combination and the measurement results.

5. The method according to claim 3, characterized in that The determining of a candidate timing parameter combination by using the target signal evaluation model includes: Converting the mapping relationship in the training data set into a feature vector; Evaluating each of the feature vectors using the target signal evaluation model to obtain a signal quality score for each of the feature vectors; Candidate timing parameter combinations are screened from the training data set based on the signal quality score.

6. The method according to claim 5, characterized in that The using the target signal evaluation model to evaluate each of the feature vectors to obtain a signal quality score for each of the mapping relationships includes: Extracting local signal features and timing dependency features from the feature vector; Analyzing the local characteristics of the signal and the timing dependency characteristics to obtain analysis results; A signal quality score of the feature vector is determined based on the analysis result.

7. The method according to claim 4, characterized in that The constructing of a Gaussian process model based on the first timing parameter combination and the first signal measurement result includes: Establishing an initial Gaussian process model based on the first timing parameter combination and the first signal measurement result; The random dynamic characteristics between the respective timing parameters in the first timing parameter combination and the preset acquisition strategy of the timing parameters are configured in the initial Gaussian process model to obtain a Gaussian process model.

8. The method according to claim 7, characterized in that The establishing of an initial Gaussian process model based on the first timing parameter combination and the first signal measurement result includes: Establishing a parameter space and a corresponding indicator space based on the debugging range in the debugging instruction; The first timing parameter combination is written into the parameter space, the first signal measurement result is written into the indicator space, and a probabilistic mapping between the parameter space and the indicator space is established according to the mapping relationship between the first timing parameter combination and the first signal measurement result to obtain an initial Gaussian process model.

9. The method according to claim 1, characterized in that Verifying whether the candidate signal measurement result meets a preset tuning condition includes: extracting a plurality of memory interface signals from the candidate signal measurement results; Calculating the effective delay width of the memory interface signal, and verifying whether the effective delay width of the memory interface signal meets the corresponding delay characteristics, to obtain a verification result; If the verification result is that the effective delay width of each memory interface signal satisfies the corresponding delay characteristics, then it is determined that the candidate signal measurement result satisfies the preset tuning conditions; or, if the verification result is that the effective delay width of any memory interface signal does not satisfy the corresponding delay characteristics, then it is determined that the candidate signal measurement result does not satisfy the preset tuning conditions.

10. The method according to claim 9, characterized in that Verifying whether the effective delay width of the memory interface signal satisfies the corresponding delay characteristic to obtain a verification result includes: Obtaining a signal type of the memory interface signal; Determining a delay threshold corresponding to the signal type based on an association between the preset signal type and the preset delay threshold; The effective delay width is verified based on the delay threshold to obtain a verification result.

11. The method according to claim 10, characterized in that The valid delay width is verified based on the delay threshold to obtain a verification result, including: Detecting whether the delay threshold hits the central area of ​​the effective delay width; If the center area of ​​the effective delay width is hit, the verification result is determined to be that the effective delay width meets the delay characteristic; or if the center area of ​​the effective delay width is not hit, the verification result is determined to be that the effective delay width does not meet the delay characteristic.

12. The method according to claim 3, characterized in that The trigger parameter optimization mechanism generates the next set of candidate timing parameter combinations to be verified, including: Adding the candidate timing parameter combination and the candidate signal measurement result to a training data set to obtain an updated training data set; Training the target signal evaluation model based on the updated training data set to obtain an optimized target signal evaluation model; The optimized target signal evaluation model is used to determine the next set of candidate timing parameter combinations to be verified.

13. A device for tuning memory timing parameters, characterized in that: include: A configuration module, configured to configure a candidate timing parameter combination to a memory controller in a server to be optimized, and obtain candidate signal measurement results of a memory interface when the memory controller operates under the candidate timing parameter combination; A verification module, configured to verify whether a measurement result of a candidate signal of the memory interface satisfies a preset tuning condition; The trigger module is used to trigger the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified if the preset tuning conditions are not met, repeatedly perform configuration and verification operations until the target signal measurement results that meet the preset tuning conditions are output, and use the candidate timing parameter combination corresponding to the target signal measurement results as the target timing parameter combination.

14. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 12 by executing the computer instructions.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 12.

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