Rapid configuration method for configuration memory in FPGA chip

Abstract

The invention provides a rapid configuration method for an FPGA (Field Programmable Gate Array) chip configuration memory. The method comprises the following steps: receiving reconfiguration information, switching a chip from a user mode to a partial module reconfiguration mode, switching partial modules in the chip from the user mode to a configuration mode, and reconfiguring the partial modules; and after the configuration is completed, the chip is switched to the user mode again. According to the method, only part of modules are reconfigured in the reconfiguration process of the configuration memory, and all modules do not need to be reconfigured, so that the time required by chip reconfiguration is greatly shortened, the flexibility of the reconfiguration process of the configuration memory is improved, and the method is particularly suitable for being applied to reconfiguration of large-scale chip configuration memories.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA chips, and in particular to a fast configuration method for a configuration memory. Background Art

[0002] Configuration memory is the core component of the FPGA chip. It is responsible for storing configuration files such as the lookup table (LUT). Each configuration process of the FPGA chip is actually the process of loading the configuration file into the configuration memory of each functional module of the chip, so that the FPGA can realize different functions.

[0003] With advances in integrated circuit technology, the size and complexity of FPGA chips are also growing. Today, FPGA devices may contain billions of programmable logic cells and tens of thousands of I / O pins. While this increase in FPGA chip size has greatly improved FPGA processing capabilities, it has also brought a new challenge: increased configuration time. As FPGA chip size continues to grow, the number of modules that need to be configured increases, significantly increasing configuration time and impacting overall system performance and efficiency. Therefore, a fast configuration method is needed to adapt to the application of large-scale FPGA chips. Summary of the Invention

[0004] To solve the above problems, the present invention provides a method for quickly configuring an FPGA chip configuration memory, wherein the configuration memory is distributed in each module of the FPGA chip. The method comprises:

[0005] receiving reconfiguration information;

[0006] The chip switches to the reconfiguration mode for some modules, and some modules switch to the configuration mode;

[0007] reconfiguring the configuration memories of the partial modules;

[0008] After reconfiguration is complete, the chip switches back to user mode.

[0009] In some embodiments, the modules are connected via a bus, each module corresponds to an address code, the reconfiguration information includes a global module address signal, and the global module address signal includes the address codes of the partial modules;

[0010] The switching of some modules to configuration mode specifically includes:

[0011] The module receives the global module address signal sent by the bus;

[0012] The module matches its own address code with the global module address signal;

[0013] If the match is successful, the module outputs a submodule configuration signal to the internal module to control the module to enter the configuration mode;

[0014] If the match is unsuccessful, the module remains in user mode.

[0015] In some embodiments, before receiving the reconfiguration information, the method further includes:

[0016] After the chip is powered on, it enters the full chip configuration mode, and all modules in the chip enter the configuration mode;

[0017] Initializing and initially configuring the configuration memories of all modules;

[0018] After configuration is completed, all modules enter user mode and the chip enters user mode.

[0019] In some embodiments, reconfiguring the partial modules specifically includes:

[0020] Initializing the configuration memory of the partial modules;

[0021] The new configuration data is written into the configuration memory of the partial module.

[0022] In some embodiments, the partial modules are one or more modules.

[0023] In some embodiments, after receiving the reconfiguration information in the method, until the configuration is completed, the modules other than the partial modules in the chip are in user mode.

[0024] On the other hand, the present invention further provides a signal conversion circuit for realizing independent configuration of modules, the signal conversion circuit comprising:

[0025] The submodule address matching circuit is used to match the module's own address code with the global module address signal; if the match is successful, the output lock of the signal conversion circuit is released; otherwise, the output of the signal conversion circuit is locked in the current state;

[0026] The signal conversion path is used to output a submodule configuration end signal to the module according to the input global configuration end signal; the submodule configuration end signal is used to control the module to enter or exit the configuration mode.

[0027] In some embodiments, the signal conversion path includes:

[0028] A first signal conversion path, configured to output a submodule initialization signal or a first submodule configuration end signal according to an input global initialization signal or a global configuration end signal;

[0029] a second signal conversion path, configured to output a second submodule configuration end signal according to the input global configuration end signal and the mode switching signal;

[0030] The submodule initialization signal is used to control the module to enter or exit the initialization phase.

[0031] The signal conversion circuit further includes:

[0032] The multiplexer is used to select one of the signals generated by the first signal conversion path and the second signal conversion path according to the current mode of the chip as the output of the signal conversion circuit; when the chip is in the full chip configuration mode, the multiplexer outputs the signal generated by the first signal conversion path; when the chip is in the partial module reconfiguration mode, the multiplexer outputs the signal generated by the second signal conversion path.

[0033] The configuration memory reconfiguration method provided by the present invention only reconfigures part of the modules during the reconfiguration process without reconfiguring all the modules, which greatly shortens the time required for chip reconfiguration and is particularly suitable for large-scale chip reconfiguration. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 This is a schematic diagram of module distribution in the FPGA chip;

[0036] Figure 2 It is a structural diagram of the signal conversion circuit in the module;

[0037] Figure 3 Schematic diagram of the overall and local signals of the chip during the configuration process. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. As the scale of FPGA chips becomes larger and larger, the various functional modules in the chip are also increasing. When reconfiguring the chip, if the configuration memories in all modules are reconfigured every time, it will take a lot of configuration time, and the larger the chip scale, the longer the configuration time. In most cases, before and after the chip is reconfigured, not all the configuration information inside the modules has changed, but only the configuration information inside some modules has changed. Therefore, in order to shorten the configuration time, during reconfiguration, only the configuration memories in some modules can be configured, rather than reconfiguring the configuration memories in all modules. Based on the above concept, the present invention proposes a fast configuration method for chip configuration memory.

[0039] The configuration method provided by the present invention is described in detail below with reference to specific embodiments.

[0040] The distribution of module blocks in FPGA chip is as follows Figure 1 As shown, the FPGA chip is composed of multiple functional module blocks. A certain number of blocks form a row, and many rows of blocks together constitute the entire FPGA chip. The blocks in each row are connected through the horizontal routing channel module (row channel seam) of the system bus, and each row channel seam is connected to the vertical routing channel module (main line spine) of the system bus, and the main line spine is connected to the external system of the chip. The configuration information from the external system is passed to each block in turn through the main line spine and the row channel seam. The vertical main line spine and the horizontal row channel seam together constitute the system bus (or bus). Each block corresponds to an address code. Each block contains a configuration memory for storing the configuration information of the module and continuously outputs the configuration information in user mode to control the module to perform its function.

[0041] The block division method depends on the chip design requirements. Different chip blocks may have different division methods and sizes, and the number of storage cells contained in each block may also vary. However, regardless of the division method, it is necessary to ensure that these blocks can be independently configured.

[0042] The following provides a specific method for implementing independent configuration of each block in hardware. This method is only one implementation of the present invention. Regardless of whether the module blocks in the chip use the following circuits, as long as independent configuration of each block is possible, the configuration memory rapid reconfiguration method provided by the present invention can be used.

[0043] In order to achieve that each block can be configured independently, each block contains Figure 2 The signal conversion circuit shown converts global input signals into sub-module control signals within the block itself. Global signals are globally broadcast signals sent to every block in the chip via the system bus. Sub-module control signals, on the other hand, are generated within each block to control initialization and configuration. They are generated and used only within each block and are not output to the bus.

[0044] The inputs of the circuit include: a mode switching signal, a global initialization signal or a global configuration end signal, and a global module address signal.

[0045] The mode switch signal controls the chip's switching between full-chip configuration mode and partial module reconfiguration mode. The global initialization signal and global configuration completion signal control chip initialization and entry into user mode, respectively. The global module address signal includes the address code for the module block that needs to be reconfigured. These signals are global and are sent to every block in the chip via the system bus.

[0046] The structure of the signal conversion circuit is as follows Figure 2 As shown, it includes: a sub-module address matching circuit, a first signal conversion path path1, a second signal conversion path path2 and a multiplexer mux. The functions of the above modules are introduced below.

[0047] The submodule address matching circuit is used to match the module's own address code with the global module address signal; if the match is successful, the output lock of the signal conversion circuit is released; otherwise, the output of the signal conversion circuit is locked in the current state.

[0048] The submodule address matching circuit is used to match the block's own address code with the global module address signal. If the match is successful, indicating that the block has been selected and requires initialization or configuration, the submodule address matching circuit will unlock the output of the signal conversion circuit, allowing the circuit's output to change based on the input. If the match is unsuccessful, indicating that the block does not need initialization or configuration, the submodule address matching circuit will lock the output of the signal conversion circuit, locking the output to the submodule configuration completion signal after the last configuration, and it will not change based on the input. In this way, the block will remain locked in user mode and will not enter configuration mode.

[0049] The above introduces the sub-module address matching circuit. The following introduces the signal conversion paths path1 and path2.

[0050] The first signal conversion path path1 is used to output a submodule initialization signal or a first submodule configuration end signal based on the input global initialization signal or the global configuration end signal; the second signal conversion path path2 is used to output a second submodule configuration end signal based on the global configuration end signal and the mode switching signal.

[0051] The submodule configuration completion signal is used to control the module to enter or exit the configuration mode; the submodule initialization signal is used to control the module to enter or exit the initialization phase.

[0052] Signal conversion paths path1 and path2 are used to convert a global initialization signal or a global configuration end signal into a submodule initialization signal or a submodule configuration end signal of the block itself.

[0053] The submodule signals generated by path 1 are used in full-chip configuration mode, while the submodule signals generated by path 2 are used in partial-module reconfiguration mode. Due to the different initialization and reconfiguration methods in full-chip configuration mode and partial-module reconfiguration mode, the submodule signals generated by path 1 and path 2 are fundamentally different. For example, with respect to initialization, in full-chip configuration mode, all modules in the chip begin initialization simultaneously, using hard initialization, corresponding to submodule initialization signals. In partial-module configuration mode, however, modules that require reconfiguration enter configuration mode and then enter initialization again, using soft initialization. Soft initialization does not require a control signal trigger, so in partial-module reconfiguration mode, path 2 does not generate submodule initialization signals, and the system performs soft initialization automatically.

[0054] The above introduces the signal conversion paths path1 and path2. The following introduces the multiplexer mux.

[0055] The multiplexer mux is used to select one of the signals generated by path 1 and path 2 according to the mode switching signal as the output of the signal conversion circuit. When the chip is in full-chip configuration mode, the multiplexer mux outputs the signal generated by path 1, namely, the first module initialization signal or the first submodule configuration completion signal; when the chip is in partial module reconfiguration mode, the multiplexer mux outputs the signal generated by path 2, namely, the second module initialization signal or the second submodule configuration completion signal.

[0056] Based on the above circuit, independent configuration of each block can be achieved. When some blocks need to be reconfigured, the system bus will send a global module address signal to all blocks, which includes the address code of the block that needs to be reconfigured. The sub-module address matching circuit inside the block will match the block's own address code with the global module address signal, and only some blocks that need to be reconfigured can be matched successfully. After the match is successful, the sub-module address matching circuit in some blocks releases the output lock of the signal conversion circuit in the block, and the block can switch to configuration mode according to the signal conversion path and the sub-module control signal output by the multiplexer. Other blocks that fail to match will remain in user mode and cannot be configured. In this way, each block can be controlled by its own address code to achieve independent configuration, and different blocks will not affect each other during the configuration process.

[0057] The above describes the distribution of modules in FPGA chips and an implementation method of independent configuration of module blocks. Figure 3 The global and local signal diagrams of the chip during the configuration process are shown in FIG, and the fast configuration method of the configuration memory provided by the present invention is specifically introduced. The method includes the following steps:

[0058] S0: The entire chip is powered on and initialized, then the entire chip is configured, and then the entire chip enters user mode.

[0059] This step corresponds to Figure 3 The "full chip configuration mode" in the , specifically includes:

[0060] S01, after the chip is powered on, it enters the full chip configuration mode, and all modules in the chip enter the configuration mode;

[0061] This step corresponds to Figure 3 At the beginning of the process, the global configuration mode end signal is low, indicating that the chip is in global configuration mode.

[0062] S02, initializing and initially configuring the configuration memories of all modules;

[0063] like Figure 3 As shown in FIG, at the beginning of the initialization phase, the chip global initialization signal and the initialization signals of all modules are turned high, indicating the start of initialization of the configuration memory of all modules. In this step, the initialization adopts the traditional hard initialization.

[0064] After the initialization phase is over, the initial configuration begins, corresponding to Figure 3In the full chip configuration stage, the global initialization signal and the initialization signal of all modules become low, and the global configuration mode end signal and the configuration mode end signal of all modules remain at a low level, indicating that the configuration memory of all modules in the full chip is in the configuration stage.

[0065] S03. After the configuration is completed, the full chip configuration mode ends, all modules enter the user mode, and the chip enters the user mode.

[0066] This step corresponds to Figure 3 In the first user mode stage, the initial configuration is completed, and the global configuration mode end signal and the configuration mode end signals of all modules become high, indicating that the entire chip has entered user mode.

[0067] The above describes the complete process of powering up the chip and performing the initial configuration. This process is consistent with the chip initialization process in the prior art. The following describes the chip reconfiguration process, corresponding to Figure 3 "Partial Module Reconfiguration Mode" in the

[0068] S1. Receive reconfiguration information; the reconfiguration information includes a global module address signal, and the global module address signal includes address codes of the partial modules.

[0069] When reconfiguration is required, the system will give reconfiguration information. When the chip receives the reconfiguration information, it means that a new round of reconfiguration is required.

[0070] The reconfiguration information includes a global module address signal, and the global module address signal includes a portion of the module block that needs to be reconfigured (i.e. Figure 1 and Figure 3 The address code of module 1) in the chip is obtained. Subsequently, only these blocks need to be reconfigured, without having to reconfigure all the blocks in the chip. This can significantly shorten the time required for large-scale chip reconfiguration.

[0071] The reconfiguration information may also include configuration data that needs to be written into each block.

[0072] Some modules can be selected arbitrarily according to configuration requirements, with no limit on the number, and can be one or more.

[0073] S2: The chip switches to the partial module reconfiguration mode, and some module blocks switch to the configuration mode.

[0074] After receiving the reconfiguration information, the chip switches from user mode to partial module reconfiguration mode. Figure 3As shown in Figure 1, the chip enters partial module reconfiguration mode. The mode switch signal goes high, indicating that the chip's configuration mode has switched from full chip configuration mode to partial module reconfiguration mode. At the same time, the global configuration mode end signal goes low, indicating that the chip has exited user mode and entered configuration mode. In configuration mode, the chip cannot operate normally and can only be configured.

[0075] Some modules in the configuration memory are switched from user mode to configuration mode, corresponding to Figure 3 The configuration mode end signal of module 1 becomes low. At this time, the configuration mode end signals of other modules remain high, indicating that the modules other than the aforementioned modules in the configuration memory are always in the configuration mode end state, that is, always in user mode.

[0076] The specific implementation method of switching some modules from user mode to configuration mode is as follows:

[0077] The bus transmits the global module address signal to each block in the chip. The submodule address matching circuit within the block matches the block's address code with the global module address signal. A successful match indicates that the block belongs to the partial module block requiring configuration. After a successful match, the output lock of the signal conversion circuit in the partial module block is released. At this point, the global configuration end signal is low, and the chip is in partial module reconfiguration mode. Path 2 converts the low-level global configuration end signal into a low-level second submodule configuration end signal, which serves as the final output of the signal conversion circuit, controlling the block's entry into configuration mode.

[0078] For other modules, after the block's own address code fails to match the global module address signal, the sub-module address matching circuit will lock the output state of the signal conversion circuit, so that the sub-module configuration end signal always remains at a high level, thereby keeping the module in the configuration mode end state, that is, always in user mode.

[0079] S3, reconfigure the configuration memory of the said part of the module. This step specifically includes:

[0080] S31, initializing the configuration memory of the partial modules;

[0081] This step corresponds to Figure 3 Part of the module reinitialization phase.

[0082] This step uses soft initialization to make some modules enter the initialization state again, which is different from the hard initialization method in the full chip configuration mode. Soft initialization does not require sub-module control signals to execute. At this time, the signal conversion circuit in the module will not output sub-module initialization signals, so Figure 3 The "module 1 initialization signal" in the figure does not become a high level at this stage. In fact, after entering the configuration mode, module 1 enters the re-initialization stage and starts to perform soft initialization on its own.

[0083] S32, writing the new configuration data into the configuration memory of the partial module;

[0084] This step corresponds to Figure 3 Partial module reconfiguration phase in .

[0085] The bus sends the configuration data that needs to be written into the configuration memory of each module to each block in the configuration mode according to the address code of each module. The configuration memory of some modules receives the configuration data and completes the reconfiguration. Figure 3 As shown, in this stage, the "module 1 configuration mode end signal" is low level, indicating that module 1 is in configuration mode; the "other module configuration mode end signal" is high level, indicating that other modules are in user mode.

[0086] In addition to the above two sub-steps S31 and S32, reconfiguring the configuration memory of the partial module may also include other steps, such as verifying the configuration data in the configuration memory of the partial module after writing the configuration data to ensure its integrity and correctness.

[0087] The above describes the process of reconfiguring some modules.

[0088] S4. After configuration is completed, the chip switches back to user mode.

[0089] This step corresponds to Figure 3 Some modules in the system re-enter the user mode stage.

[0090] After the configuration memory of some modules is reconfigured, they send a configuration completion signal to the system bus. Upon receiving these signals from all modules, the system bus sets the global configuration mode end signal high, switching the chip back to user mode. At this point, the configuration mode end signal for module 1 also goes high, placing it in user mode. The configuration mode end signals for the other modules remain high, keeping them in user mode. This completes the reconfiguration of the chip's configuration memory, allowing the chip to function normally.

[0091] The above describes in detail the fast configuration method of the FPGA chip configuration memory provided by the present invention. The following is a brief summary. After the chip is powered on, during the entire process of initial configuration and reconfiguration of the configuration memory, the overall and local signals of the chip configuration memory are as follows: Figure 3 After the chip is powered on, the whole chip is initialized, then the whole chip is configured for the first time, and then the whole chip enters the user mode; after receiving the reconfiguration information, the chip switches to the partial module reconfiguration mode, and some modules (such as Figure 3 Module 1) switches to configuration mode for reconfiguration, while other modules remain in user mode; after configuration is completed, some modules re-enter user mode, and the entire chip re-enters user mode.

[0092] Need to understand, Figure 3 The clock signal indicates that all signals in the figure are synchronous signals and require a clock to latch. Figure 3 The line lengths of the stages shown do not represent the actual duration.

[0093] The above method can be used in a loop and repeated continuously. When the previous part of the block (the first part of the module) is reconfigured and the chip is in user mode, the chip can be switched back to the partial module reconfiguration mode, and the other part of the block (the second part of the module) can be switched from user mode to configuration mode, and then reconfigured; this cycle is repeated until all blocks that need to be reconfigured are configured. Of course, after any part of the block is reconfigured and the chip is switched back to user mode, the configuration can be considered complete and the chip can be used normally. The cyclic use of this method can realize the reconfiguration of different parts of the module at any time, which greatly increases the flexibility of the configuration memory reconfiguration process.

[0094] The configuration memory reconfiguration method provided by the present invention only reconfigures part of the blocks during the reconfiguration process without having to reconfigure the entire configuration memory, which greatly shortens the time required for chip reconfiguration and increases the flexibility of the configuration memory reconfiguration process. It is particularly suitable for application in large-scale chip reconfiguration.

[0095] In the description of the embodiments of the present application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0096] In the description of the embodiments of this application, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0098] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for rapidly configuring an FPGA chip configuration memory, wherein the configuration memory is distributed in modules of the FPGA chip, the modules are connected via a bus, and each module corresponds to an address code, characterized in that: The method comprises: Receiving reconfiguration information; the reconfiguration information includes a global module address signal, the global module address signal includes an address code of a portion of the module; The chip switches to the reconfiguration mode for some modules, and some modules switch to the configuration mode; The switching of some modules to configuration mode specifically includes: The module receives the global module address signal sent by the bus; The module matches its own address code with the global module address signal; If the match is successful, the module outputs a submodule configuration signal to the internal module, controls the module to enter the configuration mode, and reconfigures the configuration memory of the part of the module; After reconfiguration is complete, the chip switches back to user mode.

2. The configuration method according to claim 1, characterized in that: After the module matches its own address code with the global module address signal, the method further includes: if the match is unsuccessful, the module maintains the user mode.

3. The configuration method according to claim 1, wherein: Before receiving the reconfiguration information, the method further includes: After the chip is powered on, it enters the full chip configuration mode, and all modules in the chip enter the configuration mode; Initializing and initially configuring the configuration memories of all modules; After configuration is complete, the chip enters user mode.

4. The configuration method according to claim 1, wherein: The reconfiguring of the configuration memory of the part of the modules specifically includes: Initializing the configuration memory of the partial modules; The new configuration data is written into the configuration memory of the partial module.

5. The configuration method according to claim 1, wherein: The partial modules are one or more modules.

6. The configuration method according to claim 1, characterized in that: In the method, after receiving the reconfiguration information, until the configuration is completed, the modules other than the partial modules in the chip are always in the user mode.

7. A signal conversion circuit, characterized in that: The signal conversion circuit is used to convert the global signal into the sub-module control signal within the module, and the signal conversion circuit includes: The submodule address matching circuit is used to receive the global module address signal sent by the bus and match the module's own address code with the global module address signal; if the match is successful, the output lock of the signal conversion circuit is released; otherwise, the output of the signal conversion circuit is locked in the current state; The signal conversion path is used to output a submodule configuration end signal to the module according to the input global configuration end signal; the submodule configuration end signal is used to control the module to enter or exit the configuration mode.

8. The signal conversion circuit according to claim 7, wherein: The signal conversion path includes: A first signal conversion path, configured to output a submodule initialization signal or a first submodule configuration end signal according to an input global initialization signal or a global configuration end signal; a second signal conversion path, configured to output a second submodule configuration end signal according to the input global configuration end signal and the mode switching signal; The submodule initialization signal is used to control the module to enter or exit the initialization phase; The signal conversion circuit further includes: The multiplexer is used to select one of the signals output by the first signal conversion path and the second signal conversion path according to the current mode of the chip as the output of the signal conversion circuit to the inside of the module; when the chip is in the full chip configuration mode, the multiplexer outputs the signal generated by the first signal conversion path; when the chip is in the partial module reconfiguration mode, the multiplexer outputs the signal generated by the second signal conversion path.

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